1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2008 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * Copyright (C) 2018 by Liviu Ionescu *
14 * This program is free software; you can redistribute it and/or modify *
15 * it under the terms of the GNU General Public License as published by *
16 * the Free Software Foundation; either version 2 of the License, or *
17 * (at your option) any later version. *
19 * This program is distributed in the hope that it will be useful, *
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
22 * GNU General Public License for more details. *
24 * You should have received a copy of the GNU General Public License *
25 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
26 ***************************************************************************/
35 #include "breakpoints.h"
36 #include "arm_disassembler.h"
37 #include <helper/binarybuffer.h>
38 #include "algorithm.h"
40 #include "semihosting_common.h"
42 /* offsets into armv4_5 core register cache */
44 /* ARMV4_5_CPSR = 31, */
45 ARMV4_5_SPSR_FIQ
= 32,
46 ARMV4_5_SPSR_IRQ
= 33,
47 ARMV4_5_SPSR_SVC
= 34,
48 ARMV4_5_SPSR_ABT
= 35,
49 ARMV4_5_SPSR_UND
= 36,
54 static const uint8_t arm_usr_indices
[17] = {
55 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, ARMV4_5_CPSR
,
58 static const uint8_t arm_fiq_indices
[8] = {
59 16, 17, 18, 19, 20, 21, 22, ARMV4_5_SPSR_FIQ
,
62 static const uint8_t arm_irq_indices
[3] = {
63 23, 24, ARMV4_5_SPSR_IRQ
,
66 static const uint8_t arm_svc_indices
[3] = {
67 25, 26, ARMV4_5_SPSR_SVC
,
70 static const uint8_t arm_abt_indices
[3] = {
71 27, 28, ARMV4_5_SPSR_ABT
,
74 static const uint8_t arm_und_indices
[3] = {
75 29, 30, ARMV4_5_SPSR_UND
,
78 static const uint8_t arm_mon_indices
[3] = {
82 static const uint8_t arm_hyp_indices
[2] = {
89 /* For user and system modes, these list indices for all registers.
90 * otherwise they're just indices for the shadow registers and SPSR.
92 unsigned short n_indices
;
93 const uint8_t *indices
;
95 /* Seven modes are standard from ARM7 on. "System" and "User" share
96 * the same registers; other modes shadow from 3 to 8 registers.
101 .n_indices
= ARRAY_SIZE(arm_usr_indices
),
102 .indices
= arm_usr_indices
,
107 .n_indices
= ARRAY_SIZE(arm_fiq_indices
),
108 .indices
= arm_fiq_indices
,
111 .name
= "Supervisor",
113 .n_indices
= ARRAY_SIZE(arm_svc_indices
),
114 .indices
= arm_svc_indices
,
119 .n_indices
= ARRAY_SIZE(arm_abt_indices
),
120 .indices
= arm_abt_indices
,
125 .n_indices
= ARRAY_SIZE(arm_irq_indices
),
126 .indices
= arm_irq_indices
,
129 .name
= "Undefined instruction",
131 .n_indices
= ARRAY_SIZE(arm_und_indices
),
132 .indices
= arm_und_indices
,
137 .n_indices
= ARRAY_SIZE(arm_usr_indices
),
138 .indices
= arm_usr_indices
,
140 /* TrustZone "Security Extensions" add a secure monitor mode.
141 * This is distinct from a "debug monitor" which can support
142 * non-halting debug, in conjunction with some debuggers.
145 .name
= "Secure Monitor",
147 .n_indices
= ARRAY_SIZE(arm_mon_indices
),
148 .indices
= arm_mon_indices
,
151 .name
= "Secure Monitor ARM1176JZF-S",
152 .psr
= ARM_MODE_1176_MON
,
153 .n_indices
= ARRAY_SIZE(arm_mon_indices
),
154 .indices
= arm_mon_indices
,
157 /* These special modes are currently only supported
158 * by ARMv6M and ARMv7M profiles */
161 .psr
= ARM_MODE_THREAD
,
164 .name
= "Thread (User)",
165 .psr
= ARM_MODE_USER_THREAD
,
169 .psr
= ARM_MODE_HANDLER
,
172 /* armv7-a with virtualization extension */
174 .name
= "Hypervisor",
176 .n_indices
= ARRAY_SIZE(arm_hyp_indices
),
177 .indices
= arm_hyp_indices
,
181 /** Map PSR mode bits to the name of an ARM processor operating mode. */
182 const char *arm_mode_name(unsigned psr_mode
)
184 for (unsigned i
= 0; i
< ARRAY_SIZE(arm_mode_data
); i
++) {
185 if (arm_mode_data
[i
].psr
== psr_mode
)
186 return arm_mode_data
[i
].name
;
188 LOG_ERROR("unrecognized psr mode: %#02x", psr_mode
);
189 return "UNRECOGNIZED";
192 /** Return true iff the parameter denotes a valid ARM processor mode. */
193 bool is_arm_mode(unsigned psr_mode
)
195 for (unsigned i
= 0; i
< ARRAY_SIZE(arm_mode_data
); i
++) {
196 if (arm_mode_data
[i
].psr
== psr_mode
)
202 /** Map PSR mode bits to linear number indexing armv4_5_core_reg_map */
203 int arm_mode_to_number(enum arm_mode mode
)
207 /* map MODE_ANY to user mode */
223 case ARM_MODE_1176_MON
:
228 LOG_ERROR("invalid mode value encountered %d", mode
);
233 /** Map linear number indexing armv4_5_core_reg_map to PSR mode bits. */
234 enum arm_mode
armv4_5_number_to_mode(int number
)
256 LOG_ERROR("mode index out of bounds %d", number
);
261 static const char *arm_state_strings
[] = {
262 "ARM", "Thumb", "Jazelle", "ThumbEE",
265 /* Templates for ARM core registers.
267 * NOTE: offsets in this table are coupled to the arm_mode_data
268 * table above, the armv4_5_core_reg_map array below, and also to
269 * the ARMV4_5_CPSR symbol (which should vanish after ARM11 updates).
271 static const struct {
272 /* The name is used for e.g. the "regs" command. */
275 /* The {cookie, mode} tuple uniquely identifies one register.
276 * In a given mode, cookies 0..15 map to registers R0..R15,
277 * with R13..R15 usually called SP, LR, PC.
279 * MODE_ANY is used as *input* to the mapping, and indicates
280 * various special cases (sigh) and errors.
282 * Cookie 16 is (currently) confusing, since it indicates
283 * CPSR -or- SPSR depending on whether 'mode' is MODE_ANY.
284 * (Exception modes have both CPSR and SPSR registers ...)
289 } arm_core_regs
[] = {
290 /* IMPORTANT: we guarantee that the first eight cached registers
291 * correspond to r0..r7, and the fifteenth to PC, so that callers
292 * don't need to map them.
294 [0] = { .name
= "r0", .cookie
= 0, .mode
= ARM_MODE_ANY
, .gdb_index
= 0, },
295 [1] = { .name
= "r1", .cookie
= 1, .mode
= ARM_MODE_ANY
, .gdb_index
= 1, },
296 [2] = { .name
= "r2", .cookie
= 2, .mode
= ARM_MODE_ANY
, .gdb_index
= 2, },
297 [3] = { .name
= "r3", .cookie
= 3, .mode
= ARM_MODE_ANY
, .gdb_index
= 3, },
298 [4] = { .name
= "r4", .cookie
= 4, .mode
= ARM_MODE_ANY
, .gdb_index
= 4, },
299 [5] = { .name
= "r5", .cookie
= 5, .mode
= ARM_MODE_ANY
, .gdb_index
= 5, },
300 [6] = { .name
= "r6", .cookie
= 6, .mode
= ARM_MODE_ANY
, .gdb_index
= 6, },
301 [7] = { .name
= "r7", .cookie
= 7, .mode
= ARM_MODE_ANY
, .gdb_index
= 7, },
303 /* NOTE: regs 8..12 might be shadowed by FIQ ... flagging
304 * them as MODE_ANY creates special cases. (ANY means
305 * "not mapped" elsewhere; here it's "everything but FIQ".)
307 [8] = { .name
= "r8", .cookie
= 8, .mode
= ARM_MODE_ANY
, .gdb_index
= 8, },
308 [9] = { .name
= "r9", .cookie
= 9, .mode
= ARM_MODE_ANY
, .gdb_index
= 9, },
309 [10] = { .name
= "r10", .cookie
= 10, .mode
= ARM_MODE_ANY
, .gdb_index
= 10, },
310 [11] = { .name
= "r11", .cookie
= 11, .mode
= ARM_MODE_ANY
, .gdb_index
= 11, },
311 [12] = { .name
= "r12", .cookie
= 12, .mode
= ARM_MODE_ANY
, .gdb_index
= 12, },
313 /* Historical GDB mapping of indices:
314 * - 13-14 are sp and lr, but banked counterparts are used
315 * - 16-24 are left for deprecated 8 FPA + 1 FPS
319 /* NOTE all MODE_USR registers are equivalent to MODE_SYS ones */
320 [13] = { .name
= "sp_usr", .cookie
= 13, .mode
= ARM_MODE_USR
, .gdb_index
= 26, },
321 [14] = { .name
= "lr_usr", .cookie
= 14, .mode
= ARM_MODE_USR
, .gdb_index
= 27, },
323 /* guaranteed to be at index 15 */
324 [15] = { .name
= "pc", .cookie
= 15, .mode
= ARM_MODE_ANY
, .gdb_index
= 15, },
325 [16] = { .name
= "r8_fiq", .cookie
= 8, .mode
= ARM_MODE_FIQ
, .gdb_index
= 28, },
326 [17] = { .name
= "r9_fiq", .cookie
= 9, .mode
= ARM_MODE_FIQ
, .gdb_index
= 29, },
327 [18] = { .name
= "r10_fiq", .cookie
= 10, .mode
= ARM_MODE_FIQ
, .gdb_index
= 30, },
328 [19] = { .name
= "r11_fiq", .cookie
= 11, .mode
= ARM_MODE_FIQ
, .gdb_index
= 31, },
329 [20] = { .name
= "r12_fiq", .cookie
= 12, .mode
= ARM_MODE_FIQ
, .gdb_index
= 32, },
331 [21] = { .name
= "sp_fiq", .cookie
= 13, .mode
= ARM_MODE_FIQ
, .gdb_index
= 33, },
332 [22] = { .name
= "lr_fiq", .cookie
= 14, .mode
= ARM_MODE_FIQ
, .gdb_index
= 34, },
334 [23] = { .name
= "sp_irq", .cookie
= 13, .mode
= ARM_MODE_IRQ
, .gdb_index
= 35, },
335 [24] = { .name
= "lr_irq", .cookie
= 14, .mode
= ARM_MODE_IRQ
, .gdb_index
= 36, },
337 [25] = { .name
= "sp_svc", .cookie
= 13, .mode
= ARM_MODE_SVC
, .gdb_index
= 37, },
338 [26] = { .name
= "lr_svc", .cookie
= 14, .mode
= ARM_MODE_SVC
, .gdb_index
= 38, },
340 [27] = { .name
= "sp_abt", .cookie
= 13, .mode
= ARM_MODE_ABT
, .gdb_index
= 39, },
341 [28] = { .name
= "lr_abt", .cookie
= 14, .mode
= ARM_MODE_ABT
, .gdb_index
= 40, },
343 [29] = { .name
= "sp_und", .cookie
= 13, .mode
= ARM_MODE_UND
, .gdb_index
= 41, },
344 [30] = { .name
= "lr_und", .cookie
= 14, .mode
= ARM_MODE_UND
, .gdb_index
= 42, },
346 [31] = { .name
= "cpsr", .cookie
= 16, .mode
= ARM_MODE_ANY
, .gdb_index
= 25, },
347 [32] = { .name
= "spsr_fiq", .cookie
= 16, .mode
= ARM_MODE_FIQ
, .gdb_index
= 43, },
348 [33] = { .name
= "spsr_irq", .cookie
= 16, .mode
= ARM_MODE_IRQ
, .gdb_index
= 44, },
349 [34] = { .name
= "spsr_svc", .cookie
= 16, .mode
= ARM_MODE_SVC
, .gdb_index
= 45, },
350 [35] = { .name
= "spsr_abt", .cookie
= 16, .mode
= ARM_MODE_ABT
, .gdb_index
= 46, },
351 [36] = { .name
= "spsr_und", .cookie
= 16, .mode
= ARM_MODE_UND
, .gdb_index
= 47, },
353 /* These are only used for GDB target description, banked registers are accessed instead */
354 [37] = { .name
= "sp", .cookie
= 13, .mode
= ARM_MODE_ANY
, .gdb_index
= 13, },
355 [38] = { .name
= "lr", .cookie
= 14, .mode
= ARM_MODE_ANY
, .gdb_index
= 14, },
357 /* These exist only when the Security Extension (TrustZone) is present */
358 [39] = { .name
= "sp_mon", .cookie
= 13, .mode
= ARM_MODE_MON
, .gdb_index
= 48, },
359 [40] = { .name
= "lr_mon", .cookie
= 14, .mode
= ARM_MODE_MON
, .gdb_index
= 49, },
360 [41] = { .name
= "spsr_mon", .cookie
= 16, .mode
= ARM_MODE_MON
, .gdb_index
= 50, },
362 /* These exist only when the Virtualization Extensions is present */
363 [42] = { .name
= "sp_hyp", .cookie
= 13, .mode
= ARM_MODE_HYP
, .gdb_index
= 51, },
364 [43] = { .name
= "spsr_hyp", .cookie
= 16, .mode
= ARM_MODE_HYP
, .gdb_index
= 52, },
367 static const struct {
375 } arm_vfp_v3_regs
[] = {
376 { ARM_VFP_V3_D0
, "d0", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
377 { ARM_VFP_V3_D1
, "d1", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
378 { ARM_VFP_V3_D2
, "d2", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
379 { ARM_VFP_V3_D3
, "d3", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
380 { ARM_VFP_V3_D4
, "d4", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
381 { ARM_VFP_V3_D5
, "d5", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
382 { ARM_VFP_V3_D6
, "d6", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
383 { ARM_VFP_V3_D7
, "d7", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
384 { ARM_VFP_V3_D8
, "d8", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
385 { ARM_VFP_V3_D9
, "d9", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
386 { ARM_VFP_V3_D10
, "d10", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
387 { ARM_VFP_V3_D11
, "d11", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
388 { ARM_VFP_V3_D12
, "d12", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
389 { ARM_VFP_V3_D13
, "d13", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
390 { ARM_VFP_V3_D14
, "d14", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
391 { ARM_VFP_V3_D15
, "d15", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
392 { ARM_VFP_V3_D16
, "d16", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
393 { ARM_VFP_V3_D17
, "d17", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
394 { ARM_VFP_V3_D18
, "d18", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
395 { ARM_VFP_V3_D19
, "d19", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
396 { ARM_VFP_V3_D20
, "d20", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
397 { ARM_VFP_V3_D21
, "d21", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
398 { ARM_VFP_V3_D22
, "d22", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
399 { ARM_VFP_V3_D23
, "d23", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
400 { ARM_VFP_V3_D24
, "d24", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
401 { ARM_VFP_V3_D25
, "d25", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
402 { ARM_VFP_V3_D26
, "d26", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
403 { ARM_VFP_V3_D27
, "d27", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
404 { ARM_VFP_V3_D28
, "d28", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
405 { ARM_VFP_V3_D29
, "d29", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
406 { ARM_VFP_V3_D30
, "d30", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
407 { ARM_VFP_V3_D31
, "d31", 64, ARM_MODE_ANY
, REG_TYPE_IEEE_DOUBLE
, NULL
, "org.gnu.gdb.arm.vfp"},
408 { ARM_VFP_V3_FPSCR
, "fpscr", 32, ARM_MODE_ANY
, REG_TYPE_INT
, "float", "org.gnu.gdb.arm.vfp"},
411 /* map core mode (USR, FIQ, ...) and register number to
412 * indices into the register cache
414 const int armv4_5_core_reg_map
[9][17] = {
416 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
418 { /* FIQ (8 shadows of USR, vs normal 3) */
419 0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 15, 32
422 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 23, 24, 15, 33
425 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 25, 26, 15, 34
428 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 28, 15, 35
431 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 29, 30, 15, 36
433 { /* SYS (same registers as USR) */
434 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
437 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 39, 40, 15, 41,
440 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 42, 14, 15, 43,
445 * Configures host-side ARM records to reflect the specified CPSR.
446 * Later, code can use arm_reg_current() to map register numbers
447 * according to how they are exposed by this mode.
449 void arm_set_cpsr(struct arm
*arm
, uint32_t cpsr
)
451 enum arm_mode mode
= cpsr
& 0x1f;
454 /* NOTE: this may be called very early, before the register
455 * cache is set up. We can't defend against many errors, in
456 * particular against CPSRs that aren't valid *here* ...
459 buf_set_u32(arm
->cpsr
->value
, 0, 32, cpsr
);
460 arm
->cpsr
->valid
= true;
461 arm
->cpsr
->dirty
= false;
464 arm
->core_mode
= mode
;
466 /* mode_to_number() warned; set up a somewhat-sane mapping */
467 num
= arm_mode_to_number(mode
);
473 arm
->map
= &armv4_5_core_reg_map
[num
][0];
474 arm
->spsr
= (mode
== ARM_MODE_USR
|| mode
== ARM_MODE_SYS
)
476 : arm
->core_cache
->reg_list
+ arm
->map
[16];
478 /* Older ARMs won't have the J bit */
479 enum arm_state state
;
481 if (cpsr
& (1 << 5)) { /* T */
482 if (cpsr
& (1 << 24)) { /* J */
483 LOG_WARNING("ThumbEE -- incomplete support");
484 state
= ARM_STATE_THUMB_EE
;
486 state
= ARM_STATE_THUMB
;
488 if (cpsr
& (1 << 24)) { /* J */
489 LOG_ERROR("Jazelle state handling is BROKEN!");
490 state
= ARM_STATE_JAZELLE
;
492 state
= ARM_STATE_ARM
;
494 arm
->core_state
= state
;
496 LOG_DEBUG("set CPSR %#8.8x: %s mode, %s state", (unsigned) cpsr
,
498 arm_state_strings
[arm
->core_state
]);
502 * Returns handle to the register currently mapped to a given number.
503 * Someone must have called arm_set_cpsr() before.
505 * \param arm This core's state and registers are used.
506 * \param regnum From 0..15 corresponding to R0..R14 and PC.
507 * Note that R0..R7 don't require mapping; you may access those
508 * as the first eight entries in the register cache. Likewise
509 * R15 (PC) doesn't need mapping; you may also access it directly.
510 * However, R8..R14, and SPSR (arm->spsr) *must* be mapped.
511 * CPSR (arm->cpsr) is also not mapped.
513 struct reg
*arm_reg_current(struct arm
*arm
, unsigned regnum
)
521 LOG_ERROR("Register map is not available yet, the target is not fully initialised");
522 r
= arm
->core_cache
->reg_list
+ regnum
;
524 r
= arm
->core_cache
->reg_list
+ arm
->map
[regnum
];
526 /* e.g. invalid CPSR said "secure monitor" mode on a core
527 * that doesn't support it...
530 LOG_ERROR("Invalid CPSR mode");
531 r
= arm
->core_cache
->reg_list
+ regnum
;
537 static const uint8_t arm_gdb_dummy_fp_value
[12];
539 static struct reg_feature arm_gdb_dummy_fp_features
= {
540 .name
= "net.sourceforge.openocd.fake_fpa"
544 * Dummy FPA registers are required to support GDB on ARM.
545 * Register packets require eight obsolete FPA register values.
546 * Modern ARM cores use Vector Floating Point (VFP), if they
547 * have any floating point support. VFP is not FPA-compatible.
549 struct reg arm_gdb_dummy_fp_reg
= {
550 .name
= "GDB dummy FPA register",
551 .value
= (uint8_t *) arm_gdb_dummy_fp_value
,
556 .feature
= &arm_gdb_dummy_fp_features
,
560 static const uint8_t arm_gdb_dummy_fps_value
[4];
563 * Dummy FPA status registers are required to support GDB on ARM.
564 * Register packets require an obsolete FPA status register.
566 struct reg arm_gdb_dummy_fps_reg
= {
567 .name
= "GDB dummy FPA status register",
568 .value
= (uint8_t *) arm_gdb_dummy_fps_value
,
573 .feature
= &arm_gdb_dummy_fp_features
,
577 static void arm_gdb_dummy_init(void) __attribute__ ((constructor
));
579 static void arm_gdb_dummy_init(void)
581 register_init_dummy(&arm_gdb_dummy_fp_reg
);
582 register_init_dummy(&arm_gdb_dummy_fps_reg
);
585 static int armv4_5_get_core_reg(struct reg
*reg
)
588 struct arm_reg
*reg_arch_info
= reg
->arch_info
;
589 struct target
*target
= reg_arch_info
->target
;
591 if (target
->state
!= TARGET_HALTED
) {
592 LOG_ERROR("Target not halted");
593 return ERROR_TARGET_NOT_HALTED
;
596 retval
= reg_arch_info
->arm
->read_core_reg(target
, reg
,
597 reg_arch_info
->num
, reg_arch_info
->mode
);
598 if (retval
== ERROR_OK
) {
606 static int armv4_5_set_core_reg(struct reg
*reg
, uint8_t *buf
)
608 struct arm_reg
*reg_arch_info
= reg
->arch_info
;
609 struct target
*target
= reg_arch_info
->target
;
610 struct arm
*armv4_5_target
= target_to_arm(target
);
611 uint32_t value
= buf_get_u32(buf
, 0, 32);
613 if (target
->state
!= TARGET_HALTED
) {
614 LOG_ERROR("Target not halted");
615 return ERROR_TARGET_NOT_HALTED
;
618 /* Except for CPSR, the "reg" command exposes a writeback model
619 * for the register cache.
621 if (reg
== armv4_5_target
->cpsr
) {
622 arm_set_cpsr(armv4_5_target
, value
);
624 /* Older cores need help to be in ARM mode during halt
625 * mode debug, so we clear the J and T bits if we flush.
626 * For newer cores (v6/v7a/v7r) we don't need that, but
627 * it won't hurt since CPSR is always flushed anyway.
629 if (armv4_5_target
->core_mode
!=
630 (enum arm_mode
)(value
& 0x1f)) {
631 LOG_DEBUG("changing ARM core mode to '%s'",
632 arm_mode_name(value
& 0x1f));
633 value
&= ~((1 << 24) | (1 << 5));
635 buf_set_u32(t
, 0, 32, value
);
636 armv4_5_target
->write_core_reg(target
, reg
,
637 16, ARM_MODE_ANY
, t
);
640 buf_set_u32(reg
->value
, 0, 32, value
);
641 if (reg
->size
== 64) {
642 value
= buf_get_u32(buf
+ 4, 0, 32);
643 buf_set_u32(reg
->value
+ 4, 0, 32, value
);
652 static const struct reg_arch_type arm_reg_type
= {
653 .get
= armv4_5_get_core_reg
,
654 .set
= armv4_5_set_core_reg
,
657 struct reg_cache
*arm_build_reg_cache(struct target
*target
, struct arm
*arm
)
659 int num_regs
= ARRAY_SIZE(arm_core_regs
);
660 int num_core_regs
= num_regs
;
661 if (arm
->arm_vfp_version
== ARM_VFP_V3
)
662 num_regs
+= ARRAY_SIZE(arm_vfp_v3_regs
);
664 struct reg_cache
*cache
= malloc(sizeof(struct reg_cache
));
665 struct reg
*reg_list
= calloc(num_regs
, sizeof(struct reg
));
666 struct arm_reg
*reg_arch_info
= calloc(num_regs
, sizeof(struct arm_reg
));
669 if (!cache
|| !reg_list
|| !reg_arch_info
) {
676 cache
->name
= "ARM registers";
678 cache
->reg_list
= reg_list
;
681 for (i
= 0; i
< num_core_regs
; i
++) {
682 /* Skip registers this core doesn't expose */
683 if (arm_core_regs
[i
].mode
== ARM_MODE_MON
684 && arm
->core_type
!= ARM_CORE_TYPE_SEC_EXT
685 && arm
->core_type
!= ARM_CORE_TYPE_VIRT_EXT
)
687 if (arm_core_regs
[i
].mode
== ARM_MODE_HYP
688 && arm
->core_type
!= ARM_CORE_TYPE_VIRT_EXT
)
691 /* REVISIT handle Cortex-M, which only shadows R13/SP */
693 reg_arch_info
[i
].num
= arm_core_regs
[i
].cookie
;
694 reg_arch_info
[i
].mode
= arm_core_regs
[i
].mode
;
695 reg_arch_info
[i
].target
= target
;
696 reg_arch_info
[i
].arm
= arm
;
698 reg_list
[i
].name
= arm_core_regs
[i
].name
;
699 reg_list
[i
].number
= arm_core_regs
[i
].gdb_index
;
700 reg_list
[i
].size
= 32;
701 reg_list
[i
].value
= reg_arch_info
[i
].value
;
702 reg_list
[i
].type
= &arm_reg_type
;
703 reg_list
[i
].arch_info
= ®_arch_info
[i
];
704 reg_list
[i
].exist
= true;
706 /* This really depends on the calling convention in use */
707 reg_list
[i
].caller_save
= false;
709 /* Registers data type, as used by GDB target description */
710 reg_list
[i
].reg_data_type
= malloc(sizeof(struct reg_data_type
));
711 switch (arm_core_regs
[i
].cookie
) {
713 reg_list
[i
].reg_data_type
->type
= REG_TYPE_DATA_PTR
;
717 reg_list
[i
].reg_data_type
->type
= REG_TYPE_CODE_PTR
;
720 reg_list
[i
].reg_data_type
->type
= REG_TYPE_UINT32
;
724 /* let GDB shows banked registers only in "info all-reg" */
725 reg_list
[i
].feature
= malloc(sizeof(struct reg_feature
));
726 if (reg_list
[i
].number
<= 15 || reg_list
[i
].number
== 25) {
727 reg_list
[i
].feature
->name
= "org.gnu.gdb.arm.core";
728 reg_list
[i
].group
= "general";
730 reg_list
[i
].feature
->name
= "net.sourceforge.openocd.banked";
731 reg_list
[i
].group
= "banked";
738 for (i
= num_core_regs
, j
= 0; i
< num_regs
; i
++, j
++) {
739 reg_arch_info
[i
].num
= arm_vfp_v3_regs
[j
].id
;
740 reg_arch_info
[i
].mode
= arm_vfp_v3_regs
[j
].mode
;
741 reg_arch_info
[i
].target
= target
;
742 reg_arch_info
[i
].arm
= arm
;
744 reg_list
[i
].name
= arm_vfp_v3_regs
[j
].name
;
745 reg_list
[i
].number
= arm_vfp_v3_regs
[j
].id
;
746 reg_list
[i
].size
= arm_vfp_v3_regs
[j
].bits
;
747 reg_list
[i
].value
= reg_arch_info
[i
].value
;
748 reg_list
[i
].type
= &arm_reg_type
;
749 reg_list
[i
].arch_info
= ®_arch_info
[i
];
750 reg_list
[i
].exist
= true;
752 reg_list
[i
].caller_save
= false;
754 reg_list
[i
].reg_data_type
= malloc(sizeof(struct reg_data_type
));
755 reg_list
[i
].reg_data_type
->type
= arm_vfp_v3_regs
[j
].type
;
757 reg_list
[i
].feature
= malloc(sizeof(struct reg_feature
));
758 reg_list
[i
].feature
->name
= arm_vfp_v3_regs
[j
].feature
;
760 reg_list
[i
].group
= arm_vfp_v3_regs
[j
].group
;
765 arm
->pc
= reg_list
+ 15;
766 arm
->cpsr
= reg_list
+ ARMV4_5_CPSR
;
767 arm
->core_cache
= cache
;
772 void arm_free_reg_cache(struct arm
*arm
)
774 if (!arm
|| !arm
->core_cache
)
777 struct reg_cache
*cache
= arm
->core_cache
;
779 for (unsigned int i
= 0; i
< cache
->num_regs
; i
++) {
780 struct reg
*reg
= &cache
->reg_list
[i
];
783 free(reg
->reg_data_type
);
786 free(cache
->reg_list
[0].arch_info
);
787 free(cache
->reg_list
);
790 arm
->core_cache
= NULL
;
793 int arm_arch_state(struct target
*target
)
795 struct arm
*arm
= target_to_arm(target
);
797 if (arm
->common_magic
!= ARM_COMMON_MAGIC
) {
798 LOG_ERROR("BUG: called for a non-ARM target");
802 /* avoid filling log waiting for fileio reply */
803 if (target
->semihosting
&& target
->semihosting
->hit_fileio
)
806 LOG_USER("target halted in %s state due to %s, current mode: %s\n"
807 "cpsr: 0x%8.8" PRIx32
" pc: 0x%8.8" PRIx32
"%s%s",
808 arm_state_strings
[arm
->core_state
],
809 debug_reason_name(target
),
810 arm_mode_name(arm
->core_mode
),
811 buf_get_u32(arm
->cpsr
->value
, 0, 32),
812 buf_get_u32(arm
->pc
->value
, 0, 32),
813 (target
->semihosting
&& target
->semihosting
->is_active
) ? ", semihosting" : "",
814 (target
->semihosting
&& target
->semihosting
->is_fileio
) ? " fileio" : "");
819 COMMAND_HANDLER(handle_armv4_5_reg_command
)
821 struct target
*target
= get_current_target(CMD_CTX
);
822 struct arm
*arm
= target_to_arm(target
);
826 command_print(CMD
, "current target isn't an ARM");
830 if (target
->state
!= TARGET_HALTED
) {
831 command_print(CMD
, "error: target must be halted for register accesses");
835 if (arm
->core_type
!= ARM_CORE_TYPE_STD
) {
837 "Microcontroller Profile not supported - use standard reg cmd");
841 if (!is_arm_mode(arm
->core_mode
)) {
842 LOG_ERROR("not a valid arm core mode - communication failure?");
846 if (!arm
->full_context
) {
847 command_print(CMD
, "error: target doesn't support %s",
852 regs
= arm
->core_cache
->reg_list
;
854 for (unsigned mode
= 0; mode
< ARRAY_SIZE(arm_mode_data
); mode
++) {
859 /* label this bank of registers (or shadows) */
860 switch (arm_mode_data
[mode
].psr
) {
864 name
= "System and User";
868 if (arm
->core_type
!= ARM_CORE_TYPE_VIRT_EXT
)
872 if (arm
->core_type
!= ARM_CORE_TYPE_SEC_EXT
873 && arm
->core_type
!= ARM_CORE_TYPE_VIRT_EXT
)
877 name
= arm_mode_data
[mode
].name
;
881 command_print(CMD
, "%s%s mode %sregisters",
884 /* display N rows of up to 4 registers each */
885 for (unsigned i
= 0; i
< arm_mode_data
[mode
].n_indices
; ) {
889 for (unsigned j
= 0; j
< 4; j
++, i
++) {
891 struct reg
*reg
= regs
;
893 if (i
>= arm_mode_data
[mode
].n_indices
)
896 reg
+= arm_mode_data
[mode
].indices
[i
];
898 /* REVISIT be smarter about faults... */
900 arm
->full_context(target
);
902 value
= buf_get_u32(reg
->value
, 0, 32);
903 output_len
+= snprintf(output
+ output_len
,
904 sizeof(output
) - output_len
,
905 "%8s: %8.8" PRIx32
" ",
908 command_print(CMD
, "%s", output
);
915 COMMAND_HANDLER(handle_armv4_5_core_state_command
)
917 struct target
*target
= get_current_target(CMD_CTX
);
918 struct arm
*arm
= target_to_arm(target
);
921 command_print(CMD
, "current target isn't an ARM");
925 if (arm
->core_type
== ARM_CORE_TYPE_M_PROFILE
) {
926 /* armv7m not supported */
927 command_print(CMD
, "Unsupported Command");
932 if (strcmp(CMD_ARGV
[0], "arm") == 0)
933 arm
->core_state
= ARM_STATE_ARM
;
934 if (strcmp(CMD_ARGV
[0], "thumb") == 0)
935 arm
->core_state
= ARM_STATE_THUMB
;
938 command_print(CMD
, "core state: %s", arm_state_strings
[arm
->core_state
]);
943 COMMAND_HANDLER(handle_arm_disassemble_command
)
945 int retval
= ERROR_OK
;
946 struct target
*target
= get_current_target(CMD_CTX
);
948 if (target
== NULL
) {
949 LOG_ERROR("No target selected");
953 struct arm
*arm
= target_to_arm(target
);
954 target_addr_t address
;
959 command_print(CMD
, "current target isn't an ARM");
963 if (arm
->core_type
== ARM_CORE_TYPE_M_PROFILE
) {
964 /* armv7m is always thumb mode */
970 if (strcmp(CMD_ARGV
[2], "thumb") != 0)
975 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[1], count
);
978 COMMAND_PARSE_ADDRESS(CMD_ARGV
[0], address
);
979 if (address
& 0x01) {
981 command_print(CMD
, "Disassemble as Thumb");
990 retval
= ERROR_COMMAND_SYNTAX_ERROR
;
993 while (count
-- > 0) {
994 struct arm_instruction cur_instruction
;
997 /* Always use Thumb2 disassembly for best handling
998 * of 32-bit BL/BLX, and to work with newer cores
999 * (some ARMv6, all ARMv7) that use Thumb2.
1001 retval
= thumb2_opcode(target
, address
,
1003 if (retval
!= ERROR_OK
)
1008 retval
= target_read_u32(target
, address
, &opcode
);
1009 if (retval
!= ERROR_OK
)
1011 retval
= arm_evaluate_opcode(opcode
, address
,
1012 &cur_instruction
) != ERROR_OK
;
1013 if (retval
!= ERROR_OK
)
1016 command_print(CMD
, "%s", cur_instruction
.text
);
1017 address
+= cur_instruction
.instruction_size
;
1023 static int jim_mcrmrc(Jim_Interp
*interp
, int argc
, Jim_Obj
* const *argv
)
1025 struct command_context
*context
;
1026 struct target
*target
;
1030 context
= current_command_context(interp
);
1031 assert(context
!= NULL
);
1033 target
= get_current_target(context
);
1034 if (target
== NULL
) {
1035 LOG_ERROR("%s: no current target", __func__
);
1038 if (!target_was_examined(target
)) {
1039 LOG_ERROR("%s: not yet examined", target_name(target
));
1042 arm
= target_to_arm(target
);
1044 LOG_ERROR("%s: not an ARM", target_name(target
));
1048 if ((argc
< 6) || (argc
> 7)) {
1049 /* FIXME use the command name to verify # params... */
1050 LOG_ERROR("%s: wrong number of arguments", __func__
);
1062 /* NOTE: parameter sequence matches ARM instruction set usage:
1063 * MCR pNUM, op1, rX, CRn, CRm, op2 ; write CP from rX
1064 * MRC pNUM, op1, rX, CRn, CRm, op2 ; read CP into rX
1065 * The "rX" is necessarily omitted; it uses Tcl mechanisms.
1067 retval
= Jim_GetLong(interp
, argv
[1], &l
);
1068 if (retval
!= JIM_OK
)
1071 LOG_ERROR("%s: %s %d out of range", __func__
,
1072 "coprocessor", (int) l
);
1077 retval
= Jim_GetLong(interp
, argv
[2], &l
);
1078 if (retval
!= JIM_OK
)
1081 LOG_ERROR("%s: %s %d out of range", __func__
,
1087 retval
= Jim_GetLong(interp
, argv
[3], &l
);
1088 if (retval
!= JIM_OK
)
1091 LOG_ERROR("%s: %s %d out of range", __func__
,
1097 retval
= Jim_GetLong(interp
, argv
[4], &l
);
1098 if (retval
!= JIM_OK
)
1101 LOG_ERROR("%s: %s %d out of range", __func__
,
1107 retval
= Jim_GetLong(interp
, argv
[5], &l
);
1108 if (retval
!= JIM_OK
)
1111 LOG_ERROR("%s: %s %d out of range", __func__
,
1119 /* FIXME don't assume "mrc" vs "mcr" from the number of params;
1120 * that could easily be a typo! Check both...
1122 * FIXME change the call syntax here ... simplest to just pass
1123 * the MRC() or MCR() instruction to be executed. That will also
1124 * let us support the "mrc2" and "mcr2" opcodes (toggling one bit)
1125 * if that's ever needed.
1128 retval
= Jim_GetLong(interp
, argv
[6], &l
);
1129 if (retval
!= JIM_OK
)
1133 /* NOTE: parameters reordered! */
1134 /* ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2) */
1135 retval
= arm
->mcr(target
, cpnum
, op1
, op2
, CRn
, CRm
, value
);
1136 if (retval
!= ERROR_OK
)
1139 /* NOTE: parameters reordered! */
1140 /* ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2) */
1141 retval
= arm
->mrc(target
, cpnum
, op1
, op2
, CRn
, CRm
, &value
);
1142 if (retval
!= ERROR_OK
)
1145 Jim_SetResult(interp
, Jim_NewIntObj(interp
, value
));
1151 extern const struct command_registration semihosting_common_handlers
[];
1153 static const struct command_registration arm_exec_command_handlers
[] = {
1156 .handler
= handle_armv4_5_reg_command
,
1157 .mode
= COMMAND_EXEC
,
1158 .help
= "display ARM core registers",
1162 .name
= "core_state",
1163 .handler
= handle_armv4_5_core_state_command
,
1164 .mode
= COMMAND_EXEC
,
1165 .usage
= "['arm'|'thumb']",
1166 .help
= "display/change ARM core state",
1169 .name
= "disassemble",
1170 .handler
= handle_arm_disassemble_command
,
1171 .mode
= COMMAND_EXEC
,
1172 .usage
= "address [count ['thumb']]",
1173 .help
= "disassemble instructions ",
1177 .mode
= COMMAND_EXEC
,
1178 .jim_handler
= &jim_mcrmrc
,
1179 .help
= "write coprocessor register",
1180 .usage
= "cpnum op1 CRn CRm op2 value",
1184 .mode
= COMMAND_EXEC
,
1185 .jim_handler
= &jim_mcrmrc
,
1186 .help
= "read coprocessor register",
1187 .usage
= "cpnum op1 CRn CRm op2",
1190 .chain
= semihosting_common_handlers
,
1192 COMMAND_REGISTRATION_DONE
1194 const struct command_registration arm_command_handlers
[] = {
1197 .mode
= COMMAND_ANY
,
1198 .help
= "ARM command group",
1200 .chain
= arm_exec_command_handlers
,
1202 COMMAND_REGISTRATION_DONE
1206 * gdb for arm targets (e.g. arm-none-eabi-gdb) supports several variants
1207 * of arm architecture. You can list them using the autocompletion of gdb
1208 * command prompt by typing "set architecture " and then press TAB key.
1209 * The default, selected automatically, is "arm".
1210 * Let's use the default value, here, to make gdb-multiarch behave in the
1211 * same way as a gdb for arm. This can be changed later on. User can still
1212 * set the specific architecture variant with the gdb command.
1214 const char *arm_get_gdb_arch(struct target
*target
)
1219 int arm_get_gdb_reg_list(struct target
*target
,
1220 struct reg
**reg_list
[], int *reg_list_size
,
1221 enum target_register_class reg_class
)
1223 struct arm
*arm
= target_to_arm(target
);
1226 if (!is_arm_mode(arm
->core_mode
)) {
1227 LOG_ERROR("not a valid arm core mode - communication failure?");
1231 switch (reg_class
) {
1232 case REG_CLASS_GENERAL
:
1233 *reg_list_size
= 26;
1234 *reg_list
= malloc(sizeof(struct reg
*) * (*reg_list_size
));
1236 for (i
= 0; i
< 16; i
++)
1237 (*reg_list
)[i
] = arm_reg_current(arm
, i
);
1239 /* For GDB compatibility, take FPA registers size into account and zero-fill it*/
1240 for (i
= 16; i
< 24; i
++)
1241 (*reg_list
)[i
] = &arm_gdb_dummy_fp_reg
;
1242 (*reg_list
)[24] = &arm_gdb_dummy_fps_reg
;
1244 (*reg_list
)[25] = arm
->cpsr
;
1249 switch (arm
->core_type
) {
1250 case ARM_CORE_TYPE_SEC_EXT
:
1251 *reg_list_size
= 51;
1253 case ARM_CORE_TYPE_VIRT_EXT
:
1254 *reg_list_size
= 53;
1257 *reg_list_size
= 48;
1259 unsigned int list_size_core
= *reg_list_size
;
1260 if (arm
->arm_vfp_version
== ARM_VFP_V3
)
1261 *reg_list_size
+= 33;
1263 *reg_list
= malloc(sizeof(struct reg
*) * (*reg_list_size
));
1265 for (i
= 0; i
< 16; i
++)
1266 (*reg_list
)[i
] = arm_reg_current(arm
, i
);
1268 for (i
= 13; i
< ARRAY_SIZE(arm_core_regs
); i
++) {
1269 int reg_index
= arm
->core_cache
->reg_list
[i
].number
;
1271 if (arm_core_regs
[i
].mode
== ARM_MODE_MON
1272 && arm
->core_type
!= ARM_CORE_TYPE_SEC_EXT
1273 && arm
->core_type
!= ARM_CORE_TYPE_VIRT_EXT
)
1275 if (arm_core_regs
[i
].mode
== ARM_MODE_HYP
1276 && arm
->core_type
!= ARM_CORE_TYPE_VIRT_EXT
)
1278 (*reg_list
)[reg_index
] = &(arm
->core_cache
->reg_list
[i
]);
1281 /* When we supply the target description, there is no need for fake FPA */
1282 for (i
= 16; i
< 24; i
++) {
1283 (*reg_list
)[i
] = &arm_gdb_dummy_fp_reg
;
1284 (*reg_list
)[i
]->size
= 0;
1286 (*reg_list
)[24] = &arm_gdb_dummy_fps_reg
;
1287 (*reg_list
)[24]->size
= 0;
1289 if (arm
->arm_vfp_version
== ARM_VFP_V3
) {
1290 unsigned int num_core_regs
= ARRAY_SIZE(arm_core_regs
);
1291 for (i
= 0; i
< 33; i
++)
1292 (*reg_list
)[list_size_core
+ i
] = &(arm
->core_cache
->reg_list
[num_core_regs
+ i
]);
1298 LOG_ERROR("not a valid register class type in query.");
1303 /* wait for execution to complete and check exit point */
1304 static int armv4_5_run_algorithm_completion(struct target
*target
,
1305 uint32_t exit_point
,
1310 struct arm
*arm
= target_to_arm(target
);
1312 retval
= target_wait_state(target
, TARGET_HALTED
, timeout_ms
);
1313 if (retval
!= ERROR_OK
)
1315 if (target
->state
!= TARGET_HALTED
) {
1316 retval
= target_halt(target
);
1317 if (retval
!= ERROR_OK
)
1319 retval
= target_wait_state(target
, TARGET_HALTED
, 500);
1320 if (retval
!= ERROR_OK
)
1322 return ERROR_TARGET_TIMEOUT
;
1325 /* fast exit: ARMv5+ code can use BKPT */
1326 if (exit_point
&& buf_get_u32(arm
->pc
->value
, 0, 32) != exit_point
) {
1328 "target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32
"",
1329 buf_get_u32(arm
->pc
->value
, 0, 32));
1330 return ERROR_TARGET_TIMEOUT
;
1336 int armv4_5_run_algorithm_inner(struct target
*target
,
1337 int num_mem_params
, struct mem_param
*mem_params
,
1338 int num_reg_params
, struct reg_param
*reg_params
,
1339 uint32_t entry_point
, uint32_t exit_point
,
1340 int timeout_ms
, void *arch_info
,
1341 int (*run_it
)(struct target
*target
, uint32_t exit_point
,
1342 int timeout_ms
, void *arch_info
))
1344 struct arm
*arm
= target_to_arm(target
);
1345 struct arm_algorithm
*arm_algorithm_info
= arch_info
;
1346 enum arm_state core_state
= arm
->core_state
;
1347 uint32_t context
[17];
1349 int exit_breakpoint_size
= 0;
1351 int retval
= ERROR_OK
;
1353 LOG_DEBUG("Running algorithm");
1355 if (arm_algorithm_info
->common_magic
!= ARM_COMMON_MAGIC
) {
1356 LOG_ERROR("current target isn't an ARMV4/5 target");
1357 return ERROR_TARGET_INVALID
;
1360 if (target
->state
!= TARGET_HALTED
) {
1361 LOG_WARNING("target not halted");
1362 return ERROR_TARGET_NOT_HALTED
;
1365 if (!is_arm_mode(arm
->core_mode
)) {
1366 LOG_ERROR("not a valid arm core mode - communication failure?");
1370 /* armv5 and later can terminate with BKPT instruction; less overhead */
1371 if (!exit_point
&& arm
->is_armv4
) {
1372 LOG_ERROR("ARMv4 target needs HW breakpoint location");
1376 /* save r0..pc, cpsr-or-spsr, and then cpsr-for-sure;
1377 * they'll be restored later.
1379 for (i
= 0; i
<= 16; i
++) {
1382 r
= &ARMV4_5_CORE_REG_MODE(arm
->core_cache
,
1383 arm_algorithm_info
->core_mode
, i
);
1385 arm
->read_core_reg(target
, r
, i
,
1386 arm_algorithm_info
->core_mode
);
1387 context
[i
] = buf_get_u32(r
->value
, 0, 32);
1389 cpsr
= buf_get_u32(arm
->cpsr
->value
, 0, 32);
1391 for (i
= 0; i
< num_mem_params
; i
++) {
1392 if (mem_params
[i
].direction
== PARAM_IN
)
1394 retval
= target_write_buffer(target
, mem_params
[i
].address
, mem_params
[i
].size
,
1395 mem_params
[i
].value
);
1396 if (retval
!= ERROR_OK
)
1400 for (i
= 0; i
< num_reg_params
; i
++) {
1401 if (reg_params
[i
].direction
== PARAM_IN
)
1404 struct reg
*reg
= register_get_by_name(arm
->core_cache
, reg_params
[i
].reg_name
, 0);
1406 LOG_ERROR("BUG: register '%s' not found", reg_params
[i
].reg_name
);
1407 return ERROR_COMMAND_SYNTAX_ERROR
;
1410 if (reg
->size
!= reg_params
[i
].size
) {
1411 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size",
1412 reg_params
[i
].reg_name
);
1413 return ERROR_COMMAND_SYNTAX_ERROR
;
1416 retval
= armv4_5_set_core_reg(reg
, reg_params
[i
].value
);
1417 if (retval
!= ERROR_OK
)
1421 arm
->core_state
= arm_algorithm_info
->core_state
;
1422 if (arm
->core_state
== ARM_STATE_ARM
)
1423 exit_breakpoint_size
= 4;
1424 else if (arm
->core_state
== ARM_STATE_THUMB
)
1425 exit_breakpoint_size
= 2;
1427 LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
1428 return ERROR_COMMAND_SYNTAX_ERROR
;
1431 if (arm_algorithm_info
->core_mode
!= ARM_MODE_ANY
) {
1432 LOG_DEBUG("setting core_mode: 0x%2.2x",
1433 arm_algorithm_info
->core_mode
);
1434 buf_set_u32(arm
->cpsr
->value
, 0, 5,
1435 arm_algorithm_info
->core_mode
);
1436 arm
->cpsr
->dirty
= true;
1437 arm
->cpsr
->valid
= true;
1440 /* terminate using a hardware or (ARMv5+) software breakpoint */
1442 retval
= breakpoint_add(target
, exit_point
,
1443 exit_breakpoint_size
, BKPT_HARD
);
1444 if (retval
!= ERROR_OK
) {
1445 LOG_ERROR("can't add HW breakpoint to terminate algorithm");
1446 return ERROR_TARGET_FAILURE
;
1450 retval
= target_resume(target
, 0, entry_point
, 1, 1);
1451 if (retval
!= ERROR_OK
)
1453 retval
= run_it(target
, exit_point
, timeout_ms
, arch_info
);
1456 breakpoint_remove(target
, exit_point
);
1458 if (retval
!= ERROR_OK
)
1461 for (i
= 0; i
< num_mem_params
; i
++) {
1462 if (mem_params
[i
].direction
!= PARAM_OUT
) {
1463 int retvaltemp
= target_read_buffer(target
, mem_params
[i
].address
,
1465 mem_params
[i
].value
);
1466 if (retvaltemp
!= ERROR_OK
)
1467 retval
= retvaltemp
;
1471 for (i
= 0; i
< num_reg_params
; i
++) {
1472 if (reg_params
[i
].direction
!= PARAM_OUT
) {
1474 struct reg
*reg
= register_get_by_name(arm
->core_cache
,
1475 reg_params
[i
].reg_name
,
1478 LOG_ERROR("BUG: register '%s' not found", reg_params
[i
].reg_name
);
1479 retval
= ERROR_COMMAND_SYNTAX_ERROR
;
1483 if (reg
->size
!= reg_params
[i
].size
) {
1485 "BUG: register '%s' size doesn't match reg_params[i].size",
1486 reg_params
[i
].reg_name
);
1487 retval
= ERROR_COMMAND_SYNTAX_ERROR
;
1491 buf_set_u32(reg_params
[i
].value
, 0, 32, buf_get_u32(reg
->value
, 0, 32));
1495 /* restore everything we saved before (17 or 18 registers) */
1496 for (i
= 0; i
<= 16; i
++) {
1498 regvalue
= buf_get_u32(ARMV4_5_CORE_REG_MODE(arm
->core_cache
,
1499 arm_algorithm_info
->core_mode
, i
).value
, 0, 32);
1500 if (regvalue
!= context
[i
]) {
1501 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32
"",
1502 ARMV4_5_CORE_REG_MODE(arm
->core_cache
,
1503 arm_algorithm_info
->core_mode
, i
).name
, context
[i
]);
1504 buf_set_u32(ARMV4_5_CORE_REG_MODE(arm
->core_cache
,
1505 arm_algorithm_info
->core_mode
, i
).value
, 0, 32, context
[i
]);
1506 ARMV4_5_CORE_REG_MODE(arm
->core_cache
, arm_algorithm_info
->core_mode
,
1508 ARMV4_5_CORE_REG_MODE(arm
->core_cache
, arm_algorithm_info
->core_mode
,
1513 arm_set_cpsr(arm
, cpsr
);
1514 arm
->cpsr
->dirty
= true;
1516 arm
->core_state
= core_state
;
1521 int armv4_5_run_algorithm(struct target
*target
,
1523 struct mem_param
*mem_params
,
1525 struct reg_param
*reg_params
,
1526 target_addr_t entry_point
,
1527 target_addr_t exit_point
,
1531 return armv4_5_run_algorithm_inner(target
,
1536 (uint32_t)entry_point
,
1537 (uint32_t)exit_point
,
1540 armv4_5_run_algorithm_completion
);
1544 * Runs ARM code in the target to calculate a CRC32 checksum.
1547 int arm_checksum_memory(struct target
*target
,
1548 target_addr_t address
, uint32_t count
, uint32_t *checksum
)
1550 struct working_area
*crc_algorithm
;
1551 struct arm_algorithm arm_algo
;
1552 struct arm
*arm
= target_to_arm(target
);
1553 struct reg_param reg_params
[2];
1556 uint32_t exit_var
= 0;
1558 static const uint8_t arm_crc_code_le
[] = {
1559 #include "../../contrib/loaders/checksum/armv4_5_crc.inc"
1562 assert(sizeof(arm_crc_code_le
) % 4 == 0);
1564 retval
= target_alloc_working_area(target
,
1565 sizeof(arm_crc_code_le
), &crc_algorithm
);
1566 if (retval
!= ERROR_OK
)
1569 /* convert code into a buffer in target endianness */
1570 for (i
= 0; i
< ARRAY_SIZE(arm_crc_code_le
) / 4; i
++) {
1571 retval
= target_write_u32(target
,
1572 crc_algorithm
->address
+ i
* sizeof(uint32_t),
1573 le_to_h_u32(&arm_crc_code_le
[i
* 4]));
1574 if (retval
!= ERROR_OK
)
1578 arm_algo
.common_magic
= ARM_COMMON_MAGIC
;
1579 arm_algo
.core_mode
= ARM_MODE_SVC
;
1580 arm_algo
.core_state
= ARM_STATE_ARM
;
1582 init_reg_param(®_params
[0], "r0", 32, PARAM_IN_OUT
);
1583 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
1585 buf_set_u32(reg_params
[0].value
, 0, 32, address
);
1586 buf_set_u32(reg_params
[1].value
, 0, 32, count
);
1588 /* 20 second timeout/megabyte */
1589 int timeout
= 20000 * (1 + (count
/ (1024 * 1024)));
1591 /* armv4 must exit using a hardware breakpoint */
1593 exit_var
= crc_algorithm
->address
+ sizeof(arm_crc_code_le
) - 8;
1595 retval
= target_run_algorithm(target
, 0, NULL
, 2, reg_params
,
1596 crc_algorithm
->address
,
1598 timeout
, &arm_algo
);
1600 if (retval
== ERROR_OK
)
1601 *checksum
= buf_get_u32(reg_params
[0].value
, 0, 32);
1603 LOG_ERROR("error executing ARM crc algorithm");
1605 destroy_reg_param(®_params
[0]);
1606 destroy_reg_param(®_params
[1]);
1609 target_free_working_area(target
, crc_algorithm
);
1615 * Runs ARM code in the target to check whether a memory block holds
1616 * all ones. NOR flash which has been erased, and thus may be written,
1620 int arm_blank_check_memory(struct target
*target
,
1621 struct target_memory_check_block
*blocks
, int num_blocks
, uint8_t erased_value
)
1623 struct working_area
*check_algorithm
;
1624 struct reg_param reg_params
[3];
1625 struct arm_algorithm arm_algo
;
1626 struct arm
*arm
= target_to_arm(target
);
1629 uint32_t exit_var
= 0;
1631 static const uint8_t check_code_le
[] = {
1632 #include "../../contrib/loaders/erase_check/armv4_5_erase_check.inc"
1635 assert(sizeof(check_code_le
) % 4 == 0);
1637 if (erased_value
!= 0xff) {
1638 LOG_ERROR("Erase value 0x%02" PRIx8
" not yet supported for ARMv4/v5 targets",
1643 /* make sure we have a working area */
1644 retval
= target_alloc_working_area(target
,
1645 sizeof(check_code_le
), &check_algorithm
);
1646 if (retval
!= ERROR_OK
)
1649 /* convert code into a buffer in target endianness */
1650 for (i
= 0; i
< ARRAY_SIZE(check_code_le
) / 4; i
++) {
1651 retval
= target_write_u32(target
,
1652 check_algorithm
->address
1653 + i
* sizeof(uint32_t),
1654 le_to_h_u32(&check_code_le
[i
* 4]));
1655 if (retval
!= ERROR_OK
)
1659 arm_algo
.common_magic
= ARM_COMMON_MAGIC
;
1660 arm_algo
.core_mode
= ARM_MODE_SVC
;
1661 arm_algo
.core_state
= ARM_STATE_ARM
;
1663 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
1664 buf_set_u32(reg_params
[0].value
, 0, 32, blocks
[0].address
);
1666 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
1667 buf_set_u32(reg_params
[1].value
, 0, 32, blocks
[0].size
);
1669 init_reg_param(®_params
[2], "r2", 32, PARAM_IN_OUT
);
1670 buf_set_u32(reg_params
[2].value
, 0, 32, erased_value
);
1672 /* armv4 must exit using a hardware breakpoint */
1674 exit_var
= check_algorithm
->address
+ sizeof(check_code_le
) - 4;
1676 retval
= target_run_algorithm(target
, 0, NULL
, 3, reg_params
,
1677 check_algorithm
->address
,
1681 if (retval
== ERROR_OK
)
1682 blocks
[0].result
= buf_get_u32(reg_params
[2].value
, 0, 32);
1684 destroy_reg_param(®_params
[0]);
1685 destroy_reg_param(®_params
[1]);
1686 destroy_reg_param(®_params
[2]);
1689 target_free_working_area(target
, check_algorithm
);
1691 if (retval
!= ERROR_OK
)
1694 return 1; /* only one block has been checked */
1697 static int arm_full_context(struct target
*target
)
1699 struct arm
*arm
= target_to_arm(target
);
1700 unsigned num_regs
= arm
->core_cache
->num_regs
;
1701 struct reg
*reg
= arm
->core_cache
->reg_list
;
1702 int retval
= ERROR_OK
;
1704 for (; num_regs
&& retval
== ERROR_OK
; num_regs
--, reg
++) {
1707 retval
= armv4_5_get_core_reg(reg
);
1712 static int arm_default_mrc(struct target
*target
, int cpnum
,
1713 uint32_t op1
, uint32_t op2
,
1714 uint32_t CRn
, uint32_t CRm
,
1717 LOG_ERROR("%s doesn't implement MRC", target_type_name(target
));
1721 static int arm_default_mcr(struct target
*target
, int cpnum
,
1722 uint32_t op1
, uint32_t op2
,
1723 uint32_t CRn
, uint32_t CRm
,
1726 LOG_ERROR("%s doesn't implement MCR", target_type_name(target
));
1730 int arm_init_arch_info(struct target
*target
, struct arm
*arm
)
1732 target
->arch_info
= arm
;
1733 arm
->target
= target
;
1735 arm
->common_magic
= ARM_COMMON_MAGIC
;
1737 /* core_type may be overridden by subtype logic */
1738 if (arm
->core_type
!= ARM_CORE_TYPE_M_PROFILE
) {
1739 arm
->core_type
= ARM_CORE_TYPE_STD
;
1740 arm_set_cpsr(arm
, ARM_MODE_USR
);
1743 /* default full_context() has no core-specific optimizations */
1744 if (!arm
->full_context
&& arm
->read_core_reg
)
1745 arm
->full_context
= arm_full_context
;
1748 arm
->mrc
= arm_default_mrc
;
1750 arm
->mcr
= arm_default_mcr
;
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