2 * Copyright (C) 2009 by David Brownell
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
24 #include <jtag/jtag.h>
26 #include "breakpoints.h"
27 #include "target_type.h"
28 #include "arm_opcodes.h"
33 * Implements various ARM DPM operations using architectural debug registers.
34 * These routines layer over core-specific communication methods to cope with
35 * implementation differences between cores like ARM1136 and Cortex-A8.
37 * The "Debug Programmers' Model" (DPM) for ARMv6 and ARMv7 is defined by
38 * Part C (Debug Architecture) of the ARM Architecture Reference Manual,
39 * ARMv7-A and ARMv7-R edition (ARM DDI 0406B). In OpenOCD, DPM operations
40 * are abstracted through internal programming interfaces to share code and
41 * to minimize needless differences in debug behavior between cores.
44 /*----------------------------------------------------------------------*/
50 /* Read coprocessor */
51 static int dpm_mrc(struct target
*target
, int cpnum
,
52 uint32_t op1
, uint32_t op2
, uint32_t CRn
, uint32_t CRm
,
55 struct arm
*arm
= target_to_arm(target
);
56 struct arm_dpm
*dpm
= arm
->dpm
;
59 retval
= dpm
->prepare(dpm
);
60 if (retval
!= ERROR_OK
)
63 LOG_DEBUG("MRC p%d, %d, r0, c%d, c%d, %d", cpnum
,
65 (int) CRm
, (int) op2
);
67 /* read coprocessor register into R0; return via DCC */
68 retval
= dpm
->instr_read_data_r0(dpm
,
69 ARMV4_5_MRC(cpnum
, op1
, 0, CRn
, CRm
, op2
),
72 /* (void) */ dpm
->finish(dpm
);
76 static int dpm_mcr(struct target
*target
, int cpnum
,
77 uint32_t op1
, uint32_t op2
, uint32_t CRn
, uint32_t CRm
,
80 struct arm
*arm
= target_to_arm(target
);
81 struct arm_dpm
*dpm
= arm
->dpm
;
84 retval
= dpm
->prepare(dpm
);
85 if (retval
!= ERROR_OK
)
88 LOG_DEBUG("MCR p%d, %d, r0, c%d, c%d, %d", cpnum
,
90 (int) CRm
, (int) op2
);
92 /* read DCC into r0; then write coprocessor register from R0 */
93 retval
= dpm
->instr_write_data_r0(dpm
,
94 ARMV4_5_MCR(cpnum
, op1
, 0, CRn
, CRm
, op2
),
97 /* (void) */ dpm
->finish(dpm
);
101 /*----------------------------------------------------------------------*/
104 * Register access utilities
107 /* Toggles between recorded core mode (USR, SVC, etc) and a temporary one.
108 * Routines *must* restore the original mode before returning!!
110 int dpm_modeswitch(struct arm_dpm
*dpm
, enum arm_mode mode
)
115 /* restore previous mode */
116 if (mode
== ARM_MODE_ANY
)
117 cpsr
= buf_get_u32(dpm
->arm
->cpsr
->value
, 0, 32);
119 /* else force to the specified mode */
123 retval
= dpm
->instr_write_data_r0(dpm
, ARMV4_5_MSR_GP(0, 0xf, 0), cpsr
);
124 if (retval
!= ERROR_OK
)
127 if (dpm
->instr_cpsr_sync
)
128 retval
= dpm
->instr_cpsr_sync(dpm
);
133 /* just read the register -- rely on the core mode being right */
134 static int dpm_read_reg(struct arm_dpm
*dpm
, struct reg
*r
, unsigned regnum
)
141 /* return via DCC: "MCR p14, 0, Rnum, c0, c5, 0" */
142 retval
= dpm
->instr_read_data_dcc(dpm
,
143 ARMV4_5_MCR(14, 0, regnum
, 0, 5, 0),
147 * "MOV r0, pc"; then return via DCC */
148 retval
= dpm
->instr_read_data_r0(dpm
, 0xe1a0000f, &value
);
150 /* NOTE: this seems like a slightly awkward place to update
151 * this value ... but if the PC gets written (the only way
152 * to change what we compute), the arch spec says subsequent
153 * reads return values which are "unpredictable". So this
154 * is always right except in those broken-by-intent cases.
156 switch (dpm
->arm
->core_state
) {
160 case ARM_STATE_THUMB
:
161 case ARM_STATE_THUMB_EE
:
164 case ARM_STATE_JAZELLE
:
165 /* core-specific ... ? */
166 LOG_WARNING("Jazelle PC adjustment unknown");
168 case ARM_STATE_AARCH64
:
169 LOG_ERROR("AARCH64: 32bit read requested");
174 /* 16: "MRS r0, CPSR"; then return via DCC
175 * 17: "MRS r0, SPSR"; then return via DCC
177 retval
= dpm
->instr_read_data_r0(dpm
,
178 ARMV4_5_MRS(0, regnum
& 1),
183 if (retval
== ERROR_OK
) {
184 buf_set_u32(r
->value
, 0, 32, value
);
187 LOG_DEBUG("READ: %s, %8.8x", r
->name
, (unsigned) value
);
193 /* just write the register -- rely on the core mode being right */
194 static int dpm_write_reg(struct arm_dpm
*dpm
, struct reg
*r
, unsigned regnum
)
197 uint32_t value
= buf_get_u32(r
->value
, 0, 32);
201 /* load register from DCC: "MRC p14, 0, Rnum, c0, c5, 0" */
202 retval
= dpm
->instr_write_data_dcc(dpm
,
203 ARMV4_5_MRC(14, 0, regnum
, 0, 5, 0),
207 * read r0 from DCC; then "MOV pc, r0" */
208 retval
= dpm
->instr_write_data_r0(dpm
, 0xe1a0f000, value
);
211 /* 16: read r0 from DCC, then "MSR r0, CPSR_cxsf"
212 * 17: read r0 from DCC, then "MSR r0, SPSR_cxsf"
214 retval
= dpm
->instr_write_data_r0(dpm
,
215 ARMV4_5_MSR_GP(0, 0xf, regnum
& 1),
217 if (retval
!= ERROR_OK
)
220 if (regnum
== 16 && dpm
->instr_cpsr_sync
)
221 retval
= dpm
->instr_cpsr_sync(dpm
);
226 if (retval
== ERROR_OK
) {
228 LOG_DEBUG("WRITE: %s, %8.8x", r
->name
, (unsigned) value
);
235 * Write to program counter and switch the core state (arm/thumb) according to
238 static int dpm_write_pc_core_state(struct arm_dpm
*dpm
, struct reg
*r
)
240 uint32_t value
= buf_get_u32(r
->value
, 0, 32);
242 /* read r0 from DCC; then "BX r0" */
243 return dpm
->instr_write_data_r0(dpm
, ARMV4_5_BX(0), value
);
247 * Read basic registers of the the current context: R0 to R15, and CPSR;
248 * sets the core mode (such as USR or IRQ) and state (such as ARM or Thumb).
249 * In normal operation this is called on entry to halting debug state,
250 * possibly after some other operations supporting restore of debug state
251 * or making sure the CPU is fully idle (drain write buffer, etc).
253 int arm_dpm_read_current_registers(struct arm_dpm
*dpm
)
255 struct arm
*arm
= dpm
->arm
;
260 retval
= dpm
->prepare(dpm
);
261 if (retval
!= ERROR_OK
)
264 /* read R0 first (it's used for scratch), then CPSR */
265 r
= arm
->core_cache
->reg_list
+ 0;
267 retval
= dpm_read_reg(dpm
, r
, 0);
268 if (retval
!= ERROR_OK
)
273 retval
= dpm
->instr_read_data_r0(dpm
, ARMV4_5_MRS(0, 0), &cpsr
);
274 if (retval
!= ERROR_OK
)
277 /* update core mode and state, plus shadow mapping for R8..R14 */
278 arm_set_cpsr(arm
, cpsr
);
280 /* REVISIT we can probably avoid reading R1..R14, saving time... */
281 for (unsigned i
= 1; i
< 16; i
++) {
282 r
= arm_reg_current(arm
, i
);
286 retval
= dpm_read_reg(dpm
, r
, i
);
287 if (retval
!= ERROR_OK
)
291 /* NOTE: SPSR ignored (if it's even relevant). */
293 /* REVISIT the debugger can trigger various exceptions. See the
294 * ARMv7A architecture spec, section C5.7, for more info about
295 * what defenses are needed; v6 debug has the most issues.
299 /* (void) */ dpm
->finish(dpm
);
303 /* Avoid needless I/O ... leave breakpoints and watchpoints alone
304 * unless they're removed, or need updating because of single-stepping
305 * or running debugger code.
307 static int dpm_maybe_update_bpwp(struct arm_dpm
*dpm
, bool bpwp
,
308 struct dpm_bpwp
*xp
, int *set_p
)
310 int retval
= ERROR_OK
;
317 /* removed or startup; we must disable it */
322 /* disabled, but we must set it */
323 xp
->dirty
= disable
= false;
328 /* set, but we must temporarily disable it */
329 xp
->dirty
= disable
= true;
334 retval
= dpm
->bpwp_disable(dpm
, xp
->number
);
336 retval
= dpm
->bpwp_enable(dpm
, xp
->number
,
337 xp
->address
, xp
->control
);
339 if (retval
!= ERROR_OK
)
340 LOG_ERROR("%s: can't %s HW %spoint %d",
341 disable
? "disable" : "enable",
342 target_name(dpm
->arm
->target
),
343 (xp
->number
< 16) ? "break" : "watch",
349 static int dpm_add_breakpoint(struct target
*target
, struct breakpoint
*bp
);
352 * Writes all modified core registers for all processor modes. In normal
353 * operation this is called on exit from halting debug state.
355 * @param dpm: represents the processor
356 * @param bpwp: true ensures breakpoints and watchpoints are set,
357 * false ensures they are cleared
359 int arm_dpm_write_dirty_registers(struct arm_dpm
*dpm
, bool bpwp
)
361 struct arm
*arm
= dpm
->arm
;
362 struct reg_cache
*cache
= arm
->core_cache
;
366 retval
= dpm
->prepare(dpm
);
367 if (retval
!= ERROR_OK
)
370 /* If we're managing hardware breakpoints for this core, enable
371 * or disable them as requested.
373 * REVISIT We don't yet manage them for ANY cores. Eventually
374 * we should be able to assume we handle them; but until then,
375 * cope with the hand-crafted breakpoint code.
377 if (arm
->target
->type
->add_breakpoint
== dpm_add_breakpoint
) {
378 for (unsigned i
= 0; i
< dpm
->nbp
; i
++) {
379 struct dpm_bp
*dbp
= dpm
->dbp
+ i
;
380 struct breakpoint
*bp
= dbp
->bp
;
382 retval
= dpm_maybe_update_bpwp(dpm
, bpwp
, &dbp
->bpwp
,
383 bp
? &bp
->set
: NULL
);
384 if (retval
!= ERROR_OK
)
389 /* enable/disable watchpoints */
390 for (unsigned i
= 0; i
< dpm
->nwp
; i
++) {
391 struct dpm_wp
*dwp
= dpm
->dwp
+ i
;
392 struct watchpoint
*wp
= dwp
->wp
;
394 retval
= dpm_maybe_update_bpwp(dpm
, bpwp
, &dwp
->bpwp
,
395 wp
? &wp
->set
: NULL
);
396 if (retval
!= ERROR_OK
)
400 /* NOTE: writes to breakpoint and watchpoint registers might
401 * be queued, and need (efficient/batched) flushing later.
404 /* Scan the registers until we find one that's both dirty and
405 * eligible for flushing. Flush that and everything else that
406 * shares the same core mode setting. Typically this won't
407 * actually find anything to do...
410 enum arm_mode mode
= ARM_MODE_ANY
;
414 /* check everything except our scratch register R0 */
415 for (unsigned i
= 1; i
< cache
->num_regs
; i
++) {
419 /* also skip PC, CPSR, and non-dirty */
422 if (arm
->cpsr
== cache
->reg_list
+ i
)
424 if (!cache
->reg_list
[i
].dirty
)
427 r
= cache
->reg_list
[i
].arch_info
;
430 /* may need to pick and set a mode */
435 mode
= tmode
= r
->mode
;
437 /* cope with special cases */
440 /* r8..r12 "anything but FIQ" case;
441 * we "know" core mode is accurate
442 * since we haven't changed it yet
444 if (arm
->core_mode
== ARM_MODE_FIQ
447 tmode
= ARM_MODE_USR
;
455 /* REVISIT error checks */
456 if (tmode
!= ARM_MODE_ANY
) {
457 retval
= dpm_modeswitch(dpm
, tmode
);
458 if (retval
!= ERROR_OK
)
465 retval
= dpm_write_reg(dpm
,
468 if (retval
!= ERROR_OK
)
474 /* Restore original CPSR ... assuming either that we changed it,
475 * or it's dirty. Must write PC to ensure the return address is
476 * defined, and must not write it before CPSR.
478 retval
= dpm_modeswitch(dpm
, ARM_MODE_ANY
);
479 if (retval
!= ERROR_OK
)
481 arm
->cpsr
->dirty
= false;
483 /* restore the PC, make sure to also switch the core state
484 * to whatever it was set to with "arm core_state" command.
485 * target code will have set PC to an appropriate resume address.
487 retval
= dpm_write_pc_core_state(dpm
, arm
->pc
);
488 if (retval
!= ERROR_OK
)
490 /* on Cortex-A5 (as found on NXP VF610 SoC), BX instruction
491 * executed in debug state doesn't appear to set the PC,
492 * explicitly set it with a "MOV pc, r0". This doesn't influence
493 * CPSR on Cortex-A9 so it should be OK. Maybe due to different
496 retval
= dpm_write_reg(dpm
, arm
->pc
, 15);
497 if (retval
!= ERROR_OK
)
499 arm
->pc
->dirty
= false;
501 /* flush R0 -- it's *very* dirty by now */
502 retval
= dpm_write_reg(dpm
, &cache
->reg_list
[0], 0);
503 if (retval
!= ERROR_OK
)
505 cache
->reg_list
[0].dirty
= false;
507 /* (void) */ dpm
->finish(dpm
);
512 /* Returns ARM_MODE_ANY or temporary mode to use while reading the
513 * specified register ... works around flakiness from ARM core calls.
514 * Caller already filtered out SPSR access; mode is never MODE_SYS
517 static enum arm_mode
dpm_mapmode(struct arm
*arm
,
518 unsigned num
, enum arm_mode mode
)
520 enum arm_mode amode
= arm
->core_mode
;
522 /* don't switch if the mode is already correct */
523 if (amode
== ARM_MODE_SYS
)
524 amode
= ARM_MODE_USR
;
529 /* don't switch for non-shadowed registers (r0..r7, r15/pc, cpsr) */
534 /* r8..r12 aren't shadowed for anything except FIQ */
536 if (mode
== ARM_MODE_FIQ
)
539 /* r13/sp, and r14/lr are always shadowed */
544 LOG_WARNING("invalid register #%u", num
);
552 * Standard ARM register accessors ... there are three methods
553 * in "struct arm", to support individual read/write and bulk read
557 static int arm_dpm_read_core_reg(struct target
*target
, struct reg
*r
,
558 int regnum
, enum arm_mode mode
)
560 struct arm_dpm
*dpm
= target_to_arm(target
)->dpm
;
563 if (regnum
< 0 || regnum
> 16)
564 return ERROR_COMMAND_SYNTAX_ERROR
;
567 if (mode
!= ARM_MODE_ANY
)
570 mode
= dpm_mapmode(dpm
->arm
, regnum
, mode
);
572 /* REVISIT what happens if we try to read SPSR in a core mode
573 * which has no such register?
576 retval
= dpm
->prepare(dpm
);
577 if (retval
!= ERROR_OK
)
580 if (mode
!= ARM_MODE_ANY
) {
581 retval
= dpm_modeswitch(dpm
, mode
);
582 if (retval
!= ERROR_OK
)
586 retval
= dpm_read_reg(dpm
, r
, regnum
);
587 if (retval
!= ERROR_OK
)
589 /* always clean up, regardless of error */
591 if (mode
!= ARM_MODE_ANY
)
592 /* (void) */ dpm_modeswitch(dpm
, ARM_MODE_ANY
);
595 /* (void) */ dpm
->finish(dpm
);
599 static int arm_dpm_write_core_reg(struct target
*target
, struct reg
*r
,
600 int regnum
, enum arm_mode mode
, uint8_t *value
)
602 struct arm_dpm
*dpm
= target_to_arm(target
)->dpm
;
606 if (regnum
< 0 || regnum
> 16)
607 return ERROR_COMMAND_SYNTAX_ERROR
;
610 if (mode
!= ARM_MODE_ANY
)
613 mode
= dpm_mapmode(dpm
->arm
, regnum
, mode
);
615 /* REVISIT what happens if we try to write SPSR in a core mode
616 * which has no such register?
619 retval
= dpm
->prepare(dpm
);
620 if (retval
!= ERROR_OK
)
623 if (mode
!= ARM_MODE_ANY
) {
624 retval
= dpm_modeswitch(dpm
, mode
);
625 if (retval
!= ERROR_OK
)
629 retval
= dpm_write_reg(dpm
, r
, regnum
);
630 /* always clean up, regardless of error */
632 if (mode
!= ARM_MODE_ANY
)
633 /* (void) */ dpm_modeswitch(dpm
, ARM_MODE_ANY
);
636 /* (void) */ dpm
->finish(dpm
);
640 static int arm_dpm_full_context(struct target
*target
)
642 struct arm
*arm
= target_to_arm(target
);
643 struct arm_dpm
*dpm
= arm
->dpm
;
644 struct reg_cache
*cache
= arm
->core_cache
;
648 retval
= dpm
->prepare(dpm
);
649 if (retval
!= ERROR_OK
)
653 enum arm_mode mode
= ARM_MODE_ANY
;
657 /* We "know" arm_dpm_read_current_registers() was called so
658 * the unmapped registers (R0..R7, PC, AND CPSR) and some
659 * view of R8..R14 are current. We also "know" oddities of
660 * register mapping: special cases for R8..R12 and SPSR.
662 * Pick some mode with unread registers and read them all.
665 for (unsigned i
= 0; i
< cache
->num_regs
; i
++) {
668 if (cache
->reg_list
[i
].valid
)
670 r
= cache
->reg_list
[i
].arch_info
;
672 /* may need to pick a mode and set CPSR */
677 /* For regular (ARM_MODE_ANY) R8..R12
678 * in case we've entered debug state
679 * in FIQ mode we need to patch mode.
681 if (mode
!= ARM_MODE_ANY
)
682 retval
= dpm_modeswitch(dpm
, mode
);
684 retval
= dpm_modeswitch(dpm
, ARM_MODE_USR
);
686 if (retval
!= ERROR_OK
)
692 /* CPSR was read, so "R16" must mean SPSR */
693 retval
= dpm_read_reg(dpm
,
695 (r
->num
== 16) ? 17 : r
->num
);
696 if (retval
!= ERROR_OK
)
702 retval
= dpm_modeswitch(dpm
, ARM_MODE_ANY
);
703 /* (void) */ dpm
->finish(dpm
);
709 /*----------------------------------------------------------------------*/
712 * Breakpoint and Watchpoint support.
714 * Hardware {break,watch}points are usually left active, to minimize
715 * debug entry/exit costs. When they are set or cleared, it's done in
716 * batches. Also, DPM-conformant hardware can update debug registers
717 * regardless of whether the CPU is running or halted ... though that
718 * fact isn't currently leveraged.
721 static int dpm_bpwp_setup(struct arm_dpm
*dpm
, struct dpm_bpwp
*xp
,
722 uint32_t addr
, uint32_t length
)
726 control
= (1 << 0) /* enable */
727 | (3 << 1); /* both user and privileged access */
729 /* Match 1, 2, or all 4 byte addresses in this word.
731 * FIXME: v7 hardware allows lengths up to 2 GB for BP and WP.
732 * Support larger length, when addr is suitably aligned. In
733 * particular, allow watchpoints on 8 byte "double" values.
735 * REVISIT allow watchpoints on unaligned 2-bit values; and on
736 * v7 hardware, unaligned 4-byte ones too.
740 control
|= (1 << (addr
& 3)) << 5;
743 /* require 2-byte alignment */
745 control
|= (3 << (addr
& 2)) << 5;
750 /* require 4-byte alignment */
757 LOG_ERROR("unsupported {break,watch}point length/alignment");
758 return ERROR_COMMAND_SYNTAX_ERROR
;
761 /* other shared control bits:
762 * bits 15:14 == 0 ... both secure and nonsecure states (v6.1+ only)
763 * bit 20 == 0 ... not linked to a context ID
764 * bit 28:24 == 0 ... not ignoring N LSBs (v7 only)
767 xp
->address
= addr
& ~3;
768 xp
->control
= control
;
771 LOG_DEBUG("BPWP: addr %8.8" PRIx32
", control %" PRIx32
", number %d",
772 xp
->address
, control
, xp
->number
);
774 /* hardware is updated in write_dirty_registers() */
778 static int dpm_add_breakpoint(struct target
*target
, struct breakpoint
*bp
)
780 struct arm
*arm
= target_to_arm(target
);
781 struct arm_dpm
*dpm
= arm
->dpm
;
782 int retval
= ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
785 return ERROR_COMMAND_SYNTAX_ERROR
;
786 if (!dpm
->bpwp_enable
)
789 /* FIXME we need a generic solution for software breakpoints. */
790 if (bp
->type
== BKPT_SOFT
)
791 LOG_DEBUG("using HW bkpt, not SW...");
793 for (unsigned i
= 0; i
< dpm
->nbp
; i
++) {
794 if (!dpm
->dbp
[i
].bp
) {
795 retval
= dpm_bpwp_setup(dpm
, &dpm
->dbp
[i
].bpwp
,
796 bp
->address
, bp
->length
);
797 if (retval
== ERROR_OK
)
806 static int dpm_remove_breakpoint(struct target
*target
, struct breakpoint
*bp
)
808 struct arm
*arm
= target_to_arm(target
);
809 struct arm_dpm
*dpm
= arm
->dpm
;
810 int retval
= ERROR_COMMAND_SYNTAX_ERROR
;
812 for (unsigned i
= 0; i
< dpm
->nbp
; i
++) {
813 if (dpm
->dbp
[i
].bp
== bp
) {
814 dpm
->dbp
[i
].bp
= NULL
;
815 dpm
->dbp
[i
].bpwp
.dirty
= true;
817 /* hardware is updated in write_dirty_registers() */
826 static int dpm_watchpoint_setup(struct arm_dpm
*dpm
, unsigned index_t
,
827 struct watchpoint
*wp
)
830 struct dpm_wp
*dwp
= dpm
->dwp
+ index_t
;
833 /* this hardware doesn't support data value matching or masking */
834 if (wp
->value
|| wp
->mask
!= ~(uint32_t)0) {
835 LOG_DEBUG("watchpoint values and masking not supported");
836 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
839 retval
= dpm_bpwp_setup(dpm
, &dwp
->bpwp
, wp
->address
, wp
->length
);
840 if (retval
!= ERROR_OK
)
843 control
= dwp
->bpwp
.control
;
855 dwp
->bpwp
.control
= control
;
857 dpm
->dwp
[index_t
].wp
= wp
;
862 static int dpm_add_watchpoint(struct target
*target
, struct watchpoint
*wp
)
864 struct arm
*arm
= target_to_arm(target
);
865 struct arm_dpm
*dpm
= arm
->dpm
;
866 int retval
= ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
868 if (dpm
->bpwp_enable
) {
869 for (unsigned i
= 0; i
< dpm
->nwp
; i
++) {
870 if (!dpm
->dwp
[i
].wp
) {
871 retval
= dpm_watchpoint_setup(dpm
, i
, wp
);
880 static int dpm_remove_watchpoint(struct target
*target
, struct watchpoint
*wp
)
882 struct arm
*arm
= target_to_arm(target
);
883 struct arm_dpm
*dpm
= arm
->dpm
;
884 int retval
= ERROR_COMMAND_SYNTAX_ERROR
;
886 for (unsigned i
= 0; i
< dpm
->nwp
; i
++) {
887 if (dpm
->dwp
[i
].wp
== wp
) {
888 dpm
->dwp
[i
].wp
= NULL
;
889 dpm
->dwp
[i
].bpwp
.dirty
= true;
891 /* hardware is updated in write_dirty_registers() */
900 void arm_dpm_report_wfar(struct arm_dpm
*dpm
, uint32_t addr
)
902 switch (dpm
->arm
->core_state
) {
906 case ARM_STATE_THUMB
:
907 case ARM_STATE_THUMB_EE
:
910 case ARM_STATE_JAZELLE
:
911 case ARM_STATE_AARCH64
:
918 /*----------------------------------------------------------------------*/
921 * Other debug and support utilities
924 void arm_dpm_report_dscr(struct arm_dpm
*dpm
, uint32_t dscr
)
926 struct target
*target
= dpm
->arm
->target
;
930 /* Examine debug reason */
931 switch (DSCR_ENTRY(dscr
)) {
932 case 6: /* Data abort (v6 only) */
933 case 7: /* Prefetch abort (v6 only) */
934 /* FALL THROUGH -- assume a v6 core in abort mode */
935 case 0: /* HALT request from debugger */
937 target
->debug_reason
= DBG_REASON_DBGRQ
;
939 case 1: /* HW breakpoint */
940 case 3: /* SW BKPT */
941 case 5: /* vector catch */
942 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
944 case 2: /* asynch watchpoint */
945 case 10:/* precise watchpoint */
946 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
949 target
->debug_reason
= DBG_REASON_UNDEFINED
;
954 /*----------------------------------------------------------------------*/
957 * Setup and management support.
961 * Hooks up this DPM to its associated target; call only once.
962 * Initially this only covers the register cache.
964 * Oh, and watchpoints. Yeah.
966 int arm_dpm_setup(struct arm_dpm
*dpm
)
968 struct arm
*arm
= dpm
->arm
;
969 struct target
*target
= arm
->target
;
970 struct reg_cache
*cache
;
974 /* register access setup */
975 arm
->full_context
= arm_dpm_full_context
;
976 arm
->read_core_reg
= arm_dpm_read_core_reg
;
977 arm
->write_core_reg
= arm_dpm_write_core_reg
;
979 /* avoid duplicating the register cache */
980 if (arm
->core_cache
== NULL
) {
981 cache
= arm_build_reg_cache(target
, arm
);
985 *register_get_last_cache_p(&target
->reg_cache
) = cache
;
988 /* coprocessor access setup */
992 /* breakpoint setup -- optional until it works everywhere */
993 if (!target
->type
->add_breakpoint
) {
994 target
->type
->add_breakpoint
= dpm_add_breakpoint
;
995 target
->type
->remove_breakpoint
= dpm_remove_breakpoint
;
998 /* watchpoint setup */
999 target
->type
->add_watchpoint
= dpm_add_watchpoint
;
1000 target
->type
->remove_watchpoint
= dpm_remove_watchpoint
;
1002 /* FIXME add vector catch support */
1004 dpm
->nbp
= 1 + ((dpm
->didr
>> 24) & 0xf);
1005 dpm
->dbp
= calloc(dpm
->nbp
, sizeof *dpm
->dbp
);
1007 dpm
->nwp
= 1 + ((dpm
->didr
>> 28) & 0xf);
1008 dpm
->dwp
= calloc(dpm
->nwp
, sizeof *dpm
->dwp
);
1010 if (!dpm
->dbp
|| !dpm
->dwp
) {
1016 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
1017 target_name(target
), dpm
->nbp
, dpm
->nwp
);
1019 /* REVISIT ... and some of those breakpoints could match
1020 * execution context IDs...
1027 * Reinitializes DPM state at the beginning of a new debug session
1028 * or after a reset which may have affected the debug module.
1030 int arm_dpm_initialize(struct arm_dpm
*dpm
)
1032 /* Disable all breakpoints and watchpoints at startup. */
1033 if (dpm
->bpwp_disable
) {
1036 for (i
= 0; i
< dpm
->nbp
; i
++) {
1037 dpm
->dbp
[i
].bpwp
.number
= i
;
1038 (void) dpm
->bpwp_disable(dpm
, i
);
1040 for (i
= 0; i
< dpm
->nwp
; i
++) {
1041 dpm
->dwp
[i
].bpwp
.number
= 16 + i
;
1042 (void) dpm
->bpwp_disable(dpm
, 16 + i
);
1045 LOG_WARNING("%s: can't disable breakpoints and watchpoints",
1046 target_name(dpm
->arm
->target
));
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