1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
20 ***************************************************************************/
22 #ifndef OPENOCD_TARGET_ARM_ADI_V5_H
23 #define OPENOCD_TARGET_ARM_ADI_V5_H
27 * This defines formats and data structures used to talk to ADIv5 entities.
28 * Those include a DAP, different types of Debug Port (DP), and memory mapped
29 * resources accessed through a MEM-AP.
32 #include <helper/list.h>
35 /* three-bit ACK values for SWD access (sent LSB first) */
36 #define SWD_ACK_OK 0x1
37 #define SWD_ACK_WAIT 0x2
38 #define SWD_ACK_FAULT 0x4
43 #define BANK_REG(bank, reg) (((bank) << 4) | (reg))
45 /* A[3:0] for DP registers; A[1:0] are always zero.
46 * - JTAG accesses all of these via JTAG_DP_DPACC, except for
47 * IDCODE (JTAG_DP_IDCODE) and ABORT (JTAG_DP_ABORT).
48 * - SWD accesses these directly, sometimes needing SELECT.DPBANKSEL
50 #define DP_DPIDR BANK_REG(0x0, 0x0) /* DPv1+: ro */
51 #define DP_ABORT BANK_REG(0x0, 0x0) /* DPv1+: SWD: wo */
52 #define DP_CTRL_STAT BANK_REG(0x0, 0x4) /* DPv0+: rw */
53 #define DP_DLCR BANK_REG(0x1, 0x4) /* DPv1+: SWD: rw */
54 #define DP_TARGETID BANK_REG(0x2, 0x4) /* DPv2: ro */
55 #define DP_DLPIDR BANK_REG(0x3, 0x4) /* DPv2: ro */
56 #define DP_EVENTSTAT BANK_REG(0x4, 0x4) /* DPv2: ro */
57 #define DP_RESEND BANK_REG(0x0, 0x8) /* DPv1+: SWD: ro */
58 #define DP_SELECT BANK_REG(0x0, 0x8) /* DPv0+: JTAG: rw; SWD: wo */
59 #define DP_RDBUFF BANK_REG(0x0, 0xC) /* DPv0+: ro */
60 #define DP_TARGETSEL BANK_REG(0x0, 0xC) /* DPv2: SWD: wo */
62 #define DLCR_TO_TRN(dlcr) ((uint32_t)(1 + ((3 & (dlcr)) >> 8))) /* 1..4 clocks */
64 /* Fields of the DP's AP ABORT register */
65 #define DAPABORT (1UL << 0)
66 #define STKCMPCLR (1UL << 1) /* SWD-only */
67 #define STKERRCLR (1UL << 2) /* SWD-only */
68 #define WDERRCLR (1UL << 3) /* SWD-only */
69 #define ORUNERRCLR (1UL << 4) /* SWD-only */
71 /* Fields of the DP's CTRL/STAT register */
72 #define CORUNDETECT (1UL << 0)
73 #define SSTICKYORUN (1UL << 1)
74 /* 3:2 - transaction mode (e.g. pushed compare) */
75 #define SSTICKYCMP (1UL << 4)
76 #define SSTICKYERR (1UL << 5)
77 #define READOK (1UL << 6) /* SWD-only */
78 #define WDATAERR (1UL << 7) /* SWD-only */
79 /* 11:8 - mask lanes for pushed compare or verify ops */
80 /* 21:12 - transaction counter */
81 #define CDBGRSTREQ (1UL << 26)
82 #define CDBGRSTACK (1UL << 27)
83 #define CDBGPWRUPREQ (1UL << 28)
84 #define CDBGPWRUPACK (1UL << 29)
85 #define CSYSPWRUPREQ (1UL << 30)
86 #define CSYSPWRUPACK (1UL << 31)
88 /* MEM-AP register addresses */
89 #define MEM_AP_REG_CSW 0x00
90 #define MEM_AP_REG_TAR 0x04
91 #define MEM_AP_REG_TAR64 0x08 /* RW: Large Physical Address Extension */
92 #define MEM_AP_REG_DRW 0x0C /* RW: Data Read/Write register */
93 #define MEM_AP_REG_BD0 0x10 /* RW: Banked Data register 0-3 */
94 #define MEM_AP_REG_BD1 0x14
95 #define MEM_AP_REG_BD2 0x18
96 #define MEM_AP_REG_BD3 0x1C
97 #define MEM_AP_REG_MBT 0x20 /* --: Memory Barrier Transfer register */
98 #define MEM_AP_REG_BASE64 0xF0 /* RO: Debug Base Address (LA) register */
99 #define MEM_AP_REG_CFG 0xF4 /* RO: Configuration register */
100 #define MEM_AP_REG_BASE 0xF8 /* RO: Debug Base Address register */
101 /* Generic AP register address */
102 #define AP_REG_IDR 0xFC /* RO: Identification Register */
104 /* Fields of the MEM-AP's CSW register */
108 #define CSW_ADDRINC_MASK (3UL << 4)
109 #define CSW_ADDRINC_OFF 0UL
110 #define CSW_ADDRINC_SINGLE (1UL << 4)
111 #define CSW_ADDRINC_PACKED (2UL << 4)
112 #define CSW_DEVICE_EN (1UL << 6)
113 #define CSW_TRIN_PROG (1UL << 7)
114 #define CSW_SPIDEN (1UL << 23)
115 /* 30:24 - implementation-defined! */
116 #define CSW_HPROT (1UL << 25) /* ? */
117 #define CSW_MASTER_DEBUG (1UL << 29) /* ? */
118 #define CSW_SPROT (1UL << 30)
119 #define CSW_DBGSWENABLE (1UL << 31)
121 /* Fields of the MEM-AP's IDR register */
122 #define IDR_REV (0xFUL << 28)
123 #define IDR_JEP106 (0x7FFUL << 17)
124 #define IDR_CLASS (0xFUL << 13)
125 #define IDR_VARIANT (0xFUL << 4)
126 #define IDR_TYPE (0xFUL << 0)
128 #define IDR_JEP106_ARM 0x04760000
130 #define DP_SELECT_APSEL 0xFF000000
131 #define DP_SELECT_APBANK 0x000000F0
132 #define DP_SELECT_DPBANK 0x0000000F
133 #define DP_SELECT_INVALID 0x00FFFF00 /* Reserved bits one */
136 * This represents an ARM Debug Interface (v5) Access Port (AP).
137 * Most common is a MEM-AP, for memory access.
141 * DAP this AP belongs to.
143 struct adiv5_dap
*dap
;
151 * Default value for (MEM-AP) AP_REG_CSW register.
153 uint32_t csw_default
;
156 * Cache for (MEM-AP) AP_REG_CSW register value. This is written to
157 * configure an access mode, such as autoincrementing AP_REG_TAR during
158 * word access. "-1" indicates no cached value.
163 * Cache for (MEM-AP) AP_REG_TAR register value This is written to
164 * configure the address being read or written
165 * "-1" indicates no cached value.
170 * Configures how many extra tck clocks are added after starting a
171 * MEM-AP access before we try to read its status (and/or result).
173 uint32_t memaccess_tck
;
175 /* Size of TAR autoincrement block, ARM ADI Specification requires at least 10 bits */
176 uint32_t tar_autoincr_block
;
178 /* true if packed transfers are supported by the MEM-AP */
179 bool packed_transfers
;
181 /* true if unaligned memory access is not supported by the MEM-AP */
182 bool unaligned_access_bad
;
187 * This represents an ARM Debug Interface (v5) Debug Access Port (DAP).
188 * A DAP has two types of component: one Debug Port (DP), which is a
189 * transport agent; and at least one Access Port (AP), controlling
192 * There are two basic DP transports: JTAG, and ARM's low pin-count SWD.
193 * Accordingly, this interface is responsible for hiding the transport
194 * differences so upper layer code can largely ignore them.
196 * When the chip is implemented with JTAG-DP or SW-DP, the transport is
197 * fixed as JTAG or SWD, respectively. Chips incorporating SWJ-DP permit
198 * a choice made at board design time (by only using the SWD pins), or
199 * as part of setting up a debug session (if all the dual-role JTAG/SWD
200 * signals are available).
203 const struct dap_ops
*ops
;
205 /* dap transaction list for WAIT support */
206 struct list_head cmd_journal
;
208 struct jtag_tap
*tap
;
210 uint32_t dp_ctrl_stat
;
212 struct adiv5_ap ap
[256];
214 /* The current manually selected AP by the "dap apsel" command */
218 * Cache for DP_SELECT register. A value of DP_SELECT_INVALID
219 * indicates no cached value and forces rewrite of the register.
223 /* information about current pending SWjDP-AHBAP transaction */
227 * Holds the pointer to the destination word for the last queued read,
228 * for use with posted AP read sequence optimization.
232 /* The TI TMS470 and TMS570 series processors use a BE-32 memory ordering
233 * despite lack of support in the ARMv7 architecture. Memory access through
234 * the AHB-AP has strange byte ordering these processors, and we need to
235 * swizzle appropriately. */
236 bool ti_be_32_quirks
;
239 * Signals that an attempt to reestablish communication afresh
240 * should be performed before the next access.
246 * Transport-neutral representation of queued DAP transactions, supporting
247 * both JTAG and SWD transports. All submitted transactions are logically
248 * queued, until the queue is executed by run(). Some implementations might
249 * execute transactions as soon as they're submitted, but no status is made
250 * available until run().
253 /** DP register read. */
254 int (*queue_dp_read
)(struct adiv5_dap
*dap
, unsigned reg
,
256 /** DP register write. */
257 int (*queue_dp_write
)(struct adiv5_dap
*dap
, unsigned reg
,
260 /** AP register read. */
261 int (*queue_ap_read
)(struct adiv5_ap
*ap
, unsigned reg
,
263 /** AP register write. */
264 int (*queue_ap_write
)(struct adiv5_ap
*ap
, unsigned reg
,
267 /** AP operation abort. */
268 int (*queue_ap_abort
)(struct adiv5_dap
*dap
, uint8_t *ack
);
270 /** Executes all queued DAP operations. */
271 int (*run
)(struct adiv5_dap
*dap
);
273 /** Executes all queued DAP operations but doesn't check
274 * sticky error conditions */
275 int (*sync
)(struct adiv5_dap
*dap
);
279 * Access Port classes
282 AP_CLASS_NONE
= 0x00000, /* No class defined */
283 AP_CLASS_MEM_AP
= 0x10000, /* MEM-AP */
290 AP_TYPE_JTAG_AP
= 0x0, /* JTAG-AP - JTAG master for controlling other JTAG devices */
291 AP_TYPE_AHB_AP
= 0x1, /* AHB Memory-AP */
292 AP_TYPE_APB_AP
= 0x2, /* APB Memory-AP */
293 AP_TYPE_AXI_AP
= 0x4, /* AXI Memory-AP */
297 * Queue a DP register read.
298 * Note that not all DP registers are readable; also, that JTAG and SWD
299 * have slight differences in DP register support.
301 * @param dap The DAP used for reading.
302 * @param reg The two-bit number of the DP register being read.
303 * @param data Pointer saying where to store the register's value
304 * (in host endianness).
306 * @return ERROR_OK for success, else a fault code.
308 static inline int dap_queue_dp_read(struct adiv5_dap
*dap
,
309 unsigned reg
, uint32_t *data
)
311 assert(dap
->ops
!= NULL
);
312 return dap
->ops
->queue_dp_read(dap
, reg
, data
);
316 * Queue a DP register write.
317 * Note that not all DP registers are writable; also, that JTAG and SWD
318 * have slight differences in DP register support.
320 * @param dap The DAP used for writing.
321 * @param reg The two-bit number of the DP register being written.
322 * @param data Value being written (host endianness)
324 * @return ERROR_OK for success, else a fault code.
326 static inline int dap_queue_dp_write(struct adiv5_dap
*dap
,
327 unsigned reg
, uint32_t data
)
329 assert(dap
->ops
!= NULL
);
330 return dap
->ops
->queue_dp_write(dap
, reg
, data
);
334 * Queue an AP register read.
336 * @param ap The AP used for reading.
337 * @param reg The number of the AP register being read.
338 * @param data Pointer saying where to store the register's value
339 * (in host endianness).
341 * @return ERROR_OK for success, else a fault code.
343 static inline int dap_queue_ap_read(struct adiv5_ap
*ap
,
344 unsigned reg
, uint32_t *data
)
346 assert(ap
->dap
->ops
!= NULL
);
347 return ap
->dap
->ops
->queue_ap_read(ap
, reg
, data
);
351 * Queue an AP register write.
353 * @param ap The AP used for writing.
354 * @param reg The number of the AP register being written.
355 * @param data Value being written (host endianness)
357 * @return ERROR_OK for success, else a fault code.
359 static inline int dap_queue_ap_write(struct adiv5_ap
*ap
,
360 unsigned reg
, uint32_t data
)
362 assert(ap
->dap
->ops
!= NULL
);
363 return ap
->dap
->ops
->queue_ap_write(ap
, reg
, data
);
367 * Queue an AP abort operation. The current AP transaction is aborted,
368 * including any update of the transaction counter. The AP is left in
369 * an unknown state (so it must be re-initialized). For use only after
370 * the AP has reported WAIT status for an extended period.
372 * @param dap The DAP used for writing.
373 * @param ack Pointer to where transaction status will be stored.
375 * @return ERROR_OK for success, else a fault code.
377 static inline int dap_queue_ap_abort(struct adiv5_dap
*dap
, uint8_t *ack
)
379 assert(dap
->ops
!= NULL
);
380 return dap
->ops
->queue_ap_abort(dap
, ack
);
384 * Perform all queued DAP operations, and clear any errors posted in the
385 * CTRL_STAT register when they are done. Note that if more than one AP
386 * operation will be queued, one of the first operations in the queue
387 * should probably enable CORUNDETECT in the CTRL/STAT register.
389 * @param dap The DAP used.
391 * @return ERROR_OK for success, else a fault code.
393 static inline int dap_run(struct adiv5_dap
*dap
)
395 assert(dap
->ops
!= NULL
);
396 return dap
->ops
->run(dap
);
399 static inline int dap_sync(struct adiv5_dap
*dap
)
401 assert(dap
->ops
!= NULL
);
403 return dap
->ops
->sync(dap
);
407 static inline int dap_dp_read_atomic(struct adiv5_dap
*dap
, unsigned reg
,
412 retval
= dap_queue_dp_read(dap
, reg
, value
);
413 if (retval
!= ERROR_OK
)
419 static inline int dap_dp_poll_register(struct adiv5_dap
*dap
, unsigned reg
,
420 uint32_t mask
, uint32_t value
, int timeout
)
423 assert((value
& mask
) == value
);
427 LOG_DEBUG("DAP: poll %x, mask 0x%08" PRIx32
", value 0x%08" PRIx32
,
430 ret
= dap_dp_read_atomic(dap
, reg
, ®val
);
434 if ((regval
& mask
) == value
)
441 LOG_DEBUG("DAP: poll %x timeout", reg
);
448 /* Queued MEM-AP memory mapped single word transfers. */
449 int mem_ap_read_u32(struct adiv5_ap
*ap
,
450 uint32_t address
, uint32_t *value
);
451 int mem_ap_write_u32(struct adiv5_ap
*ap
,
452 uint32_t address
, uint32_t value
);
454 /* Synchronous MEM-AP memory mapped single word transfers. */
455 int mem_ap_read_atomic_u32(struct adiv5_ap
*ap
,
456 uint32_t address
, uint32_t *value
);
457 int mem_ap_write_atomic_u32(struct adiv5_ap
*ap
,
458 uint32_t address
, uint32_t value
);
460 /* Synchronous MEM-AP memory mapped bus block transfers. */
461 int mem_ap_read_buf(struct adiv5_ap
*ap
,
462 uint8_t *buffer
, uint32_t size
, uint32_t count
, uint32_t address
);
463 int mem_ap_write_buf(struct adiv5_ap
*ap
,
464 const uint8_t *buffer
, uint32_t size
, uint32_t count
, uint32_t address
);
466 /* Synchronous, non-incrementing buffer functions for accessing fifos. */
467 int mem_ap_read_buf_noincr(struct adiv5_ap
*ap
,
468 uint8_t *buffer
, uint32_t size
, uint32_t count
, uint32_t address
);
469 int mem_ap_write_buf_noincr(struct adiv5_ap
*ap
,
470 const uint8_t *buffer
, uint32_t size
, uint32_t count
, uint32_t address
);
472 /* Create DAP struct */
473 struct adiv5_dap
*dap_init(void);
475 /* Initialisation of the debug system, power domains and registers */
476 int dap_dp_init(struct adiv5_dap
*dap
);
477 int mem_ap_init(struct adiv5_ap
*ap
);
479 /* Probe the AP for ROM Table location */
480 int dap_get_debugbase(struct adiv5_ap
*ap
,
481 uint32_t *dbgbase
, uint32_t *apid
);
483 /* Probe Access Ports to find a particular type */
484 int dap_find_ap(struct adiv5_dap
*dap
,
485 enum ap_type type_to_find
,
486 struct adiv5_ap
**ap_out
);
488 static inline struct adiv5_ap
*dap_ap(struct adiv5_dap
*dap
, uint8_t ap_num
)
490 return &dap
->ap
[ap_num
];
493 /* Lookup CoreSight component */
494 int dap_lookup_cs_component(struct adiv5_ap
*ap
,
495 uint32_t dbgbase
, uint8_t type
, uint32_t *addr
, int32_t *idx
);
499 /* Put debug link into SWD mode */
500 int dap_to_swd(struct target
*target
);
502 /* Put debug link into JTAG mode */
503 int dap_to_jtag(struct target
*target
);
505 extern const struct command_registration dap_command_handlers
[];
507 #endif /* OPENOCD_TARGET_ARM_ADI_V5_H */
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