1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
22 ***************************************************************************/
29 * This defines formats and data structures used to talk to ADIv5 entities.
30 * Those include a DAP, different types of Debug Port (DP), and memory mapped
31 * resources accessed through a MEM-AP.
36 /* FIXME remove these JTAG-specific decls when mem_ap_read_buf_u32()
37 * is no longer JTAG-specific
39 #define JTAG_DP_DPACC 0xA
40 #define JTAG_DP_APACC 0xB
42 /* three-bit ACK values for SWD access (sent LSB first) */
43 #define SWD_ACK_OK 0x4
44 #define SWD_ACK_WAIT 0x2
45 #define SWD_ACK_FAULT 0x1
50 /* A[3:0] for DP registers; A[1:0] are always zero.
51 * - JTAG accesses all of these via JTAG_DP_DPACC, except for
52 * IDCODE (JTAG_DP_IDCODE) and ABORT (JTAG_DP_ABORT).
53 * - SWD accesses these directly, sometimes needing SELECT.CTRLSEL
55 #define DP_IDCODE 0 /* SWD: read */
56 #define DP_ABORT 0 /* SWD: write */
57 #define DP_CTRL_STAT 0x4 /* r/w */
58 #define DP_WCR 0x4 /* SWD: r/w (mux CTRLSEL) */
59 #define DP_RESEND 0x8 /* SWD: read */
60 #define DP_SELECT 0x8 /* JTAG: r/w; SWD: write */
61 #define DP_RDBUFF 0xC /* read-only */
63 #define WCR_TO_TRN(wcr) ((uint32_t)(1 + (3 & ((wcr)) >> 8))) /* 1..4 clocks */
64 #define WCR_TO_PRESCALE(wcr) ((uint32_t)(7 & ((wcr)))) /* impl defined */
66 /* Fields of the DP's AP ABORT register */
67 #define DAPABORT (1 << 0)
68 #define STKCMPCLR (1 << 1) /* SWD-only */
69 #define STKERRCLR (1 << 2) /* SWD-only */
70 #define WDERRCLR (1 << 3) /* SWD-only */
71 #define ORUNERRCLR (1 << 4) /* SWD-only */
73 /* Fields of the DP's CTRL/STAT register */
74 #define CORUNDETECT (1 << 0)
75 #define SSTICKYORUN (1 << 1)
76 /* 3:2 - transaction mode (e.g. pushed compare) */
77 #define SSTICKYCMP (1 << 4)
78 #define SSTICKYERR (1 << 5)
79 #define READOK (1 << 6) /* SWD-only */
80 #define WDATAERR (1 << 7) /* SWD-only */
81 /* 11:8 - mask lanes for pushed compare or verify ops */
82 /* 21:12 - transaction counter */
83 #define CDBGRSTREQ (1 << 26)
84 #define CDBGRSTACK (1 << 27)
85 #define CDBGPWRUPREQ (1 << 28)
86 #define CDBGPWRUPACK (1 << 29)
87 #define CSYSPWRUPREQ (1 << 30)
88 #define CSYSPWRUPACK (1 << 31)
90 /* MEM-AP register addresses */
91 /* TODO: rename as MEM_AP_REG_* */
92 #define AP_REG_CSW 0x00
93 #define AP_REG_TAR 0x04
94 #define AP_REG_DRW 0x0C
95 #define AP_REG_BD0 0x10
96 #define AP_REG_BD1 0x14
97 #define AP_REG_BD2 0x18
98 #define AP_REG_BD3 0x1C
99 #define AP_REG_CFG 0xF4 /* big endian? */
100 #define AP_REG_BASE 0xF8
102 /* Generic AP register address */
103 #define AP_REG_IDR 0xFC
105 /* Fields of the MEM-AP's CSW register */
109 #define CSW_ADDRINC_MASK (3 << 4)
110 #define CSW_ADDRINC_OFF 0
111 #define CSW_ADDRINC_SINGLE (1 << 4)
112 #define CSW_ADDRINC_PACKED (2 << 4)
113 #define CSW_DEVICE_EN (1 << 6)
114 #define CSW_TRIN_PROG (1 << 7)
115 #define CSW_SPIDEN (1 << 23)
116 /* 30:24 - implementation-defined! */
117 #define CSW_HPROT (1 << 25) /* ? */
118 #define CSW_MASTER_DEBUG (1 << 29) /* ? */
119 #define CSW_SPROT (1 << 30)
120 #define CSW_DBGSWENABLE (1 << 31)
123 * This represents an ARM Debug Interface (v5) Debug Access Port (DAP).
124 * A DAP has two types of component: one Debug Port (DP), which is a
125 * transport agent; and at least one Access Port (AP), controlling
126 * resource access. Most common is a MEM-AP, for memory access.
128 * There are two basic DP transports: JTAG, and ARM's low pin-count SWD.
129 * Accordingly, this interface is responsible for hiding the transport
130 * differences so upper layer code can largely ignore them.
132 * When the chip is implemented with JTAG-DP or SW-DP, the transport is
133 * fixed as JTAG or SWD, respectively. Chips incorporating SWJ-DP permit
134 * a choice made at board design time (by only using the SWD pins), or
135 * as part of setting up a debug session (if all the dual-role JTAG/SWD
136 * signals are available).
139 const struct dap_ops
*ops
;
141 struct arm_jtag
*jtag_info
;
143 uint32_t dp_ctrl_stat
;
149 * Cache for DP_SELECT bits identifying the current AP. A DAP may
150 * connect to multiple APs, such as one MEM-AP for general access,
151 * another reserved for accessing debug modules, and a JTAG-DP.
152 * "-1" indicates no cached value.
157 * Cache for DP_SELECT bits identifying the current four-word AP
158 * register bank. This caches AP register addresss bits 7:4; JTAG
159 * and SWD access primitves pass address bits 3:2; bits 1:0 are zero.
160 * "-1" indicates no cached value.
162 uint32_t ap_bank_value
;
165 * Cache for (MEM-AP) AP_REG_CSW register value. This is written to
166 * configure an access mode, such as autoincrementing AP_REG_TAR during
167 * word access. "-1" indicates no cached value.
169 uint32_t ap_csw_value
;
172 * Cache for (MEM-AP) AP_REG_TAR register value This is written to
173 * configure the address being read or written
174 * "-1" indicates no cached value.
176 uint32_t ap_tar_value
;
178 /* information about current pending SWjDP-AHBAP transaction */
182 * Configures how many extra tck clocks are added after starting a
183 * MEM-AP access before we try to read its status (and/or result).
185 uint32_t memaccess_tck
;
187 /* Size of TAR autoincrement block, ARM ADI Specification requires at least 10 bits */
188 uint32_t tar_autoincr_block
;
190 /* true if packed transfers are supported by the MEM-AP */
191 bool packed_transfers
;
195 * Transport-neutral representation of queued DAP transactions, supporting
196 * both JTAG and SWD transports. All submitted transactions are logically
197 * queued, until the queue is executed by run(). Some implementations might
198 * execute transactions as soon as they're submitted, but no status is made
199 * availablue until run().
202 /** If the DAP transport isn't SWD, it must be JTAG. Upper level
203 * code may need to care about the difference in some cases.
207 /** Reads the DAP's IDCODe register. */
208 int (*queue_idcode_read
)(struct adiv5_dap
*dap
,
209 uint8_t *ack
, uint32_t *data
);
211 /** DP register read. */
212 int (*queue_dp_read
)(struct adiv5_dap
*dap
, unsigned reg
,
214 /** DP register write. */
215 int (*queue_dp_write
)(struct adiv5_dap
*dap
, unsigned reg
,
218 /** AP register read. */
219 int (*queue_ap_read
)(struct adiv5_dap
*dap
, unsigned reg
,
221 /** AP register write. */
222 int (*queue_ap_write
)(struct adiv5_dap
*dap
, unsigned reg
,
224 /** AP read block. */
225 int (*queue_ap_read_block
)(struct adiv5_dap
*dap
, unsigned reg
,
226 uint32_t blocksize
, uint8_t *buffer
);
228 /** AP operation abort. */
229 int (*queue_ap_abort
)(struct adiv5_dap
*dap
, uint8_t *ack
);
231 /** Executes all queued DAP operations. */
232 int (*run
)(struct adiv5_dap
*dap
);
239 AP_TYPE_AHB_AP
= 0x01, /* AHB Memory-AP */
240 AP_TYPE_APB_AP
= 0x02, /* APB Memory-AP */
241 AP_TYPE_JTAG_AP
= 0x10 /* JTAG-AP - JTAG master for controlling other JTAG devices */
245 * Queue an IDCODE register read. This is primarily useful for SWD
246 * transports, where it is required as part of link initialization.
247 * (For JTAG, this register is read as part of scan chain setup.)
249 * @param dap The DAP used for reading.
250 * @param ack Pointer to where transaction status will be stored.
251 * @param data Pointer saying where to store the IDCODE value.
253 * @return ERROR_OK for success, else a fault code.
255 static inline int dap_queue_idcode_read(struct adiv5_dap
*dap
,
256 uint8_t *ack
, uint32_t *data
)
258 assert(dap
->ops
!= NULL
);
259 return dap
->ops
->queue_idcode_read(dap
, ack
, data
);
263 * Queue a DP register read.
264 * Note that not all DP registers are readable; also, that JTAG and SWD
265 * have slight differences in DP register support.
267 * @param dap The DAP used for reading.
268 * @param reg The two-bit number of the DP register being read.
269 * @param data Pointer saying where to store the register's value
270 * (in host endianness).
272 * @return ERROR_OK for success, else a fault code.
274 static inline int dap_queue_dp_read(struct adiv5_dap
*dap
,
275 unsigned reg
, uint32_t *data
)
277 assert(dap
->ops
!= NULL
);
278 return dap
->ops
->queue_dp_read(dap
, reg
, data
);
282 * Queue a DP register write.
283 * Note that not all DP registers are writable; also, that JTAG and SWD
284 * have slight differences in DP register support.
286 * @param dap The DAP used for writing.
287 * @param reg The two-bit number of the DP register being written.
288 * @param data Value being written (host endianness)
290 * @return ERROR_OK for success, else a fault code.
292 static inline int dap_queue_dp_write(struct adiv5_dap
*dap
,
293 unsigned reg
, uint32_t data
)
295 assert(dap
->ops
!= NULL
);
296 return dap
->ops
->queue_dp_write(dap
, reg
, data
);
300 * Queue an AP register read.
302 * @param dap The DAP used for reading.
303 * @param reg The number of the AP register being read.
304 * @param data Pointer saying where to store the register's value
305 * (in host endianness).
307 * @return ERROR_OK for success, else a fault code.
309 static inline int dap_queue_ap_read(struct adiv5_dap
*dap
,
310 unsigned reg
, uint32_t *data
)
312 assert(dap
->ops
!= NULL
);
313 return dap
->ops
->queue_ap_read(dap
, reg
, data
);
317 * Queue an AP register write.
319 * @param dap The DAP used for writing.
320 * @param reg The number of the AP register being written.
321 * @param data Value being written (host endianness)
323 * @return ERROR_OK for success, else a fault code.
325 static inline int dap_queue_ap_write(struct adiv5_dap
*dap
,
326 unsigned reg
, uint32_t data
)
328 assert(dap
->ops
!= NULL
);
329 return dap
->ops
->queue_ap_write(dap
, reg
, data
);
333 * Queue an AP block read.
335 * @param dap The DAP used for reading.
336 * @param reg The number of the AP register being read.
337 * @param blocksize The number of the AP register being read.
338 * @param buffer Pointer saying where to store the data
339 * (in host endianness).
341 * @return ERROR_OK for success, else a fault code.
343 static inline int dap_queue_ap_read_block(struct adiv5_dap
*dap
,
344 unsigned reg
, unsigned blocksize
, uint8_t *buffer
)
346 assert(dap
->ops
!= NULL
);
347 return dap
->ops
->queue_ap_read_block(dap
, reg
, blocksize
, buffer
);
351 * Queue an AP abort operation. The current AP transaction is aborted,
352 * including any update of the transaction counter. The AP is left in
353 * an unknown state (so it must be re-initialized). For use only after
354 * the AP has reported WAIT status for an extended period.
356 * @param dap The DAP used for writing.
357 * @param ack Pointer to where transaction status will be stored.
359 * @return ERROR_OK for success, else a fault code.
361 static inline int dap_queue_ap_abort(struct adiv5_dap
*dap
, uint8_t *ack
)
363 assert(dap
->ops
!= NULL
);
364 return dap
->ops
->queue_ap_abort(dap
, ack
);
368 * Perform all queued DAP operations, and clear any errors posted in the
369 * CTRL_STAT register when they are done. Note that if more than one AP
370 * operation will be queued, one of the first operations in the queue
371 * should probably enable CORUNDETECT in the CTRL/STAT register.
373 * @param dap The DAP used.
375 * @return ERROR_OK for success, else a fault code.
377 static inline int dap_run(struct adiv5_dap
*dap
)
379 assert(dap
->ops
!= NULL
);
380 return dap
->ops
->run(dap
);
383 /** Accessor for currently selected DAP-AP number (0..255) */
384 static inline uint8_t dap_ap_get_select(struct adiv5_dap
*swjdp
)
386 return (uint8_t)(swjdp
->ap_current
>> 24);
389 /* AP selection applies to future AP transactions */
390 void dap_ap_select(struct adiv5_dap
*dap
, uint8_t ap
);
392 /* Queued AP transactions */
393 int dap_setup_accessport(struct adiv5_dap
*swjdp
,
394 uint32_t csw
, uint32_t tar
);
396 /* Queued MEM-AP memory mapped single word transfers */
397 int mem_ap_read_u32(struct adiv5_dap
*swjdp
, uint32_t address
, uint32_t *value
);
398 int mem_ap_write_u32(struct adiv5_dap
*swjdp
, uint32_t address
, uint32_t value
);
400 /* Synchronous MEM-AP memory mapped single word transfers */
401 int mem_ap_read_atomic_u32(struct adiv5_dap
*swjdp
,
402 uint32_t address
, uint32_t *value
);
403 int mem_ap_write_atomic_u32(struct adiv5_dap
*swjdp
,
404 uint32_t address
, uint32_t value
);
406 /* Queued MEM-AP memory mapped single word transfers with selection of ap */
407 int mem_ap_sel_read_u32(struct adiv5_dap
*swjdp
, uint8_t ap
,
408 uint32_t address
, uint32_t *value
);
409 int mem_ap_sel_write_u32(struct adiv5_dap
*swjdp
, uint8_t ap
,
410 uint32_t address
, uint32_t value
);
412 /* Synchronous MEM-AP memory mapped single word transfers with selection of ap */
413 int mem_ap_sel_read_atomic_u32(struct adiv5_dap
*swjdp
, uint8_t ap
,
414 uint32_t address
, uint32_t *value
);
415 int mem_ap_sel_write_atomic_u32(struct adiv5_dap
*swjdp
, uint8_t ap
,
416 uint32_t address
, uint32_t value
);
418 /* Synchronous MEM-AP memory mapped bus block transfers */
419 int mem_ap_read(struct adiv5_dap
*dap
, uint8_t *buffer
, uint32_t size
,
420 uint32_t count
, uint32_t address
, bool addrinc
);
421 int mem_ap_write(struct adiv5_dap
*dap
, const uint8_t *buffer
, uint32_t size
,
422 uint32_t count
, uint32_t address
, bool addrinc
);
424 /* Synchronous MEM-AP memory mapped bus block transfers with selection of ap */
425 int mem_ap_sel_read_buf(struct adiv5_dap
*swjdp
, uint8_t ap
,
426 uint8_t *buffer
, uint32_t size
, uint32_t count
, uint32_t address
);
427 int mem_ap_sel_write_buf(struct adiv5_dap
*swjdp
, uint8_t ap
,
428 const uint8_t *buffer
, uint32_t size
, uint32_t count
, uint32_t address
);
430 /* Synchronous, non-incrementing buffer functions for accessing fifos, with
432 int mem_ap_sel_read_buf_noincr(struct adiv5_dap
*swjdp
, uint8_t ap
,
433 uint8_t *buffer
, uint32_t size
, uint32_t count
, uint32_t address
);
434 int mem_ap_sel_write_buf_noincr(struct adiv5_dap
*swjdp
, uint8_t ap
,
435 const uint8_t *buffer
, uint32_t size
, uint32_t count
, uint32_t address
);
437 /* Initialisation of the debug system, power domains and registers */
438 int ahbap_debugport_init(struct adiv5_dap
*swjdp
);
440 /* Probe the AP for ROM Table location */
441 int dap_get_debugbase(struct adiv5_dap
*dap
, int ap
,
442 uint32_t *dbgbase
, uint32_t *apid
);
444 /* Probe Access Ports to find a particular type */
445 int dap_find_ap(struct adiv5_dap
*dap
,
446 enum ap_type type_to_find
,
447 uint8_t *ap_num_out
);
449 /* Lookup CoreSight component */
450 int dap_lookup_cs_component(struct adiv5_dap
*dap
, int ap
,
451 uint32_t dbgbase
, uint8_t type
, uint32_t *addr
);
455 /* Put debug link into SWD mode */
456 int dap_to_swd(struct target
*target
);
458 /* Put debug link into JTAG mode */
459 int dap_to_jtag(struct target
*target
);
461 extern const struct command_registration dap_command_handlers
[];
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