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[openocd.git] / src / target / arm_adi_v5.c
1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
3 * lundin@mlu.mine.nu *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2009 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
26
27 /**
28 * @file
29 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
30 * debugging architecture. Compared with previous versions, this includes
31 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
32 * transport, and focusses on memory mapped resources as defined by the
33 * CoreSight architecture.
34 *
35 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
36 * basic components: a Debug Port (DP) transporting messages to and from a
37 * debugger, and an Access Port (AP) accessing resources. Three types of DP
38 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
39 * One uses only SWD for communication, and is called SW-DP. The third can
40 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
41 * is used to access memory mapped resources and is called a MEM-AP. Also a
42 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
43 */
44
45 /*
46 * Relevant specifications from ARM include:
47 *
48 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
49 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
50 *
51 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
52 * Cortex-M3(tm) TRM, ARM DDI 0337G
53 */
54
55 #ifdef HAVE_CONFIG_H
56 #include "config.h"
57 #endif
58
59 #include "arm_adi_v5.h"
60 #include <helper/time_support.h>
61
62 /*
63 * Transaction Mode:
64 * swjdp->trans_mode = TRANS_MODE_COMPOSITE;
65 * Uses Overrun checking mode and does not do actual JTAG send/receive or transaction
66 * result checking until swjdp_end_transaction()
67 * This must be done before using or deallocating any return variables.
68 * swjdp->trans_mode == TRANS_MODE_ATOMIC
69 * All reads and writes to the AHB bus are checked for valid completion, and return values
70 * are immediatley available.
71 */
72
73
74 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
75
76 /*
77 uint32_t tar_block_size(uint32_t address)
78 Return the largest block starting at address that does not cross a tar block size alignment boundary
79 */
80 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
81 {
82 return (tar_autoincr_block - ((tar_autoincr_block - 1) & address)) >> 2;
83 }
84
85 /***************************************************************************
86 * *
87 * DPACC and APACC scanchain access through JTAG-DP *
88 * *
89 ***************************************************************************/
90
91 /* Scan out and in from target ordered uint8_t buffers */
92 int adi_jtag_dp_scan(struct swjdp_common *swjdp, uint8_t instr, uint8_t reg_addr, uint8_t RnW, uint8_t *outvalue, uint8_t *invalue, uint8_t *ack)
93 {
94 struct arm_jtag *jtag_info = swjdp->jtag_info;
95 struct scan_field fields[2];
96 uint8_t out_addr_buf;
97
98 jtag_set_end_state(TAP_IDLE);
99 arm_jtag_set_instr(jtag_info, instr, NULL);
100
101 /* Add specified number of tck clocks before accessing memory bus */
102 if ((instr == DAP_IR_APACC) && ((reg_addr == AP_REG_DRW)||((reg_addr&0xF0) == AP_REG_BD0))&& (swjdp->memaccess_tck != 0))
103 jtag_add_runtest(swjdp->memaccess_tck, jtag_set_end_state(TAP_IDLE));
104
105 fields[0].tap = jtag_info->tap;
106 fields[0].num_bits = 3;
107 buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
108 fields[0].out_value = &out_addr_buf;
109 fields[0].in_value = ack;
110
111 fields[1].tap = jtag_info->tap;
112 fields[1].num_bits = 32;
113 fields[1].out_value = outvalue;
114 fields[1].in_value = invalue;
115
116 jtag_add_dr_scan(2, fields, jtag_get_end_state());
117
118 return ERROR_OK;
119 }
120
121 /* Scan out and in from host ordered uint32_t variables */
122 int adi_jtag_dp_scan_u32(struct swjdp_common *swjdp, uint8_t instr, uint8_t reg_addr, uint8_t RnW, uint32_t outvalue, uint32_t *invalue, uint8_t *ack)
123 {
124 struct arm_jtag *jtag_info = swjdp->jtag_info;
125 struct scan_field fields[2];
126 uint8_t out_value_buf[4];
127 uint8_t out_addr_buf;
128
129 jtag_set_end_state(TAP_IDLE);
130 arm_jtag_set_instr(jtag_info, instr, NULL);
131
132 /* Add specified number of tck clocks before accessing memory bus */
133 if ((instr == DAP_IR_APACC) && ((reg_addr == AP_REG_DRW)||((reg_addr&0xF0) == AP_REG_BD0))&& (swjdp->memaccess_tck != 0))
134 jtag_add_runtest(swjdp->memaccess_tck, jtag_set_end_state(TAP_IDLE));
135
136 fields[0].tap = jtag_info->tap;
137 fields[0].num_bits = 3;
138 buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
139 fields[0].out_value = &out_addr_buf;
140 fields[0].in_value = ack;
141
142 fields[1].tap = jtag_info->tap;
143 fields[1].num_bits = 32;
144 buf_set_u32(out_value_buf, 0, 32, outvalue);
145 fields[1].out_value = out_value_buf;
146 fields[1].in_value = NULL;
147
148 if (invalue)
149 {
150 fields[1].in_value = (uint8_t *)invalue;
151 jtag_add_dr_scan(2, fields, jtag_get_end_state());
152
153 jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t) invalue);
154 } else
155 {
156
157 jtag_add_dr_scan(2, fields, jtag_get_end_state());
158 }
159
160 return ERROR_OK;
161 }
162
163 /* scan_inout_check adds one extra inscan for DPAP_READ commands to read variables */
164 int scan_inout_check(struct swjdp_common *swjdp, uint8_t instr, uint8_t reg_addr, uint8_t RnW, uint8_t *outvalue, uint8_t *invalue)
165 {
166 adi_jtag_dp_scan(swjdp, instr, reg_addr, RnW, outvalue, NULL, NULL);
167
168 if ((RnW == DPAP_READ) && (invalue != NULL))
169 {
170 adi_jtag_dp_scan(swjdp, DAP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
171 }
172
173 /* In TRANS_MODE_ATOMIC all DAP_IR_APACC transactions wait for ack = OK/FAULT and the check CTRL_STAT */
174 if ((instr == DAP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
175 {
176 return swjdp_transaction_endcheck(swjdp);
177 }
178
179 return ERROR_OK;
180 }
181
182 int scan_inout_check_u32(struct swjdp_common *swjdp, uint8_t instr, uint8_t reg_addr, uint8_t RnW, uint32_t outvalue, uint32_t *invalue)
183 {
184 adi_jtag_dp_scan_u32(swjdp, instr, reg_addr, RnW, outvalue, NULL, NULL);
185
186 if ((RnW == DPAP_READ) && (invalue != NULL))
187 {
188 adi_jtag_dp_scan_u32(swjdp, DAP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
189 }
190
191 /* In TRANS_MODE_ATOMIC all DAP_IR_APACC transactions wait for ack = OK/FAULT and then check CTRL_STAT */
192 if ((instr == DAP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
193 {
194 return swjdp_transaction_endcheck(swjdp);
195 }
196
197 return ERROR_OK;
198 }
199
200 int swjdp_transaction_endcheck(struct swjdp_common *swjdp)
201 {
202 int retval;
203 uint32_t ctrlstat;
204
205 /* too expensive to call keep_alive() here */
206
207 #if 0
208 /* Danger!!!! BROKEN!!!! */
209 scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
210 /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here????
211 R956 introduced the check on return value here and now Michael Schwingen reports
212 that this code no longer works....
213
214 https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html
215 */
216 if ((retval = jtag_execute_queue()) != ERROR_OK)
217 {
218 LOG_ERROR("BUG: Why does this fail the first time????");
219 }
220 /* Why??? second time it works??? */
221 #endif
222
223 scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
224 if ((retval = jtag_execute_queue()) != ERROR_OK)
225 return retval;
226
227 swjdp->ack = swjdp->ack & 0x7;
228
229 if (swjdp->ack != 2)
230 {
231 long long then = timeval_ms();
232 while (swjdp->ack != 2)
233 {
234 if (swjdp->ack == 1)
235 {
236 if ((timeval_ms()-then) > 1000)
237 {
238 LOG_WARNING("Timeout (1000ms) waiting for ACK = OK/FAULT in SWJDP transaction");
239 return ERROR_JTAG_DEVICE_ERROR;
240 }
241 }
242 else
243 {
244 LOG_WARNING("Invalid ACK in SWJDP transaction");
245 return ERROR_JTAG_DEVICE_ERROR;
246 }
247
248 scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
249 if ((retval = jtag_execute_queue()) != ERROR_OK)
250 return retval;
251 swjdp->ack = swjdp->ack & 0x7;
252 }
253 } else
254 {
255 /* common code path avoids fn to timeval_ms() */
256 }
257
258 /* Check for STICKYERR and STICKYORUN */
259 if (ctrlstat & (SSTICKYORUN | SSTICKYERR))
260 {
261 LOG_DEBUG("swjdp: CTRL/STAT error 0x%" PRIx32 "", ctrlstat);
262 /* Check power to debug regions */
263 if ((ctrlstat & 0xf0000000) != 0xf0000000)
264 {
265 ahbap_debugport_init(swjdp);
266 }
267 else
268 {
269 uint32_t mem_ap_csw, mem_ap_tar;
270
271 /* Print information about last AHBAP access */
272 LOG_ERROR("AHBAP Cached values: dp_select 0x%" PRIx32 ", ap_csw 0x%" PRIx32 ", ap_tar 0x%" PRIx32 "", swjdp->dp_select_value, swjdp->ap_csw_value, swjdp->ap_tar_value);
273 if (ctrlstat & SSTICKYORUN)
274 LOG_ERROR("SWJ-DP OVERRUN - check clock or reduce jtag speed");
275
276 if (ctrlstat & SSTICKYERR)
277 LOG_ERROR("SWJ-DP STICKY ERROR");
278
279 /* Clear Sticky Error Bits */
280 scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_WRITE, swjdp->dp_ctrl_stat | SSTICKYORUN | SSTICKYERR, NULL);
281 scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
282 if ((retval = jtag_execute_queue()) != ERROR_OK)
283 return retval;
284
285 LOG_DEBUG("swjdp: status 0x%" PRIx32 "", ctrlstat);
286
287 dap_ap_read_reg_u32(swjdp, AP_REG_CSW, &mem_ap_csw);
288 dap_ap_read_reg_u32(swjdp, AP_REG_TAR, &mem_ap_tar);
289 if ((retval = jtag_execute_queue()) != ERROR_OK)
290 return retval;
291 LOG_ERROR("Read MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%" PRIx32 "", mem_ap_csw, mem_ap_tar);
292
293 }
294 if ((retval = jtag_execute_queue()) != ERROR_OK)
295 return retval;
296 return ERROR_JTAG_DEVICE_ERROR;
297 }
298
299 return ERROR_OK;
300 }
301
302 /***************************************************************************
303 * *
304 * DP and MEM-AP register access through APACC and DPACC *
305 * *
306 ***************************************************************************/
307
308 int dap_dp_write_reg(struct swjdp_common *swjdp, uint32_t value, uint8_t reg_addr)
309 {
310 return scan_inout_check_u32(swjdp, DAP_IR_DPACC, reg_addr, DPAP_WRITE, value, NULL);
311 }
312
313 int dap_dp_read_reg(struct swjdp_common *swjdp, uint32_t *value, uint8_t reg_addr)
314 {
315 return scan_inout_check_u32(swjdp, DAP_IR_DPACC, reg_addr, DPAP_READ, 0, value);
316 }
317
318 int dap_ap_select(struct swjdp_common *swjdp,uint8_t apsel)
319 {
320 uint32_t select;
321 select = (apsel << 24) & 0xFF000000;
322
323 if (select != swjdp->apsel)
324 {
325 swjdp->apsel = select;
326 /* Switching AP invalidates cached values */
327 swjdp->dp_select_value = -1;
328 swjdp->ap_csw_value = -1;
329 swjdp->ap_tar_value = -1;
330 }
331
332 return ERROR_OK;
333 }
334
335 int dap_dp_bankselect(struct swjdp_common *swjdp,uint32_t ap_reg)
336 {
337 uint32_t select;
338 select = (ap_reg & 0x000000F0);
339
340 if (select != swjdp->dp_select_value)
341 {
342 dap_dp_write_reg(swjdp, select | swjdp->apsel, DP_SELECT);
343 swjdp->dp_select_value = select;
344 }
345
346 return ERROR_OK;
347 }
348
349 int dap_ap_write_reg(struct swjdp_common *swjdp, uint32_t reg_addr, uint8_t* out_value_buf)
350 {
351 dap_dp_bankselect(swjdp, reg_addr);
352 scan_inout_check(swjdp, DAP_IR_APACC, reg_addr, DPAP_WRITE, out_value_buf, NULL);
353
354 return ERROR_OK;
355 }
356
357 int dap_ap_read_reg(struct swjdp_common *swjdp, uint32_t reg_addr, uint8_t *in_value_buf)
358 {
359 dap_dp_bankselect(swjdp, reg_addr);
360 scan_inout_check(swjdp, DAP_IR_APACC, reg_addr, DPAP_READ, 0, in_value_buf);
361
362 return ERROR_OK;
363 }
364 int dap_ap_write_reg_u32(struct swjdp_common *swjdp, uint32_t reg_addr, uint32_t value)
365 {
366 uint8_t out_value_buf[4];
367
368 buf_set_u32(out_value_buf, 0, 32, value);
369 dap_dp_bankselect(swjdp, reg_addr);
370 scan_inout_check(swjdp, DAP_IR_APACC, reg_addr, DPAP_WRITE, out_value_buf, NULL);
371
372 return ERROR_OK;
373 }
374
375 int dap_ap_read_reg_u32(struct swjdp_common *swjdp, uint32_t reg_addr, uint32_t *value)
376 {
377 dap_dp_bankselect(swjdp, reg_addr);
378 scan_inout_check_u32(swjdp, DAP_IR_APACC, reg_addr, DPAP_READ, 0, value);
379
380 return ERROR_OK;
381 }
382
383 /***************************************************************************
384 * *
385 * AHB-AP access to memory and system registers on AHB bus *
386 * *
387 ***************************************************************************/
388
389 int dap_setup_accessport(struct swjdp_common *swjdp, uint32_t csw, uint32_t tar)
390 {
391 csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
392 if (csw != swjdp->ap_csw_value)
393 {
394 /* LOG_DEBUG("swjdp : Set CSW %x",csw); */
395 dap_ap_write_reg_u32(swjdp, AP_REG_CSW, csw);
396 swjdp->ap_csw_value = csw;
397 }
398 if (tar != swjdp->ap_tar_value)
399 {
400 /* LOG_DEBUG("swjdp : Set TAR %x",tar); */
401 dap_ap_write_reg_u32(swjdp, AP_REG_TAR, tar);
402 swjdp->ap_tar_value = tar;
403 }
404 if (csw & CSW_ADDRINC_MASK)
405 {
406 /* Do not cache TAR value when autoincrementing */
407 swjdp->ap_tar_value = -1;
408 }
409 return ERROR_OK;
410 }
411
412 /*****************************************************************************
413 * *
414 * mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value) *
415 * *
416 * Read a uint32_t value from memory or system register *
417 * Functionally equivalent to target_read_u32(target, address, uint32_t *value), *
418 * but with less overhead *
419 *****************************************************************************/
420 int mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value)
421 {
422 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
423
424 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
425 dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value);
426
427 return ERROR_OK;
428 }
429
430 int mem_ap_read_atomic_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value)
431 {
432 mem_ap_read_u32(swjdp, address, value);
433
434 return swjdp_transaction_endcheck(swjdp);
435 }
436
437 /*****************************************************************************
438 * *
439 * mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value) *
440 * *
441 * Write a uint32_t value to memory or memory mapped register *
442 * *
443 *****************************************************************************/
444 int mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value)
445 {
446 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
447
448 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
449 dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value);
450
451 return ERROR_OK;
452 }
453
454 int mem_ap_write_atomic_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value)
455 {
456 mem_ap_write_u32(swjdp, address, value);
457
458 return swjdp_transaction_endcheck(swjdp);
459 }
460
461 /*****************************************************************************
462 * *
463 * mem_ap_write_buf(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) *
464 * *
465 * Write a buffer in target order (little endian) *
466 * *
467 *****************************************************************************/
468 int mem_ap_write_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
469 {
470 int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
471 uint32_t adr = address;
472 uint8_t* pBuffer = buffer;
473
474 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
475
476 count >>= 2;
477 wcount = count;
478
479 /* if we have an unaligned access - reorder data */
480 if (adr & 0x3u)
481 {
482 for (writecount = 0; writecount < count; writecount++)
483 {
484 int i;
485 uint32_t outvalue;
486 memcpy(&outvalue, pBuffer, sizeof(uint32_t));
487
488 for (i = 0; i < 4; i++)
489 {
490 *((uint8_t*)pBuffer + (adr & 0x3)) = outvalue;
491 outvalue >>= 8;
492 adr++;
493 }
494 pBuffer += sizeof(uint32_t);
495 }
496 }
497
498 while (wcount > 0)
499 {
500 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
501 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
502 if (wcount < blocksize)
503 blocksize = wcount;
504
505 /* handle unaligned data at 4k boundary */
506 if (blocksize == 0)
507 blocksize = 1;
508
509 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
510
511 for (writecount = 0; writecount < blocksize; writecount++)
512 {
513 dap_ap_write_reg(swjdp, AP_REG_DRW, buffer + 4 * writecount);
514 }
515
516 if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
517 {
518 wcount = wcount - blocksize;
519 address = address + 4 * blocksize;
520 buffer = buffer + 4 * blocksize;
521 }
522 else
523 {
524 errorcount++;
525 }
526
527 if (errorcount > 1)
528 {
529 LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount);
530 return ERROR_JTAG_DEVICE_ERROR;
531 }
532 }
533
534 return retval;
535 }
536
537 int mem_ap_write_buf_packed_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
538 {
539 int retval = ERROR_OK;
540 int wcount, blocksize, writecount, i;
541
542 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
543
544 wcount = count >> 1;
545
546 while (wcount > 0)
547 {
548 int nbytes;
549
550 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
551 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
552
553 if (wcount < blocksize)
554 blocksize = wcount;
555
556 /* handle unaligned data at 4k boundary */
557 if (blocksize == 0)
558 blocksize = 1;
559
560 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
561 writecount = blocksize;
562
563 do
564 {
565 nbytes = MIN((writecount << 1), 4);
566
567 if (nbytes < 4)
568 {
569 if (mem_ap_write_buf_u16(swjdp, buffer, nbytes, address) != ERROR_OK)
570 {
571 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
572 return ERROR_JTAG_DEVICE_ERROR;
573 }
574
575 address += nbytes >> 1;
576 }
577 else
578 {
579 uint32_t outvalue;
580 memcpy(&outvalue, buffer, sizeof(uint32_t));
581
582 for (i = 0; i < nbytes; i++)
583 {
584 *((uint8_t*)buffer + (address & 0x3)) = outvalue;
585 outvalue >>= 8;
586 address++;
587 }
588
589 memcpy(&outvalue, buffer, sizeof(uint32_t));
590 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
591 if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
592 {
593 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
594 return ERROR_JTAG_DEVICE_ERROR;
595 }
596 }
597
598 buffer += nbytes >> 1;
599 writecount -= nbytes >> 1;
600
601 } while (writecount);
602 wcount -= blocksize;
603 }
604
605 return retval;
606 }
607
608 int mem_ap_write_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
609 {
610 int retval = ERROR_OK;
611
612 if (count >= 4)
613 return mem_ap_write_buf_packed_u16(swjdp, buffer, count, address);
614
615 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
616
617 while (count > 0)
618 {
619 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
620 uint16_t svalue;
621 memcpy(&svalue, buffer, sizeof(uint16_t));
622 uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
623 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
624 retval = swjdp_transaction_endcheck(swjdp);
625 count -= 2;
626 address += 2;
627 buffer += 2;
628 }
629
630 return retval;
631 }
632
633 int mem_ap_write_buf_packed_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
634 {
635 int retval = ERROR_OK;
636 int wcount, blocksize, writecount, i;
637
638 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
639
640 wcount = count;
641
642 while (wcount > 0)
643 {
644 int nbytes;
645
646 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
647 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
648
649 if (wcount < blocksize)
650 blocksize = wcount;
651
652 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
653 writecount = blocksize;
654
655 do
656 {
657 nbytes = MIN(writecount, 4);
658
659 if (nbytes < 4)
660 {
661 if (mem_ap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK)
662 {
663 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
664 return ERROR_JTAG_DEVICE_ERROR;
665 }
666
667 address += nbytes;
668 }
669 else
670 {
671 uint32_t outvalue;
672 memcpy(&outvalue, buffer, sizeof(uint32_t));
673
674 for (i = 0; i < nbytes; i++)
675 {
676 *((uint8_t*)buffer + (address & 0x3)) = outvalue;
677 outvalue >>= 8;
678 address++;
679 }
680
681 memcpy(&outvalue, buffer, sizeof(uint32_t));
682 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
683 if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
684 {
685 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
686 return ERROR_JTAG_DEVICE_ERROR;
687 }
688 }
689
690 buffer += nbytes;
691 writecount -= nbytes;
692
693 } while (writecount);
694 wcount -= blocksize;
695 }
696
697 return retval;
698 }
699
700 int mem_ap_write_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
701 {
702 int retval = ERROR_OK;
703
704 if (count >= 4)
705 return mem_ap_write_buf_packed_u8(swjdp, buffer, count, address);
706
707 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
708
709 while (count > 0)
710 {
711 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
712 uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
713 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
714 retval = swjdp_transaction_endcheck(swjdp);
715 count--;
716 address++;
717 buffer++;
718 }
719
720 return retval;
721 }
722
723 /*********************************************************************************
724 * *
725 * mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) *
726 * *
727 * Read block fast in target order (little endian) into a buffer *
728 * *
729 **********************************************************************************/
730 int mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
731 {
732 int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
733 uint32_t adr = address;
734 uint8_t* pBuffer = buffer;
735
736 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
737
738 count >>= 2;
739 wcount = count;
740
741 while (wcount > 0)
742 {
743 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
744 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
745 if (wcount < blocksize)
746 blocksize = wcount;
747
748 /* handle unaligned data at 4k boundary */
749 if (blocksize == 0)
750 blocksize = 1;
751
752 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
753
754 /* Scan out first read */
755 adi_jtag_dp_scan(swjdp, DAP_IR_APACC, AP_REG_DRW, DPAP_READ, 0, NULL, NULL);
756 for (readcount = 0; readcount < blocksize - 1; readcount++)
757 {
758 /* Scan out read instruction and scan in previous value */
759 adi_jtag_dp_scan(swjdp, DAP_IR_APACC, AP_REG_DRW, DPAP_READ, 0, buffer + 4 * readcount, &swjdp->ack);
760 }
761
762 /* Scan in last value */
763 adi_jtag_dp_scan(swjdp, DAP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, buffer + 4 * readcount, &swjdp->ack);
764 if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
765 {
766 wcount = wcount - blocksize;
767 address += 4 * blocksize;
768 buffer += 4 * blocksize;
769 }
770 else
771 {
772 errorcount++;
773 }
774
775 if (errorcount > 1)
776 {
777 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
778 return ERROR_JTAG_DEVICE_ERROR;
779 }
780 }
781
782 /* if we have an unaligned access - reorder data */
783 if (adr & 0x3u)
784 {
785 for (readcount = 0; readcount < count; readcount++)
786 {
787 int i;
788 uint32_t data;
789 memcpy(&data, pBuffer, sizeof(uint32_t));
790
791 for (i = 0; i < 4; i++)
792 {
793 *((uint8_t*)pBuffer) = (data >> 8 * (adr & 0x3));
794 pBuffer++;
795 adr++;
796 }
797 }
798 }
799
800 return retval;
801 }
802
803 int mem_ap_read_buf_packed_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
804 {
805 uint32_t invalue;
806 int retval = ERROR_OK;
807 int wcount, blocksize, readcount, i;
808
809 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
810
811 wcount = count >> 1;
812
813 while (wcount > 0)
814 {
815 int nbytes;
816
817 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
818 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
819 if (wcount < blocksize)
820 blocksize = wcount;
821
822 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
823
824 /* handle unaligned data at 4k boundary */
825 if (blocksize == 0)
826 blocksize = 1;
827 readcount = blocksize;
828
829 do
830 {
831 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
832 if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
833 {
834 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
835 return ERROR_JTAG_DEVICE_ERROR;
836 }
837
838 nbytes = MIN((readcount << 1), 4);
839
840 for (i = 0; i < nbytes; i++)
841 {
842 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
843 buffer++;
844 address++;
845 }
846
847 readcount -= (nbytes >> 1);
848 } while (readcount);
849 wcount -= blocksize;
850 }
851
852 return retval;
853 }
854
855 int mem_ap_read_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
856 {
857 uint32_t invalue, i;
858 int retval = ERROR_OK;
859
860 if (count >= 4)
861 return mem_ap_read_buf_packed_u16(swjdp, buffer, count, address);
862
863 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
864
865 while (count > 0)
866 {
867 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
868 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
869 retval = swjdp_transaction_endcheck(swjdp);
870 if (address & 0x1)
871 {
872 for (i = 0; i < 2; i++)
873 {
874 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
875 buffer++;
876 address++;
877 }
878 }
879 else
880 {
881 uint16_t svalue = (invalue >> 8 * (address & 0x3));
882 memcpy(buffer, &svalue, sizeof(uint16_t));
883 address += 2;
884 buffer += 2;
885 }
886 count -= 2;
887 }
888
889 return retval;
890 }
891
892 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
893 * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
894 *
895 * The solution is to arrange for a large out/in scan in this loop and
896 * and convert data afterwards.
897 */
898 int mem_ap_read_buf_packed_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
899 {
900 uint32_t invalue;
901 int retval = ERROR_OK;
902 int wcount, blocksize, readcount, i;
903
904 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
905
906 wcount = count;
907
908 while (wcount > 0)
909 {
910 int nbytes;
911
912 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
913 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
914
915 if (wcount < blocksize)
916 blocksize = wcount;
917
918 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
919 readcount = blocksize;
920
921 do
922 {
923 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
924 if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
925 {
926 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
927 return ERROR_JTAG_DEVICE_ERROR;
928 }
929
930 nbytes = MIN(readcount, 4);
931
932 for (i = 0; i < nbytes; i++)
933 {
934 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
935 buffer++;
936 address++;
937 }
938
939 readcount -= nbytes;
940 } while (readcount);
941 wcount -= blocksize;
942 }
943
944 return retval;
945 }
946
947 int mem_ap_read_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
948 {
949 uint32_t invalue;
950 int retval = ERROR_OK;
951
952 if (count >= 4)
953 return mem_ap_read_buf_packed_u8(swjdp, buffer, count, address);
954
955 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
956
957 while (count > 0)
958 {
959 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
960 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
961 retval = swjdp_transaction_endcheck(swjdp);
962 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
963 count--;
964 address++;
965 buffer++;
966 }
967
968 return retval;
969 }
970
971 /**
972 * Initialize a DAP.
973 *
974 * @todo Rename this. We also need an initialization scheme which account
975 * for SWD transports not just JTAG; that will need to address differences
976 * in layering. (JTAG is useful without any debug target; but not SWD.)
977 */
978 int ahbap_debugport_init(struct swjdp_common *swjdp)
979 {
980 uint32_t idreg, romaddr, dummy;
981 uint32_t ctrlstat;
982 int cnt = 0;
983 int retval;
984
985 LOG_DEBUG(" ");
986
987 /* Default MEM-AP setup.
988 *
989 * REVISIT AP #0 may be an inappropriate default for this.
990 * Should we probe, or receve a hint from the caller?
991 * Presumably we can ignore the possibility of multiple APs.
992 */
993 swjdp->apsel = 0;
994 swjdp->ap_csw_value = -1;
995 swjdp->ap_tar_value = -1;
996
997 /* DP initialization */
998 swjdp->trans_mode = TRANS_MODE_ATOMIC;
999 dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1000 dap_dp_write_reg(swjdp, SSTICKYERR, DP_CTRL_STAT);
1001 dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1002
1003 swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
1004
1005 dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
1006 dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
1007 if ((retval = jtag_execute_queue()) != ERROR_OK)
1008 return retval;
1009
1010 /* Check that we have debug power domains activated */
1011 while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
1012 {
1013 LOG_DEBUG("swjdp: wait CDBGPWRUPACK");
1014 dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
1015 if ((retval = jtag_execute_queue()) != ERROR_OK)
1016 return retval;
1017 alive_sleep(10);
1018 }
1019
1020 while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
1021 {
1022 LOG_DEBUG("swjdp: wait CSYSPWRUPACK");
1023 dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
1024 if ((retval = jtag_execute_queue()) != ERROR_OK)
1025 return retval;
1026 alive_sleep(10);
1027 }
1028
1029 dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1030 /* With debug power on we can activate OVERRUN checking */
1031 swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
1032 dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
1033 dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1034
1035 /*
1036 * REVISIT this isn't actually *initializing* anything in an AP,
1037 * and doesn't care if it's a MEM-AP at all (much less AHB-AP).
1038 * Should it? If the ROM address is valid, is this the right
1039 * place to scan the table and do any topology detection?
1040 */
1041 dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &idreg);
1042 dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &romaddr);
1043
1044 LOG_DEBUG("AHB-AP ID Register 0x%" PRIx32 ", Debug ROM Address 0x%" PRIx32 "", idreg, romaddr);
1045
1046 return ERROR_OK;
1047 }
1048
1049 /* CID interpretation -- see ARM IHI 0029B section 3
1050 * and ARM IHI 0031A table 13-3.
1051 */
1052 static const char *class_description[16] ={
1053 "Reserved", "ROM table", "Reserved", "Reserved",
1054 "Reserved", "Reserved", "Reserved", "Reserved",
1055 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
1056 "Reserved", "OptimoDE DESS",
1057 "Generic IP component", "PrimeCell or System component"
1058 };
1059
1060 static bool
1061 is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
1062 {
1063 return cid3 == 0xb1 && cid2 == 0x05
1064 && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
1065 }
1066
1067 int dap_info_command(struct command_context *cmd_ctx, struct swjdp_common *swjdp, int apsel)
1068 {
1069
1070 uint32_t dbgbase,apid;
1071 int romtable_present = 0;
1072 uint8_t mem_ap;
1073 uint32_t apselold;
1074
1075 apselold = swjdp->apsel;
1076 dap_ap_select(swjdp, apsel);
1077 dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &dbgbase);
1078 dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1079 swjdp_transaction_endcheck(swjdp);
1080 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1081 mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1082 command_print(cmd_ctx, "ap identification register 0x%8.8" PRIx32 "", apid);
1083 if (apid)
1084 {
1085 switch (apid&0x0F)
1086 {
1087 case 0:
1088 command_print(cmd_ctx, "\tType is jtag-ap");
1089 break;
1090 case 1:
1091 command_print(cmd_ctx, "\tType is mem-ap AHB");
1092 break;
1093 case 2:
1094 command_print(cmd_ctx, "\tType is mem-ap APB");
1095 break;
1096 default:
1097 command_print(cmd_ctx, "\tUnknown AP-type");
1098 break;
1099 }
1100 command_print(cmd_ctx, "ap debugbase 0x%8.8" PRIx32 "", dbgbase);
1101 }
1102 else
1103 {
1104 command_print(cmd_ctx, "No AP found at this apsel 0x%x", apsel);
1105 }
1106
1107 romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1108 if (romtable_present)
1109 {
1110 uint32_t cid0,cid1,cid2,cid3,memtype,romentry;
1111 uint16_t entry_offset;
1112
1113 /* bit 16 of apid indicates a memory access port */
1114 if (dbgbase & 0x02)
1115 command_print(cmd_ctx, "\tValid ROM table present");
1116 else
1117 command_print(cmd_ctx, "\tROM table in legacy format");
1118
1119 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1120 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
1121 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
1122 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
1123 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
1124 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
1125 swjdp_transaction_endcheck(swjdp);
1126 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1127 command_print(cmd_ctx, "\tCID3 0x%2.2" PRIx32
1128 ", CID2 0x%2.2" PRIx32
1129 ", CID1 0x%2.2" PRIx32
1130 ", CID0 0x%2.2" PRIx32,
1131 cid3, cid2, cid1, cid0);
1132 if (memtype & 0x01)
1133 command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
1134 else
1135 command_print(cmd_ctx, "\tMEMTYPE System memory not present. "
1136 "Dedicated debug bus.");
1137
1138 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1139 entry_offset = 0;
1140 do
1141 {
1142 mem_ap_read_atomic_u32(swjdp, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1143 command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry);
1144 if (romentry&0x01)
1145 {
1146 uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1147 uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1148 uint32_t component_start, component_base;
1149 unsigned part_num;
1150 char *type, *full;
1151
1152 component_base = (uint32_t)((dbgbase & 0xFFFFF000)
1153 + (int)(romentry & 0xFFFFF000));
1154 mem_ap_read_atomic_u32(swjdp,
1155 (component_base & 0xFFFFF000) | 0xFE0, &c_pid0);
1156 mem_ap_read_atomic_u32(swjdp,
1157 (component_base & 0xFFFFF000) | 0xFE4, &c_pid1);
1158 mem_ap_read_atomic_u32(swjdp,
1159 (component_base & 0xFFFFF000) | 0xFE8, &c_pid2);
1160 mem_ap_read_atomic_u32(swjdp,
1161 (component_base & 0xFFFFF000) | 0xFEC, &c_pid3);
1162 mem_ap_read_atomic_u32(swjdp,
1163 (component_base & 0xFFFFF000) | 0xFD0, &c_pid4);
1164 mem_ap_read_atomic_u32(swjdp,
1165 (component_base & 0xFFFFF000) | 0xFF0, &c_cid0);
1166 mem_ap_read_atomic_u32(swjdp,
1167 (component_base & 0xFFFFF000) | 0xFF4, &c_cid1);
1168 mem_ap_read_atomic_u32(swjdp,
1169 (component_base & 0xFFFFF000) | 0xFF8, &c_cid2);
1170 mem_ap_read_atomic_u32(swjdp,
1171 (component_base & 0xFFFFF000) | 0xFFC, &c_cid3);
1172 component_start = component_base - 0x1000*(c_pid4 >> 4);
1173
1174 command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32
1175 ", start address 0x%" PRIx32,
1176 component_base, component_start);
1177 command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
1178 (int) (c_cid1 >> 4) & 0xf,
1179 /* See ARM IHI 0029B Table 3-3 */
1180 class_description[(c_cid1 >> 4) & 0xf]);
1181
1182 /* CoreSight component? */
1183 if (((c_cid1 >> 4) & 0x0f) == 9) {
1184 uint32_t devtype;
1185 unsigned minor;
1186 char *major = "Reserved", *subtype = "Reserved";
1187
1188 mem_ap_read_atomic_u32(swjdp,
1189 (component_base & 0xfffff000) | 0xfcc,
1190 &devtype);
1191 minor = (devtype >> 4) & 0x0f;
1192 switch (devtype & 0x0f) {
1193 case 0:
1194 major = "Miscellaneous";
1195 switch (minor) {
1196 case 0:
1197 subtype = "other";
1198 break;
1199 case 4:
1200 subtype = "Validation component";
1201 break;
1202 }
1203 break;
1204 case 1:
1205 major = "Trace Sink";
1206 switch (minor) {
1207 case 0:
1208 subtype = "other";
1209 break;
1210 case 1:
1211 subtype = "Port";
1212 break;
1213 case 2:
1214 subtype = "Buffer";
1215 break;
1216 }
1217 break;
1218 case 2:
1219 major = "Trace Link";
1220 switch (minor) {
1221 case 0:
1222 subtype = "other";
1223 break;
1224 case 1:
1225 subtype = "Funnel, router";
1226 break;
1227 case 2:
1228 subtype = "Filter";
1229 break;
1230 case 3:
1231 subtype = "FIFO, buffer";
1232 break;
1233 }
1234 break;
1235 case 3:
1236 major = "Trace Source";
1237 switch (minor) {
1238 case 0:
1239 subtype = "other";
1240 break;
1241 case 1:
1242 subtype = "Processor";
1243 break;
1244 case 2:
1245 subtype = "DSP";
1246 break;
1247 case 3:
1248 subtype = "Engine/Coprocessor";
1249 break;
1250 case 4:
1251 subtype = "Bus";
1252 break;
1253 }
1254 break;
1255 case 4:
1256 major = "Debug Control";
1257 switch (minor) {
1258 case 0:
1259 subtype = "other";
1260 break;
1261 case 1:
1262 subtype = "Trigger Matrix";
1263 break;
1264 case 2:
1265 subtype = "Debug Auth";
1266 break;
1267 }
1268 break;
1269 case 5:
1270 major = "Debug Logic";
1271 switch (minor) {
1272 case 0:
1273 subtype = "other";
1274 break;
1275 case 1:
1276 subtype = "Processor";
1277 break;
1278 case 2:
1279 subtype = "DSP";
1280 break;
1281 case 3:
1282 subtype = "Engine/Coprocessor";
1283 break;
1284 }
1285 break;
1286 }
1287 command_print(cmd_ctx, "\t\tType is 0x%2.2x, %s, %s",
1288 (unsigned) (devtype & 0xff),
1289 major, subtype);
1290 /* REVISIT also show 0xfc8 DevId */
1291 }
1292
1293 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1294 command_print(cmd_ctx, "\t\tCID3 0x%2.2" PRIx32
1295 ", CID2 0x%2.2" PRIx32
1296 ", CID1 0x%2.2" PRIx32
1297 ", CID0 0x%2.2" PRIx32,
1298 c_cid3, c_cid2, c_cid1, c_cid0);
1299 command_print(cmd_ctx, "\t\tPeripheral ID[4..0] = hex "
1300 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1301 (int) c_pid4,
1302 (int) c_pid3, (int) c_pid2,
1303 (int) c_pid1, (int) c_pid0);
1304
1305 /* Part number interpretations are from Cortex
1306 * core specs, the CoreSight components TRM
1307 * (ARM DDI 0314H), and ETM specs; also from
1308 * chip observation (e.g. TI SDTI).
1309 */
1310 part_num = c_pid0 & 0xff;
1311 part_num |= (c_pid1 & 0x0f) << 8;
1312 switch (part_num) {
1313 case 0x000:
1314 type = "Cortex-M3 NVIC";
1315 full = "(Interrupt Controller)";
1316 break;
1317 case 0x001:
1318 type = "Cortex-M3 ITM";
1319 full = "(Instrumentation Trace Module)";
1320 break;
1321 case 0x002:
1322 type = "Cortex-M3 DWT";
1323 full = "(Data Watchpoint and Trace)";
1324 break;
1325 case 0x003:
1326 type = "Cortex-M3 FBP";
1327 full = "(Flash Patch and Breakpoint)";
1328 break;
1329 case 0x00d:
1330 type = "CoreSight ETM11";
1331 full = "(Embedded Trace)";
1332 break;
1333 // case 0x113: what?
1334 case 0x120: /* from OMAP3 memmap */
1335 type = "TI SDTI";
1336 full = "(System Debug Trace Interface)";
1337 break;
1338 case 0x343: /* from OMAP3 memmap */
1339 type = "TI DAPCTL";
1340 full = "";
1341 break;
1342 case 0x4e0:
1343 type = "Cortex-M3 ETM";
1344 full = "(Embedded Trace)";
1345 break;
1346 case 0x906:
1347 type = "Coresight CTI";
1348 full = "(Cross Trigger)";
1349 break;
1350 case 0x907:
1351 type = "Coresight ETB";
1352 full = "(Trace Buffer)";
1353 break;
1354 case 0x908:
1355 type = "Coresight CSTF";
1356 full = "(Trace Funnel)";
1357 break;
1358 case 0x910:
1359 type = "CoreSight ETM9";
1360 full = "(Embedded Trace)";
1361 break;
1362 case 0x912:
1363 type = "Coresight TPIU";
1364 full = "(Trace Port Interface Unit)";
1365 break;
1366 case 0x921:
1367 type = "Cortex-A8 ETM";
1368 full = "(Embedded Trace)";
1369 break;
1370 case 0x922:
1371 type = "Cortex-A8 CTI";
1372 full = "(Cross Trigger)";
1373 break;
1374 case 0x923:
1375 type = "Cortex-M3 TPIU";
1376 full = "(Trace Port Interface Unit)";
1377 break;
1378 case 0xc08:
1379 type = "Cortex-A8 Debug";
1380 full = "(Debug Unit)";
1381 break;
1382 default:
1383 type = "-*- unrecognized -*-";
1384 full = "";
1385 break;
1386 }
1387 command_print(cmd_ctx, "\t\tPart is %s %s",
1388 type, full);
1389 }
1390 else
1391 {
1392 if (romentry)
1393 command_print(cmd_ctx, "\t\tComponent not present");
1394 else
1395 command_print(cmd_ctx, "\t\tEnd of ROM table");
1396 }
1397 entry_offset += 4;
1398 } while (romentry > 0);
1399 }
1400 else
1401 {
1402 command_print(cmd_ctx, "\tNo ROM table present");
1403 }
1404 dap_ap_select(swjdp, apselold);
1405
1406 return ERROR_OK;
1407 }
1408
1409 DAP_COMMAND_HANDLER(dap_baseaddr_command)
1410 {
1411 uint32_t apsel, apselsave, baseaddr;
1412 int retval;
1413
1414 apselsave = swjdp->apsel;
1415 switch (CMD_ARGC) {
1416 case 0:
1417 apsel = swjdp->apsel;
1418 break;
1419 case 1:
1420 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1421 break;
1422 default:
1423 return ERROR_COMMAND_SYNTAX_ERROR;
1424 }
1425
1426 if (apselsave != apsel)
1427 dap_ap_select(swjdp, apsel);
1428
1429 dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &baseaddr);
1430 retval = swjdp_transaction_endcheck(swjdp);
1431 command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1432
1433 if (apselsave != apsel)
1434 dap_ap_select(swjdp, apselsave);
1435
1436 return retval;
1437 }
1438
1439 DAP_COMMAND_HANDLER(dap_memaccess_command)
1440 {
1441 uint32_t memaccess_tck;
1442
1443 switch (CMD_ARGC) {
1444 case 0:
1445 memaccess_tck = swjdp->memaccess_tck;
1446 break;
1447 case 1:
1448 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1449 break;
1450 default:
1451 return ERROR_COMMAND_SYNTAX_ERROR;
1452 }
1453 swjdp->memaccess_tck = memaccess_tck;
1454
1455 command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1456 swjdp->memaccess_tck);
1457
1458 return ERROR_OK;
1459 }
1460
1461 DAP_COMMAND_HANDLER(dap_apsel_command)
1462 {
1463 uint32_t apsel, apid;
1464 int retval;
1465
1466 switch (CMD_ARGC) {
1467 case 0:
1468 apsel = 0;
1469 break;
1470 case 1:
1471 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1472 break;
1473 default:
1474 return ERROR_COMMAND_SYNTAX_ERROR;
1475 }
1476
1477 dap_ap_select(swjdp, apsel);
1478 dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1479 retval = swjdp_transaction_endcheck(swjdp);
1480 command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1481 apsel, apid);
1482
1483 return retval;
1484 }
1485
1486 DAP_COMMAND_HANDLER(dap_apid_command)
1487 {
1488 uint32_t apsel, apselsave, apid;
1489 int retval;
1490
1491 apselsave = swjdp->apsel;
1492 switch (CMD_ARGC) {
1493 case 0:
1494 apsel = swjdp->apsel;
1495 break;
1496 case 1:
1497 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1498 break;
1499 default:
1500 return ERROR_COMMAND_SYNTAX_ERROR;
1501 }
1502
1503 if (apselsave != apsel)
1504 dap_ap_select(swjdp, apsel);
1505
1506 dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1507 retval = swjdp_transaction_endcheck(swjdp);
1508 command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1509 if (apselsave != apsel)
1510 dap_ap_select(swjdp, apselsave);
1511
1512 return retval;
1513 }
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