1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2008 by Hongtao Zheng *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
31 #include "target_type.h"
33 #include "arm_opcodes.h"
37 * NOTE: this holds code that's used with multiple ARM9 processors:
38 * - ARM9TDMI (ARMv4T) ... in ARM920, ARM922, and ARM940 cores
39 * - ARM9E-S (ARMv5TE) ... in ARM946, ARM966, and ARM968 cores
40 * - ARM9EJS (ARMv5TEJ) ... in ARM926 core
42 * In short, the file name is a misnomer ... it is NOT specific to
43 * that first generation ARM9 processor, or cores using it.
47 #define _DEBUG_INSTRUCTION_EXECUTION_
50 enum arm9tdmi_vector_bit
52 ARM9TDMI_RESET_VECTOR
= 0x01,
53 ARM9TDMI_UNDEF_VECTOR
= 0x02,
54 ARM9TDMI_SWI_VECTOR
= 0x04,
55 ARM9TDMI_PABT_VECTOR
= 0x08,
56 ARM9TDMI_DABT_VECTOR
= 0x10,
57 /* BIT(5) reserved -- must be zero */
58 ARM9TDMI_IRQ_VECTOR
= 0x40,
59 ARM9TDMI_FIQ_VECTOR
= 0x80,
62 static const struct arm9tdmi_vector
{
65 } arm9tdmi_vectors
[] = {
66 {"reset", ARM9TDMI_RESET_VECTOR
},
67 {"undef", ARM9TDMI_UNDEF_VECTOR
},
68 {"swi", ARM9TDMI_SWI_VECTOR
},
69 {"pabt", ARM9TDMI_PABT_VECTOR
},
70 {"dabt", ARM9TDMI_DABT_VECTOR
},
71 {"irq", ARM9TDMI_IRQ_VECTOR
},
72 {"fiq", ARM9TDMI_FIQ_VECTOR
},
76 int arm9tdmi_examine_debug_reason(struct target
*target
)
78 int retval
= ERROR_OK
;
79 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
81 /* only check the debug reason if we don't know it already */
82 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
83 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
))
85 struct scan_field fields
[3];
87 uint8_t instructionbus
[4];
90 fields
[0].num_bits
= 32;
91 fields
[0].out_value
= NULL
;
92 fields
[0].in_value
= databus
;
94 fields
[1].num_bits
= 3;
95 fields
[1].out_value
= NULL
;
96 fields
[1].in_value
= &debug_reason
;
98 fields
[2].num_bits
= 32;
99 fields
[2].out_value
= NULL
;
100 fields
[2].in_value
= instructionbus
;
102 if ((retval
= arm_jtag_scann(&arm7_9
->jtag_info
, 0x1, TAP_DRPAUSE
)) != ERROR_OK
)
106 retval
= arm_jtag_set_instr(&arm7_9
->jtag_info
, arm7_9
->jtag_info
.intest_instr
, NULL
, TAP_DRPAUSE
);
107 if (retval
!= ERROR_OK
)
110 jtag_add_dr_scan(arm7_9
->jtag_info
.tap
, 3, fields
, TAP_DRPAUSE
);
111 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
116 fields
[0].in_value
= NULL
;
117 fields
[0].out_value
= databus
;
118 fields
[1].in_value
= NULL
;
119 fields
[1].out_value
= &debug_reason
;
120 fields
[2].in_value
= NULL
;
121 fields
[2].out_value
= instructionbus
;
123 jtag_add_dr_scan(arm7_9
->jtag_info
.tap
, 3, fields
, TAP_DRPAUSE
);
125 if (debug_reason
& 0x4)
126 if (debug_reason
& 0x2)
127 target
->debug_reason
= DBG_REASON_WPTANDBKPT
;
129 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
131 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
137 /* put an instruction in the ARM9TDMI pipeline or write the data bus,
138 * and optionally read data
140 int arm9tdmi_clock_out(struct arm_jtag
*jtag_info
, uint32_t instr
,
141 uint32_t out
, uint32_t *in
, int sysspeed
)
143 int retval
= ERROR_OK
;
144 struct scan_field fields
[3];
146 uint8_t instr_buf
[4];
147 uint8_t sysspeed_buf
= 0x0;
150 buf_set_u32(out_buf
, 0, 32, out
);
152 buf_set_u32(instr_buf
, 0, 32, flip_u32(instr
, 32));
155 buf_set_u32(&sysspeed_buf
, 2, 1, 1);
157 if ((retval
= arm_jtag_scann(jtag_info
, 0x1, TAP_DRPAUSE
)) != ERROR_OK
)
162 retval
= arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
, TAP_DRPAUSE
);
163 if (retval
!= ERROR_OK
)
166 fields
[0].num_bits
= 32;
167 fields
[0].out_value
= out_buf
;
168 fields
[0].in_value
= NULL
;
170 fields
[1].num_bits
= 3;
171 fields
[1].out_value
= &sysspeed_buf
;
172 fields
[1].in_value
= NULL
;
174 fields
[2].num_bits
= 32;
175 fields
[2].out_value
= instr_buf
;
176 fields
[2].in_value
= NULL
;
180 fields
[0].in_value
= (uint8_t *)in
;
181 jtag_add_dr_scan(jtag_info
->tap
, 3, fields
, TAP_DRPAUSE
);
183 jtag_add_callback(arm_le_to_h_u32
, (jtag_callback_data_t
)in
);
187 jtag_add_dr_scan(jtag_info
->tap
, 3, fields
, TAP_DRPAUSE
);
190 jtag_add_runtest(0, TAP_DRPAUSE
);
192 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
194 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
201 LOG_DEBUG("instr: 0x%8.8x, out: 0x%8.8x, in: 0x%8.8x", instr
, out
, *in
);
204 LOG_DEBUG("instr: 0x%8.8x, out: 0x%8.8x", instr
, out
);
211 /* just read data (instruction and data-out = don't care) */
212 int arm9tdmi_clock_data_in(struct arm_jtag
*jtag_info
, uint32_t *in
)
214 int retval
= ERROR_OK
;;
215 struct scan_field fields
[3];
217 if ((retval
= arm_jtag_scann(jtag_info
, 0x1, TAP_DRPAUSE
)) != ERROR_OK
)
222 retval
= arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
, TAP_DRPAUSE
);
223 if (retval
!= ERROR_OK
)
226 fields
[0].num_bits
= 32;
227 fields
[0].out_value
= NULL
;
228 fields
[0].in_value
= (uint8_t *)in
;
230 fields
[1].num_bits
= 3;
231 fields
[1].out_value
= NULL
;
232 fields
[1].in_value
= NULL
;
234 fields
[2].num_bits
= 32;
235 fields
[2].out_value
= NULL
;
236 fields
[2].in_value
= NULL
;
238 jtag_add_dr_scan(jtag_info
->tap
, 3, fields
, TAP_DRPAUSE
);
240 jtag_add_callback(arm_le_to_h_u32
, (jtag_callback_data_t
)in
);
242 jtag_add_runtest(0, TAP_DRPAUSE
);
244 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
246 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
253 LOG_DEBUG("in: 0x%8.8x", *in
);
257 LOG_ERROR("BUG: called with in == NULL");
265 static int arm9endianness(jtag_callback_data_t arg
,
266 jtag_callback_data_t size
, jtag_callback_data_t be
,
267 jtag_callback_data_t captured
)
269 uint8_t *in
= (uint8_t *)arg
;
271 arm_endianness((uint8_t *)captured
, in
, (int)size
, (int)be
, 0);
275 /* clock the target, and read the databus
276 * the *in pointer points to a buffer where elements of 'size' bytes
277 * are stored in big (be == 1) or little (be == 0) endianness
279 int arm9tdmi_clock_data_in_endianness(struct arm_jtag
*jtag_info
,
280 void *in
, int size
, int be
)
282 int retval
= ERROR_OK
;
283 struct scan_field fields
[3];
285 if ((retval
= arm_jtag_scann(jtag_info
, 0x1, TAP_DRPAUSE
)) != ERROR_OK
)
290 retval
= arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
, TAP_DRPAUSE
);
291 if (retval
!= ERROR_OK
)
294 fields
[0].num_bits
= 32;
295 fields
[0].out_value
= NULL
;
296 fields
[0].in_value
= in
;
298 fields
[1].num_bits
= 3;
299 fields
[1].out_value
= NULL
;
300 fields
[1].in_value
= NULL
;
302 fields
[2].num_bits
= 32;
303 fields
[2].out_value
= NULL
;
304 fields
[2].in_value
= NULL
;
306 jtag_add_dr_scan(jtag_info
->tap
, 3, fields
, TAP_DRPAUSE
);
308 jtag_add_callback4(arm9endianness
,
309 (jtag_callback_data_t
)in
,
310 (jtag_callback_data_t
)size
,
311 (jtag_callback_data_t
)be
,
312 (jtag_callback_data_t
)in
);
314 jtag_add_runtest(0, TAP_DRPAUSE
);
316 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
318 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
325 LOG_DEBUG("in: 0x%8.8x", *(uint32_t*)in
);
329 LOG_ERROR("BUG: called with in == NULL");
337 static void arm9tdmi_change_to_arm(struct target
*target
,
338 uint32_t *r0
, uint32_t *pc
)
340 int retval
= ERROR_OK
;
341 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
342 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
344 /* save r0 before using it and put system in ARM state
345 * to allow common handling of ARM and THUMB debugging */
347 /* fetch STR r0, [r0] */
348 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_STR(0, 0), 0, NULL
, 0);
349 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
350 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
351 /* STR r0, [r0] in Memory */
352 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, r0
, 0);
354 /* MOV r0, r15 fetched, STR in Decode */
355 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_MOV(0, 15), 0, NULL
, 0);
356 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
357 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_STR(0, 0), 0, NULL
, 0);
358 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
359 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
360 /* nothing fetched, STR r0, [r0] in Memory */
361 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, pc
, 0);
363 /* use pc-relative LDR to clear r0[1:0] (for switch to ARM mode) */
364 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_LDR_PCREL(0), 0, NULL
, 0);
366 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
368 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
369 /* LDR in Memory (to account for interlock) */
370 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
373 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_BX(0), 0, NULL
, 0);
374 /* NOP fetched, BX in Decode, MOV in Execute */
375 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
376 /* NOP fetched, BX in Execute (1) */
377 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
379 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
384 /* fix program counter:
385 * MOV r0, r15 was the 5th instruction (+8)
386 * reading PC in Thumb state gives address of instruction + 4
391 void arm9tdmi_read_core_regs(struct target
*target
,
392 uint32_t mask
, uint32_t* core_regs
[16])
395 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
396 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
398 /* STMIA r0-15, [r0] at debug speed
399 * register values will start to appear on 4th DCLK
401 arm9tdmi_clock_out(jtag_info
, ARMV4_5_STMIA(0, mask
& 0xffff, 0, 0), 0, NULL
, 0);
403 /* fetch NOP, STM in DECODE stage */
404 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
405 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
406 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
408 for (i
= 0; i
<= 15; i
++)
411 /* nothing fetched, STM in MEMORY (i'th cycle) */
412 arm9tdmi_clock_data_in(jtag_info
, core_regs
[i
]);
416 static void arm9tdmi_read_core_regs_target_buffer(struct target
*target
,
417 uint32_t mask
, void* buffer
, int size
)
420 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
421 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
422 int be
= (target
->endianness
== TARGET_BIG_ENDIAN
) ? 1 : 0;
423 uint32_t *buf_u32
= buffer
;
424 uint16_t *buf_u16
= buffer
;
425 uint8_t *buf_u8
= buffer
;
427 /* STMIA r0-15, [r0] at debug speed
428 * register values will start to appear on 4th DCLK
430 arm9tdmi_clock_out(jtag_info
, ARMV4_5_STMIA(0, mask
& 0xffff, 0, 0), 0, NULL
, 0);
432 /* fetch NOP, STM in DECODE stage */
433 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
434 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
435 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
437 for (i
= 0; i
<= 15; i
++)
440 /* nothing fetched, STM in MEMORY (i'th cycle) */
444 arm9tdmi_clock_data_in_endianness(jtag_info
, buf_u32
++, 4, be
);
447 arm9tdmi_clock_data_in_endianness(jtag_info
, buf_u16
++, 2, be
);
450 arm9tdmi_clock_data_in_endianness(jtag_info
, buf_u8
++, 1, be
);
456 static void arm9tdmi_read_xpsr(struct target
*target
, uint32_t *xpsr
, int spsr
)
458 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
459 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
462 arm9tdmi_clock_out(jtag_info
, ARMV4_5_MRS(0, spsr
& 1), 0, NULL
, 0);
463 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
464 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
465 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
466 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
469 arm9tdmi_clock_out(jtag_info
, ARMV4_5_STR(0, 15), 0, NULL
, 0);
470 /* fetch NOP, STR in DECODE stage */
471 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
472 /* fetch NOP, STR in EXECUTE stage (1st cycle) */
473 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
474 /* nothing fetched, STR in MEMORY */
475 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, xpsr
, 0);
478 static void arm9tdmi_write_xpsr(struct target
*target
, uint32_t xpsr
, int spsr
)
480 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
481 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
483 LOG_DEBUG("xpsr: %8.8" PRIx32
", spsr: %i", xpsr
, spsr
);
486 arm9tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM(xpsr
& 0xff, 0, 1, spsr
), 0, NULL
, 0);
487 /* MSR2 fetched, MSR1 in DECODE */
488 arm9tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM((xpsr
& 0xff00) >> 8, 0xc, 2, spsr
), 0, NULL
, 0);
489 /* MSR3 fetched, MSR1 in EXECUTE (1), MSR2 in DECODE */
490 arm9tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM((xpsr
& 0xff0000) >> 16, 0x8, 4, spsr
), 0, NULL
, 0);
491 /* nothing fetched, MSR1 in EXECUTE (2) */
492 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
493 /* nothing fetched, MSR1 in EXECUTE (3) */
494 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
495 /* MSR4 fetched, MSR2 in EXECUTE (1), MSR3 in DECODE */
496 arm9tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM((xpsr
& 0xff000000) >> 24, 0x4, 8, spsr
), 0, NULL
, 0);
497 /* nothing fetched, MSR2 in EXECUTE (2) */
498 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
499 /* nothing fetched, MSR2 in EXECUTE (3) */
500 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
501 /* NOP fetched, MSR3 in EXECUTE (1), MSR4 in DECODE */
502 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
503 /* nothing fetched, MSR3 in EXECUTE (2) */
504 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
505 /* nothing fetched, MSR3 in EXECUTE (3) */
506 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
507 /* NOP fetched, MSR4 in EXECUTE (1) */
508 /* last MSR writes flags, which takes only one cycle */
509 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
512 static void arm9tdmi_write_xpsr_im8(struct target
*target
,
513 uint8_t xpsr_im
, int rot
, int spsr
)
515 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
516 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
518 LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im
, rot
, spsr
);
521 arm9tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM(xpsr_im
, rot
, 1, spsr
), 0, NULL
, 0);
522 /* NOP fetched, MSR in DECODE */
523 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
524 /* NOP fetched, MSR in EXECUTE (1) */
525 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
527 /* rot == 4 writes flags, which takes only one cycle */
530 /* nothing fetched, MSR in EXECUTE (2) */
531 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
532 /* nothing fetched, MSR in EXECUTE (3) */
533 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
537 void arm9tdmi_write_core_regs(struct target
*target
,
538 uint32_t mask
, uint32_t core_regs
[16])
541 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
542 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
544 /* LDMIA r0-15, [r0] at debug speed
545 * register values will start to appear on 4th DCLK
547 arm9tdmi_clock_out(jtag_info
, ARMV4_5_LDMIA(0, mask
& 0xffff, 0, 0), 0, NULL
, 0);
549 /* fetch NOP, LDM in DECODE stage */
550 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
551 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
552 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
554 for (i
= 0; i
<= 15; i
++)
557 /* nothing fetched, LDM still in EXECUTE (1 + i cycle) */
558 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, core_regs
[i
], NULL
, 0);
560 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
563 void arm9tdmi_load_word_regs(struct target
*target
, uint32_t mask
)
565 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
566 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
568 /* put system-speed load-multiple into the pipeline */
569 arm9tdmi_clock_out(jtag_info
, ARMV4_5_LDMIA(0, mask
& 0xffff, 0, 1), 0, NULL
, 0);
570 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
573 void arm9tdmi_load_hword_reg(struct target
*target
, int num
)
575 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
576 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
578 /* put system-speed load half-word into the pipeline */
579 arm9tdmi_clock_out(jtag_info
, ARMV4_5_LDRH_IP(num
, 0), 0, NULL
, 0);
580 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
583 void arm9tdmi_load_byte_reg(struct target
*target
, int num
)
585 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
586 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
588 /* put system-speed load byte into the pipeline */
589 arm9tdmi_clock_out(jtag_info
, ARMV4_5_LDRB_IP(num
, 0), 0, NULL
, 0);
590 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
593 void arm9tdmi_store_word_regs(struct target
*target
, uint32_t mask
)
595 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
596 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
598 /* put system-speed store-multiple into the pipeline */
599 arm9tdmi_clock_out(jtag_info
, ARMV4_5_STMIA(0, mask
, 0, 1), 0, NULL
, 0);
600 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
603 void arm9tdmi_store_hword_reg(struct target
*target
, int num
)
605 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
606 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
608 /* put system-speed store half-word into the pipeline */
609 arm9tdmi_clock_out(jtag_info
, ARMV4_5_STRH_IP(num
, 0), 0, NULL
, 0);
610 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
613 void arm9tdmi_store_byte_reg(struct target
*target
, int num
)
615 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
616 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
618 /* put system-speed store byte into the pipeline */
619 arm9tdmi_clock_out(jtag_info
, ARMV4_5_STRB_IP(num
, 0), 0, NULL
, 0);
620 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
623 static void arm9tdmi_write_pc(struct target
*target
, uint32_t pc
)
625 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
626 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
628 /* LDMIA r0-15, [r0] at debug speed
629 * register values will start to appear on 4th DCLK
631 arm9tdmi_clock_out(jtag_info
, ARMV4_5_LDMIA(0, 0x8000, 0, 0), 0, NULL
, 0);
633 /* fetch NOP, LDM in DECODE stage */
634 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
635 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
636 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
637 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) (output data) */
638 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, pc
, NULL
, 0);
639 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
640 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
641 /* fetch NOP, LDM in EXECUTE stage (4th cycle) */
642 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
643 /* fetch NOP, LDM in EXECUTE stage (5th cycle) */
644 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
647 void arm9tdmi_branch_resume(struct target
*target
)
649 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
650 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
652 arm9tdmi_clock_out(jtag_info
, ARMV4_5_B(0xfffffc, 0), 0, NULL
, 0);
653 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
656 static void arm9tdmi_branch_resume_thumb(struct target
*target
)
660 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
661 struct arm
*armv4_5
= &arm7_9
->armv4_5_common
;
662 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
663 struct reg
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
665 /* LDMIA r0-15, [r0] at debug speed
666 * register values will start to appear on 4th DCLK
668 arm9tdmi_clock_out(jtag_info
, ARMV4_5_LDMIA(0, 0x1, 0, 0), 0, NULL
, 0);
670 /* fetch NOP, LDM in DECODE stage */
671 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
672 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
673 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
674 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) */
675 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
,
676 buf_get_u32(armv4_5
->pc
->value
, 0, 32) | 1, NULL
, 0);
677 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
678 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
680 /* Branch and eXchange */
681 arm9tdmi_clock_out(jtag_info
, ARMV4_5_BX(0), 0, NULL
, 0);
683 embeddedice_read_reg(dbg_stat
);
685 /* fetch NOP, BX in DECODE stage */
686 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
688 embeddedice_read_reg(dbg_stat
);
690 /* fetch NOP, BX in EXECUTE stage (1st cycle) */
691 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
693 /* target is now in Thumb state */
694 embeddedice_read_reg(dbg_stat
);
696 /* load r0 value, MOV_IM in Decode*/
697 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_LDR_PCREL(0), 0, NULL
, 0);
698 /* fetch NOP, LDR in Decode, MOV_IM in Execute */
699 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
700 /* fetch NOP, LDR in Execute */
701 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
702 /* nothing fetched, LDR in EXECUTE stage (2nd cycle) */
703 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, buf_get_u32(armv4_5
->core_cache
->reg_list
[0].value
, 0, 32), NULL
, 0);
704 /* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
705 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
707 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
708 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
710 embeddedice_read_reg(dbg_stat
);
712 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_B(0x7f7), 0, NULL
, 1);
713 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
716 void arm9tdmi_enable_single_step(struct target
*target
, uint32_t next_pc
)
718 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
720 if (arm7_9
->has_single_step
)
722 buf_set_u32(arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
].value
, 3, 1, 1);
723 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
]);
727 arm7_9_enable_eice_step(target
, next_pc
);
731 void arm9tdmi_disable_single_step(struct target
*target
)
733 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
735 if (arm7_9
->has_single_step
)
737 buf_set_u32(arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
].value
, 3, 1, 0);
738 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
]);
742 arm7_9_disable_eice_step(target
);
746 static void arm9tdmi_build_reg_cache(struct target
*target
)
748 struct reg_cache
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
749 struct arm
*armv4_5
= target_to_arm(target
);
751 (*cache_p
) = arm_build_reg_cache(target
, armv4_5
);
754 int arm9tdmi_init_target(struct command_context
*cmd_ctx
,
755 struct target
*target
)
757 arm9tdmi_build_reg_cache(target
);
761 int arm9tdmi_init_arch_info(struct target
*target
,
762 struct arm7_9_common
*arm7_9
, struct jtag_tap
*tap
)
764 /* prepare JTAG information for the new target */
765 arm7_9
->jtag_info
.tap
= tap
;
766 arm7_9
->jtag_info
.scann_size
= 5;
768 /* register arch-specific functions */
769 arm7_9
->examine_debug_reason
= arm9tdmi_examine_debug_reason
;
770 arm7_9
->change_to_arm
= arm9tdmi_change_to_arm
;
771 arm7_9
->read_core_regs
= arm9tdmi_read_core_regs
;
772 arm7_9
->read_core_regs_target_buffer
= arm9tdmi_read_core_regs_target_buffer
;
773 arm7_9
->read_xpsr
= arm9tdmi_read_xpsr
;
775 arm7_9
->write_xpsr
= arm9tdmi_write_xpsr
;
776 arm7_9
->write_xpsr_im8
= arm9tdmi_write_xpsr_im8
;
777 arm7_9
->write_core_regs
= arm9tdmi_write_core_regs
;
779 arm7_9
->load_word_regs
= arm9tdmi_load_word_regs
;
780 arm7_9
->load_hword_reg
= arm9tdmi_load_hword_reg
;
781 arm7_9
->load_byte_reg
= arm9tdmi_load_byte_reg
;
783 arm7_9
->store_word_regs
= arm9tdmi_store_word_regs
;
784 arm7_9
->store_hword_reg
= arm9tdmi_store_hword_reg
;
785 arm7_9
->store_byte_reg
= arm9tdmi_store_byte_reg
;
787 arm7_9
->write_pc
= arm9tdmi_write_pc
;
788 arm7_9
->branch_resume
= arm9tdmi_branch_resume
;
789 arm7_9
->branch_resume_thumb
= arm9tdmi_branch_resume_thumb
;
791 arm7_9
->enable_single_step
= arm9tdmi_enable_single_step
;
792 arm7_9
->disable_single_step
= arm9tdmi_disable_single_step
;
794 arm7_9
->post_debug_entry
= NULL
;
796 arm7_9
->pre_restore_context
= NULL
;
798 /* initialize arch-specific breakpoint handling */
799 arm7_9
->arm_bkpt
= 0xdeeedeee;
800 arm7_9
->thumb_bkpt
= 0xdeee;
802 arm7_9
->dbgreq_adjust_pc
= 3;
804 arm7_9_init_arch_info(target
, arm7_9
);
806 /* override use of DBGRQ, this is safe on ARM9TDMI */
807 arm7_9
->use_dbgrq
= 1;
809 /* all ARM9s have the vector catch register */
810 arm7_9
->has_vector_catch
= 1;
815 static int arm9tdmi_target_create(struct target
*target
, Jim_Interp
*interp
)
817 struct arm7_9_common
*arm7_9
= calloc(1,sizeof(struct arm7_9_common
));
819 arm9tdmi_init_arch_info(target
, arm7_9
, target
->tap
);
820 arm7_9
->armv4_5_common
.is_armv4
= true;
825 COMMAND_HANDLER(handle_arm9tdmi_catch_vectors_command
)
827 struct target
*target
= get_current_target(CMD_CTX
);
828 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
829 struct reg
*vector_catch
;
830 uint32_t vector_catch_value
;
832 if (!target_was_examined(target
))
834 LOG_ERROR("Target not examined yet");
838 /* it's uncommon, but some ARM7 chips can support this */
839 if (arm7_9
->common_magic
!= ARM7_9_COMMON_MAGIC
840 || !arm7_9
->has_vector_catch
) {
841 command_print(CMD_CTX
, "target doesn't have EmbeddedICE "
842 "with vector_catch");
843 return ERROR_TARGET_INVALID
;
846 vector_catch
= &arm7_9
->eice_cache
->reg_list
[EICE_VEC_CATCH
];
848 /* read the vector catch register if necessary */
849 if (!vector_catch
->valid
)
850 embeddedice_read_reg(vector_catch
);
852 /* get the current setting */
853 vector_catch_value
= buf_get_u32(vector_catch
->value
, 0, 8);
857 vector_catch_value
= 0x0;
858 if (strcmp(CMD_ARGV
[0], "all") == 0)
860 vector_catch_value
= 0xdf;
862 else if (strcmp(CMD_ARGV
[0], "none") == 0)
868 for (unsigned i
= 0; i
< CMD_ARGC
; i
++)
870 /* go through list of vectors */
872 for (j
= 0; arm9tdmi_vectors
[j
].name
; j
++)
874 if (strcmp(CMD_ARGV
[i
], arm9tdmi_vectors
[j
].name
) == 0)
876 vector_catch_value
|= arm9tdmi_vectors
[j
].value
;
881 /* complain if vector wasn't found */
882 if (!arm9tdmi_vectors
[j
].name
)
884 command_print(CMD_CTX
, "vector '%s' not found, leaving current setting unchanged", CMD_ARGV
[i
]);
886 /* reread current setting */
887 vector_catch_value
= buf_get_u32(
896 /* store new settings */
897 buf_set_u32(vector_catch
->value
, 0, 8, vector_catch_value
);
898 embeddedice_store_reg(vector_catch
);
901 /* output current settings */
902 for (unsigned i
= 0; arm9tdmi_vectors
[i
].name
; i
++) {
903 command_print(CMD_CTX
, "%s: %s", arm9tdmi_vectors
[i
].name
,
904 (vector_catch_value
& arm9tdmi_vectors
[i
].value
)
905 ? "catch" : "don't catch");
911 static const struct command_registration arm9tdmi_exec_command_handlers
[] = {
913 .name
= "vector_catch",
914 .handler
= handle_arm9tdmi_catch_vectors_command
,
915 .mode
= COMMAND_EXEC
,
916 .help
= "Display, after optionally updating, configuration "
917 "of vector catch unit.",
918 .usage
= "[all|none|(reset|undef|swi|pabt|dabt|irq|fiq)*]",
920 COMMAND_REGISTRATION_DONE
922 const struct command_registration arm9tdmi_command_handlers
[] = {
924 .chain
= arm7_9_command_handlers
,
929 .help
= "arm9 command group",
930 .chain
= arm9tdmi_exec_command_handlers
,
932 COMMAND_REGISTRATION_DONE
935 /** Holds methods for ARM9TDMI targets. */
936 struct target_type arm9tdmi_target
=
941 .arch_state
= arm_arch_state
,
943 .target_request_data
= arm7_9_target_request_data
,
946 .resume
= arm7_9_resume
,
949 .assert_reset
= arm7_9_assert_reset
,
950 .deassert_reset
= arm7_9_deassert_reset
,
951 .soft_reset_halt
= arm7_9_soft_reset_halt
,
953 .get_gdb_reg_list
= arm_get_gdb_reg_list
,
955 .read_memory
= arm7_9_read_memory
,
956 .write_memory
= arm7_9_write_memory
,
957 .bulk_write_memory
= arm7_9_bulk_write_memory
,
959 .checksum_memory
= arm_checksum_memory
,
960 .blank_check_memory
= arm_blank_check_memory
,
962 .run_algorithm
= armv4_5_run_algorithm
,
964 .add_breakpoint
= arm7_9_add_breakpoint
,
965 .remove_breakpoint
= arm7_9_remove_breakpoint
,
966 .add_watchpoint
= arm7_9_add_watchpoint
,
967 .remove_watchpoint
= arm7_9_remove_watchpoint
,
969 .commands
= arm9tdmi_command_handlers
,
970 .target_create
= arm9tdmi_target_create
,
971 .init_target
= arm9tdmi_init_target
,
972 .examine
= arm7_9_examine
,
973 .check_reset
= arm7_9_check_reset
,
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