1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
26 #include "arm7_9_common.h"
30 #include "embeddedice.h"
41 #define _DEBUG_INSTRUCTION_EXECUTION_
45 int arm9tdmi_register_commands(struct command_context_s
*cmd_ctx
);
46 int handle_arm9tdmi_catch_vectors_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
48 /* forward declarations */
49 int arm9tdmi_target_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct target_s
*target
);
50 int arm9tdmi_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
);
53 target_type_t arm9tdmi_target
=
58 .arch_state
= armv4_5_arch_state
,
60 .target_request_data
= arm7_9_target_request_data
,
63 .resume
= arm7_9_resume
,
66 .assert_reset
= arm7_9_assert_reset
,
67 .deassert_reset
= arm7_9_deassert_reset
,
68 .soft_reset_halt
= arm7_9_soft_reset_halt
,
70 .get_gdb_reg_list
= armv4_5_get_gdb_reg_list
,
72 .read_memory
= arm7_9_read_memory
,
73 .write_memory
= arm7_9_write_memory
,
74 .bulk_write_memory
= arm7_9_bulk_write_memory
,
75 .checksum_memory
= arm7_9_checksum_memory
,
76 .blank_check_memory
= arm7_9_blank_check_memory
,
78 .run_algorithm
= armv4_5_run_algorithm
,
80 .add_breakpoint
= arm7_9_add_breakpoint
,
81 .remove_breakpoint
= arm7_9_remove_breakpoint
,
82 .add_watchpoint
= arm7_9_add_watchpoint
,
83 .remove_watchpoint
= arm7_9_remove_watchpoint
,
85 .register_commands
= arm9tdmi_register_commands
,
86 .target_command
= arm9tdmi_target_command
,
87 .init_target
= arm9tdmi_init_target
,
88 .examine
= arm9tdmi_examine
,
92 arm9tdmi_vector_t arm9tdmi_vectors
[] =
94 {"reset", ARM9TDMI_RESET_VECTOR
},
95 {"undef", ARM9TDMI_UNDEF_VECTOR
},
96 {"swi", ARM9TDMI_SWI_VECTOR
},
97 {"pabt", ARM9TDMI_PABT_VECTOR
},
98 {"dabt", ARM9TDMI_DABT_VECTOR
},
99 {"reserved", ARM9TDMI_RESERVED_VECTOR
},
100 {"irq", ARM9TDMI_IRQ_VECTOR
},
101 {"fiq", ARM9TDMI_FIQ_VECTOR
},
105 int arm9tdmi_examine_debug_reason(target_t
*target
)
107 /* get pointers to arch-specific information */
108 armv4_5_common_t
*armv4_5
= target
->arch_info
;
109 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
111 /* only check the debug reason if we don't know it already */
112 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
113 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
))
115 scan_field_t fields
[3];
117 u8 instructionbus
[4];
120 jtag_add_end_state(TAP_PD
);
122 fields
[0].device
= arm7_9
->jtag_info
.chain_pos
;
123 fields
[0].num_bits
= 32;
124 fields
[0].out_value
= NULL
;
125 fields
[0].out_mask
= NULL
;
126 fields
[0].in_value
= databus
;
127 fields
[0].in_check_value
= NULL
;
128 fields
[0].in_check_mask
= NULL
;
129 fields
[0].in_handler
= NULL
;
130 fields
[0].in_handler_priv
= NULL
;
132 fields
[1].device
= arm7_9
->jtag_info
.chain_pos
;
133 fields
[1].num_bits
= 3;
134 fields
[1].out_value
= NULL
;
135 fields
[1].out_mask
= NULL
;
136 fields
[1].in_value
= &debug_reason
;
137 fields
[1].in_check_value
= NULL
;
138 fields
[1].in_check_mask
= NULL
;
139 fields
[1].in_handler
= NULL
;
140 fields
[1].in_handler_priv
= NULL
;
142 fields
[2].device
= arm7_9
->jtag_info
.chain_pos
;
143 fields
[2].num_bits
= 32;
144 fields
[2].out_value
= NULL
;
145 fields
[2].out_mask
= NULL
;
146 fields
[2].in_value
= instructionbus
;
147 fields
[2].in_check_value
= NULL
;
148 fields
[2].in_check_mask
= NULL
;
149 fields
[2].in_handler
= NULL
;
150 fields
[2].in_handler_priv
= NULL
;
152 arm_jtag_scann(&arm7_9
->jtag_info
, 0x1);
153 arm_jtag_set_instr(&arm7_9
->jtag_info
, arm7_9
->jtag_info
.intest_instr
, NULL
);
155 jtag_add_dr_scan(3, fields
, TAP_PD
);
156 jtag_execute_queue();
158 fields
[0].in_value
= NULL
;
159 fields
[0].out_value
= databus
;
160 fields
[1].in_value
= NULL
;
161 fields
[1].out_value
= &debug_reason
;
162 fields
[2].in_value
= NULL
;
163 fields
[2].out_value
= instructionbus
;
165 jtag_add_dr_scan(3, fields
, TAP_PD
);
167 if (debug_reason
& 0x4)
168 if (debug_reason
& 0x2)
169 target
->debug_reason
= DBG_REASON_WPTANDBKPT
;
171 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
173 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
179 /* put an instruction in the ARM9TDMI pipeline or write the data bus, and optionally read data */
180 int arm9tdmi_clock_out(arm_jtag_t
*jtag_info
, u32 instr
, u32 out
, u32
*in
, int sysspeed
)
182 scan_field_t fields
[3];
185 u8 sysspeed_buf
= 0x0;
188 buf_set_u32(out_buf
, 0, 32, out
);
190 buf_set_u32(instr_buf
, 0, 32, flip_u32(instr
, 32));
193 buf_set_u32(&sysspeed_buf
, 2, 1, 1);
195 jtag_add_end_state(TAP_PD
);
196 arm_jtag_scann(jtag_info
, 0x1);
198 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
200 fields
[0].device
= jtag_info
->chain_pos
;
201 fields
[0].num_bits
= 32;
202 fields
[0].out_value
= out_buf
;
203 fields
[0].out_mask
= NULL
;
204 fields
[0].in_value
= NULL
;
207 fields
[0].in_handler
= arm_jtag_buf_to_u32
;
208 fields
[0].in_handler_priv
= in
;
212 fields
[0].in_handler
= NULL
;
213 fields
[0].in_handler_priv
= NULL
;
215 fields
[0].in_check_value
= NULL
;
216 fields
[0].in_check_mask
= NULL
;
218 fields
[1].device
= jtag_info
->chain_pos
;
219 fields
[1].num_bits
= 3;
220 fields
[1].out_value
= &sysspeed_buf
;
221 fields
[1].out_mask
= NULL
;
222 fields
[1].in_value
= NULL
;
223 fields
[1].in_check_value
= NULL
;
224 fields
[1].in_check_mask
= NULL
;
225 fields
[1].in_handler
= NULL
;
226 fields
[1].in_handler_priv
= NULL
;
228 fields
[2].device
= jtag_info
->chain_pos
;
229 fields
[2].num_bits
= 32;
230 fields
[2].out_value
= instr_buf
;
231 fields
[2].out_mask
= NULL
;
232 fields
[2].in_value
= NULL
;
233 fields
[2].in_check_value
= NULL
;
234 fields
[2].in_check_mask
= NULL
;
235 fields
[2].in_handler
= NULL
;
236 fields
[2].in_handler_priv
= NULL
;
238 jtag_add_dr_scan(3, fields
, -1);
240 jtag_add_runtest(0, -1);
242 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
244 jtag_execute_queue();
248 LOG_DEBUG("instr: 0x%8.8x, out: 0x%8.8x, in: 0x%8.8x", instr
, out
, *in
);
251 LOG_DEBUG("instr: 0x%8.8x, out: 0x%8.8x", instr
, out
);
258 /* just read data (instruction and data-out = don't care) */
259 int arm9tdmi_clock_data_in(arm_jtag_t
*jtag_info
, u32
*in
)
261 scan_field_t fields
[3];
263 jtag_add_end_state(TAP_PD
);
264 arm_jtag_scann(jtag_info
, 0x1);
266 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
268 fields
[0].device
= jtag_info
->chain_pos
;
269 fields
[0].num_bits
= 32;
270 fields
[0].out_value
= NULL
;
271 fields
[0].out_mask
= NULL
;
272 fields
[0].in_value
= NULL
;
273 fields
[0].in_handler
= arm_jtag_buf_to_u32
;
274 fields
[0].in_handler_priv
= in
;
275 fields
[0].in_check_value
= NULL
;
276 fields
[0].in_check_mask
= NULL
;
278 fields
[1].device
= jtag_info
->chain_pos
;
279 fields
[1].num_bits
= 3;
280 fields
[1].out_value
= NULL
;
281 fields
[1].out_mask
= NULL
;
282 fields
[1].in_value
= NULL
;
283 fields
[1].in_handler
= NULL
;
284 fields
[1].in_handler_priv
= NULL
;
285 fields
[1].in_check_value
= NULL
;
286 fields
[1].in_check_mask
= NULL
;
288 fields
[2].device
= jtag_info
->chain_pos
;
289 fields
[2].num_bits
= 32;
290 fields
[2].out_value
= NULL
;
291 fields
[2].out_mask
= NULL
;
292 fields
[2].in_value
= NULL
;
293 fields
[2].in_check_value
= NULL
;
294 fields
[2].in_check_mask
= NULL
;
295 fields
[2].in_handler
= NULL
;
296 fields
[2].in_handler_priv
= NULL
;
298 jtag_add_dr_scan(3, fields
, -1);
300 jtag_add_runtest(0, -1);
302 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
304 jtag_execute_queue();
308 LOG_DEBUG("in: 0x%8.8x", *in
);
312 LOG_ERROR("BUG: called with in == NULL");
320 /* clock the target, and read the databus
321 * the *in pointer points to a buffer where elements of 'size' bytes
322 * are stored in big (be==1) or little (be==0) endianness
324 int arm9tdmi_clock_data_in_endianness(arm_jtag_t
*jtag_info
, void *in
, int size
, int be
)
326 scan_field_t fields
[3];
328 jtag_add_end_state(TAP_PD
);
329 arm_jtag_scann(jtag_info
, 0x1);
331 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
333 fields
[0].device
= jtag_info
->chain_pos
;
334 fields
[0].num_bits
= 32;
335 fields
[0].out_value
= NULL
;
336 fields
[0].out_mask
= NULL
;
337 fields
[0].in_value
= NULL
;
341 fields
[0].in_handler
= (be
) ? arm_jtag_buf_to_be32
: arm_jtag_buf_to_le32
;
344 fields
[0].in_handler
= (be
) ? arm_jtag_buf_to_be16
: arm_jtag_buf_to_le16
;
347 fields
[0].in_handler
= arm_jtag_buf_to_8
;
350 fields
[0].in_handler_priv
= in
;
351 fields
[0].in_check_value
= NULL
;
352 fields
[0].in_check_mask
= NULL
;
354 fields
[1].device
= jtag_info
->chain_pos
;
355 fields
[1].num_bits
= 3;
356 fields
[1].out_value
= NULL
;
357 fields
[1].out_mask
= NULL
;
358 fields
[1].in_value
= NULL
;
359 fields
[1].in_handler
= NULL
;
360 fields
[1].in_handler_priv
= NULL
;
361 fields
[1].in_check_value
= NULL
;
362 fields
[1].in_check_mask
= NULL
;
364 fields
[2].device
= jtag_info
->chain_pos
;
365 fields
[2].num_bits
= 32;
366 fields
[2].out_value
= NULL
;
367 fields
[2].out_mask
= NULL
;
368 fields
[2].in_value
= NULL
;
369 fields
[2].in_check_value
= NULL
;
370 fields
[2].in_check_mask
= NULL
;
371 fields
[2].in_handler
= NULL
;
372 fields
[2].in_handler_priv
= NULL
;
374 jtag_add_dr_scan(3, fields
, -1);
376 jtag_add_runtest(0, -1);
378 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
380 jtag_execute_queue();
384 LOG_DEBUG("in: 0x%8.8x", *in
);
388 LOG_ERROR("BUG: called with in == NULL");
396 void arm9tdmi_change_to_arm(target_t
*target
, u32
*r0
, u32
*pc
)
398 /* get pointers to arch-specific information */
399 armv4_5_common_t
*armv4_5
= target
->arch_info
;
400 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
401 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
403 /* save r0 before using it and put system in ARM state
404 * to allow common handling of ARM and THUMB debugging */
406 /* fetch STR r0, [r0] */
407 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_STR(0, 0), 0, NULL
, 0);
408 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
409 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
410 /* STR r0, [r0] in Memory */
411 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, r0
, 0);
413 /* MOV r0, r15 fetched, STR in Decode */
414 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_MOV(0, 15), 0, NULL
, 0);
415 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
416 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_STR(0, 0), 0, NULL
, 0);
417 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
418 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
419 /* nothing fetched, STR r0, [r0] in Memory */
420 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, pc
, 0);
422 /* use pc-relative LDR to clear r0[1:0] (for switch to ARM mode) */
423 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_LDR_PCREL(0), 0, NULL
, 0);
425 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
427 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
428 /* LDR in Memory (to account for interlock) */
429 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
432 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_BX(0), 0, NULL
, 0);
433 /* NOP fetched, BX in Decode, MOV in Execute */
434 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
435 /* NOP fetched, BX in Execute (1) */
436 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
438 jtag_execute_queue();
440 /* fix program counter:
441 * MOV r0, r15 was the 5th instruction (+8)
442 * reading PC in Thumb state gives address of instruction + 4
447 void arm9tdmi_read_core_regs(target_t
*target
, u32 mask
, u32
* core_regs
[16])
450 /* get pointers to arch-specific information */
451 armv4_5_common_t
*armv4_5
= target
->arch_info
;
452 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
453 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
455 /* STMIA r0-15, [r0] at debug speed
456 * register values will start to appear on 4th DCLK
458 arm9tdmi_clock_out(jtag_info
, ARMV4_5_STMIA(0, mask
& 0xffff, 0, 0), 0, NULL
, 0);
460 /* fetch NOP, STM in DECODE stage */
461 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
462 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
463 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
465 for (i
= 0; i
<= 15; i
++)
468 /* nothing fetched, STM in MEMORY (i'th cycle) */
469 arm9tdmi_clock_data_in(jtag_info
, core_regs
[i
]);
474 void arm9tdmi_read_core_regs_target_buffer(target_t
*target
, u32 mask
, void* buffer
, int size
)
477 /* get pointers to arch-specific information */
478 armv4_5_common_t
*armv4_5
= target
->arch_info
;
479 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
480 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
481 int be
= (target
->endianness
== TARGET_BIG_ENDIAN
) ? 1 : 0;
482 u32
*buf_u32
= buffer
;
483 u16
*buf_u16
= buffer
;
486 /* STMIA r0-15, [r0] at debug speed
487 * register values will start to appear on 4th DCLK
489 arm9tdmi_clock_out(jtag_info
, ARMV4_5_STMIA(0, mask
& 0xffff, 0, 0), 0, NULL
, 0);
491 /* fetch NOP, STM in DECODE stage */
492 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
493 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
494 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
496 for (i
= 0; i
<= 15; i
++)
499 /* nothing fetched, STM in MEMORY (i'th cycle) */
503 arm9tdmi_clock_data_in_endianness(jtag_info
, buf_u32
++, 4, be
);
506 arm9tdmi_clock_data_in_endianness(jtag_info
, buf_u16
++, 2, be
);
509 arm9tdmi_clock_data_in_endianness(jtag_info
, buf_u8
++, 1, be
);
516 void arm9tdmi_read_xpsr(target_t
*target
, u32
*xpsr
, int spsr
)
518 /* get pointers to arch-specific information */
519 armv4_5_common_t
*armv4_5
= target
->arch_info
;
520 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
521 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
524 arm9tdmi_clock_out(jtag_info
, ARMV4_5_MRS(0, spsr
& 1), 0, NULL
, 0);
525 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
526 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
527 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
528 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
531 arm9tdmi_clock_out(jtag_info
, ARMV4_5_STR(0, 15), 0, NULL
, 0);
532 /* fetch NOP, STR in DECODE stage */
533 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
534 /* fetch NOP, STR in EXECUTE stage (1st cycle) */
535 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
536 /* nothing fetched, STR in MEMORY */
537 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, xpsr
, 0);
541 void arm9tdmi_write_xpsr(target_t
*target
, u32 xpsr
, int spsr
)
543 /* get pointers to arch-specific information */
544 armv4_5_common_t
*armv4_5
= target
->arch_info
;
545 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
546 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
548 LOG_DEBUG("xpsr: %8.8x, spsr: %i", xpsr
, spsr
);
551 arm9tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM(xpsr
& 0xff, 0, 1, spsr
), 0, NULL
, 0);
552 /* MSR2 fetched, MSR1 in DECODE */
553 arm9tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM((xpsr
& 0xff00) >> 8, 0xc, 2, spsr
), 0, NULL
, 0);
554 /* MSR3 fetched, MSR1 in EXECUTE (1), MSR2 in DECODE */
555 arm9tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM((xpsr
& 0xff0000) >> 16, 0x8, 4, spsr
), 0, NULL
, 0);
556 /* nothing fetched, MSR1 in EXECUTE (2) */
557 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
558 /* nothing fetched, MSR1 in EXECUTE (3) */
559 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
560 /* MSR4 fetched, MSR2 in EXECUTE (1), MSR3 in DECODE */
561 arm9tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM((xpsr
& 0xff000000) >> 24, 0x4, 8, spsr
), 0, NULL
, 0);
562 /* nothing fetched, MSR2 in EXECUTE (2) */
563 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
564 /* nothing fetched, MSR2 in EXECUTE (3) */
565 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
566 /* NOP fetched, MSR3 in EXECUTE (1), MSR4 in DECODE */
567 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
568 /* nothing fetched, MSR3 in EXECUTE (2) */
569 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
570 /* nothing fetched, MSR3 in EXECUTE (3) */
571 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
572 /* NOP fetched, MSR4 in EXECUTE (1) */
573 /* last MSR writes flags, which takes only one cycle */
574 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
577 void arm9tdmi_write_xpsr_im8(target_t
*target
, u8 xpsr_im
, int rot
, int spsr
)
579 /* get pointers to arch-specific information */
580 armv4_5_common_t
*armv4_5
= target
->arch_info
;
581 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
582 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
584 LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im
, rot
, spsr
);
587 arm9tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM(xpsr_im
, rot
, 1, spsr
), 0, NULL
, 0);
588 /* NOP fetched, MSR in DECODE */
589 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
590 /* NOP fetched, MSR in EXECUTE (1) */
591 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
593 /* rot == 4 writes flags, which takes only one cycle */
596 /* nothing fetched, MSR in EXECUTE (2) */
597 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
598 /* nothing fetched, MSR in EXECUTE (3) */
599 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
603 void arm9tdmi_write_core_regs(target_t
*target
, u32 mask
, u32 core_regs
[16])
606 /* get pointers to arch-specific information */
607 armv4_5_common_t
*armv4_5
= target
->arch_info
;
608 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
609 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
611 /* LDMIA r0-15, [r0] at debug speed
612 * register values will start to appear on 4th DCLK
614 arm9tdmi_clock_out(jtag_info
, ARMV4_5_LDMIA(0, mask
& 0xffff, 0, 0), 0, NULL
, 0);
616 /* fetch NOP, LDM in DECODE stage */
617 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
618 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
619 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
621 for (i
= 0; i
<= 15; i
++)
624 /* nothing fetched, LDM still in EXECUTE (1+i cycle) */
625 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, core_regs
[i
], NULL
, 0);
627 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
631 void arm9tdmi_load_word_regs(target_t
*target
, u32 mask
)
633 /* get pointers to arch-specific information */
634 armv4_5_common_t
*armv4_5
= target
->arch_info
;
635 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
636 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
638 /* put system-speed load-multiple into the pipeline */
639 arm9tdmi_clock_out(jtag_info
, ARMV4_5_LDMIA(0, mask
& 0xffff, 0, 1), 0, NULL
, 0);
640 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
644 void arm9tdmi_load_hword_reg(target_t
*target
, int num
)
646 /* get pointers to arch-specific information */
647 armv4_5_common_t
*armv4_5
= target
->arch_info
;
648 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
649 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
651 /* put system-speed load half-word into the pipeline */
652 arm9tdmi_clock_out(jtag_info
, ARMV4_5_LDRH_IP(num
, 0), 0, NULL
, 0);
653 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
656 void arm9tdmi_load_byte_reg(target_t
*target
, int num
)
658 /* get pointers to arch-specific information */
659 armv4_5_common_t
*armv4_5
= target
->arch_info
;
660 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
661 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
663 /* put system-speed load byte into the pipeline */
664 arm9tdmi_clock_out(jtag_info
, ARMV4_5_LDRB_IP(num
, 0), 0, NULL
, 0);
665 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
669 void arm9tdmi_store_word_regs(target_t
*target
, u32 mask
)
671 /* get pointers to arch-specific information */
672 armv4_5_common_t
*armv4_5
= target
->arch_info
;
673 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
674 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
676 /* put system-speed store-multiple into the pipeline */
677 arm9tdmi_clock_out(jtag_info
, ARMV4_5_STMIA(0, mask
, 0, 1), 0, NULL
, 0);
678 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
682 void arm9tdmi_store_hword_reg(target_t
*target
, int num
)
684 /* get pointers to arch-specific information */
685 armv4_5_common_t
*armv4_5
= target
->arch_info
;
686 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
687 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
689 /* put system-speed store half-word into the pipeline */
690 arm9tdmi_clock_out(jtag_info
, ARMV4_5_STRH_IP(num
, 0), 0, NULL
, 0);
691 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
695 void arm9tdmi_store_byte_reg(target_t
*target
, int num
)
697 /* get pointers to arch-specific information */
698 armv4_5_common_t
*armv4_5
= target
->arch_info
;
699 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
700 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
702 /* put system-speed store byte into the pipeline */
703 arm9tdmi_clock_out(jtag_info
, ARMV4_5_STRB_IP(num
, 0), 0, NULL
, 0);
704 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
708 void arm9tdmi_write_pc(target_t
*target
, u32 pc
)
710 /* get pointers to arch-specific information */
711 armv4_5_common_t
*armv4_5
= target
->arch_info
;
712 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
713 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
715 /* LDMIA r0-15, [r0] at debug speed
716 * register values will start to appear on 4th DCLK
718 arm9tdmi_clock_out(jtag_info
, ARMV4_5_LDMIA(0, 0x8000, 0, 0), 0, NULL
, 0);
720 /* fetch NOP, LDM in DECODE stage */
721 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
722 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
723 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
724 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) (output data) */
725 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, pc
, NULL
, 0);
726 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
727 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
728 /* fetch NOP, LDM in EXECUTE stage (4th cycle) */
729 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
730 /* fetch NOP, LDM in EXECUTE stage (5th cycle) */
731 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
735 void arm9tdmi_branch_resume(target_t
*target
)
737 /* get pointers to arch-specific information */
738 armv4_5_common_t
*armv4_5
= target
->arch_info
;
739 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
740 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
742 arm9tdmi_clock_out(jtag_info
, ARMV4_5_B(0xfffffc, 0), 0, NULL
, 0);
743 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
747 void arm9tdmi_branch_resume_thumb(target_t
*target
)
751 /* get pointers to arch-specific information */
752 armv4_5_common_t
*armv4_5
= target
->arch_info
;
753 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
754 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
755 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
757 /* LDMIA r0-15, [r0] at debug speed
758 * register values will start to appear on 4th DCLK
760 arm9tdmi_clock_out(jtag_info
, ARMV4_5_LDMIA(0, 0x1, 0, 0), 0, NULL
, 0);
762 /* fetch NOP, LDM in DECODE stage */
763 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
764 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
765 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
766 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) */
767 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32) | 1, NULL
, 0);
768 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
769 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
771 /* Branch and eXchange */
772 arm9tdmi_clock_out(jtag_info
, ARMV4_5_BX(0), 0, NULL
, 0);
774 embeddedice_read_reg(dbg_stat
);
776 /* fetch NOP, BX in DECODE stage */
777 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
779 embeddedice_read_reg(dbg_stat
);
781 /* fetch NOP, BX in EXECUTE stage (1st cycle) */
782 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
784 /* target is now in Thumb state */
785 embeddedice_read_reg(dbg_stat
);
787 /* load r0 value, MOV_IM in Decode*/
788 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_LDR_PCREL(0), 0, NULL
, 0);
789 /* fetch NOP, LDR in Decode, MOV_IM in Execute */
790 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
791 /* fetch NOP, LDR in Execute */
792 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
793 /* nothing fetched, LDR in EXECUTE stage (2nd cycle) */
794 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, buf_get_u32(armv4_5
->core_cache
->reg_list
[0].value
, 0, 32), NULL
, 0);
795 /* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
796 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
798 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
799 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
801 embeddedice_read_reg(dbg_stat
);
803 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_B(0x7f7), 0, NULL
, 1);
804 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
808 void arm9tdmi_enable_single_step(target_t
*target
)
810 /* get pointers to arch-specific information */
811 armv4_5_common_t
*armv4_5
= target
->arch_info
;
812 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
814 if (arm7_9
->has_single_step
)
816 buf_set_u32(arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
].value
, 3, 1, 1);
817 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
]);
821 arm7_9_enable_eice_step(target
);
825 void arm9tdmi_disable_single_step(target_t
*target
)
827 /* get pointers to arch-specific information */
828 armv4_5_common_t
*armv4_5
= target
->arch_info
;
829 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
831 if (arm7_9
->has_single_step
)
833 buf_set_u32(arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
].value
, 3, 1, 0);
834 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
]);
838 arm7_9_disable_eice_step(target
);
842 void arm9tdmi_build_reg_cache(target_t
*target
)
844 reg_cache_t
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
845 /* get pointers to arch-specific information */
846 armv4_5_common_t
*armv4_5
= target
->arch_info
;
848 (*cache_p
) = armv4_5_build_reg_cache(target
, armv4_5
);
849 armv4_5
->core_cache
= (*cache_p
);
853 int arm9tdmi_examine(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
855 /* get pointers to arch-specific information */
857 armv4_5_common_t
*armv4_5
= target
->arch_info
;
858 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
859 if (!target
->type
->examined
)
861 reg_cache_t
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
863 /* one extra register (vector catch) */
864 t
=embeddedice_build_reg_cache(target
, arm7_9
);
868 arm7_9
->eice_cache
= (*cache_p
);
872 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
873 (*cache_p
)->next
= etm_build_reg_cache(target
, jtag_info
, arm7_9
->etm_ctx
);
874 arm7_9
->etm_ctx
->reg_cache
= (*cache_p
)->next
;
876 target
->type
->examined
= 1;
878 if ((retval
=embeddedice_setup(target
))!=ERROR_OK
)
880 if ((retval
=arm7_9_setup(target
))!=ERROR_OK
)
884 if ((retval
=etm_setup(target
))!=ERROR_OK
)
890 int arm9tdmi_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
893 arm9tdmi_build_reg_cache(target
);
905 int arm9tdmi_init_arch_info(target_t
*target
, arm9tdmi_common_t
*arm9tdmi
, int chain_pos
, char *variant
)
907 armv4_5_common_t
*armv4_5
;
908 arm7_9_common_t
*arm7_9
;
910 arm7_9
= &arm9tdmi
->arm7_9_common
;
911 armv4_5
= &arm7_9
->armv4_5_common
;
913 /* prepare JTAG information for the new target */
914 arm7_9
->jtag_info
.chain_pos
= chain_pos
;
915 arm7_9
->jtag_info
.scann_size
= 5;
917 /* register arch-specific functions */
918 arm7_9
->examine_debug_reason
= arm9tdmi_examine_debug_reason
;
919 arm7_9
->change_to_arm
= arm9tdmi_change_to_arm
;
920 arm7_9
->read_core_regs
= arm9tdmi_read_core_regs
;
921 arm7_9
->read_core_regs_target_buffer
= arm9tdmi_read_core_regs_target_buffer
;
922 arm7_9
->read_xpsr
= arm9tdmi_read_xpsr
;
924 arm7_9
->write_xpsr
= arm9tdmi_write_xpsr
;
925 arm7_9
->write_xpsr_im8
= arm9tdmi_write_xpsr_im8
;
926 arm7_9
->write_core_regs
= arm9tdmi_write_core_regs
;
928 arm7_9
->load_word_regs
= arm9tdmi_load_word_regs
;
929 arm7_9
->load_hword_reg
= arm9tdmi_load_hword_reg
;
930 arm7_9
->load_byte_reg
= arm9tdmi_load_byte_reg
;
932 arm7_9
->store_word_regs
= arm9tdmi_store_word_regs
;
933 arm7_9
->store_hword_reg
= arm9tdmi_store_hword_reg
;
934 arm7_9
->store_byte_reg
= arm9tdmi_store_byte_reg
;
936 arm7_9
->write_pc
= arm9tdmi_write_pc
;
937 arm7_9
->branch_resume
= arm9tdmi_branch_resume
;
938 arm7_9
->branch_resume_thumb
= arm9tdmi_branch_resume_thumb
;
940 arm7_9
->enable_single_step
= arm9tdmi_enable_single_step
;
941 arm7_9
->disable_single_step
= arm9tdmi_disable_single_step
;
943 arm7_9
->pre_debug_entry
= NULL
;
944 arm7_9
->post_debug_entry
= NULL
;
946 arm7_9
->pre_restore_context
= NULL
;
947 arm7_9
->post_restore_context
= NULL
;
949 /* initialize arch-specific breakpoint handling */
950 arm7_9
->arm_bkpt
= 0xdeeedeee;
951 arm7_9
->thumb_bkpt
= 0xdeee;
953 arm7_9
->sw_bkpts_use_wp
= 1;
954 arm7_9
->sw_bkpts_enabled
= 0;
955 arm7_9
->dbgreq_adjust_pc
= 3;
956 arm7_9
->arch_info
= arm9tdmi
;
958 arm9tdmi
->common_magic
= ARM9TDMI_COMMON_MAGIC
;
959 arm9tdmi
->arch_info
= NULL
;
963 arm9tdmi
->variant
= strdup(variant
);
967 arm9tdmi
->variant
= strdup("");
970 arm7_9_init_arch_info(target
, arm7_9
);
972 /* override use of DBGRQ, this is safe on ARM9TDMI */
973 arm7_9
->use_dbgrq
= 1;
975 /* all ARM9s have the vector catch register */
976 arm7_9
->has_vector_catch
= 1;
981 int arm9tdmi_get_arch_pointers(target_t
*target
, armv4_5_common_t
**armv4_5_p
, arm7_9_common_t
**arm7_9_p
, arm9tdmi_common_t
**arm9tdmi_p
)
983 armv4_5_common_t
*armv4_5
= target
->arch_info
;
984 arm7_9_common_t
*arm7_9
;
985 arm9tdmi_common_t
*arm9tdmi
;
987 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
992 arm7_9
= armv4_5
->arch_info
;
993 if (arm7_9
->common_magic
!= ARM7_9_COMMON_MAGIC
)
998 arm9tdmi
= arm7_9
->arch_info
;
999 if (arm9tdmi
->common_magic
!= ARM9TDMI_COMMON_MAGIC
)
1004 *armv4_5_p
= armv4_5
;
1006 *arm9tdmi_p
= arm9tdmi
;
1012 /* target arm9tdmi <endianess> <startup_mode> <chain_pos> <variant>*/
1013 int arm9tdmi_target_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct target_s
*target
)
1016 char *variant
= NULL
;
1017 arm9tdmi_common_t
*arm9tdmi
= malloc(sizeof(arm9tdmi_common_t
));
1018 memset(arm9tdmi
, 0, sizeof(*arm9tdmi
));
1022 LOG_ERROR("'target arm9tdmi' requires at least one additional argument");
1026 chain_pos
= strtoul(args
[3], NULL
, 0);
1031 arm9tdmi_init_arch_info(target
, arm9tdmi
, chain_pos
, variant
);
1036 int arm9tdmi_register_commands(struct command_context_s
*cmd_ctx
)
1040 command_t
*arm9tdmi_cmd
;
1043 retval
= arm7_9_register_commands(cmd_ctx
);
1045 arm9tdmi_cmd
= register_command(cmd_ctx
, NULL
, "arm9tdmi", NULL
, COMMAND_ANY
, "arm9tdmi specific commands");
1047 register_command(cmd_ctx
, arm9tdmi_cmd
, "vector_catch", handle_arm9tdmi_catch_vectors_command
, COMMAND_EXEC
, "catch arm920t vectors ['all'|'none'|'<vec1 vec2 ...>']");
1054 int handle_arm9tdmi_catch_vectors_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1056 target_t
*target
= get_current_target(cmd_ctx
);
1057 armv4_5_common_t
*armv4_5
;
1058 arm7_9_common_t
*arm7_9
;
1059 arm9tdmi_common_t
*arm9tdmi
;
1060 reg_t
*vector_catch
;
1061 u32 vector_catch_value
;
1064 if (arm9tdmi_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
) != ERROR_OK
)
1066 command_print(cmd_ctx
, "current target isn't an ARM9TDMI based target");
1070 vector_catch
= &arm7_9
->eice_cache
->reg_list
[EICE_VEC_CATCH
];
1072 /* read the vector catch register if necessary */
1073 if (!vector_catch
->valid
)
1074 embeddedice_read_reg(vector_catch
);
1076 /* get the current setting */
1077 vector_catch_value
= buf_get_u32(vector_catch
->value
, 0, 32);
1081 vector_catch_value
= 0x0;
1082 if (strcmp(args
[0], "all") == 0)
1084 vector_catch_value
= 0xdf;
1086 else if (strcmp(args
[0], "none") == 0)
1092 for (i
= 0; i
< argc
; i
++)
1094 /* go through list of vectors */
1095 for(j
= 0; arm9tdmi_vectors
[j
].name
; j
++)
1097 if (strcmp(args
[i
], arm9tdmi_vectors
[j
].name
) == 0)
1099 vector_catch_value
|= arm9tdmi_vectors
[j
].value
;
1104 /* complain if vector wasn't found */
1105 if (!arm9tdmi_vectors
[j
].name
)
1107 command_print(cmd_ctx
, "vector '%s' not found, leaving current setting unchanged", args
[i
]);
1109 /* reread current setting */
1110 vector_catch_value
= buf_get_u32(vector_catch
->value
, 0, 32);
1117 /* store new settings */
1118 buf_set_u32(vector_catch
->value
, 0, 32, vector_catch_value
);
1119 embeddedice_store_reg(vector_catch
);
1122 /* output current settings (skip RESERVED vector) */
1123 for (i
= 0; i
< 8; i
++)
1127 command_print(cmd_ctx
, "%s: %s", arm9tdmi_vectors
[i
].name
,
1128 (vector_catch_value
& (1 << i
)) ? "catch" : "don't catch");
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