1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2008 by Hongtao Zheng *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
31 #include "target_type.h"
35 #define _DEBUG_INSTRUCTION_EXECUTION_
39 int handle_arm9tdmi_catch_vectors_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
41 /* forward declarations */
42 int arm9tdmi_target_create(struct target_s
*target
, Jim_Interp
*interp
);
44 int arm9tdmi_quit(void);
46 target_type_t arm9tdmi_target
=
51 .arch_state
= armv4_5_arch_state
,
53 .target_request_data
= arm7_9_target_request_data
,
56 .resume
= arm7_9_resume
,
59 .assert_reset
= arm7_9_assert_reset
,
60 .deassert_reset
= arm7_9_deassert_reset
,
61 .soft_reset_halt
= arm7_9_soft_reset_halt
,
63 .get_gdb_reg_list
= armv4_5_get_gdb_reg_list
,
65 .read_memory
= arm7_9_read_memory
,
66 .write_memory
= arm7_9_write_memory
,
67 .bulk_write_memory
= arm7_9_bulk_write_memory
,
68 .checksum_memory
= arm7_9_checksum_memory
,
69 .blank_check_memory
= arm7_9_blank_check_memory
,
71 .run_algorithm
= armv4_5_run_algorithm
,
73 .add_breakpoint
= arm7_9_add_breakpoint
,
74 .remove_breakpoint
= arm7_9_remove_breakpoint
,
75 .add_watchpoint
= arm7_9_add_watchpoint
,
76 .remove_watchpoint
= arm7_9_remove_watchpoint
,
78 .register_commands
= arm9tdmi_register_commands
,
79 .target_create
= arm9tdmi_target_create
,
80 .init_target
= arm9tdmi_init_target
,
81 .examine
= arm9tdmi_examine
,
85 arm9tdmi_vector_t arm9tdmi_vectors
[] =
87 {"reset", ARM9TDMI_RESET_VECTOR
},
88 {"undef", ARM9TDMI_UNDEF_VECTOR
},
89 {"swi", ARM9TDMI_SWI_VECTOR
},
90 {"pabt", ARM9TDMI_PABT_VECTOR
},
91 {"dabt", ARM9TDMI_DABT_VECTOR
},
92 {"reserved", ARM9TDMI_RESERVED_VECTOR
},
93 {"irq", ARM9TDMI_IRQ_VECTOR
},
94 {"fiq", ARM9TDMI_FIQ_VECTOR
},
98 int arm9tdmi_examine_debug_reason(target_t
*target
)
100 int retval
= ERROR_OK
;
101 /* get pointers to arch-specific information */
102 armv4_5_common_t
*armv4_5
= target
->arch_info
;
103 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
105 /* only check the debug reason if we don't know it already */
106 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
107 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
))
109 scan_field_t fields
[3];
111 uint8_t instructionbus
[4];
112 uint8_t debug_reason
;
114 jtag_set_end_state(TAP_DRPAUSE
);
116 fields
[0].tap
= arm7_9
->jtag_info
.tap
;
117 fields
[0].num_bits
= 32;
118 fields
[0].out_value
= NULL
;
119 fields
[0].in_value
= databus
;
121 fields
[1].tap
= arm7_9
->jtag_info
.tap
;
122 fields
[1].num_bits
= 3;
123 fields
[1].out_value
= NULL
;
124 fields
[1].in_value
= &debug_reason
;
126 fields
[2].tap
= arm7_9
->jtag_info
.tap
;
127 fields
[2].num_bits
= 32;
128 fields
[2].out_value
= NULL
;
129 fields
[2].in_value
= instructionbus
;
131 if ((retval
= arm_jtag_scann(&arm7_9
->jtag_info
, 0x1)) != ERROR_OK
)
135 arm_jtag_set_instr(&arm7_9
->jtag_info
, arm7_9
->jtag_info
.intest_instr
, NULL
);
137 jtag_add_dr_scan(3, fields
, jtag_set_end_state(TAP_DRPAUSE
));
138 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
143 fields
[0].in_value
= NULL
;
144 fields
[0].out_value
= databus
;
145 fields
[1].in_value
= NULL
;
146 fields
[1].out_value
= &debug_reason
;
147 fields
[2].in_value
= NULL
;
148 fields
[2].out_value
= instructionbus
;
150 jtag_add_dr_scan(3, fields
, jtag_set_end_state(TAP_DRPAUSE
));
152 if (debug_reason
& 0x4)
153 if (debug_reason
& 0x2)
154 target
->debug_reason
= DBG_REASON_WPTANDBKPT
;
156 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
158 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
164 /* put an instruction in the ARM9TDMI pipeline or write the data bus, and optionally read data */
165 int arm9tdmi_clock_out(arm_jtag_t
*jtag_info
, uint32_t instr
, uint32_t out
, uint32_t *in
, int sysspeed
)
167 int retval
= ERROR_OK
;
168 scan_field_t fields
[3];
170 uint8_t instr_buf
[4];
171 uint8_t sysspeed_buf
= 0x0;
174 buf_set_u32(out_buf
, 0, 32, out
);
176 buf_set_u32(instr_buf
, 0, 32, flip_u32(instr
, 32));
179 buf_set_u32(&sysspeed_buf
, 2, 1, 1);
181 jtag_set_end_state(TAP_DRPAUSE
);
182 if ((retval
= arm_jtag_scann(jtag_info
, 0x1)) != ERROR_OK
)
187 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
189 fields
[0].tap
= jtag_info
->tap
;
190 fields
[0].num_bits
= 32;
191 fields
[0].out_value
= out_buf
;
192 fields
[0].in_value
= NULL
;
194 fields
[1].tap
= jtag_info
->tap
;
195 fields
[1].num_bits
= 3;
196 fields
[1].out_value
= &sysspeed_buf
;
197 fields
[1].in_value
= NULL
;
199 fields
[2].tap
= jtag_info
->tap
;
200 fields
[2].num_bits
= 32;
201 fields
[2].out_value
= instr_buf
;
202 fields
[2].in_value
= NULL
;
206 fields
[0].in_value
= (uint8_t *)in
;
207 jtag_add_dr_scan(3, fields
, jtag_get_end_state());
209 jtag_add_callback(arm_le_to_h_u32
, (jtag_callback_data_t
)in
);
213 jtag_add_dr_scan(3, fields
, jtag_get_end_state());
216 jtag_add_runtest(0, jtag_get_end_state());
218 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
220 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
227 LOG_DEBUG("instr: 0x%8.8x, out: 0x%8.8x, in: 0x%8.8x", instr
, out
, *in
);
230 LOG_DEBUG("instr: 0x%8.8x, out: 0x%8.8x", instr
, out
);
237 /* just read data (instruction and data-out = don't care) */
238 int arm9tdmi_clock_data_in(arm_jtag_t
*jtag_info
, uint32_t *in
)
240 int retval
= ERROR_OK
;;
241 scan_field_t fields
[3];
243 jtag_set_end_state(TAP_DRPAUSE
);
244 if ((retval
= arm_jtag_scann(jtag_info
, 0x1)) != ERROR_OK
)
249 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
251 fields
[0].tap
= jtag_info
->tap
;
252 fields
[0].num_bits
= 32;
253 fields
[0].out_value
= NULL
;
254 fields
[0].in_value
= (uint8_t *)in
;
256 fields
[1].tap
= jtag_info
->tap
;
257 fields
[1].num_bits
= 3;
258 fields
[1].out_value
= NULL
;
259 fields
[1].in_value
= NULL
;
261 fields
[2].tap
= jtag_info
->tap
;
262 fields
[2].num_bits
= 32;
263 fields
[2].out_value
= NULL
;
264 fields
[2].in_value
= NULL
;
266 jtag_add_dr_scan(3, fields
, jtag_get_end_state());
268 jtag_add_callback(arm_le_to_h_u32
, (jtag_callback_data_t
)in
);
270 jtag_add_runtest(0, jtag_get_end_state());
272 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
274 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
281 LOG_DEBUG("in: 0x%8.8x", *in
);
285 LOG_ERROR("BUG: called with in == NULL");
293 extern void arm_endianness(uint8_t *tmp
, void *in
, int size
, int be
, int flip
);
295 static int arm9endianness(jtag_callback_data_t arg
, jtag_callback_data_t size
, jtag_callback_data_t be
, jtag_callback_data_t captured
)
297 uint8_t *in
= (uint8_t *)arg
;
298 arm_endianness((uint8_t *)captured
, in
, (int)size
, (int)be
, 0);
302 /* clock the target, and read the databus
303 * the *in pointer points to a buffer where elements of 'size' bytes
304 * are stored in big (be == 1) or little (be == 0) endianness
306 int arm9tdmi_clock_data_in_endianness(arm_jtag_t
*jtag_info
, void *in
, int size
, int be
)
308 int retval
= ERROR_OK
;
309 scan_field_t fields
[3];
311 jtag_set_end_state(TAP_DRPAUSE
);
312 if ((retval
= arm_jtag_scann(jtag_info
, 0x1)) != ERROR_OK
)
317 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
319 fields
[0].tap
= jtag_info
->tap
;
320 fields
[0].num_bits
= 32;
321 fields
[0].out_value
= NULL
;
322 jtag_alloc_in_value32(&fields
[0]);
324 fields
[1].tap
= jtag_info
->tap
;
325 fields
[1].num_bits
= 3;
326 fields
[1].out_value
= NULL
;
327 fields
[1].in_value
= NULL
;
329 fields
[2].tap
= jtag_info
->tap
;
330 fields
[2].num_bits
= 32;
331 fields
[2].out_value
= NULL
;
332 fields
[2].in_value
= NULL
;
334 jtag_add_dr_scan(3, fields
, jtag_get_end_state());
336 jtag_add_callback4(arm9endianness
, (jtag_callback_data_t
)in
, (jtag_callback_data_t
)size
, (jtag_callback_data_t
)be
, (jtag_callback_data_t
)fields
[0].in_value
);
338 jtag_add_runtest(0, jtag_get_end_state());
340 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
342 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
349 LOG_DEBUG("in: 0x%8.8x", *(uint32_t*)in
);
353 LOG_ERROR("BUG: called with in == NULL");
361 void arm9tdmi_change_to_arm(target_t
*target
, uint32_t *r0
, uint32_t *pc
)
363 int retval
= ERROR_OK
;
364 /* get pointers to arch-specific information */
365 armv4_5_common_t
*armv4_5
= target
->arch_info
;
366 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
367 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
369 /* save r0 before using it and put system in ARM state
370 * to allow common handling of ARM and THUMB debugging */
372 /* fetch STR r0, [r0] */
373 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_STR(0, 0), 0, NULL
, 0);
374 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
375 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
376 /* STR r0, [r0] in Memory */
377 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, r0
, 0);
379 /* MOV r0, r15 fetched, STR in Decode */
380 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_MOV(0, 15), 0, NULL
, 0);
381 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
382 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_STR(0, 0), 0, NULL
, 0);
383 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
384 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
385 /* nothing fetched, STR r0, [r0] in Memory */
386 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, pc
, 0);
388 /* use pc-relative LDR to clear r0[1:0] (for switch to ARM mode) */
389 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_LDR_PCREL(0), 0, NULL
, 0);
391 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
393 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
394 /* LDR in Memory (to account for interlock) */
395 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
398 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_BX(0), 0, NULL
, 0);
399 /* NOP fetched, BX in Decode, MOV in Execute */
400 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
401 /* NOP fetched, BX in Execute (1) */
402 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
404 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
409 /* fix program counter:
410 * MOV r0, r15 was the 5th instruction (+8)
411 * reading PC in Thumb state gives address of instruction + 4
416 void arm9tdmi_read_core_regs(target_t
*target
, uint32_t mask
, uint32_t* core_regs
[16])
419 /* get pointers to arch-specific information */
420 armv4_5_common_t
*armv4_5
= target
->arch_info
;
421 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
422 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
424 /* STMIA r0-15, [r0] at debug speed
425 * register values will start to appear on 4th DCLK
427 arm9tdmi_clock_out(jtag_info
, ARMV4_5_STMIA(0, mask
& 0xffff, 0, 0), 0, NULL
, 0);
429 /* fetch NOP, STM in DECODE stage */
430 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
431 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
432 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
434 for (i
= 0; i
<= 15; i
++)
437 /* nothing fetched, STM in MEMORY (i'th cycle) */
438 arm9tdmi_clock_data_in(jtag_info
, core_regs
[i
]);
442 void arm9tdmi_read_core_regs_target_buffer(target_t
*target
, uint32_t mask
, void* buffer
, int size
)
445 /* get pointers to arch-specific information */
446 armv4_5_common_t
*armv4_5
= target
->arch_info
;
447 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
448 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
449 int be
= (target
->endianness
== TARGET_BIG_ENDIAN
) ? 1 : 0;
450 uint32_t *buf_u32
= buffer
;
451 uint16_t *buf_u16
= buffer
;
452 uint8_t *buf_u8
= buffer
;
454 /* STMIA r0-15, [r0] at debug speed
455 * register values will start to appear on 4th DCLK
457 arm9tdmi_clock_out(jtag_info
, ARMV4_5_STMIA(0, mask
& 0xffff, 0, 0), 0, NULL
, 0);
459 /* fetch NOP, STM in DECODE stage */
460 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
461 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
462 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
464 for (i
= 0; i
<= 15; i
++)
467 /* nothing fetched, STM in MEMORY (i'th cycle) */
471 arm9tdmi_clock_data_in_endianness(jtag_info
, buf_u32
++, 4, be
);
474 arm9tdmi_clock_data_in_endianness(jtag_info
, buf_u16
++, 2, be
);
477 arm9tdmi_clock_data_in_endianness(jtag_info
, buf_u8
++, 1, be
);
483 void arm9tdmi_read_xpsr(target_t
*target
, uint32_t *xpsr
, int spsr
)
485 /* get pointers to arch-specific information */
486 armv4_5_common_t
*armv4_5
= target
->arch_info
;
487 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
488 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
491 arm9tdmi_clock_out(jtag_info
, ARMV4_5_MRS(0, spsr
& 1), 0, NULL
, 0);
492 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
493 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
494 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
495 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
498 arm9tdmi_clock_out(jtag_info
, ARMV4_5_STR(0, 15), 0, NULL
, 0);
499 /* fetch NOP, STR in DECODE stage */
500 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
501 /* fetch NOP, STR in EXECUTE stage (1st cycle) */
502 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
503 /* nothing fetched, STR in MEMORY */
504 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, xpsr
, 0);
507 void arm9tdmi_write_xpsr(target_t
*target
, uint32_t xpsr
, int spsr
)
509 /* get pointers to arch-specific information */
510 armv4_5_common_t
*armv4_5
= target
->arch_info
;
511 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
512 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
514 LOG_DEBUG("xpsr: %8.8" PRIx32
", spsr: %i", xpsr
, spsr
);
517 arm9tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM(xpsr
& 0xff, 0, 1, spsr
), 0, NULL
, 0);
518 /* MSR2 fetched, MSR1 in DECODE */
519 arm9tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM((xpsr
& 0xff00) >> 8, 0xc, 2, spsr
), 0, NULL
, 0);
520 /* MSR3 fetched, MSR1 in EXECUTE (1), MSR2 in DECODE */
521 arm9tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM((xpsr
& 0xff0000) >> 16, 0x8, 4, spsr
), 0, NULL
, 0);
522 /* nothing fetched, MSR1 in EXECUTE (2) */
523 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
524 /* nothing fetched, MSR1 in EXECUTE (3) */
525 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
526 /* MSR4 fetched, MSR2 in EXECUTE (1), MSR3 in DECODE */
527 arm9tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM((xpsr
& 0xff000000) >> 24, 0x4, 8, spsr
), 0, NULL
, 0);
528 /* nothing fetched, MSR2 in EXECUTE (2) */
529 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
530 /* nothing fetched, MSR2 in EXECUTE (3) */
531 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
532 /* NOP fetched, MSR3 in EXECUTE (1), MSR4 in DECODE */
533 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
534 /* nothing fetched, MSR3 in EXECUTE (2) */
535 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
536 /* nothing fetched, MSR3 in EXECUTE (3) */
537 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
538 /* NOP fetched, MSR4 in EXECUTE (1) */
539 /* last MSR writes flags, which takes only one cycle */
540 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
543 void arm9tdmi_write_xpsr_im8(target_t
*target
, uint8_t xpsr_im
, int rot
, int spsr
)
545 /* get pointers to arch-specific information */
546 armv4_5_common_t
*armv4_5
= target
->arch_info
;
547 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
548 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
550 LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im
, rot
, spsr
);
553 arm9tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM(xpsr_im
, rot
, 1, spsr
), 0, NULL
, 0);
554 /* NOP fetched, MSR in DECODE */
555 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
556 /* NOP fetched, MSR in EXECUTE (1) */
557 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
559 /* rot == 4 writes flags, which takes only one cycle */
562 /* nothing fetched, MSR in EXECUTE (2) */
563 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
564 /* nothing fetched, MSR in EXECUTE (3) */
565 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
569 void arm9tdmi_write_core_regs(target_t
*target
, uint32_t mask
, uint32_t core_regs
[16])
572 /* get pointers to arch-specific information */
573 armv4_5_common_t
*armv4_5
= target
->arch_info
;
574 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
575 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
577 /* LDMIA r0-15, [r0] at debug speed
578 * register values will start to appear on 4th DCLK
580 arm9tdmi_clock_out(jtag_info
, ARMV4_5_LDMIA(0, mask
& 0xffff, 0, 0), 0, NULL
, 0);
582 /* fetch NOP, LDM in DECODE stage */
583 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
584 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
585 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
587 for (i
= 0; i
<= 15; i
++)
590 /* nothing fetched, LDM still in EXECUTE (1 + i cycle) */
591 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, core_regs
[i
], NULL
, 0);
593 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
596 void arm9tdmi_load_word_regs(target_t
*target
, uint32_t mask
)
598 /* get pointers to arch-specific information */
599 armv4_5_common_t
*armv4_5
= target
->arch_info
;
600 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
601 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
603 /* put system-speed load-multiple into the pipeline */
604 arm9tdmi_clock_out(jtag_info
, ARMV4_5_LDMIA(0, mask
& 0xffff, 0, 1), 0, NULL
, 0);
605 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
608 void arm9tdmi_load_hword_reg(target_t
*target
, int num
)
610 /* get pointers to arch-specific information */
611 armv4_5_common_t
*armv4_5
= target
->arch_info
;
612 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
613 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
615 /* put system-speed load half-word into the pipeline */
616 arm9tdmi_clock_out(jtag_info
, ARMV4_5_LDRH_IP(num
, 0), 0, NULL
, 0);
617 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
620 void arm9tdmi_load_byte_reg(target_t
*target
, int num
)
622 /* get pointers to arch-specific information */
623 armv4_5_common_t
*armv4_5
= target
->arch_info
;
624 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
625 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
627 /* put system-speed load byte into the pipeline */
628 arm9tdmi_clock_out(jtag_info
, ARMV4_5_LDRB_IP(num
, 0), 0, NULL
, 0);
629 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
632 void arm9tdmi_store_word_regs(target_t
*target
, uint32_t mask
)
634 /* get pointers to arch-specific information */
635 armv4_5_common_t
*armv4_5
= target
->arch_info
;
636 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
637 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
639 /* put system-speed store-multiple into the pipeline */
640 arm9tdmi_clock_out(jtag_info
, ARMV4_5_STMIA(0, mask
, 0, 1), 0, NULL
, 0);
641 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
644 void arm9tdmi_store_hword_reg(target_t
*target
, int num
)
646 /* get pointers to arch-specific information */
647 armv4_5_common_t
*armv4_5
= target
->arch_info
;
648 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
649 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
651 /* put system-speed store half-word into the pipeline */
652 arm9tdmi_clock_out(jtag_info
, ARMV4_5_STRH_IP(num
, 0), 0, NULL
, 0);
653 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
656 void arm9tdmi_store_byte_reg(target_t
*target
, int num
)
658 /* get pointers to arch-specific information */
659 armv4_5_common_t
*armv4_5
= target
->arch_info
;
660 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
661 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
663 /* put system-speed store byte into the pipeline */
664 arm9tdmi_clock_out(jtag_info
, ARMV4_5_STRB_IP(num
, 0), 0, NULL
, 0);
665 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
668 void arm9tdmi_write_pc(target_t
*target
, uint32_t pc
)
670 /* get pointers to arch-specific information */
671 armv4_5_common_t
*armv4_5
= target
->arch_info
;
672 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
673 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
675 /* LDMIA r0-15, [r0] at debug speed
676 * register values will start to appear on 4th DCLK
678 arm9tdmi_clock_out(jtag_info
, ARMV4_5_LDMIA(0, 0x8000, 0, 0), 0, NULL
, 0);
680 /* fetch NOP, LDM in DECODE stage */
681 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
682 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
683 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
684 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) (output data) */
685 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, pc
, NULL
, 0);
686 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
687 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
688 /* fetch NOP, LDM in EXECUTE stage (4th cycle) */
689 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
690 /* fetch NOP, LDM in EXECUTE stage (5th cycle) */
691 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
694 void arm9tdmi_branch_resume(target_t
*target
)
696 /* get pointers to arch-specific information */
697 armv4_5_common_t
*armv4_5
= target
->arch_info
;
698 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
699 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
701 arm9tdmi_clock_out(jtag_info
, ARMV4_5_B(0xfffffc, 0), 0, NULL
, 0);
702 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
705 void arm9tdmi_branch_resume_thumb(target_t
*target
)
709 /* get pointers to arch-specific information */
710 armv4_5_common_t
*armv4_5
= target
->arch_info
;
711 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
712 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
713 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
715 /* LDMIA r0-15, [r0] at debug speed
716 * register values will start to appear on 4th DCLK
718 arm9tdmi_clock_out(jtag_info
, ARMV4_5_LDMIA(0, 0x1, 0, 0), 0, NULL
, 0);
720 /* fetch NOP, LDM in DECODE stage */
721 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
722 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
723 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
724 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) */
725 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32) | 1, NULL
, 0);
726 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
727 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
729 /* Branch and eXchange */
730 arm9tdmi_clock_out(jtag_info
, ARMV4_5_BX(0), 0, NULL
, 0);
732 embeddedice_read_reg(dbg_stat
);
734 /* fetch NOP, BX in DECODE stage */
735 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
737 embeddedice_read_reg(dbg_stat
);
739 /* fetch NOP, BX in EXECUTE stage (1st cycle) */
740 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
742 /* target is now in Thumb state */
743 embeddedice_read_reg(dbg_stat
);
745 /* load r0 value, MOV_IM in Decode*/
746 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_LDR_PCREL(0), 0, NULL
, 0);
747 /* fetch NOP, LDR in Decode, MOV_IM in Execute */
748 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
749 /* fetch NOP, LDR in Execute */
750 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
751 /* nothing fetched, LDR in EXECUTE stage (2nd cycle) */
752 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, buf_get_u32(armv4_5
->core_cache
->reg_list
[0].value
, 0, 32), NULL
, 0);
753 /* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
754 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
756 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
757 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
759 embeddedice_read_reg(dbg_stat
);
761 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_B(0x7f7), 0, NULL
, 1);
762 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
765 void arm9tdmi_enable_single_step(target_t
*target
, uint32_t next_pc
)
767 /* get pointers to arch-specific information */
768 armv4_5_common_t
*armv4_5
= target
->arch_info
;
769 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
771 if (arm7_9
->has_single_step
)
773 buf_set_u32(arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
].value
, 3, 1, 1);
774 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
]);
778 arm7_9_enable_eice_step(target
, next_pc
);
782 void arm9tdmi_disable_single_step(target_t
*target
)
784 /* get pointers to arch-specific information */
785 armv4_5_common_t
*armv4_5
= target
->arch_info
;
786 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
788 if (arm7_9
->has_single_step
)
790 buf_set_u32(arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
].value
, 3, 1, 0);
791 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
]);
795 arm7_9_disable_eice_step(target
);
799 void arm9tdmi_build_reg_cache(target_t
*target
)
801 reg_cache_t
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
802 /* get pointers to arch-specific information */
803 armv4_5_common_t
*armv4_5
= target
->arch_info
;
805 (*cache_p
) = armv4_5_build_reg_cache(target
, armv4_5
);
806 armv4_5
->core_cache
= (*cache_p
);
809 int arm9tdmi_examine(struct target_s
*target
)
811 /* get pointers to arch-specific information */
813 armv4_5_common_t
*armv4_5
= target
->arch_info
;
814 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
815 if (!target_was_examined(target
))
817 reg_cache_t
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
819 /* one extra register (vector catch) */
820 t
= embeddedice_build_reg_cache(target
, arm7_9
);
824 arm7_9
->eice_cache
= (*cache_p
);
828 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
829 (*cache_p
)->next
= etm_build_reg_cache(target
, jtag_info
, arm7_9
->etm_ctx
);
830 arm7_9
->etm_ctx
->reg_cache
= (*cache_p
)->next
;
832 target_set_examined(target
);
834 if ((retval
= embeddedice_setup(target
)) != ERROR_OK
)
836 if ((retval
= arm7_9_setup(target
)) != ERROR_OK
)
840 if ((retval
= etm_setup(target
)) != ERROR_OK
)
846 int arm9tdmi_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
849 arm9tdmi_build_reg_cache(target
);
854 int arm9tdmi_quit(void)
859 int arm9tdmi_init_arch_info(target_t
*target
, arm9tdmi_common_t
*arm9tdmi
, jtag_tap_t
*tap
)
861 armv4_5_common_t
*armv4_5
;
862 arm7_9_common_t
*arm7_9
;
864 arm7_9
= &arm9tdmi
->arm7_9_common
;
865 armv4_5
= &arm7_9
->armv4_5_common
;
867 /* prepare JTAG information for the new target */
868 arm7_9
->jtag_info
.tap
= tap
;
869 arm7_9
->jtag_info
.scann_size
= 5;
871 /* register arch-specific functions */
872 arm7_9
->examine_debug_reason
= arm9tdmi_examine_debug_reason
;
873 arm7_9
->change_to_arm
= arm9tdmi_change_to_arm
;
874 arm7_9
->read_core_regs
= arm9tdmi_read_core_regs
;
875 arm7_9
->read_core_regs_target_buffer
= arm9tdmi_read_core_regs_target_buffer
;
876 arm7_9
->read_xpsr
= arm9tdmi_read_xpsr
;
878 arm7_9
->write_xpsr
= arm9tdmi_write_xpsr
;
879 arm7_9
->write_xpsr_im8
= arm9tdmi_write_xpsr_im8
;
880 arm7_9
->write_core_regs
= arm9tdmi_write_core_regs
;
882 arm7_9
->load_word_regs
= arm9tdmi_load_word_regs
;
883 arm7_9
->load_hword_reg
= arm9tdmi_load_hword_reg
;
884 arm7_9
->load_byte_reg
= arm9tdmi_load_byte_reg
;
886 arm7_9
->store_word_regs
= arm9tdmi_store_word_regs
;
887 arm7_9
->store_hword_reg
= arm9tdmi_store_hword_reg
;
888 arm7_9
->store_byte_reg
= arm9tdmi_store_byte_reg
;
890 arm7_9
->write_pc
= arm9tdmi_write_pc
;
891 arm7_9
->branch_resume
= arm9tdmi_branch_resume
;
892 arm7_9
->branch_resume_thumb
= arm9tdmi_branch_resume_thumb
;
894 arm7_9
->enable_single_step
= arm9tdmi_enable_single_step
;
895 arm7_9
->disable_single_step
= arm9tdmi_disable_single_step
;
897 arm7_9
->pre_debug_entry
= NULL
;
898 arm7_9
->post_debug_entry
= NULL
;
900 arm7_9
->pre_restore_context
= NULL
;
901 arm7_9
->post_restore_context
= NULL
;
903 /* initialize arch-specific breakpoint handling */
904 arm7_9
->arm_bkpt
= 0xdeeedeee;
905 arm7_9
->thumb_bkpt
= 0xdeee;
907 arm7_9
->dbgreq_adjust_pc
= 3;
908 arm7_9
->arch_info
= arm9tdmi
;
910 arm9tdmi
->common_magic
= ARM9TDMI_COMMON_MAGIC
;
911 arm9tdmi
->arch_info
= NULL
;
913 arm7_9_init_arch_info(target
, arm7_9
);
915 /* override use of DBGRQ, this is safe on ARM9TDMI */
916 arm7_9
->use_dbgrq
= 1;
918 /* all ARM9s have the vector catch register */
919 arm7_9
->has_vector_catch
= 1;
924 int arm9tdmi_get_arch_pointers(target_t
*target
, armv4_5_common_t
**armv4_5_p
, arm7_9_common_t
**arm7_9_p
, arm9tdmi_common_t
**arm9tdmi_p
)
926 armv4_5_common_t
*armv4_5
= target
->arch_info
;
927 arm7_9_common_t
*arm7_9
;
928 arm9tdmi_common_t
*arm9tdmi
;
930 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
935 arm7_9
= armv4_5
->arch_info
;
936 if (arm7_9
->common_magic
!= ARM7_9_COMMON_MAGIC
)
941 arm9tdmi
= arm7_9
->arch_info
;
942 if (arm9tdmi
->common_magic
!= ARM9TDMI_COMMON_MAGIC
)
947 *armv4_5_p
= armv4_5
;
949 *arm9tdmi_p
= arm9tdmi
;
954 int arm9tdmi_target_create(struct target_s
*target
, Jim_Interp
*interp
)
956 arm9tdmi_common_t
*arm9tdmi
= calloc(1,sizeof(arm9tdmi_common_t
));
958 arm9tdmi_init_arch_info(target
, arm9tdmi
, target
->tap
);
959 arm9tdmi
->arm7_9_common
.armv4_5_common
.is_armv4
= true;
964 int arm9tdmi_register_commands(struct command_context_s
*cmd_ctx
)
967 command_t
*arm9tdmi_cmd
;
969 retval
= arm7_9_register_commands(cmd_ctx
);
970 arm9tdmi_cmd
= register_command(cmd_ctx
, NULL
, "arm9tdmi", NULL
, COMMAND_ANY
, "arm9tdmi specific commands");
971 register_command(cmd_ctx
, arm9tdmi_cmd
, "vector_catch", handle_arm9tdmi_catch_vectors_command
, COMMAND_EXEC
, "catch arm920t vectors ['all'|'none'|'<vec1 vec2 ...>']");
976 int handle_arm9tdmi_catch_vectors_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
978 target_t
*target
= get_current_target(cmd_ctx
);
979 armv4_5_common_t
*armv4_5
;
980 arm7_9_common_t
*arm7_9
;
981 arm9tdmi_common_t
*arm9tdmi
;
983 uint32_t vector_catch_value
;
986 if (arm9tdmi_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
) != ERROR_OK
)
988 command_print(cmd_ctx
, "current target isn't an ARM9TDMI based target");
992 vector_catch
= &arm7_9
->eice_cache
->reg_list
[EICE_VEC_CATCH
];
994 /* read the vector catch register if necessary */
995 if (!vector_catch
->valid
)
996 embeddedice_read_reg(vector_catch
);
998 /* get the current setting */
999 vector_catch_value
= buf_get_u32(vector_catch
->value
, 0, 8);
1003 vector_catch_value
= 0x0;
1004 if (strcmp(args
[0], "all") == 0)
1006 vector_catch_value
= 0xdf;
1008 else if (strcmp(args
[0], "none") == 0)
1014 for (i
= 0; i
< argc
; i
++)
1016 /* go through list of vectors */
1017 for (j
= 0; arm9tdmi_vectors
[j
].name
; j
++)
1019 if (strcmp(args
[i
], arm9tdmi_vectors
[j
].name
) == 0)
1021 vector_catch_value
|= arm9tdmi_vectors
[j
].value
;
1026 /* complain if vector wasn't found */
1027 if (!arm9tdmi_vectors
[j
].name
)
1029 command_print(cmd_ctx
, "vector '%s' not found, leaving current setting unchanged", args
[i
]);
1031 /* reread current setting */
1032 vector_catch_value
= buf_get_u32(
1033 vector_catch
->value
,
1041 /* store new settings */
1042 buf_set_u32(vector_catch
->value
, 0, 8, vector_catch_value
);
1043 embeddedice_store_reg(vector_catch
);
1046 /* output current settings (skip RESERVED vector) */
1047 for (i
= 0; i
< 8; i
++)
1051 command_print(cmd_ctx
, "%s: %s", arm9tdmi_vectors
[i
].name
,
1052 (vector_catch_value
& (1 << i
)) ? "catch" : "don't catch");
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