1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2007,2008,2009 by Øyvind Harboe *
6 * oyvind.harboe@zylin.com *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
27 #include "arm926ejs.h"
28 #include <helper/time_support.h>
29 #include "target_type.h"
31 #include "arm_opcodes.h"
35 * The ARM926 is built around the ARM9EJ-S core, and most JTAG docs
36 * are in the ARM9EJ-S Technical Reference Manual (ARM DDI 0222B) not
37 * the ARM926 manual (ARM DDI 0198E). The scan chains are:
39 * 1 ... core debugging
41 * 3 ... external boundary scan (SoC-specific, unused here)
43 * 15 ... coprocessor 15
47 #define _DEBUG_INSTRUCTION_EXECUTION_
50 #define ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm) ((opcode_1 << 11) | (opcode_2 << 8) | (CRn << 4) | (CRm << 0))
52 static int arm926ejs_cp15_read(struct target
*target
, uint32_t op1
, uint32_t op2
,
53 uint32_t CRn
, uint32_t CRm
, uint32_t *value
)
55 int retval
= ERROR_OK
;
56 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
57 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
58 uint32_t address
= ARM926EJS_CP15_ADDR(op1
, op2
, CRn
, CRm
);
59 struct scan_field fields
[4];
60 uint8_t address_buf
[2] = {0, 0};
64 buf_set_u32(address_buf
, 0, 14, address
);
66 if ((retval
= arm_jtag_scann(jtag_info
, 0xf, TAP_IDLE
)) != ERROR_OK
)
70 retval
= arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
, TAP_IDLE
);
71 if (retval
!= ERROR_OK
)
74 fields
[0].num_bits
= 32;
75 fields
[0].out_value
= NULL
;
76 fields
[0].in_value
= (uint8_t *)value
;
78 fields
[1].num_bits
= 1;
79 fields
[1].out_value
= &access_t
;
80 fields
[1].in_value
= &access_t
;
82 fields
[2].num_bits
= 14;
83 fields
[2].out_value
= address_buf
;
84 fields
[2].in_value
= NULL
;
86 fields
[3].num_bits
= 1;
87 fields
[3].out_value
= &nr_w_buf
;
88 fields
[3].in_value
= NULL
;
90 jtag_add_dr_scan(jtag_info
->tap
, 4, fields
, TAP_IDLE
);
92 long long then
= timeval_ms();
96 /* rescan with NOP, to wait for the access to complete */
99 jtag_add_dr_scan(jtag_info
->tap
, 4, fields
, TAP_IDLE
);
101 jtag_add_callback(arm_le_to_h_u32
, (jtag_callback_data_t
)value
);
103 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
108 if (buf_get_u32(&access_t
, 0, 1) == 1)
114 if ((timeval_ms()-then
)>10)
116 LOG_ERROR("cp15 read operation timed out");
121 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
122 LOG_DEBUG("addr: 0x%x value: %8.8x", address
, *value
);
125 retval
= arm_jtag_set_instr(jtag_info
, 0xc, NULL
, TAP_IDLE
);
126 if (retval
!= ERROR_OK
)
132 static int arm926ejs_mrc(struct target
*target
, int cpnum
, uint32_t op1
,
133 uint32_t op2
, uint32_t CRn
, uint32_t CRm
, uint32_t *value
)
136 LOG_ERROR("Only cp15 is supported");
139 return arm926ejs_cp15_read(target
, op1
, op2
, CRn
, CRm
, value
);
142 static int arm926ejs_cp15_write(struct target
*target
, uint32_t op1
, uint32_t op2
,
143 uint32_t CRn
, uint32_t CRm
, uint32_t value
)
145 int retval
= ERROR_OK
;
146 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
147 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
148 uint32_t address
= ARM926EJS_CP15_ADDR(op1
, op2
, CRn
, CRm
);
149 struct scan_field fields
[4];
150 uint8_t value_buf
[4];
151 uint8_t address_buf
[2] = {0, 0};
152 uint8_t nr_w_buf
= 1;
153 uint8_t access_t
= 1;
155 buf_set_u32(address_buf
, 0, 14, address
);
156 buf_set_u32(value_buf
, 0, 32, value
);
158 if ((retval
= arm_jtag_scann(jtag_info
, 0xf, TAP_IDLE
)) != ERROR_OK
)
162 retval
= arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
, TAP_IDLE
);
163 if (retval
!= ERROR_OK
)
166 fields
[0].num_bits
= 32;
167 fields
[0].out_value
= value_buf
;
168 fields
[0].in_value
= NULL
;
170 fields
[1].num_bits
= 1;
171 fields
[1].out_value
= &access_t
;
172 fields
[1].in_value
= &access_t
;
174 fields
[2].num_bits
= 14;
175 fields
[2].out_value
= address_buf
;
176 fields
[2].in_value
= NULL
;
178 fields
[3].num_bits
= 1;
179 fields
[3].out_value
= &nr_w_buf
;
180 fields
[3].in_value
= NULL
;
182 jtag_add_dr_scan(jtag_info
->tap
, 4, fields
, TAP_IDLE
);
184 long long then
= timeval_ms();
188 /* rescan with NOP, to wait for the access to complete */
191 jtag_add_dr_scan(jtag_info
->tap
, 4, fields
, TAP_IDLE
);
192 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
197 if (buf_get_u32(&access_t
, 0, 1) == 1)
203 if ((timeval_ms()-then
)>10)
205 LOG_ERROR("cp15 write operation timed out");
210 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
211 LOG_DEBUG("addr: 0x%x value: %8.8x", address
, value
);
214 retval
= arm_jtag_set_instr(jtag_info
, 0xf, NULL
, TAP_IDLE
);
215 if (retval
!= ERROR_OK
)
221 static int arm926ejs_mcr(struct target
*target
, int cpnum
, uint32_t op1
,
222 uint32_t op2
, uint32_t CRn
, uint32_t CRm
, uint32_t value
)
225 LOG_ERROR("Only cp15 is supported");
228 return arm926ejs_cp15_write(target
, op1
, op2
, CRn
, CRm
, value
);
231 static int arm926ejs_examine_debug_reason(struct target
*target
)
233 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
234 struct reg
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
238 embeddedice_read_reg(dbg_stat
);
239 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
242 /* Method-Of-Entry (MOE) field */
243 debug_reason
= buf_get_u32(dbg_stat
->value
, 6, 4);
245 switch (debug_reason
)
248 LOG_DEBUG("no *NEW* debug entry (?missed one?)");
249 /* ... since last restart or debug reset ... */
250 target
->debug_reason
= DBG_REASON_DBGRQ
;
253 LOG_DEBUG("breakpoint from EICE unit 0");
254 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
257 LOG_DEBUG("breakpoint from EICE unit 1");
258 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
261 LOG_DEBUG("soft breakpoint (BKPT instruction)");
262 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
265 LOG_DEBUG("vector catch breakpoint");
266 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
269 LOG_DEBUG("external breakpoint");
270 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
273 LOG_DEBUG("watchpoint from EICE unit 0");
274 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
277 LOG_DEBUG("watchpoint from EICE unit 1");
278 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
281 LOG_DEBUG("external watchpoint");
282 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
285 LOG_DEBUG("internal debug request");
286 target
->debug_reason
= DBG_REASON_DBGRQ
;
289 LOG_DEBUG("external debug request");
290 target
->debug_reason
= DBG_REASON_DBGRQ
;
293 LOG_DEBUG("debug re-entry from system speed access");
294 /* This is normal when connecting to something that's
295 * already halted, or in some related code paths, but
296 * otherwise is surprising (and presumably wrong).
298 switch (target
->debug_reason
) {
299 case DBG_REASON_DBGRQ
:
302 LOG_ERROR("unexpected -- debug re-entry");
304 case DBG_REASON_UNDEFINED
:
305 target
->debug_reason
= DBG_REASON_DBGRQ
;
310 /* FIX!!!! here be dragons!!! We need to fail here so
311 * the target will interpreted as halted but we won't
312 * try to talk to it right now... a resume + halt seems
313 * to sync things up again. Please send an email to
314 * openocd development mailing list if you have hardware
315 * to donate to look into this problem....
317 LOG_WARNING("WARNING: mystery debug reason MOE = 0xc. Try issuing a resume + halt.");
318 target
->debug_reason
= DBG_REASON_DBGRQ
;
321 LOG_WARNING("WARNING: unknown debug reason: 0x%x", debug_reason
);
322 /* Oh agony! should we interpret this as a halt request or
323 * that the target stopped on it's own accord?
325 target
->debug_reason
= DBG_REASON_DBGRQ
;
326 /* if we fail here, we won't talk to the target and it will
327 * be reported to be in the halted state */
334 static int arm926ejs_get_ttb(struct target
*target
, uint32_t *result
)
336 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
340 if ((retval
= arm926ejs
->read_cp15(target
, 0, 0, 2, 0, &ttb
)) != ERROR_OK
)
348 static int arm926ejs_disable_mmu_caches(struct target
*target
, int mmu
,
349 int d_u_cache
, int i_cache
)
351 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
352 uint32_t cp15_control
;
355 /* read cp15 control register */
356 retval
= arm926ejs
->read_cp15(target
, 0, 0, 1, 0, &cp15_control
);
357 if (retval
!= ERROR_OK
)
359 retval
= jtag_execute_queue();
360 if (retval
!= ERROR_OK
)
366 retval
= arm926ejs
->write_cp15(target
, 0, 0, 8, 7, 0x0);
367 if (retval
!= ERROR_OK
)
370 cp15_control
&= ~0x1U
;
375 uint32_t debug_override
;
376 /* read-modify-write CP15 debug override register
377 * to enable "test and clean all" */
378 retval
= arm926ejs
->read_cp15(target
, 0, 0, 15, 0, &debug_override
);
379 if (retval
!= ERROR_OK
)
381 debug_override
|= 0x80000;
382 retval
= arm926ejs
->write_cp15(target
, 0, 0, 15, 0, debug_override
);
383 if (retval
!= ERROR_OK
)
386 /* clean and invalidate DCache */
387 retval
= arm926ejs
->write_cp15(target
, 0, 0, 7, 5, 0x0);
388 if (retval
!= ERROR_OK
)
391 /* write CP15 debug override register
392 * to disable "test and clean all" */
393 debug_override
&= ~0x80000;
394 retval
= arm926ejs
->write_cp15(target
, 0, 0, 15, 0, debug_override
);
395 if (retval
!= ERROR_OK
)
398 cp15_control
&= ~0x4U
;
403 /* invalidate ICache */
404 retval
= arm926ejs
->write_cp15(target
, 0, 0, 7, 5, 0x0);
405 if (retval
!= ERROR_OK
)
408 cp15_control
&= ~0x1000U
;
411 retval
= arm926ejs
->write_cp15(target
, 0, 0, 1, 0, cp15_control
);
415 static int arm926ejs_enable_mmu_caches(struct target
*target
, int mmu
,
416 int d_u_cache
, int i_cache
)
418 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
419 uint32_t cp15_control
;
422 /* read cp15 control register */
423 retval
= arm926ejs
->read_cp15(target
, 0, 0, 1, 0, &cp15_control
);
424 if (retval
!= ERROR_OK
)
426 retval
= jtag_execute_queue();
427 if (retval
!= ERROR_OK
)
431 cp15_control
|= 0x1U
;
434 cp15_control
|= 0x4U
;
437 cp15_control
|= 0x1000U
;
439 retval
= arm926ejs
->write_cp15(target
, 0, 0, 1, 0, cp15_control
);
443 static int arm926ejs_post_debug_entry(struct target
*target
)
445 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
448 /* examine cp15 control reg */
449 retval
= arm926ejs
->read_cp15(target
, 0, 0, 1, 0, &arm926ejs
->cp15_control_reg
);
450 if (retval
!= ERROR_OK
)
452 retval
= jtag_execute_queue();
453 if (retval
!= ERROR_OK
)
455 LOG_DEBUG("cp15_control_reg: %8.8" PRIx32
"", arm926ejs
->cp15_control_reg
);
457 if (arm926ejs
->armv4_5_mmu
.armv4_5_cache
.ctype
== -1)
459 uint32_t cache_type_reg
;
460 /* identify caches */
461 retval
= arm926ejs
->read_cp15(target
, 0, 1, 0, 0, &cache_type_reg
);
462 if (retval
!= ERROR_OK
)
464 retval
= jtag_execute_queue();
465 if (retval
!= ERROR_OK
)
467 armv4_5_identify_cache(cache_type_reg
, &arm926ejs
->armv4_5_mmu
.armv4_5_cache
);
470 arm926ejs
->armv4_5_mmu
.mmu_enabled
= (arm926ejs
->cp15_control_reg
& 0x1U
) ? 1 : 0;
471 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= (arm926ejs
->cp15_control_reg
& 0x4U
) ? 1 : 0;
472 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= (arm926ejs
->cp15_control_reg
& 0x1000U
) ? 1 : 0;
474 /* save i/d fault status and address register */
475 retval
= arm926ejs
->read_cp15(target
, 0, 0, 5, 0, &arm926ejs
->d_fsr
);
476 if (retval
!= ERROR_OK
)
478 retval
= arm926ejs
->read_cp15(target
, 0, 1, 5, 0, &arm926ejs
->i_fsr
);
479 if (retval
!= ERROR_OK
)
481 retval
= arm926ejs
->read_cp15(target
, 0, 0, 6, 0, &arm926ejs
->d_far
);
482 if (retval
!= ERROR_OK
)
485 LOG_DEBUG("D FSR: 0x%8.8" PRIx32
", D FAR: 0x%8.8" PRIx32
", I FSR: 0x%8.8" PRIx32
"",
486 arm926ejs
->d_fsr
, arm926ejs
->d_far
, arm926ejs
->i_fsr
);
488 uint32_t cache_dbg_ctrl
;
490 /* read-modify-write CP15 cache debug control register
491 * to disable I/D-cache linefills and force WT */
492 retval
= arm926ejs
->read_cp15(target
, 7, 0, 15, 0, &cache_dbg_ctrl
);
493 if (retval
!= ERROR_OK
)
495 cache_dbg_ctrl
|= 0x7;
496 retval
= arm926ejs
->write_cp15(target
, 7, 0, 15, 0, cache_dbg_ctrl
);
500 static void arm926ejs_pre_restore_context(struct target
*target
)
502 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
504 /* restore i/d fault status and address register */
505 arm926ejs
->write_cp15(target
, 0, 0, 5, 0, arm926ejs
->d_fsr
);
506 arm926ejs
->write_cp15(target
, 0, 1, 5, 0, arm926ejs
->i_fsr
);
507 arm926ejs
->write_cp15(target
, 0, 0, 6, 0, arm926ejs
->d_far
);
509 uint32_t cache_dbg_ctrl
;
511 /* read-modify-write CP15 cache debug control register
512 * to reenable I/D-cache linefills and disable WT */
513 arm926ejs
->read_cp15(target
, 7, 0, 15, 0, &cache_dbg_ctrl
);
514 cache_dbg_ctrl
&= ~0x7;
515 arm926ejs
->write_cp15(target
, 7, 0, 15, 0, cache_dbg_ctrl
);
518 static const char arm926_not
[] = "target is not an ARM926";
520 static int arm926ejs_verify_pointer(struct command_context
*cmd_ctx
,
521 struct arm926ejs_common
*arm926
)
523 if (arm926
->common_magic
!= ARM926EJS_COMMON_MAGIC
) {
524 command_print(cmd_ctx
, arm926_not
);
525 return ERROR_TARGET_INVALID
;
530 /** Logs summary of ARM926 state for a halted target. */
531 int arm926ejs_arch_state(struct target
*target
)
533 static const char *state
[] =
535 "disabled", "enabled"
538 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
540 if (arm926ejs
->common_magic
!= ARM926EJS_COMMON_MAGIC
)
542 LOG_ERROR("BUG: %s", arm926_not
);
543 return ERROR_TARGET_INVALID
;
546 arm_arch_state(target
);
547 LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
548 state
[arm926ejs
->armv4_5_mmu
.mmu_enabled
],
549 state
[arm926ejs
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
],
550 state
[arm926ejs
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
]);
555 int arm926ejs_soft_reset_halt(struct target
*target
)
557 int retval
= ERROR_OK
;
558 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
559 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
560 struct arm
*armv4_5
= &arm7_9
->armv4_5_common
;
561 struct reg
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
563 if ((retval
= target_halt(target
)) != ERROR_OK
)
568 long long then
= timeval_ms();
570 while (!(timeout
= ((timeval_ms()-then
) > 1000)))
572 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1) == 0)
574 embeddedice_read_reg(dbg_stat
);
575 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
583 if (debug_level
>= 1)
585 /* do not eat all CPU, time out after 1 se*/
594 LOG_ERROR("Failed to halt CPU after 1 sec");
595 return ERROR_TARGET_TIMEOUT
;
598 target
->state
= TARGET_HALTED
;
600 /* SVC, ARM state, IRQ and FIQ disabled */
603 cpsr
= buf_get_u32(armv4_5
->cpsr
->value
, 0, 32);
606 arm_set_cpsr(armv4_5
, cpsr
);
607 armv4_5
->cpsr
->dirty
= 1;
609 /* start fetching from 0x0 */
610 buf_set_u32(armv4_5
->pc
->value
, 0, 32, 0x0);
611 armv4_5
->pc
->dirty
= 1;
612 armv4_5
->pc
->valid
= 1;
614 retval
= arm926ejs_disable_mmu_caches(target
, 1, 1, 1);
615 if (retval
!= ERROR_OK
)
617 arm926ejs
->armv4_5_mmu
.mmu_enabled
= 0;
618 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= 0;
619 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 0;
621 return target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
624 /** Writes a buffer, in the specified word size, with current MMU settings. */
625 int arm926ejs_write_memory(struct target
*target
, uint32_t address
,
626 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
629 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
631 /* FIX!!!! this should be cleaned up and made much more general. The
632 * plan is to write up and test on arm926ejs specifically and
633 * then generalize and clean up afterwards.
636 * Also it should be moved to the callbacks that handle breakpoints
637 * specifically and not the generic memory write fn's. See XScale code.
639 if (arm926ejs
->armv4_5_mmu
.mmu_enabled
&& (count
== 1) && ((size
==2) || (size
==4)))
641 /* special case the handling of single word writes to bypass MMU
642 * to allow implementation of breakpoints in memory marked read only
644 if (arm926ejs
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
)
646 /* flush and invalidate data cache
648 * MCR p15,0,p,c7,c10,1 - clean cache line using virtual address
651 retval
= arm926ejs
->write_cp15(target
, 0, 1, 7, 10, address
&~0x3);
652 if (retval
!= ERROR_OK
)
657 retval
= target
->type
->virt2phys(target
, address
, &pa
);
658 if (retval
!= ERROR_OK
)
661 /* write directly to physical memory bypassing any read only MMU bits, etc. */
662 retval
= armv4_5_mmu_write_physical(target
, &arm926ejs
->armv4_5_mmu
, pa
, size
, count
, buffer
);
663 if (retval
!= ERROR_OK
)
667 if ((retval
= arm7_9_write_memory(target
, address
, size
, count
, buffer
)) != ERROR_OK
)
671 /* If ICache is enabled, we have to invalidate affected ICache lines
672 * the DCache is forced to write-through, so we don't have to clean it here
674 if (arm926ejs
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
)
678 /* invalidate ICache single entry with MVA */
679 arm926ejs
->write_cp15(target
, 0, 1, 7, 5, address
);
683 /* invalidate ICache */
684 arm926ejs
->write_cp15(target
, 0, 0, 7, 5, address
);
691 static int arm926ejs_write_phys_memory(struct target
*target
,
692 uint32_t address
, uint32_t size
,
693 uint32_t count
, const uint8_t *buffer
)
695 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
697 return armv4_5_mmu_write_physical(target
, &arm926ejs
->armv4_5_mmu
,
698 address
, size
, count
, buffer
);
701 static int arm926ejs_read_phys_memory(struct target
*target
,
702 uint32_t address
, uint32_t size
,
703 uint32_t count
, uint8_t *buffer
)
705 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
707 return armv4_5_mmu_read_physical(target
, &arm926ejs
->armv4_5_mmu
,
708 address
, size
, count
, buffer
);
711 int arm926ejs_init_arch_info(struct target
*target
, struct arm926ejs_common
*arm926ejs
,
712 struct jtag_tap
*tap
)
714 struct arm7_9_common
*arm7_9
= &arm926ejs
->arm7_9_common
;
716 arm7_9
->armv4_5_common
.mrc
= arm926ejs_mrc
;
717 arm7_9
->armv4_5_common
.mcr
= arm926ejs_mcr
;
719 /* initialize arm7/arm9 specific info (including armv4_5) */
720 arm9tdmi_init_arch_info(target
, arm7_9
, tap
);
722 arm926ejs
->common_magic
= ARM926EJS_COMMON_MAGIC
;
724 arm7_9
->post_debug_entry
= arm926ejs_post_debug_entry
;
725 arm7_9
->pre_restore_context
= arm926ejs_pre_restore_context
;
727 arm926ejs
->read_cp15
= arm926ejs_cp15_read
;
728 arm926ejs
->write_cp15
= arm926ejs_cp15_write
;
729 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.ctype
= -1;
730 arm926ejs
->armv4_5_mmu
.get_ttb
= arm926ejs_get_ttb
;
731 arm926ejs
->armv4_5_mmu
.read_memory
= arm7_9_read_memory
;
732 arm926ejs
->armv4_5_mmu
.write_memory
= arm7_9_write_memory
;
733 arm926ejs
->armv4_5_mmu
.disable_mmu_caches
= arm926ejs_disable_mmu_caches
;
734 arm926ejs
->armv4_5_mmu
.enable_mmu_caches
= arm926ejs_enable_mmu_caches
;
735 arm926ejs
->armv4_5_mmu
.has_tiny_pages
= 1;
736 arm926ejs
->armv4_5_mmu
.mmu_enabled
= 0;
738 arm7_9
->examine_debug_reason
= arm926ejs_examine_debug_reason
;
740 /* The ARM926EJ-S implements the ARMv5TE architecture which
741 * has the BKPT instruction, so we don't have to use a watchpoint comparator
743 arm7_9
->arm_bkpt
= ARMV5_BKPT(0x0);
744 arm7_9
->thumb_bkpt
= ARMV5_T_BKPT(0x0) & 0xffff;
749 static int arm926ejs_target_create(struct target
*target
, Jim_Interp
*interp
)
751 struct arm926ejs_common
*arm926ejs
= calloc(1,sizeof(struct arm926ejs_common
));
753 /* ARM9EJ-S core always reports 0x1 in Capture-IR */
754 target
->tap
->ir_capture_mask
= 0x0f;
756 return arm926ejs_init_arch_info(target
, arm926ejs
, target
->tap
);
759 COMMAND_HANDLER(arm926ejs_handle_cache_info_command
)
762 struct target
*target
= get_current_target(CMD_CTX
);
763 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
765 retval
= arm926ejs_verify_pointer(CMD_CTX
, arm926ejs
);
766 if (retval
!= ERROR_OK
)
769 return armv4_5_handle_cache_info_command(CMD_CTX
, &arm926ejs
->armv4_5_mmu
.armv4_5_cache
);
772 static int arm926ejs_virt2phys(struct target
*target
, uint32_t virtual, uint32_t *physical
)
775 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
778 int retval
= armv4_5_mmu_translate_va(target
, &arm926ejs
->armv4_5_mmu
,
780 if (retval
!= ERROR_OK
)
786 static int arm926ejs_mmu(struct target
*target
, int *enabled
)
788 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
790 if (target
->state
!= TARGET_HALTED
)
792 LOG_ERROR("Target not halted");
793 return ERROR_TARGET_INVALID
;
795 *enabled
= arm926ejs
->armv4_5_mmu
.mmu_enabled
;
799 static const struct command_registration arm926ejs_exec_command_handlers
[] = {
801 .name
= "cache_info",
802 .handler
= arm926ejs_handle_cache_info_command
,
803 .mode
= COMMAND_EXEC
,
804 .help
= "display information about target caches",
807 COMMAND_REGISTRATION_DONE
809 const struct command_registration arm926ejs_command_handlers
[] = {
811 .chain
= arm9tdmi_command_handlers
,
816 .help
= "arm926ejs command group",
817 .chain
= arm926ejs_exec_command_handlers
,
819 COMMAND_REGISTRATION_DONE
822 /** Holds methods for ARM926 targets. */
823 struct target_type arm926ejs_target
=
828 .arch_state
= arm926ejs_arch_state
,
830 .target_request_data
= arm7_9_target_request_data
,
833 .resume
= arm7_9_resume
,
836 .assert_reset
= arm7_9_assert_reset
,
837 .deassert_reset
= arm7_9_deassert_reset
,
838 .soft_reset_halt
= arm926ejs_soft_reset_halt
,
840 .get_gdb_reg_list
= arm_get_gdb_reg_list
,
842 .read_memory
= arm7_9_read_memory
,
843 .write_memory
= arm926ejs_write_memory
,
844 .bulk_write_memory
= arm7_9_bulk_write_memory
,
846 .checksum_memory
= arm_checksum_memory
,
847 .blank_check_memory
= arm_blank_check_memory
,
849 .run_algorithm
= armv4_5_run_algorithm
,
851 .add_breakpoint
= arm7_9_add_breakpoint
,
852 .remove_breakpoint
= arm7_9_remove_breakpoint
,
853 .add_watchpoint
= arm7_9_add_watchpoint
,
854 .remove_watchpoint
= arm7_9_remove_watchpoint
,
856 .commands
= arm926ejs_command_handlers
,
857 .target_create
= arm926ejs_target_create
,
858 .init_target
= arm9tdmi_init_target
,
859 .examine
= arm7_9_examine
,
860 .check_reset
= arm7_9_check_reset
,
861 .virt2phys
= arm926ejs_virt2phys
,
862 .mmu
= arm926ejs_mmu
,
864 .read_phys_memory
= arm926ejs_read_phys_memory
,
865 .write_phys_memory
= arm926ejs_write_phys_memory
,
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