1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include "arm926ejs.h"
27 #include "time_support.h"
33 #define _DEBUG_INSTRUCTION_EXECUTION_
37 int arm926ejs_register_commands(struct command_context_s
*cmd_ctx
);
39 int arm926ejs_handle_cp15_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
40 int arm926ejs_handle_cp15i_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
41 int arm926ejs_handle_virt2phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
42 int arm926ejs_handle_cache_info_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
43 int arm926ejs_handle_md_phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
44 int arm926ejs_handle_mw_phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
46 int arm926ejs_handle_read_cache_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
47 int arm926ejs_handle_read_mmu_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
49 /* forward declarations */
50 int arm926ejs_target_create(struct target_s
*target
, Jim_Interp
*interp
);
51 int arm926ejs_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
);
52 int arm926ejs_quit(void);
53 int arm926ejs_arch_state(struct target_s
*target
);
54 int arm926ejs_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
55 int arm926ejs_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
56 int arm926ejs_soft_reset_halt(struct target_s
*target
);
57 static int arm926ejs_virt2phys(struct target_s
*target
, u32
virtual, u32
*physical
);
58 static int arm926ejs_mmu(struct target_s
*target
, int *enabled
);
60 target_type_t arm926ejs_target
=
65 .arch_state
= arm926ejs_arch_state
,
67 .target_request_data
= arm7_9_target_request_data
,
70 .resume
= arm7_9_resume
,
73 .assert_reset
= arm7_9_assert_reset
,
74 .deassert_reset
= arm7_9_deassert_reset
,
75 .soft_reset_halt
= arm926ejs_soft_reset_halt
,
77 .get_gdb_reg_list
= armv4_5_get_gdb_reg_list
,
79 .read_memory
= arm7_9_read_memory
,
80 .write_memory
= arm926ejs_write_memory
,
81 .bulk_write_memory
= arm7_9_bulk_write_memory
,
82 .checksum_memory
= arm7_9_checksum_memory
,
83 .blank_check_memory
= arm7_9_blank_check_memory
,
85 .run_algorithm
= armv4_5_run_algorithm
,
87 .add_breakpoint
= arm7_9_add_breakpoint
,
88 .remove_breakpoint
= arm7_9_remove_breakpoint
,
89 .add_watchpoint
= arm7_9_add_watchpoint
,
90 .remove_watchpoint
= arm7_9_remove_watchpoint
,
92 .register_commands
= arm926ejs_register_commands
,
93 .target_create
= arm926ejs_target_create
,
94 .init_target
= arm926ejs_init_target
,
95 .examine
= arm9tdmi_examine
,
96 .quit
= arm926ejs_quit
,
97 .virt2phys
= arm926ejs_virt2phys
,
102 int arm926ejs_catch_broken_irscan(u8
*captured
, void *priv
, scan_field_t
*field
)
104 /* The ARM926EJ-S' instruction register is 4 bits wide */
105 u8 t
= *captured
& 0xf;
106 u8 t2
= *field
->in_check_value
& 0xf;
111 else if ((t
== 0x0f) || (t
== 0x00))
113 LOG_DEBUG("caught ARM926EJ-S invalid Capture-IR result after CP15 access");
116 return ERROR_JTAG_QUEUE_FAILED
;;
119 #define ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm) ((opcode_1 << 11) | (opcode_2 << 8) | (CRn << 4) | (CRm << 0))
121 int arm926ejs_cp15_read(target_t
*target
, u32 op1
, u32 op2
, u32 CRn
, u32 CRm
, u32
*value
)
123 int retval
= ERROR_OK
;
124 armv4_5_common_t
*armv4_5
= target
->arch_info
;
125 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
126 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
127 u32 address
= ARM926EJS_CP15_ADDR(op1
, op2
, CRn
, CRm
);
128 scan_field_t fields
[4];
133 buf_set_u32(address_buf
, 0, 14, address
);
135 jtag_add_end_state(TAP_RTI
);
136 if((retval
= arm_jtag_scann(jtag_info
, 0xf)) != ERROR_OK
)
140 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
142 fields
[0].device
= jtag_info
->chain_pos
;
143 fields
[0].num_bits
= 32;
144 fields
[0].out_value
= NULL
;
145 fields
[0].out_mask
= NULL
;
146 fields
[0].in_value
= NULL
;
147 fields
[0].in_check_value
= NULL
;
148 fields
[0].in_check_mask
= NULL
;
149 fields
[0].in_handler
= NULL
;
150 fields
[0].in_handler_priv
= NULL
;
152 fields
[1].device
= jtag_info
->chain_pos
;
153 fields
[1].num_bits
= 1;
154 fields
[1].out_value
= &access
;
155 fields
[1].out_mask
= NULL
;
156 fields
[1].in_value
= &access
;
157 fields
[1].in_check_value
= NULL
;
158 fields
[1].in_check_mask
= NULL
;
159 fields
[1].in_handler
= NULL
;
160 fields
[1].in_handler_priv
= NULL
;
162 fields
[2].device
= jtag_info
->chain_pos
;
163 fields
[2].num_bits
= 14;
164 fields
[2].out_value
= address_buf
;
165 fields
[2].out_mask
= NULL
;
166 fields
[2].in_value
= NULL
;
167 fields
[2].in_check_value
= NULL
;
168 fields
[2].in_check_mask
= NULL
;
169 fields
[2].in_handler
= NULL
;
170 fields
[2].in_handler_priv
= NULL
;
172 fields
[3].device
= jtag_info
->chain_pos
;
173 fields
[3].num_bits
= 1;
174 fields
[3].out_value
= &nr_w_buf
;
175 fields
[3].out_mask
= NULL
;
176 fields
[3].in_value
= NULL
;
177 fields
[3].in_check_value
= NULL
;
178 fields
[3].in_check_mask
= NULL
;
179 fields
[3].in_handler
= NULL
;
180 fields
[3].in_handler_priv
= NULL
;
182 jtag_add_dr_scan(4, fields
, -1);
184 fields
[0].in_handler_priv
= value
;
185 fields
[0].in_handler
= arm_jtag_buf_to_u32
;
187 /*TODO: add timeout*/
190 /* rescan with NOP, to wait for the access to complete */
193 jtag_add_dr_scan(4, fields
, -1);
194 if((retval
= jtag_execute_queue()) != ERROR_OK
)
198 } while (buf_get_u32(&access
, 0, 1) != 1);
200 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
201 LOG_DEBUG("addr: 0x%x value: %8.8x", address
, *value
);
204 arm_jtag_set_instr(jtag_info
, 0xc, &arm926ejs_catch_broken_irscan
);
209 int arm926ejs_cp15_write(target_t
*target
, u32 op1
, u32 op2
, u32 CRn
, u32 CRm
, u32 value
)
211 int retval
= ERROR_OK
;
212 armv4_5_common_t
*armv4_5
= target
->arch_info
;
213 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
214 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
215 u32 address
= ARM926EJS_CP15_ADDR(op1
, op2
, CRn
, CRm
);
216 scan_field_t fields
[4];
222 buf_set_u32(address_buf
, 0, 14, address
);
223 buf_set_u32(value_buf
, 0, 32, value
);
225 jtag_add_end_state(TAP_RTI
);
226 if((retval
= arm_jtag_scann(jtag_info
, 0xf)) != ERROR_OK
)
230 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
232 fields
[0].device
= jtag_info
->chain_pos
;
233 fields
[0].num_bits
= 32;
234 fields
[0].out_value
= value_buf
;
235 fields
[0].out_mask
= NULL
;
236 fields
[0].in_value
= NULL
;
237 fields
[0].in_check_value
= NULL
;
238 fields
[0].in_check_mask
= NULL
;
239 fields
[0].in_handler
= NULL
;
240 fields
[0].in_handler_priv
= NULL
;
242 fields
[1].device
= jtag_info
->chain_pos
;
243 fields
[1].num_bits
= 1;
244 fields
[1].out_value
= &access
;
245 fields
[1].out_mask
= NULL
;
246 fields
[1].in_value
= &access
;
247 fields
[1].in_check_value
= NULL
;
248 fields
[1].in_check_mask
= NULL
;
249 fields
[1].in_handler
= NULL
;
250 fields
[1].in_handler_priv
= NULL
;
252 fields
[2].device
= jtag_info
->chain_pos
;
253 fields
[2].num_bits
= 14;
254 fields
[2].out_value
= address_buf
;
255 fields
[2].out_mask
= NULL
;
256 fields
[2].in_value
= NULL
;
257 fields
[2].in_check_value
= NULL
;
258 fields
[2].in_check_mask
= NULL
;
259 fields
[2].in_handler
= NULL
;
260 fields
[2].in_handler_priv
= NULL
;
262 fields
[3].device
= jtag_info
->chain_pos
;
263 fields
[3].num_bits
= 1;
264 fields
[3].out_value
= &nr_w_buf
;
265 fields
[3].out_mask
= NULL
;
266 fields
[3].in_value
= NULL
;
267 fields
[3].in_check_value
= NULL
;
268 fields
[3].in_check_mask
= NULL
;
269 fields
[3].in_handler
= NULL
;
270 fields
[3].in_handler_priv
= NULL
;
272 jtag_add_dr_scan(4, fields
, -1);
273 /*TODO: add timeout*/
276 /* rescan with NOP, to wait for the access to complete */
279 jtag_add_dr_scan(4, fields
, -1);
280 if((retval
= jtag_execute_queue()) != ERROR_OK
)
284 } while (buf_get_u32(&access
, 0, 1) != 1);
286 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
287 LOG_DEBUG("addr: 0x%x value: %8.8x", address
, value
);
290 arm_jtag_set_instr(jtag_info
, 0xf, &arm926ejs_catch_broken_irscan
);
295 int arm926ejs_examine_debug_reason(target_t
*target
)
297 armv4_5_common_t
*armv4_5
= target
->arch_info
;
298 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
299 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
303 embeddedice_read_reg(dbg_stat
);
304 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
307 debug_reason
= buf_get_u32(dbg_stat
->value
, 6, 4);
309 switch (debug_reason
)
312 LOG_DEBUG("breakpoint from EICE unit 0");
313 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
316 LOG_DEBUG("breakpoint from EICE unit 1");
317 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
320 LOG_DEBUG("soft breakpoint (BKPT instruction)");
321 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
324 LOG_DEBUG("vector catch breakpoint");
325 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
328 LOG_DEBUG("external breakpoint");
329 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
332 LOG_DEBUG("watchpoint from EICE unit 0");
333 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
336 LOG_DEBUG("watchpoint from EICE unit 1");
337 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
340 LOG_DEBUG("external watchpoint");
341 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
344 LOG_DEBUG("internal debug request");
345 target
->debug_reason
= DBG_REASON_DBGRQ
;
348 LOG_DEBUG("external debug request");
349 target
->debug_reason
= DBG_REASON_DBGRQ
;
352 LOG_ERROR("BUG: debug re-entry from system speed access shouldn't be handled here");
355 /* FIX!!!! here be dragons!!! We need to fail here so
356 * the target will interpreted as halted but we won't
357 * try to talk to it right now... a resume + halt seems
358 * to sync things up again. Please send an email to
359 * openocd development mailing list if you have hardware
360 * to donate to look into this problem....
362 LOG_ERROR("mystery debug reason MOE=0xc. Try issuing a resume + halt.");
363 target
->debug_reason
= DBG_REASON_DBGRQ
;
364 retval
= ERROR_TARGET_FAILURE
;
367 LOG_ERROR("BUG: unknown debug reason: 0x%x", debug_reason
);
368 target
->debug_reason
= DBG_REASON_DBGRQ
;
369 /* if we fail here, we won't talk to the target and it will
370 * be reported to be in the halted state */
371 retval
= ERROR_TARGET_FAILURE
;
378 u32
arm926ejs_get_ttb(target_t
*target
)
380 armv4_5_common_t
*armv4_5
= target
->arch_info
;
381 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
382 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
383 arm926ejs_common_t
*arm926ejs
= arm9tdmi
->arch_info
;
387 if ((retval
= arm926ejs
->read_cp15(target
, 0, 0, 2, 0, &ttb
)) != ERROR_OK
)
393 void arm926ejs_disable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
395 armv4_5_common_t
*armv4_5
= target
->arch_info
;
396 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
397 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
398 arm926ejs_common_t
*arm926ejs
= arm9tdmi
->arch_info
;
401 /* read cp15 control register */
402 arm926ejs
->read_cp15(target
, 0, 0, 1, 0, &cp15_control
);
403 jtag_execute_queue();
408 arm926ejs
->write_cp15(target
, 0, 0, 8, 7, 0x0);
410 cp15_control
&= ~0x1U
;
416 /* read-modify-write CP15 debug override register
417 * to enable "test and clean all" */
418 arm926ejs
->read_cp15(target
, 0, 0, 15, 0, &debug_override
);
419 debug_override
|= 0x80000;
420 arm926ejs
->write_cp15(target
, 0, 0, 15, 0, debug_override
);
422 /* clean and invalidate DCache */
423 arm926ejs
->write_cp15(target
, 0, 0, 7, 5, 0x0);
425 /* write CP15 debug override register
426 * to disable "test and clean all" */
427 debug_override
&= ~0x80000;
428 arm926ejs
->write_cp15(target
, 0, 0, 15, 0, debug_override
);
430 cp15_control
&= ~0x4U
;
435 /* invalidate ICache */
436 arm926ejs
->write_cp15(target
, 0, 0, 7, 5, 0x0);
438 cp15_control
&= ~0x1000U
;
441 arm926ejs
->write_cp15(target
, 0, 0, 1, 0, cp15_control
);
444 void arm926ejs_enable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
446 armv4_5_common_t
*armv4_5
= target
->arch_info
;
447 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
448 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
449 arm926ejs_common_t
*arm926ejs
= arm9tdmi
->arch_info
;
452 /* read cp15 control register */
453 arm926ejs
->read_cp15(target
, 0, 0, 1, 0, &cp15_control
);
454 jtag_execute_queue();
457 cp15_control
|= 0x1U
;
460 cp15_control
|= 0x4U
;
463 cp15_control
|= 0x1000U
;
465 arm926ejs
->write_cp15(target
, 0, 0, 1, 0, cp15_control
);
468 void arm926ejs_post_debug_entry(target_t
*target
)
470 armv4_5_common_t
*armv4_5
= target
->arch_info
;
471 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
472 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
473 arm926ejs_common_t
*arm926ejs
= arm9tdmi
->arch_info
;
475 /* examine cp15 control reg */
476 arm926ejs
->read_cp15(target
, 0, 0, 1, 0, &arm926ejs
->cp15_control_reg
);
477 jtag_execute_queue();
478 LOG_DEBUG("cp15_control_reg: %8.8x", arm926ejs
->cp15_control_reg
);
480 if (arm926ejs
->armv4_5_mmu
.armv4_5_cache
.ctype
== -1)
483 /* identify caches */
484 arm926ejs
->read_cp15(target
, 0, 1, 0, 0, &cache_type_reg
);
485 jtag_execute_queue();
486 armv4_5_identify_cache(cache_type_reg
, &arm926ejs
->armv4_5_mmu
.armv4_5_cache
);
489 arm926ejs
->armv4_5_mmu
.mmu_enabled
= (arm926ejs
->cp15_control_reg
& 0x1U
) ? 1 : 0;
490 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= (arm926ejs
->cp15_control_reg
& 0x4U
) ? 1 : 0;
491 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= (arm926ejs
->cp15_control_reg
& 0x1000U
) ? 1 : 0;
493 /* save i/d fault status and address register */
494 arm926ejs
->read_cp15(target
, 0, 0, 5, 0, &arm926ejs
->d_fsr
);
495 arm926ejs
->read_cp15(target
, 0, 1, 5, 0, &arm926ejs
->i_fsr
);
496 arm926ejs
->read_cp15(target
, 0, 0, 6, 0, &arm926ejs
->d_far
);
498 LOG_DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x",
499 arm926ejs
->d_fsr
, arm926ejs
->d_far
, arm926ejs
->i_fsr
);
504 /* read-modify-write CP15 cache debug control register
505 * to disable I/D-cache linefills and force WT */
506 arm926ejs
->read_cp15(target
, 7, 0, 15, 0, &cache_dbg_ctrl
);
507 cache_dbg_ctrl
|= 0x7;
508 arm926ejs
->write_cp15(target
, 7, 0, 15, 0, cache_dbg_ctrl
);
511 void arm926ejs_pre_restore_context(target_t
*target
)
513 armv4_5_common_t
*armv4_5
= target
->arch_info
;
514 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
515 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
516 arm926ejs_common_t
*arm926ejs
= arm9tdmi
->arch_info
;
518 /* restore i/d fault status and address register */
519 arm926ejs
->write_cp15(target
, 0, 0, 5, 0, arm926ejs
->d_fsr
);
520 arm926ejs
->write_cp15(target
, 0, 1, 5, 0, arm926ejs
->i_fsr
);
521 arm926ejs
->write_cp15(target
, 0, 0, 6, 0, arm926ejs
->d_far
);
525 /* read-modify-write CP15 cache debug control register
526 * to reenable I/D-cache linefills and disable WT */
527 arm926ejs
->read_cp15(target
, 7, 0, 15, 0, &cache_dbg_ctrl
);
528 cache_dbg_ctrl
&= ~0x7;
529 arm926ejs
->write_cp15(target
, 7, 0, 15, 0, cache_dbg_ctrl
);
532 int arm926ejs_get_arch_pointers(target_t
*target
, armv4_5_common_t
**armv4_5_p
, arm7_9_common_t
**arm7_9_p
, arm9tdmi_common_t
**arm9tdmi_p
, arm926ejs_common_t
**arm926ejs_p
)
534 armv4_5_common_t
*armv4_5
= target
->arch_info
;
535 arm7_9_common_t
*arm7_9
;
536 arm9tdmi_common_t
*arm9tdmi
;
537 arm926ejs_common_t
*arm926ejs
;
539 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
544 arm7_9
= armv4_5
->arch_info
;
545 if (arm7_9
->common_magic
!= ARM7_9_COMMON_MAGIC
)
550 arm9tdmi
= arm7_9
->arch_info
;
551 if (arm9tdmi
->common_magic
!= ARM9TDMI_COMMON_MAGIC
)
556 arm926ejs
= arm9tdmi
->arch_info
;
557 if (arm926ejs
->common_magic
!= ARM926EJS_COMMON_MAGIC
)
562 *armv4_5_p
= armv4_5
;
564 *arm9tdmi_p
= arm9tdmi
;
565 *arm926ejs_p
= arm926ejs
;
570 int arm926ejs_arch_state(struct target_s
*target
)
572 armv4_5_common_t
*armv4_5
= target
->arch_info
;
573 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
574 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
575 arm926ejs_common_t
*arm926ejs
= arm9tdmi
->arch_info
;
579 "disabled", "enabled"
582 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
584 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
589 "target halted in %s state due to %s, current mode: %s\n"
590 "cpsr: 0x%8.8x pc: 0x%8.8x\n"
591 "MMU: %s, D-Cache: %s, I-Cache: %s",
592 armv4_5_state_strings
[armv4_5
->core_state
],
593 Jim_Nvp_value2name_simple( nvp_target_debug_reason
,target
->debug_reason
)->name
,
594 armv4_5_mode_strings
[armv4_5_mode_to_number(armv4_5
->core_mode
)],
595 buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32),
596 buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32),
597 state
[arm926ejs
->armv4_5_mmu
.mmu_enabled
],
598 state
[arm926ejs
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
],
599 state
[arm926ejs
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
]);
604 int arm926ejs_soft_reset_halt(struct target_s
*target
)
606 int retval
= ERROR_OK
;
607 armv4_5_common_t
*armv4_5
= target
->arch_info
;
608 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
609 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
610 arm926ejs_common_t
*arm926ejs
= arm9tdmi
->arch_info
;
611 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
613 if((retval
= target_halt(target
)) != ERROR_OK
)
618 long long then
=timeval_ms();
620 while (!(timeout
=((timeval_ms()-then
)>1000)))
622 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1) == 0)
624 embeddedice_read_reg(dbg_stat
);
625 if((retval
= jtag_execute_queue()) != ERROR_OK
)
635 /* do not eat all CPU, time out after 1 se*/
644 LOG_ERROR("Failed to halt CPU after 1 sec");
645 return ERROR_TARGET_TIMEOUT
;
648 target
->state
= TARGET_HALTED
;
650 /* SVC, ARM state, IRQ and FIQ disabled */
651 buf_set_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8, 0xd3);
652 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 1;
653 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
655 /* start fetching from 0x0 */
656 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, 0x0);
657 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
658 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
660 armv4_5
->core_mode
= ARMV4_5_MODE_SVC
;
661 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
663 arm926ejs_disable_mmu_caches(target
, 1, 1, 1);
664 arm926ejs
->armv4_5_mmu
.mmu_enabled
= 0;
665 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= 0;
666 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 0;
668 return target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
672 int arm926ejs_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
675 armv4_5_common_t
*armv4_5
= target
->arch_info
;
676 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
677 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
678 arm926ejs_common_t
*arm926ejs
= arm9tdmi
->arch_info
;
680 if ((retval
= arm7_9_write_memory(target
, address
, size
, count
, buffer
)) != ERROR_OK
)
683 /* If ICache is enabled, we have to invalidate affected ICache lines
684 * the DCache is forced to write-through, so we don't have to clean it here
686 if (arm926ejs
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
)
690 /* invalidate ICache single entry with MVA */
691 arm926ejs
->write_cp15(target
, 0, 1, 7, 5, address
);
695 /* invalidate ICache */
696 arm926ejs
->write_cp15(target
, 0, 0, 7, 5, address
);
703 int arm926ejs_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
705 arm9tdmi_init_target(cmd_ctx
, target
);
711 int arm926ejs_quit(void)
717 int arm926ejs_init_arch_info(target_t
*target
, arm926ejs_common_t
*arm926ejs
, int chain_pos
, const char *variant
)
719 arm9tdmi_common_t
*arm9tdmi
= &arm926ejs
->arm9tdmi_common
;
720 arm7_9_common_t
*arm7_9
= &arm9tdmi
->arm7_9_common
;
722 /* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
724 arm9tdmi_init_arch_info(target
, arm9tdmi
, chain_pos
, variant
);
726 arm9tdmi
->arch_info
= arm926ejs
;
727 arm926ejs
->common_magic
= ARM926EJS_COMMON_MAGIC
;
729 arm7_9
->post_debug_entry
= arm926ejs_post_debug_entry
;
730 arm7_9
->pre_restore_context
= arm926ejs_pre_restore_context
;
732 arm926ejs
->read_cp15
= arm926ejs_cp15_read
;
733 arm926ejs
->write_cp15
= arm926ejs_cp15_write
;
734 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.ctype
= -1;
735 arm926ejs
->armv4_5_mmu
.get_ttb
= arm926ejs_get_ttb
;
736 arm926ejs
->armv4_5_mmu
.read_memory
= arm7_9_read_memory
;
737 arm926ejs
->armv4_5_mmu
.write_memory
= arm7_9_write_memory
;
738 arm926ejs
->armv4_5_mmu
.disable_mmu_caches
= arm926ejs_disable_mmu_caches
;
739 arm926ejs
->armv4_5_mmu
.enable_mmu_caches
= arm926ejs_enable_mmu_caches
;
740 arm926ejs
->armv4_5_mmu
.has_tiny_pages
= 1;
741 arm926ejs
->armv4_5_mmu
.mmu_enabled
= 0;
743 arm7_9
->examine_debug_reason
= arm926ejs_examine_debug_reason
;
745 /* The ARM926EJ-S implements the ARMv5TE architecture which
746 * has the BKPT instruction, so we don't have to use a watchpoint comparator
748 arm7_9
->arm_bkpt
= ARMV5_BKPT(0x0);
749 arm7_9
->thumb_bkpt
= ARMV5_T_BKPT(0x0) & 0xffff;
754 int arm926ejs_target_create(struct target_s
*target
, Jim_Interp
*interp
)
756 arm926ejs_common_t
*arm926ejs
= calloc(1,sizeof(arm926ejs_common_t
));
758 arm926ejs_init_arch_info(target
, arm926ejs
, target
->chain_position
, target
->variant
);
763 int arm926ejs_register_commands(struct command_context_s
*cmd_ctx
)
766 command_t
*arm926ejs_cmd
;
769 retval
= arm9tdmi_register_commands(cmd_ctx
);
771 arm926ejs_cmd
= register_command(cmd_ctx
, NULL
, "arm926ejs", NULL
, COMMAND_ANY
, "arm926ejs specific commands");
773 register_command(cmd_ctx
, arm926ejs_cmd
, "cp15", arm926ejs_handle_cp15_command
, COMMAND_EXEC
, "display/modify cp15 register <opcode_1> <opcode_2> <CRn> <CRm> [value]");
775 register_command(cmd_ctx
, arm926ejs_cmd
, "cache_info", arm926ejs_handle_cache_info_command
, COMMAND_EXEC
, "display information about target caches");
776 register_command(cmd_ctx
, arm926ejs_cmd
, "virt2phys", arm926ejs_handle_virt2phys_command
, COMMAND_EXEC
, "translate va to pa <va>");
778 register_command(cmd_ctx
, arm926ejs_cmd
, "mdw_phys", arm926ejs_handle_md_phys_command
, COMMAND_EXEC
, "display memory words <physical addr> [count]");
779 register_command(cmd_ctx
, arm926ejs_cmd
, "mdh_phys", arm926ejs_handle_md_phys_command
, COMMAND_EXEC
, "display memory half-words <physical addr> [count]");
780 register_command(cmd_ctx
, arm926ejs_cmd
, "mdb_phys", arm926ejs_handle_md_phys_command
, COMMAND_EXEC
, "display memory bytes <physical addr> [count]");
782 register_command(cmd_ctx
, arm926ejs_cmd
, "mww_phys", arm926ejs_handle_mw_phys_command
, COMMAND_EXEC
, "write memory word <physical addr> <value>");
783 register_command(cmd_ctx
, arm926ejs_cmd
, "mwh_phys", arm926ejs_handle_mw_phys_command
, COMMAND_EXEC
, "write memory half-word <physical addr> <value>");
784 register_command(cmd_ctx
, arm926ejs_cmd
, "mwb_phys", arm926ejs_handle_mw_phys_command
, COMMAND_EXEC
, "write memory byte <physical addr> <value>");
789 int arm926ejs_handle_cp15_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
792 target_t
*target
= get_current_target(cmd_ctx
);
793 armv4_5_common_t
*armv4_5
;
794 arm7_9_common_t
*arm7_9
;
795 arm9tdmi_common_t
*arm9tdmi
;
796 arm926ejs_common_t
*arm926ejs
;
802 if ((argc
< 4) || (argc
> 5))
804 command_print(cmd_ctx
, "usage: arm926ejs cp15 <opcode_1> <opcode_2> <CRn> <CRm> [value]");
808 opcode_1
= strtoul(args
[0], NULL
, 0);
809 opcode_2
= strtoul(args
[1], NULL
, 0);
810 CRn
= strtoul(args
[2], NULL
, 0);
811 CRm
= strtoul(args
[3], NULL
, 0);
813 if (arm926ejs_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm926ejs
) != ERROR_OK
)
815 command_print(cmd_ctx
, "current target isn't an ARM926EJ-S target");
819 if (target
->state
!= TARGET_HALTED
)
821 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
828 if ((retval
= arm926ejs
->read_cp15(target
, opcode_1
, opcode_2
, CRn
, CRm
, &value
)) != ERROR_OK
)
830 command_print(cmd_ctx
, "couldn't access register");
833 if((retval
= jtag_execute_queue()) != ERROR_OK
)
838 command_print(cmd_ctx
, "%i %i %i %i: %8.8x", opcode_1
, opcode_2
, CRn
, CRm
, value
);
842 u32 value
= strtoul(args
[4], NULL
, 0);
843 if ((retval
= arm926ejs
->write_cp15(target
, opcode_1
, opcode_2
, CRn
, CRm
, value
)) != ERROR_OK
)
845 command_print(cmd_ctx
, "couldn't access register");
848 command_print(cmd_ctx
, "%i %i %i %i: %8.8x", opcode_1
, opcode_2
, CRn
, CRm
, value
);
854 int arm926ejs_handle_cache_info_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
856 target_t
*target
= get_current_target(cmd_ctx
);
857 armv4_5_common_t
*armv4_5
;
858 arm7_9_common_t
*arm7_9
;
859 arm9tdmi_common_t
*arm9tdmi
;
860 arm926ejs_common_t
*arm926ejs
;
862 if (arm926ejs_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm926ejs
) != ERROR_OK
)
864 command_print(cmd_ctx
, "current target isn't an ARM926EJ-S target");
868 return armv4_5_handle_cache_info_command(cmd_ctx
, &arm926ejs
->armv4_5_mmu
.armv4_5_cache
);
871 int arm926ejs_handle_virt2phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
873 target_t
*target
= get_current_target(cmd_ctx
);
874 armv4_5_common_t
*armv4_5
;
875 arm7_9_common_t
*arm7_9
;
876 arm9tdmi_common_t
*arm9tdmi
;
877 arm926ejs_common_t
*arm926ejs
;
878 arm_jtag_t
*jtag_info
;
880 if (arm926ejs_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm926ejs
) != ERROR_OK
)
882 command_print(cmd_ctx
, "current target isn't an ARM926EJ-S target");
886 jtag_info
= &arm7_9
->jtag_info
;
888 if (target
->state
!= TARGET_HALTED
)
890 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
894 return armv4_5_mmu_handle_virt2phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm926ejs
->armv4_5_mmu
);
897 int arm926ejs_handle_md_phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
899 target_t
*target
= get_current_target(cmd_ctx
);
900 armv4_5_common_t
*armv4_5
;
901 arm7_9_common_t
*arm7_9
;
902 arm9tdmi_common_t
*arm9tdmi
;
903 arm926ejs_common_t
*arm926ejs
;
904 arm_jtag_t
*jtag_info
;
906 if (arm926ejs_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm926ejs
) != ERROR_OK
)
908 command_print(cmd_ctx
, "current target isn't an ARM926EJ-S target");
912 jtag_info
= &arm7_9
->jtag_info
;
914 if (target
->state
!= TARGET_HALTED
)
916 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
920 return armv4_5_mmu_handle_md_phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm926ejs
->armv4_5_mmu
);
923 int arm926ejs_handle_mw_phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
925 target_t
*target
= get_current_target(cmd_ctx
);
926 armv4_5_common_t
*armv4_5
;
927 arm7_9_common_t
*arm7_9
;
928 arm9tdmi_common_t
*arm9tdmi
;
929 arm926ejs_common_t
*arm926ejs
;
930 arm_jtag_t
*jtag_info
;
932 if (arm926ejs_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm926ejs
) != ERROR_OK
)
934 command_print(cmd_ctx
, "current target isn't an ARM926EJ-S target");
938 jtag_info
= &arm7_9
->jtag_info
;
940 if (target
->state
!= TARGET_HALTED
)
942 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
946 return armv4_5_mmu_handle_mw_phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm926ejs
->armv4_5_mmu
);
948 static int arm926ejs_virt2phys(struct target_s
*target
, u32
virtual, u32
*physical
)
956 armv4_5_common_t
*armv4_5
;
957 arm7_9_common_t
*arm7_9
;
958 arm9tdmi_common_t
*arm9tdmi
;
959 arm926ejs_common_t
*arm926ejs
;
960 retval
= arm926ejs_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm926ejs
);
961 if (retval
!= ERROR_OK
)
965 u32 ret
= armv4_5_mmu_translate_va(target
, &arm926ejs
->armv4_5_mmu
, virtual, &type
, &cb
, &domain
, &ap
);
974 static int arm926ejs_mmu(struct target_s
*target
, int *enabled
)
976 armv4_5_common_t
*armv4_5
= target
->arch_info
;
977 arm926ejs_common_t
*arm926ejs
= armv4_5
->arch_info
;
979 if (target
->state
!= TARGET_HALTED
)
981 LOG_ERROR("Target not halted");
982 return ERROR_TARGET_INVALID
;
984 *enabled
= arm926ejs
->armv4_5_mmu
.mmu_enabled
;
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