1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
32 #define _DEBUG_INSTRUCTION_EXECUTION_
36 int arm920t_register_commands(struct command_context_s
*cmd_ctx
);
38 int arm920t_handle_cp15_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
39 int arm920t_handle_cp15i_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
40 int arm920t_handle_virt2phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
41 int arm920t_handle_cache_info_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
42 int arm920t_handle_md_phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
43 int arm920t_handle_mw_phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
45 int arm920t_handle_read_cache_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
46 int arm920t_handle_read_mmu_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
48 /* forward declarations */
49 int arm920t_target_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct target_s
*target
);
50 int arm920t_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
);
52 int arm920t_arch_state(struct target_s
*target
);
53 int arm920t_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
54 int arm920t_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
55 int arm920t_soft_reset_halt(struct target_s
*target
);
57 #define ARM920T_CP15_PHYS_ADDR(x, y, z) ((x << 5) | (y << 1) << (z))
59 target_type_t arm920t_target
=
64 .arch_state
= arm920t_arch_state
,
66 .target_request_data
= arm7_9_target_request_data
,
69 .resume
= arm7_9_resume
,
72 .assert_reset
= arm7_9_assert_reset
,
73 .deassert_reset
= arm7_9_deassert_reset
,
74 .soft_reset_halt
= arm920t_soft_reset_halt
,
76 .get_gdb_reg_list
= armv4_5_get_gdb_reg_list
,
78 .read_memory
= arm920t_read_memory
,
79 .write_memory
= arm920t_write_memory
,
80 .bulk_write_memory
= arm7_9_bulk_write_memory
,
81 .checksum_memory
= arm7_9_checksum_memory
,
83 .run_algorithm
= armv4_5_run_algorithm
,
85 .add_breakpoint
= arm7_9_add_breakpoint
,
86 .remove_breakpoint
= arm7_9_remove_breakpoint
,
87 .add_watchpoint
= arm7_9_add_watchpoint
,
88 .remove_watchpoint
= arm7_9_remove_watchpoint
,
90 .register_commands
= arm920t_register_commands
,
91 .target_command
= arm920t_target_command
,
92 .init_target
= arm920t_init_target
,
93 .examine
= arm9tdmi_examine
,
97 int arm920t_read_cp15_physical(target_t
*target
, int reg_addr
, u32
*value
)
99 armv4_5_common_t
*armv4_5
= target
->arch_info
;
100 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
101 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
102 scan_field_t fields
[4];
103 u8 access_type_buf
= 1;
104 u8 reg_addr_buf
= reg_addr
& 0x3f;
107 jtag_add_end_state(TAP_RTI
);
108 arm_jtag_scann(jtag_info
, 0xf);
109 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
111 fields
[0].device
= jtag_info
->chain_pos
;
112 fields
[0].num_bits
= 1;
113 fields
[0].out_value
= &access_type_buf
;
114 fields
[0].out_mask
= NULL
;
115 fields
[0].in_value
= NULL
;
116 fields
[0].in_check_value
= NULL
;
117 fields
[0].in_check_mask
= NULL
;
118 fields
[0].in_handler
= NULL
;
119 fields
[0].in_handler_priv
= NULL
;
121 fields
[1].device
= jtag_info
->chain_pos
;
122 fields
[1].num_bits
= 32;
123 fields
[1].out_value
= NULL
;
124 fields
[1].out_mask
= NULL
;
125 fields
[1].in_value
= NULL
;
126 fields
[1].in_check_value
= NULL
;
127 fields
[1].in_check_mask
= NULL
;
128 fields
[1].in_handler
= NULL
;
129 fields
[1].in_handler_priv
= NULL
;
131 fields
[2].device
= jtag_info
->chain_pos
;
132 fields
[2].num_bits
= 6;
133 fields
[2].out_value
= ®_addr_buf
;
134 fields
[2].out_mask
= NULL
;
135 fields
[2].in_value
= NULL
;
136 fields
[2].in_check_value
= NULL
;
137 fields
[2].in_check_mask
= NULL
;
138 fields
[2].in_handler
= NULL
;
139 fields
[2].in_handler_priv
= NULL
;
141 fields
[3].device
= jtag_info
->chain_pos
;
142 fields
[3].num_bits
= 1;
143 fields
[3].out_value
= &nr_w_buf
;
144 fields
[3].out_mask
= NULL
;
145 fields
[3].in_value
= NULL
;
146 fields
[3].in_check_value
= NULL
;
147 fields
[3].in_check_mask
= NULL
;
148 fields
[3].in_handler
= NULL
;
149 fields
[3].in_handler_priv
= NULL
;
151 jtag_add_dr_scan(4, fields
, -1);
153 fields
[1].in_handler_priv
= value
;
154 fields
[1].in_handler
= arm_jtag_buf_to_u32
;
156 jtag_add_dr_scan(4, fields
, -1);
158 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
159 jtag_execute_queue();
160 LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr
, *value
);
166 int arm920t_write_cp15_physical(target_t
*target
, int reg_addr
, u32 value
)
168 armv4_5_common_t
*armv4_5
= target
->arch_info
;
169 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
170 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
171 scan_field_t fields
[4];
172 u8 access_type_buf
= 1;
173 u8 reg_addr_buf
= reg_addr
& 0x3f;
177 buf_set_u32(value_buf
, 0, 32, value
);
179 jtag_add_end_state(TAP_RTI
);
180 arm_jtag_scann(jtag_info
, 0xf);
181 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
183 fields
[0].device
= jtag_info
->chain_pos
;
184 fields
[0].num_bits
= 1;
185 fields
[0].out_value
= &access_type_buf
;
186 fields
[0].out_mask
= NULL
;
187 fields
[0].in_value
= NULL
;
188 fields
[0].in_check_value
= NULL
;
189 fields
[0].in_check_mask
= NULL
;
190 fields
[0].in_handler
= NULL
;
191 fields
[0].in_handler_priv
= NULL
;
193 fields
[1].device
= jtag_info
->chain_pos
;
194 fields
[1].num_bits
= 32;
195 fields
[1].out_value
= value_buf
;
196 fields
[1].out_mask
= NULL
;
197 fields
[1].in_value
= NULL
;
198 fields
[1].in_check_value
= NULL
;
199 fields
[1].in_check_mask
= NULL
;
200 fields
[1].in_handler
= NULL
;
201 fields
[1].in_handler_priv
= NULL
;
203 fields
[2].device
= jtag_info
->chain_pos
;
204 fields
[2].num_bits
= 6;
205 fields
[2].out_value
= ®_addr_buf
;
206 fields
[2].out_mask
= NULL
;
207 fields
[2].in_value
= NULL
;
208 fields
[2].in_check_value
= NULL
;
209 fields
[2].in_check_mask
= NULL
;
210 fields
[2].in_handler
= NULL
;
211 fields
[2].in_handler_priv
= NULL
;
213 fields
[3].device
= jtag_info
->chain_pos
;
214 fields
[3].num_bits
= 1;
215 fields
[3].out_value
= &nr_w_buf
;
216 fields
[3].out_mask
= NULL
;
217 fields
[3].in_value
= NULL
;
218 fields
[3].in_check_value
= NULL
;
219 fields
[3].in_check_mask
= NULL
;
220 fields
[3].in_handler
= NULL
;
221 fields
[3].in_handler_priv
= NULL
;
223 jtag_add_dr_scan(4, fields
, -1);
225 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
226 LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr
, value
);
232 int arm920t_execute_cp15(target_t
*target
, u32 cp15_opcode
, u32 arm_opcode
)
234 armv4_5_common_t
*armv4_5
= target
->arch_info
;
235 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
236 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
237 scan_field_t fields
[4];
238 u8 access_type_buf
= 0; /* interpreted access */
239 u8 reg_addr_buf
= 0x0;
241 u8 cp15_opcode_buf
[4];
243 jtag_add_end_state(TAP_RTI
);
244 arm_jtag_scann(jtag_info
, 0xf);
245 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
247 buf_set_u32(cp15_opcode_buf
, 0, 32, cp15_opcode
);
249 fields
[0].device
= jtag_info
->chain_pos
;
250 fields
[0].num_bits
= 1;
251 fields
[0].out_value
= &access_type_buf
;
252 fields
[0].out_mask
= NULL
;
253 fields
[0].in_value
= NULL
;
254 fields
[0].in_check_value
= NULL
;
255 fields
[0].in_check_mask
= NULL
;
256 fields
[0].in_handler
= NULL
;
257 fields
[0].in_handler_priv
= NULL
;
259 fields
[1].device
= jtag_info
->chain_pos
;
260 fields
[1].num_bits
= 32;
261 fields
[1].out_value
= cp15_opcode_buf
;
262 fields
[1].out_mask
= NULL
;
263 fields
[1].in_value
= NULL
;
264 fields
[1].in_check_value
= NULL
;
265 fields
[1].in_check_mask
= NULL
;
266 fields
[1].in_handler
= NULL
;
267 fields
[1].in_handler_priv
= NULL
;
269 fields
[2].device
= jtag_info
->chain_pos
;
270 fields
[2].num_bits
= 6;
271 fields
[2].out_value
= ®_addr_buf
;
272 fields
[2].out_mask
= NULL
;
273 fields
[2].in_value
= NULL
;
274 fields
[2].in_check_value
= NULL
;
275 fields
[2].in_check_mask
= NULL
;
276 fields
[2].in_handler
= NULL
;
277 fields
[2].in_handler_priv
= NULL
;
279 fields
[3].device
= jtag_info
->chain_pos
;
280 fields
[3].num_bits
= 1;
281 fields
[3].out_value
= &nr_w_buf
;
282 fields
[3].out_mask
= NULL
;
283 fields
[3].in_value
= NULL
;
284 fields
[3].in_check_value
= NULL
;
285 fields
[3].in_check_mask
= NULL
;
286 fields
[3].in_handler
= NULL
;
287 fields
[3].in_handler_priv
= NULL
;
289 jtag_add_dr_scan(4, fields
, -1);
291 arm9tdmi_clock_out(jtag_info
, arm_opcode
, 0, NULL
, 0);
292 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
293 arm7_9_execute_sys_speed(target
);
295 if (jtag_execute_queue() != ERROR_OK
)
297 LOG_ERROR("failed executing JTAG queue, exiting");
304 int arm920t_read_cp15_interpreted(target_t
*target
, u32 cp15_opcode
, u32 address
, u32
*value
)
306 armv4_5_common_t
*armv4_5
= target
->arch_info
;
311 /* load address into R1 */
313 arm9tdmi_write_core_regs(target
, 0x2, regs
);
315 /* read-modify-write CP15 test state register
316 * to enable interpreted access mode */
317 arm920t_read_cp15_physical(target
, 0x1e, &cp15c15
);
318 jtag_execute_queue();
319 cp15c15
|= 1; /* set interpret mode */
320 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
322 /* execute CP15 instruction and ARM load (reading from coprocessor) */
323 arm920t_execute_cp15(target
, cp15_opcode
, ARMV4_5_LDR(0, 1));
325 /* disable interpreted access mode */
326 cp15c15
&= ~1U; /* clear interpret mode */
327 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
329 /* retrieve value from R0 */
331 arm9tdmi_read_core_regs(target
, 0x1, regs_p
);
332 jtag_execute_queue();
334 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
335 LOG_DEBUG("cp15_opcode: %8.8x, address: %8.8x, value: %8.8x", cp15_opcode
, address
, *value
);
338 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).dirty
= 1;
339 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 1).dirty
= 1;
344 int arm920t_write_cp15_interpreted(target_t
*target
, u32 cp15_opcode
, u32 value
, u32 address
)
347 armv4_5_common_t
*armv4_5
= target
->arch_info
;
350 /* load value, address into R0, R1 */
353 arm9tdmi_write_core_regs(target
, 0x3, regs
);
355 /* read-modify-write CP15 test state register
356 * to enable interpreted access mode */
357 arm920t_read_cp15_physical(target
, 0x1e, &cp15c15
);
358 jtag_execute_queue();
359 cp15c15
|= 1; /* set interpret mode */
360 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
362 /* execute CP15 instruction and ARM store (writing to coprocessor) */
363 arm920t_execute_cp15(target
, cp15_opcode
, ARMV4_5_STR(0, 1));
365 /* disable interpreted access mode */
366 cp15c15
&= ~1U; /* set interpret mode */
367 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
369 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
370 LOG_DEBUG("cp15_opcode: %8.8x, value: %8.8x, address: %8.8x", cp15_opcode
, value
, address
);
373 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).dirty
= 1;
374 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 1).dirty
= 1;
379 u32
arm920t_get_ttb(target_t
*target
)
384 if ((retval
= arm920t_read_cp15_interpreted(target
, 0xeebf0f51, 0x0, &ttb
)) != ERROR_OK
)
390 void arm920t_disable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
394 /* read cp15 control register */
395 arm920t_read_cp15_physical(target
, 0x2, &cp15_control
);
396 jtag_execute_queue();
399 cp15_control
&= ~0x1U
;
402 cp15_control
&= ~0x4U
;
405 cp15_control
&= ~0x1000U
;
407 arm920t_write_cp15_physical(target
, 0x2, cp15_control
);
410 void arm920t_enable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
414 /* read cp15 control register */
415 arm920t_read_cp15_physical(target
, 0x2, &cp15_control
);
416 jtag_execute_queue();
419 cp15_control
|= 0x1U
;
422 cp15_control
|= 0x4U
;
425 cp15_control
|= 0x1000U
;
427 arm920t_write_cp15_physical(target
, 0x2, cp15_control
);
430 void arm920t_post_debug_entry(target_t
*target
)
433 armv4_5_common_t
*armv4_5
= target
->arch_info
;
434 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
435 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
436 arm920t_common_t
*arm920t
= arm9tdmi
->arch_info
;
438 /* examine cp15 control reg */
439 arm920t_read_cp15_physical(target
, 0x2, &arm920t
->cp15_control_reg
);
440 jtag_execute_queue();
441 LOG_DEBUG("cp15_control_reg: %8.8x", arm920t
->cp15_control_reg
);
443 if (arm920t
->armv4_5_mmu
.armv4_5_cache
.ctype
== -1)
446 /* identify caches */
447 arm920t_read_cp15_physical(target
, 0x1, &cache_type_reg
);
448 jtag_execute_queue();
449 armv4_5_identify_cache(cache_type_reg
, &arm920t
->armv4_5_mmu
.armv4_5_cache
);
452 arm920t
->armv4_5_mmu
.mmu_enabled
= (arm920t
->cp15_control_reg
& 0x1U
) ? 1 : 0;
453 arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= (arm920t
->cp15_control_reg
& 0x4U
) ? 1 : 0;
454 arm920t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= (arm920t
->cp15_control_reg
& 0x1000U
) ? 1 : 0;
456 /* save i/d fault status and address register */
457 arm920t_read_cp15_interpreted(target
, 0xee150f10, 0x0, &arm920t
->d_fsr
);
458 arm920t_read_cp15_interpreted(target
, 0xee150f30, 0x0, &arm920t
->i_fsr
);
459 arm920t_read_cp15_interpreted(target
, 0xee160f10, 0x0, &arm920t
->d_far
);
460 arm920t_read_cp15_interpreted(target
, 0xee160f30, 0x0, &arm920t
->i_far
);
462 LOG_DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x, I FAR: 0x%8.8x",
463 arm920t
->d_fsr
, arm920t
->d_far
, arm920t
->i_fsr
, arm920t
->i_far
);
465 if (arm920t
->preserve_cache
)
467 /* read-modify-write CP15 test state register
468 * to disable I/D-cache linefills */
469 arm920t_read_cp15_physical(target
, 0x1e, &cp15c15
);
470 jtag_execute_queue();
472 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
476 void arm920t_pre_restore_context(target_t
*target
)
479 armv4_5_common_t
*armv4_5
= target
->arch_info
;
480 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
481 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
482 arm920t_common_t
*arm920t
= arm9tdmi
->arch_info
;
484 /* restore i/d fault status and address register */
485 arm920t_write_cp15_interpreted(target
, 0xee050f10, arm920t
->d_fsr
, 0x0);
486 arm920t_write_cp15_interpreted(target
, 0xee050f30, arm920t
->i_fsr
, 0x0);
487 arm920t_write_cp15_interpreted(target
, 0xee060f10, arm920t
->d_far
, 0x0);
488 arm920t_write_cp15_interpreted(target
, 0xee060f30, arm920t
->i_far
, 0x0);
490 /* read-modify-write CP15 test state register
491 * to reenable I/D-cache linefills */
492 if (arm920t
->preserve_cache
)
494 arm920t_read_cp15_physical(target
, 0x1e, &cp15c15
);
495 jtag_execute_queue();
497 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
501 int arm920t_get_arch_pointers(target_t
*target
, armv4_5_common_t
**armv4_5_p
, arm7_9_common_t
**arm7_9_p
, arm9tdmi_common_t
**arm9tdmi_p
, arm920t_common_t
**arm920t_p
)
503 armv4_5_common_t
*armv4_5
= target
->arch_info
;
504 arm7_9_common_t
*arm7_9
;
505 arm9tdmi_common_t
*arm9tdmi
;
506 arm920t_common_t
*arm920t
;
508 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
513 arm7_9
= armv4_5
->arch_info
;
514 if (arm7_9
->common_magic
!= ARM7_9_COMMON_MAGIC
)
519 arm9tdmi
= arm7_9
->arch_info
;
520 if (arm9tdmi
->common_magic
!= ARM9TDMI_COMMON_MAGIC
)
525 arm920t
= arm9tdmi
->arch_info
;
526 if (arm920t
->common_magic
!= ARM920T_COMMON_MAGIC
)
531 *armv4_5_p
= armv4_5
;
533 *arm9tdmi_p
= arm9tdmi
;
534 *arm920t_p
= arm920t
;
539 int arm920t_arch_state(struct target_s
*target
)
541 armv4_5_common_t
*armv4_5
= target
->arch_info
;
542 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
543 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
544 arm920t_common_t
*arm920t
= arm9tdmi
->arch_info
;
548 "disabled", "enabled"
551 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
553 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
557 LOG_USER( "target halted in %s state due to %s, current mode: %s\n"
558 "cpsr: 0x%8.8x pc: 0x%8.8x\n"
559 "MMU: %s, D-Cache: %s, I-Cache: %s",
560 armv4_5_state_strings
[armv4_5
->core_state
],
561 target_debug_reason_strings
[target
->debug_reason
],
562 armv4_5_mode_strings
[armv4_5_mode_to_number(armv4_5
->core_mode
)],
563 buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32),
564 buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32),
565 state
[arm920t
->armv4_5_mmu
.mmu_enabled
],
566 state
[arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
],
567 state
[arm920t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
]);
572 int arm920t_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
576 retval
= arm7_9_read_memory(target
, address
, size
, count
, buffer
);
581 int arm920t_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
584 armv4_5_common_t
*armv4_5
= target
->arch_info
;
585 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
586 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
587 arm920t_common_t
*arm920t
= arm9tdmi
->arch_info
;
589 if ((retval
= arm7_9_write_memory(target
, address
, size
, count
, buffer
)) != ERROR_OK
)
592 if (((size
== 4) || (size
== 2)) && (count
== 1))
594 if (arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
)
596 LOG_DEBUG("D-Cache enabled, writing through to main memory");
600 pa
= armv4_5_mmu_translate_va(target
, &arm920t
->armv4_5_mmu
, address
, &type
, &cb
, &domain
, &ap
);
603 /* cacheable & bufferable means write-back region */
605 armv4_5_mmu_write_physical(target
, &arm920t
->armv4_5_mmu
, pa
, size
, count
, buffer
);
608 if (arm920t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
)
610 LOG_DEBUG("I-Cache enabled, invalidating affected I-Cache line");
611 arm920t_write_cp15_interpreted(target
, 0xee070f35, 0x0, address
);
618 int arm920t_soft_reset_halt(struct target_s
*target
)
620 armv4_5_common_t
*armv4_5
= target
->arch_info
;
621 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
622 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
623 arm920t_common_t
*arm920t
= arm9tdmi
->arch_info
;
624 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
631 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1) == 0)
633 embeddedice_read_reg(dbg_stat
);
634 jtag_execute_queue();
639 /* do not eat all CPU, time out after 1 se*/
644 LOG_ERROR("Failed to halt CPU after 1 sec");
645 return ERROR_TARGET_TIMEOUT
;
648 target
->state
= TARGET_HALTED
;
650 /* SVC, ARM state, IRQ and FIQ disabled */
651 buf_set_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8, 0xd3);
652 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 1;
653 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
655 /* start fetching from 0x0 */
656 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, 0x0);
657 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
658 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
660 armv4_5
->core_mode
= ARMV4_5_MODE_SVC
;
661 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
663 arm920t_disable_mmu_caches(target
, 1, 1, 1);
664 arm920t
->armv4_5_mmu
.mmu_enabled
= 0;
665 arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= 0;
666 arm920t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 0;
668 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
673 int arm920t_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
675 arm9tdmi_init_target(cmd_ctx
, target
);
687 int arm920t_init_arch_info(target_t
*target
, arm920t_common_t
*arm920t
, int chain_pos
, char *variant
)
689 arm9tdmi_common_t
*arm9tdmi
= &arm920t
->arm9tdmi_common
;
690 arm7_9_common_t
*arm7_9
= &arm9tdmi
->arm7_9_common
;
692 /* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
694 arm9tdmi_init_arch_info(target
, arm9tdmi
, chain_pos
, variant
);
696 arm9tdmi
->arch_info
= arm920t
;
697 arm920t
->common_magic
= ARM920T_COMMON_MAGIC
;
699 arm7_9
->post_debug_entry
= arm920t_post_debug_entry
;
700 arm7_9
->pre_restore_context
= arm920t_pre_restore_context
;
702 arm920t
->armv4_5_mmu
.armv4_5_cache
.ctype
= -1;
703 arm920t
->armv4_5_mmu
.get_ttb
= arm920t_get_ttb
;
704 arm920t
->armv4_5_mmu
.read_memory
= arm7_9_read_memory
;
705 arm920t
->armv4_5_mmu
.write_memory
= arm7_9_write_memory
;
706 arm920t
->armv4_5_mmu
.disable_mmu_caches
= arm920t_disable_mmu_caches
;
707 arm920t
->armv4_5_mmu
.enable_mmu_caches
= arm920t_enable_mmu_caches
;
708 arm920t
->armv4_5_mmu
.has_tiny_pages
= 1;
709 arm920t
->armv4_5_mmu
.mmu_enabled
= 0;
711 /* disabling linefills leads to lockups, so keep them enabled for now
712 * this doesn't affect correctness, but might affect timing issues, if
713 * important data is evicted from the cache during the debug session
715 arm920t
->preserve_cache
= 0;
717 /* override hw single-step capability from ARM9TDMI */
718 arm7_9
->has_single_step
= 1;
723 int arm920t_target_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct target_s
*target
)
726 char *variant
= NULL
;
727 arm920t_common_t
*arm920t
= malloc(sizeof(arm920t_common_t
));
728 memset(arm920t
, 0, sizeof(*arm920t
));
732 LOG_ERROR("'target arm920t' requires at least one additional argument");
736 chain_pos
= strtoul(args
[3], NULL
, 0);
741 LOG_DEBUG("chain_pos: %i, variant: %s", chain_pos
, variant
);
743 arm920t_init_arch_info(target
, arm920t
, chain_pos
, variant
);
748 int arm920t_register_commands(struct command_context_s
*cmd_ctx
)
751 command_t
*arm920t_cmd
;
754 retval
= arm9tdmi_register_commands(cmd_ctx
);
756 arm920t_cmd
= register_command(cmd_ctx
, NULL
, "arm920t", NULL
, COMMAND_ANY
, "arm920t specific commands");
758 register_command(cmd_ctx
, arm920t_cmd
, "cp15", arm920t_handle_cp15_command
, COMMAND_EXEC
, "display/modify cp15 register <num> [value]");
759 register_command(cmd_ctx
, arm920t_cmd
, "cp15i", arm920t_handle_cp15i_command
, COMMAND_EXEC
, "display/modify cp15 (interpreted access) <opcode> [value] [address]");
760 register_command(cmd_ctx
, arm920t_cmd
, "cache_info", arm920t_handle_cache_info_command
, COMMAND_EXEC
, "display information about target caches");
761 register_command(cmd_ctx
, arm920t_cmd
, "virt2phys", arm920t_handle_virt2phys_command
, COMMAND_EXEC
, "translate va to pa <va>");
763 register_command(cmd_ctx
, arm920t_cmd
, "mdw_phys", arm920t_handle_md_phys_command
, COMMAND_EXEC
, "display memory words <physical addr> [count]");
764 register_command(cmd_ctx
, arm920t_cmd
, "mdh_phys", arm920t_handle_md_phys_command
, COMMAND_EXEC
, "display memory half-words <physical addr> [count]");
765 register_command(cmd_ctx
, arm920t_cmd
, "mdb_phys", arm920t_handle_md_phys_command
, COMMAND_EXEC
, "display memory bytes <physical addr> [count]");
767 register_command(cmd_ctx
, arm920t_cmd
, "mww_phys", arm920t_handle_mw_phys_command
, COMMAND_EXEC
, "write memory word <physical addr> <value>");
768 register_command(cmd_ctx
, arm920t_cmd
, "mwh_phys", arm920t_handle_mw_phys_command
, COMMAND_EXEC
, "write memory half-word <physical addr> <value>");
769 register_command(cmd_ctx
, arm920t_cmd
, "mwb_phys", arm920t_handle_mw_phys_command
, COMMAND_EXEC
, "write memory byte <physical addr> <value>");
771 register_command(cmd_ctx
, arm920t_cmd
, "read_cache", arm920t_handle_read_cache_command
, COMMAND_EXEC
, "display I/D cache content");
772 register_command(cmd_ctx
, arm920t_cmd
, "read_mmu", arm920t_handle_read_mmu_command
, COMMAND_EXEC
, "display I/D mmu content");
777 int arm920t_handle_read_cache_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
779 target_t
*target
= get_current_target(cmd_ctx
);
780 armv4_5_common_t
*armv4_5
;
781 arm7_9_common_t
*arm7_9
;
782 arm9tdmi_common_t
*arm9tdmi
;
783 arm920t_common_t
*arm920t
;
784 arm_jtag_t
*jtag_info
;
786 u32 cp15_ctrl
, cp15_ctrl_saved
;
789 u32 C15_C_D_Ind
, C15_C_I_Ind
;
792 arm920t_cache_line_t d_cache
[8][64], i_cache
[8][64];
797 command_print(cmd_ctx
, "usage: arm920t read_cache <filename>");
801 if ((output
= fopen(args
[0], "w")) == NULL
)
803 LOG_DEBUG("error opening cache content file");
807 for (i
= 0; i
< 16; i
++)
808 regs_p
[i
] = ®s
[i
];
810 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
812 command_print(cmd_ctx
, "current target isn't an ARM920t target");
816 jtag_info
= &arm7_9
->jtag_info
;
818 /* disable MMU and Caches */
819 arm920t_read_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl
);
820 jtag_execute_queue();
821 cp15_ctrl_saved
= cp15_ctrl
;
822 cp15_ctrl
&= ~(ARMV4_5_MMU_ENABLED
| ARMV4_5_D_U_CACHE_ENABLED
| ARMV4_5_I_CACHE_ENABLED
);
823 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl
);
825 /* read CP15 test state register */
826 arm920t_read_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15
);
827 jtag_execute_queue();
829 /* read DCache content */
830 fprintf(output
, "DCache:\n");
832 /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
833 for (segment
= 0; segment
< arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_size
.nsets
; segment
++)
835 fprintf(output
, "\nsegment: %i\n----------", segment
);
837 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
838 regs
[0] = 0x0 | (segment
<< 5);
839 arm9tdmi_write_core_regs(target
, 0x1, regs
);
841 /* set interpret mode */
843 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
845 /* D CAM Read, loads current victim into C15.C.D.Ind */
846 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(1, 0));
848 /* read current victim */
849 arm920t_read_cp15_physical(target
, 0x3d, &C15_C_D_Ind
);
851 /* clear interpret mode */
853 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
855 for (index
= 0; index
< 64; index
++)
857 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
858 regs
[0] = 0x0 | (segment
<< 5) | (index
<< 26);
859 arm9tdmi_write_core_regs(target
, 0x1, regs
);
861 /* set interpret mode */
863 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
865 /* Write DCache victim */
866 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
869 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,10,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
872 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(9, 0));
874 /* clear interpret mode */
876 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
878 /* read D RAM and CAM content */
879 arm9tdmi_read_core_regs(target
, 0x3fe, regs_p
);
880 jtag_execute_queue();
882 d_cache
[segment
][index
].cam
= regs
[9];
885 regs
[9] &= 0xfffffffe;
886 fprintf(output
, "\nsegment: %i, index: %i, CAM: 0x%8.8x, content (%s):\n", segment
, index
, regs
[9], (regs
[9] & 0x10) ? "valid" : "invalid");
888 for (i
= 1; i
< 9; i
++)
890 d_cache
[segment
][index
].data
[i
] = regs
[i
];
891 fprintf(output
, "%i: 0x%8.8x\n", i
-1, regs
[i
]);
896 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
897 regs
[0] = 0x0 | (segment
<< 5) | (C15_C_D_Ind
<< 26);
898 arm9tdmi_write_core_regs(target
, 0x1, regs
);
900 /* set interpret mode */
902 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
904 /* Write DCache victim */
905 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
907 /* clear interpret mode */
909 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
912 /* read ICache content */
913 fprintf(output
, "ICache:\n");
915 /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
916 for (segment
= 0; segment
< arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_size
.nsets
; segment
++)
918 fprintf(output
, "segment: %i\n----------", segment
);
920 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
921 regs
[0] = 0x0 | (segment
<< 5);
922 arm9tdmi_write_core_regs(target
, 0x1, regs
);
924 /* set interpret mode */
926 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
928 /* I CAM Read, loads current victim into C15.C.I.Ind */
929 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(1, 0));
931 /* read current victim */
932 arm920t_read_cp15_physical(target
, 0x3b, &C15_C_I_Ind
);
934 /* clear interpret mode */
936 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
938 for (index
= 0; index
< 64; index
++)
940 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
941 regs
[0] = 0x0 | (segment
<< 5) | (index
<< 26);
942 arm9tdmi_write_core_regs(target
, 0x1, regs
);
944 /* set interpret mode */
946 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
948 /* Write ICache victim */
949 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
952 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,9,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
955 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(9, 0));
957 /* clear interpret mode */
959 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
961 /* read I RAM and CAM content */
962 arm9tdmi_read_core_regs(target
, 0x3fe, regs_p
);
963 jtag_execute_queue();
965 i_cache
[segment
][index
].cam
= regs
[9];
968 regs
[9] &= 0xfffffffe;
969 fprintf(output
, "\nsegment: %i, index: %i, CAM: 0x%8.8x, content (%s):\n", segment
, index
, regs
[9], (regs
[9] & 0x10) ? "valid" : "invalid");
971 for (i
= 1; i
< 9; i
++)
973 i_cache
[segment
][index
].data
[i
] = regs
[i
];
974 fprintf(output
, "%i: 0x%8.8x\n", i
-1, regs
[i
]);
980 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
981 regs
[0] = 0x0 | (segment
<< 5) | (C15_C_D_Ind
<< 26);
982 arm9tdmi_write_core_regs(target
, 0x1, regs
);
984 /* set interpret mode */
986 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
988 /* Write ICache victim */
989 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
991 /* clear interpret mode */
993 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
996 /* restore CP15 MMU and Cache settings */
997 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved
);
999 command_print(cmd_ctx
, "cache content successfully output to %s", args
[0]);
1003 /* mark registers dirty. */
1004 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).valid
;
1005 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 1).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 1).valid
;
1006 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 2).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 2).valid
;
1007 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 3).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 3).valid
;
1008 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 4).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 4).valid
;
1009 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 5).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 5).valid
;
1010 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 6).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 6).valid
;
1011 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 7).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 7).valid
;
1012 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 8).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 8).valid
;
1013 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 9).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 9).valid
;
1018 int arm920t_handle_read_mmu_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1020 target_t
*target
= get_current_target(cmd_ctx
);
1021 armv4_5_common_t
*armv4_5
;
1022 arm7_9_common_t
*arm7_9
;
1023 arm9tdmi_common_t
*arm9tdmi
;
1024 arm920t_common_t
*arm920t
;
1025 arm_jtag_t
*jtag_info
;
1027 u32 cp15_ctrl
, cp15_ctrl_saved
;
1032 u32 Dlockdown
, Ilockdown
;
1033 arm920t_tlb_entry_t d_tlb
[64], i_tlb
[64];
1038 command_print(cmd_ctx
, "usage: arm920t read_mmu <filename>");
1042 if ((output
= fopen(args
[0], "w")) == NULL
)
1044 LOG_DEBUG("error opening mmu content file");
1048 for (i
= 0; i
< 16; i
++)
1049 regs_p
[i
] = ®s
[i
];
1051 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
1053 command_print(cmd_ctx
, "current target isn't an ARM920t target");
1057 jtag_info
= &arm7_9
->jtag_info
;
1059 /* disable MMU and Caches */
1060 arm920t_read_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl
);
1061 jtag_execute_queue();
1062 cp15_ctrl_saved
= cp15_ctrl
;
1063 cp15_ctrl
&= ~(ARMV4_5_MMU_ENABLED
| ARMV4_5_D_U_CACHE_ENABLED
| ARMV4_5_I_CACHE_ENABLED
);
1064 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl
);
1066 /* read CP15 test state register */
1067 arm920t_read_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15
);
1068 jtag_execute_queue();
1070 /* prepare reading D TLB content
1073 /* set interpret mode */
1075 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1077 /* Read D TLB lockdown */
1078 arm920t_execute_cp15(target
, ARMV4_5_MRC(15,0,0,10,0,0), ARMV4_5_LDR(1, 0));
1080 /* clear interpret mode */
1082 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1084 /* read D TLB lockdown stored to r1 */
1085 arm9tdmi_read_core_regs(target
, 0x2, regs_p
);
1086 jtag_execute_queue();
1087 Dlockdown
= regs
[1];
1089 for (victim
= 0; victim
< 64; victim
+= 8)
1091 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1092 * base remains unchanged, victim goes through entries 0 to 63 */
1093 regs
[1] = (Dlockdown
& 0xfc000000) | (victim
<< 20);
1094 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1096 /* set interpret mode */
1098 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1100 /* Write D TLB lockdown */
1101 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1103 /* Read D TLB CAM */
1104 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,6,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1106 /* clear interpret mode */
1108 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1110 /* read D TLB CAM content stored to r2-r9 */
1111 arm9tdmi_read_core_regs(target
, 0x3fc, regs_p
);
1112 jtag_execute_queue();
1114 for (i
= 0; i
< 8; i
++)
1115 d_tlb
[victim
+ i
].cam
= regs
[i
+ 2];
1118 for (victim
= 0; victim
< 64; victim
++)
1120 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1121 * base remains unchanged, victim goes through entries 0 to 63 */
1122 regs
[1] = (Dlockdown
& 0xfc000000) | (victim
<< 20);
1123 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1125 /* set interpret mode */
1127 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1129 /* Write D TLB lockdown */
1130 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1132 /* Read D TLB RAM1 */
1133 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,10,4), ARMV4_5_LDR(2,0));
1135 /* Read D TLB RAM2 */
1136 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,2,5), ARMV4_5_LDR(3,0));
1138 /* clear interpret mode */
1140 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1142 /* read D TLB RAM content stored to r2 and r3 */
1143 arm9tdmi_read_core_regs(target
, 0xc, regs_p
);
1144 jtag_execute_queue();
1146 d_tlb
[victim
].ram1
= regs
[2];
1147 d_tlb
[victim
].ram2
= regs
[3];
1150 /* restore D TLB lockdown */
1151 regs
[1] = Dlockdown
;
1152 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1154 /* Write D TLB lockdown */
1155 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1157 /* prepare reading I TLB content
1160 /* set interpret mode */
1162 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1164 /* Read I TLB lockdown */
1165 arm920t_execute_cp15(target
, ARMV4_5_MRC(15,0,0,10,0,1), ARMV4_5_LDR(1, 0));
1167 /* clear interpret mode */
1169 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1171 /* read I TLB lockdown stored to r1 */
1172 arm9tdmi_read_core_regs(target
, 0x2, regs_p
);
1173 jtag_execute_queue();
1174 Ilockdown
= regs
[1];
1176 for (victim
= 0; victim
< 64; victim
+= 8)
1178 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1179 * base remains unchanged, victim goes through entries 0 to 63 */
1180 regs
[1] = (Ilockdown
& 0xfc000000) | (victim
<< 20);
1181 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1183 /* set interpret mode */
1185 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1187 /* Write I TLB lockdown */
1188 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1190 /* Read I TLB CAM */
1191 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,5,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1193 /* clear interpret mode */
1195 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1197 /* read I TLB CAM content stored to r2-r9 */
1198 arm9tdmi_read_core_regs(target
, 0x3fc, regs_p
);
1199 jtag_execute_queue();
1201 for (i
= 0; i
< 8; i
++)
1202 i_tlb
[i
+ victim
].cam
= regs
[i
+ 2];
1205 for (victim
= 0; victim
< 64; victim
++)
1207 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1208 * base remains unchanged, victim goes through entries 0 to 63 */
1209 regs
[1] = (Dlockdown
& 0xfc000000) | (victim
<< 20);
1210 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1212 /* set interpret mode */
1214 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1216 /* Write I TLB lockdown */
1217 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1219 /* Read I TLB RAM1 */
1220 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,9,4), ARMV4_5_LDR(2,0));
1222 /* Read I TLB RAM2 */
1223 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,1,5), ARMV4_5_LDR(3,0));
1225 /* clear interpret mode */
1227 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1229 /* read I TLB RAM content stored to r2 and r3 */
1230 arm9tdmi_read_core_regs(target
, 0xc, regs_p
);
1231 jtag_execute_queue();
1233 i_tlb
[victim
].ram1
= regs
[2];
1234 i_tlb
[victim
].ram2
= regs
[3];
1237 /* restore I TLB lockdown */
1238 regs
[1] = Ilockdown
;
1239 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1241 /* Write I TLB lockdown */
1242 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1244 /* restore CP15 MMU and Cache settings */
1245 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved
);
1247 /* output data to file */
1248 fprintf(output
, "D TLB content:\n");
1249 for (i
= 0; i
< 64; i
++)
1251 fprintf(output
, "%i: 0x%8.8x 0x%8.8x 0x%8.8x %s\n", i
, d_tlb
[i
].cam
, d_tlb
[i
].ram1
, d_tlb
[i
].ram2
, (d_tlb
[i
].cam
& 0x20) ? "(valid)" : "(invalid)");
1254 fprintf(output
, "\n\nI TLB content:\n");
1255 for (i
= 0; i
< 64; i
++)
1257 fprintf(output
, "%i: 0x%8.8x 0x%8.8x 0x%8.8x %s\n", i
, i_tlb
[i
].cam
, i_tlb
[i
].ram1
, i_tlb
[i
].ram2
, (i_tlb
[i
].cam
& 0x20) ? "(valid)" : "(invalid)");
1260 command_print(cmd_ctx
, "mmu content successfully output to %s", args
[0]);
1264 /* mark registers dirty */
1265 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).valid
;
1266 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 1).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 1).valid
;
1267 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 2).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 2).valid
;
1268 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 3).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 3).valid
;
1269 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 4).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 4).valid
;
1270 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 5).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 5).valid
;
1271 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 6).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 6).valid
;
1272 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 7).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 7).valid
;
1273 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 8).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 8).valid
;
1274 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 9).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 9).valid
;
1278 int arm920t_handle_cp15_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1281 target_t
*target
= get_current_target(cmd_ctx
);
1282 armv4_5_common_t
*armv4_5
;
1283 arm7_9_common_t
*arm7_9
;
1284 arm9tdmi_common_t
*arm9tdmi
;
1285 arm920t_common_t
*arm920t
;
1286 arm_jtag_t
*jtag_info
;
1288 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
1290 command_print(cmd_ctx
, "current target isn't an ARM920t target");
1294 jtag_info
= &arm7_9
->jtag_info
;
1296 if (target
->state
!= TARGET_HALTED
)
1298 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
1302 /* one or more argument, access a single register (write if second argument is given */
1305 int address
= strtoul(args
[0], NULL
, 0);
1310 if ((retval
= arm920t_read_cp15_physical(target
, address
, &value
)) != ERROR_OK
)
1312 command_print(cmd_ctx
, "couldn't access reg %i", address
);
1315 jtag_execute_queue();
1317 command_print(cmd_ctx
, "%i: %8.8x", address
, value
);
1321 u32 value
= strtoul(args
[1], NULL
, 0);
1322 if ((retval
= arm920t_write_cp15_physical(target
, address
, value
)) != ERROR_OK
)
1324 command_print(cmd_ctx
, "couldn't access reg %i", address
);
1327 command_print(cmd_ctx
, "%i: %8.8x", address
, value
);
1334 int arm920t_handle_cp15i_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1337 target_t
*target
= get_current_target(cmd_ctx
);
1338 armv4_5_common_t
*armv4_5
;
1339 arm7_9_common_t
*arm7_9
;
1340 arm9tdmi_common_t
*arm9tdmi
;
1341 arm920t_common_t
*arm920t
;
1342 arm_jtag_t
*jtag_info
;
1344 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
1346 command_print(cmd_ctx
, "current target isn't an ARM920t target");
1350 jtag_info
= &arm7_9
->jtag_info
;
1352 if (target
->state
!= TARGET_HALTED
)
1354 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
1358 /* one or more argument, access a single register (write if second argument is given */
1361 u32 opcode
= strtoul(args
[0], NULL
, 0);
1366 if ((retval
= arm920t_read_cp15_interpreted(target
, opcode
, 0x0, &value
)) != ERROR_OK
)
1368 command_print(cmd_ctx
, "couldn't execute %8.8x", opcode
);
1372 command_print(cmd_ctx
, "%8.8x: %8.8x", opcode
, value
);
1376 u32 value
= strtoul(args
[1], NULL
, 0);
1377 if ((retval
= arm920t_write_cp15_interpreted(target
, opcode
, value
, 0)) != ERROR_OK
)
1379 command_print(cmd_ctx
, "couldn't execute %8.8x", opcode
);
1382 command_print(cmd_ctx
, "%8.8x: %8.8x", opcode
, value
);
1386 u32 value
= strtoul(args
[1], NULL
, 0);
1387 u32 address
= strtoul(args
[2], NULL
, 0);
1388 if ((retval
= arm920t_write_cp15_interpreted(target
, opcode
, value
, address
)) != ERROR_OK
)
1390 command_print(cmd_ctx
, "couldn't execute %8.8x", opcode
);
1393 command_print(cmd_ctx
, "%8.8x: %8.8x %8.8x", opcode
, value
, address
);
1398 command_print(cmd_ctx
, "usage: arm920t cp15i <opcode> [value] [address]");
1404 int arm920t_handle_cache_info_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1406 target_t
*target
= get_current_target(cmd_ctx
);
1407 armv4_5_common_t
*armv4_5
;
1408 arm7_9_common_t
*arm7_9
;
1409 arm9tdmi_common_t
*arm9tdmi
;
1410 arm920t_common_t
*arm920t
;
1412 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
1414 command_print(cmd_ctx
, "current target isn't an ARM920t target");
1418 return armv4_5_handle_cache_info_command(cmd_ctx
, &arm920t
->armv4_5_mmu
.armv4_5_cache
);
1421 int arm920t_handle_virt2phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1423 target_t
*target
= get_current_target(cmd_ctx
);
1424 armv4_5_common_t
*armv4_5
;
1425 arm7_9_common_t
*arm7_9
;
1426 arm9tdmi_common_t
*arm9tdmi
;
1427 arm920t_common_t
*arm920t
;
1428 arm_jtag_t
*jtag_info
;
1430 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
1432 command_print(cmd_ctx
, "current target isn't an ARM920t target");
1436 jtag_info
= &arm7_9
->jtag_info
;
1438 if (target
->state
!= TARGET_HALTED
)
1440 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
1444 return armv4_5_mmu_handle_virt2phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm920t
->armv4_5_mmu
);
1447 int arm920t_handle_md_phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1449 target_t
*target
= get_current_target(cmd_ctx
);
1450 armv4_5_common_t
*armv4_5
;
1451 arm7_9_common_t
*arm7_9
;
1452 arm9tdmi_common_t
*arm9tdmi
;
1453 arm920t_common_t
*arm920t
;
1454 arm_jtag_t
*jtag_info
;
1456 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
1458 command_print(cmd_ctx
, "current target isn't an ARM920t target");
1462 jtag_info
= &arm7_9
->jtag_info
;
1464 if (target
->state
!= TARGET_HALTED
)
1466 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
1470 return armv4_5_mmu_handle_md_phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm920t
->armv4_5_mmu
);
1473 int arm920t_handle_mw_phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1475 target_t
*target
= get_current_target(cmd_ctx
);
1476 armv4_5_common_t
*armv4_5
;
1477 arm7_9_common_t
*arm7_9
;
1478 arm9tdmi_common_t
*arm9tdmi
;
1479 arm920t_common_t
*arm920t
;
1480 arm_jtag_t
*jtag_info
;
1482 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
1484 command_print(cmd_ctx
, "current target isn't an ARM920t target");
1488 jtag_info
= &arm7_9
->jtag_info
;
1490 if (target
->state
!= TARGET_HALTED
)
1492 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
1496 return armv4_5_mmu_handle_mw_phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm920t
->armv4_5_mmu
);
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)