1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
27 #include "time_support.h"
33 #define _DEBUG_INSTRUCTION_EXECUTION_
37 int arm920t_register_commands(struct command_context_s
*cmd_ctx
);
39 int arm920t_handle_cp15_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
40 int arm920t_handle_cp15i_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
41 int arm920t_handle_virt2phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
42 int arm920t_handle_cache_info_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
43 int arm920t_handle_md_phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
44 int arm920t_handle_mw_phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
46 int arm920t_handle_read_cache_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
47 int arm920t_handle_read_mmu_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
49 /* forward declarations */
50 int arm920t_target_create(struct target_s
*target
, Jim_Interp
*interp
);
51 int arm920t_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
);
52 int arm920t_quit(void);
53 int arm920t_arch_state(struct target_s
*target
);
54 int arm920t_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
55 int arm920t_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
56 int arm920t_soft_reset_halt(struct target_s
*target
);
58 #define ARM920T_CP15_PHYS_ADDR(x, y, z) ((x << 5) | (y << 1) << (z))
60 target_type_t arm920t_target
=
65 .arch_state
= arm920t_arch_state
,
67 .target_request_data
= arm7_9_target_request_data
,
70 .resume
= arm7_9_resume
,
73 .assert_reset
= arm7_9_assert_reset
,
74 .deassert_reset
= arm7_9_deassert_reset
,
75 .soft_reset_halt
= arm920t_soft_reset_halt
,
77 .get_gdb_reg_list
= armv4_5_get_gdb_reg_list
,
79 .read_memory
= arm920t_read_memory
,
80 .write_memory
= arm920t_write_memory
,
81 .bulk_write_memory
= arm7_9_bulk_write_memory
,
82 .checksum_memory
= arm7_9_checksum_memory
,
83 .blank_check_memory
= arm7_9_blank_check_memory
,
85 .run_algorithm
= armv4_5_run_algorithm
,
87 .add_breakpoint
= arm7_9_add_breakpoint
,
88 .remove_breakpoint
= arm7_9_remove_breakpoint
,
89 .add_watchpoint
= arm7_9_add_watchpoint
,
90 .remove_watchpoint
= arm7_9_remove_watchpoint
,
92 .register_commands
= arm920t_register_commands
,
93 .target_create
= arm920t_target_create
,
94 .init_target
= arm920t_init_target
,
95 .examine
= arm9tdmi_examine
,
99 int arm920t_read_cp15_physical(target_t
*target
, int reg_addr
, u32
*value
)
101 armv4_5_common_t
*armv4_5
= target
->arch_info
;
102 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
103 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
104 scan_field_t fields
[4];
105 u8 access_type_buf
= 1;
106 u8 reg_addr_buf
= reg_addr
& 0x3f;
109 jtag_add_end_state(TAP_IDLE
);
110 arm_jtag_scann(jtag_info
, 0xf);
111 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
113 fields
[0].tap
= jtag_info
->tap
;
114 fields
[0].num_bits
= 1;
115 fields
[0].out_value
= &access_type_buf
;
116 fields
[0].out_mask
= NULL
;
117 fields
[0].in_value
= NULL
;
118 fields
[0].in_check_value
= NULL
;
119 fields
[0].in_check_mask
= NULL
;
120 fields
[0].in_handler
= NULL
;
121 fields
[0].in_handler_priv
= NULL
;
123 fields
[1].tap
= jtag_info
->tap
;
124 fields
[1].num_bits
= 32;
125 fields
[1].out_value
= NULL
;
126 fields
[1].out_mask
= NULL
;
127 fields
[1].in_value
= NULL
;
128 fields
[1].in_check_value
= NULL
;
129 fields
[1].in_check_mask
= NULL
;
130 fields
[1].in_handler
= NULL
;
131 fields
[1].in_handler_priv
= NULL
;
133 fields
[2].tap
= jtag_info
->tap
;
134 fields
[2].num_bits
= 6;
135 fields
[2].out_value
= ®_addr_buf
;
136 fields
[2].out_mask
= NULL
;
137 fields
[2].in_value
= NULL
;
138 fields
[2].in_check_value
= NULL
;
139 fields
[2].in_check_mask
= NULL
;
140 fields
[2].in_handler
= NULL
;
141 fields
[2].in_handler_priv
= NULL
;
143 fields
[3].tap
= jtag_info
->tap
;
144 fields
[3].num_bits
= 1;
145 fields
[3].out_value
= &nr_w_buf
;
146 fields
[3].out_mask
= NULL
;
147 fields
[3].in_value
= NULL
;
148 fields
[3].in_check_value
= NULL
;
149 fields
[3].in_check_mask
= NULL
;
150 fields
[3].in_handler
= NULL
;
151 fields
[3].in_handler_priv
= NULL
;
153 jtag_add_dr_scan(4, fields
, TAP_INVALID
);
155 fields
[1].in_handler_priv
= value
;
156 fields
[1].in_handler
= arm_jtag_buf_to_u32
;
158 jtag_add_dr_scan(4, fields
, TAP_INVALID
);
160 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
161 jtag_execute_queue();
162 LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr
, *value
);
168 int arm920t_write_cp15_physical(target_t
*target
, int reg_addr
, u32 value
)
170 armv4_5_common_t
*armv4_5
= target
->arch_info
;
171 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
172 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
173 scan_field_t fields
[4];
174 u8 access_type_buf
= 1;
175 u8 reg_addr_buf
= reg_addr
& 0x3f;
179 buf_set_u32(value_buf
, 0, 32, value
);
181 jtag_add_end_state(TAP_IDLE
);
182 arm_jtag_scann(jtag_info
, 0xf);
183 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
185 fields
[0].tap
= jtag_info
->tap
;
186 fields
[0].num_bits
= 1;
187 fields
[0].out_value
= &access_type_buf
;
188 fields
[0].out_mask
= NULL
;
189 fields
[0].in_value
= NULL
;
190 fields
[0].in_check_value
= NULL
;
191 fields
[0].in_check_mask
= NULL
;
192 fields
[0].in_handler
= NULL
;
193 fields
[0].in_handler_priv
= NULL
;
195 fields
[1].tap
= jtag_info
->tap
;
196 fields
[1].num_bits
= 32;
197 fields
[1].out_value
= value_buf
;
198 fields
[1].out_mask
= NULL
;
199 fields
[1].in_value
= NULL
;
200 fields
[1].in_check_value
= NULL
;
201 fields
[1].in_check_mask
= NULL
;
202 fields
[1].in_handler
= NULL
;
203 fields
[1].in_handler_priv
= NULL
;
205 fields
[2].tap
= jtag_info
->tap
;
206 fields
[2].num_bits
= 6;
207 fields
[2].out_value
= ®_addr_buf
;
208 fields
[2].out_mask
= NULL
;
209 fields
[2].in_value
= NULL
;
210 fields
[2].in_check_value
= NULL
;
211 fields
[2].in_check_mask
= NULL
;
212 fields
[2].in_handler
= NULL
;
213 fields
[2].in_handler_priv
= NULL
;
215 fields
[3].tap
= jtag_info
->tap
;
216 fields
[3].num_bits
= 1;
217 fields
[3].out_value
= &nr_w_buf
;
218 fields
[3].out_mask
= NULL
;
219 fields
[3].in_value
= NULL
;
220 fields
[3].in_check_value
= NULL
;
221 fields
[3].in_check_mask
= NULL
;
222 fields
[3].in_handler
= NULL
;
223 fields
[3].in_handler_priv
= NULL
;
225 jtag_add_dr_scan(4, fields
, TAP_INVALID
);
227 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
228 LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr
, value
);
234 int arm920t_execute_cp15(target_t
*target
, u32 cp15_opcode
, u32 arm_opcode
)
237 armv4_5_common_t
*armv4_5
= target
->arch_info
;
238 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
239 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
240 scan_field_t fields
[4];
241 u8 access_type_buf
= 0; /* interpreted access */
242 u8 reg_addr_buf
= 0x0;
244 u8 cp15_opcode_buf
[4];
246 jtag_add_end_state(TAP_IDLE
);
247 arm_jtag_scann(jtag_info
, 0xf);
248 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
250 buf_set_u32(cp15_opcode_buf
, 0, 32, cp15_opcode
);
252 fields
[0].tap
= jtag_info
->tap
;
253 fields
[0].num_bits
= 1;
254 fields
[0].out_value
= &access_type_buf
;
255 fields
[0].out_mask
= NULL
;
256 fields
[0].in_value
= NULL
;
257 fields
[0].in_check_value
= NULL
;
258 fields
[0].in_check_mask
= NULL
;
259 fields
[0].in_handler
= NULL
;
260 fields
[0].in_handler_priv
= NULL
;
262 fields
[1].tap
= jtag_info
->tap
;
263 fields
[1].num_bits
= 32;
264 fields
[1].out_value
= cp15_opcode_buf
;
265 fields
[1].out_mask
= NULL
;
266 fields
[1].in_value
= NULL
;
267 fields
[1].in_check_value
= NULL
;
268 fields
[1].in_check_mask
= NULL
;
269 fields
[1].in_handler
= NULL
;
270 fields
[1].in_handler_priv
= NULL
;
272 fields
[2].tap
= jtag_info
->tap
;
273 fields
[2].num_bits
= 6;
274 fields
[2].out_value
= ®_addr_buf
;
275 fields
[2].out_mask
= NULL
;
276 fields
[2].in_value
= NULL
;
277 fields
[2].in_check_value
= NULL
;
278 fields
[2].in_check_mask
= NULL
;
279 fields
[2].in_handler
= NULL
;
280 fields
[2].in_handler_priv
= NULL
;
282 fields
[3].tap
= jtag_info
->tap
;
283 fields
[3].num_bits
= 1;
284 fields
[3].out_value
= &nr_w_buf
;
285 fields
[3].out_mask
= NULL
;
286 fields
[3].in_value
= NULL
;
287 fields
[3].in_check_value
= NULL
;
288 fields
[3].in_check_mask
= NULL
;
289 fields
[3].in_handler
= NULL
;
290 fields
[3].in_handler_priv
= NULL
;
292 jtag_add_dr_scan(4, fields
, TAP_INVALID
);
294 arm9tdmi_clock_out(jtag_info
, arm_opcode
, 0, NULL
, 0);
295 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
296 retval
= arm7_9_execute_sys_speed(target
);
297 if (retval
!= ERROR_OK
)
300 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
302 LOG_ERROR("failed executing JTAG queue, exiting");
309 int arm920t_read_cp15_interpreted(target_t
*target
, u32 cp15_opcode
, u32 address
, u32
*value
)
311 armv4_5_common_t
*armv4_5
= target
->arch_info
;
316 /* load address into R1 */
318 arm9tdmi_write_core_regs(target
, 0x2, regs
);
320 /* read-modify-write CP15 test state register
321 * to enable interpreted access mode */
322 arm920t_read_cp15_physical(target
, 0x1e, &cp15c15
);
323 jtag_execute_queue();
324 cp15c15
|= 1; /* set interpret mode */
325 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
327 /* execute CP15 instruction and ARM load (reading from coprocessor) */
328 arm920t_execute_cp15(target
, cp15_opcode
, ARMV4_5_LDR(0, 1));
330 /* disable interpreted access mode */
331 cp15c15
&= ~1U; /* clear interpret mode */
332 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
334 /* retrieve value from R0 */
336 arm9tdmi_read_core_regs(target
, 0x1, regs_p
);
337 jtag_execute_queue();
339 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
340 LOG_DEBUG("cp15_opcode: %8.8x, address: %8.8x, value: %8.8x", cp15_opcode
, address
, *value
);
343 if (armv4_5_mode_to_number(armv4_5
->core_mode
)==-1)
346 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).dirty
= 1;
347 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 1).dirty
= 1;
352 int arm920t_write_cp15_interpreted(target_t
*target
, u32 cp15_opcode
, u32 value
, u32 address
)
355 armv4_5_common_t
*armv4_5
= target
->arch_info
;
358 /* load value, address into R0, R1 */
361 arm9tdmi_write_core_regs(target
, 0x3, regs
);
363 /* read-modify-write CP15 test state register
364 * to enable interpreted access mode */
365 arm920t_read_cp15_physical(target
, 0x1e, &cp15c15
);
366 jtag_execute_queue();
367 cp15c15
|= 1; /* set interpret mode */
368 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
370 /* execute CP15 instruction and ARM store (writing to coprocessor) */
371 arm920t_execute_cp15(target
, cp15_opcode
, ARMV4_5_STR(0, 1));
373 /* disable interpreted access mode */
374 cp15c15
&= ~1U; /* set interpret mode */
375 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
377 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
378 LOG_DEBUG("cp15_opcode: %8.8x, value: %8.8x, address: %8.8x", cp15_opcode
, value
, address
);
381 if (armv4_5_mode_to_number(armv4_5
->core_mode
)==-1)
384 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).dirty
= 1;
385 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 1).dirty
= 1;
390 u32
arm920t_get_ttb(target_t
*target
)
395 if ((retval
= arm920t_read_cp15_interpreted(target
, 0xeebf0f51, 0x0, &ttb
)) != ERROR_OK
)
401 void arm920t_disable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
405 /* read cp15 control register */
406 arm920t_read_cp15_physical(target
, 0x2, &cp15_control
);
407 jtag_execute_queue();
410 cp15_control
&= ~0x1U
;
413 cp15_control
&= ~0x4U
;
416 cp15_control
&= ~0x1000U
;
418 arm920t_write_cp15_physical(target
, 0x2, cp15_control
);
421 void arm920t_enable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
425 /* read cp15 control register */
426 arm920t_read_cp15_physical(target
, 0x2, &cp15_control
);
427 jtag_execute_queue();
430 cp15_control
|= 0x1U
;
433 cp15_control
|= 0x4U
;
436 cp15_control
|= 0x1000U
;
438 arm920t_write_cp15_physical(target
, 0x2, cp15_control
);
441 void arm920t_post_debug_entry(target_t
*target
)
444 armv4_5_common_t
*armv4_5
= target
->arch_info
;
445 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
446 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
447 arm920t_common_t
*arm920t
= arm9tdmi
->arch_info
;
449 /* examine cp15 control reg */
450 arm920t_read_cp15_physical(target
, 0x2, &arm920t
->cp15_control_reg
);
451 jtag_execute_queue();
452 LOG_DEBUG("cp15_control_reg: %8.8x", arm920t
->cp15_control_reg
);
454 if (arm920t
->armv4_5_mmu
.armv4_5_cache
.ctype
== -1)
457 /* identify caches */
458 arm920t_read_cp15_physical(target
, 0x1, &cache_type_reg
);
459 jtag_execute_queue();
460 armv4_5_identify_cache(cache_type_reg
, &arm920t
->armv4_5_mmu
.armv4_5_cache
);
463 arm920t
->armv4_5_mmu
.mmu_enabled
= (arm920t
->cp15_control_reg
& 0x1U
) ? 1 : 0;
464 arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= (arm920t
->cp15_control_reg
& 0x4U
) ? 1 : 0;
465 arm920t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= (arm920t
->cp15_control_reg
& 0x1000U
) ? 1 : 0;
467 /* save i/d fault status and address register */
468 arm920t_read_cp15_interpreted(target
, 0xee150f10, 0x0, &arm920t
->d_fsr
);
469 arm920t_read_cp15_interpreted(target
, 0xee150f30, 0x0, &arm920t
->i_fsr
);
470 arm920t_read_cp15_interpreted(target
, 0xee160f10, 0x0, &arm920t
->d_far
);
471 arm920t_read_cp15_interpreted(target
, 0xee160f30, 0x0, &arm920t
->i_far
);
473 LOG_DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x, I FAR: 0x%8.8x",
474 arm920t
->d_fsr
, arm920t
->d_far
, arm920t
->i_fsr
, arm920t
->i_far
);
476 if (arm920t
->preserve_cache
)
478 /* read-modify-write CP15 test state register
479 * to disable I/D-cache linefills */
480 arm920t_read_cp15_physical(target
, 0x1e, &cp15c15
);
481 jtag_execute_queue();
483 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
487 void arm920t_pre_restore_context(target_t
*target
)
490 armv4_5_common_t
*armv4_5
= target
->arch_info
;
491 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
492 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
493 arm920t_common_t
*arm920t
= arm9tdmi
->arch_info
;
495 /* restore i/d fault status and address register */
496 arm920t_write_cp15_interpreted(target
, 0xee050f10, arm920t
->d_fsr
, 0x0);
497 arm920t_write_cp15_interpreted(target
, 0xee050f30, arm920t
->i_fsr
, 0x0);
498 arm920t_write_cp15_interpreted(target
, 0xee060f10, arm920t
->d_far
, 0x0);
499 arm920t_write_cp15_interpreted(target
, 0xee060f30, arm920t
->i_far
, 0x0);
501 /* read-modify-write CP15 test state register
502 * to reenable I/D-cache linefills */
503 if (arm920t
->preserve_cache
)
505 arm920t_read_cp15_physical(target
, 0x1e, &cp15c15
);
506 jtag_execute_queue();
508 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
512 int arm920t_get_arch_pointers(target_t
*target
, armv4_5_common_t
**armv4_5_p
, arm7_9_common_t
**arm7_9_p
, arm9tdmi_common_t
**arm9tdmi_p
, arm920t_common_t
**arm920t_p
)
514 armv4_5_common_t
*armv4_5
= target
->arch_info
;
515 arm7_9_common_t
*arm7_9
;
516 arm9tdmi_common_t
*arm9tdmi
;
517 arm920t_common_t
*arm920t
;
519 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
524 arm7_9
= armv4_5
->arch_info
;
525 if (arm7_9
->common_magic
!= ARM7_9_COMMON_MAGIC
)
530 arm9tdmi
= arm7_9
->arch_info
;
531 if (arm9tdmi
->common_magic
!= ARM9TDMI_COMMON_MAGIC
)
536 arm920t
= arm9tdmi
->arch_info
;
537 if (arm920t
->common_magic
!= ARM920T_COMMON_MAGIC
)
542 *armv4_5_p
= armv4_5
;
544 *arm9tdmi_p
= arm9tdmi
;
545 *arm920t_p
= arm920t
;
550 int arm920t_arch_state(struct target_s
*target
)
552 armv4_5_common_t
*armv4_5
= target
->arch_info
;
553 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
554 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
555 arm920t_common_t
*arm920t
= arm9tdmi
->arch_info
;
559 "disabled", "enabled"
562 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
564 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
568 LOG_USER( "target halted in %s state due to %s, current mode: %s\n"
569 "cpsr: 0x%8.8x pc: 0x%8.8x\n"
570 "MMU: %s, D-Cache: %s, I-Cache: %s",
571 armv4_5_state_strings
[armv4_5
->core_state
],
572 Jim_Nvp_value2name_simple(nvp_target_debug_reason
, target
->debug_reason
)->name
,
573 armv4_5_mode_strings
[armv4_5_mode_to_number(armv4_5
->core_mode
)],
574 buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32),
575 buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32),
576 state
[arm920t
->armv4_5_mmu
.mmu_enabled
],
577 state
[arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
],
578 state
[arm920t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
]);
583 int arm920t_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
587 retval
= arm7_9_read_memory(target
, address
, size
, count
, buffer
);
592 int arm920t_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
595 armv4_5_common_t
*armv4_5
= target
->arch_info
;
596 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
597 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
598 arm920t_common_t
*arm920t
= arm9tdmi
->arch_info
;
600 if ((retval
= arm7_9_write_memory(target
, address
, size
, count
, buffer
)) != ERROR_OK
)
603 if (((size
== 4) || (size
== 2)) && (count
== 1))
605 if (arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
)
607 LOG_DEBUG("D-Cache enabled, writing through to main memory");
611 pa
= armv4_5_mmu_translate_va(target
, &arm920t
->armv4_5_mmu
, address
, &type
, &cb
, &domain
, &ap
);
614 /* cacheable & bufferable means write-back region */
616 armv4_5_mmu_write_physical(target
, &arm920t
->armv4_5_mmu
, pa
, size
, count
, buffer
);
619 if (arm920t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
)
621 LOG_DEBUG("I-Cache enabled, invalidating affected I-Cache line");
622 arm920t_write_cp15_interpreted(target
, 0xee070f35, 0x0, address
);
629 int arm920t_soft_reset_halt(struct target_s
*target
)
631 int retval
= ERROR_OK
;
632 armv4_5_common_t
*armv4_5
= target
->arch_info
;
633 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
634 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
635 arm920t_common_t
*arm920t
= arm9tdmi
->arch_info
;
636 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
638 if((retval
= target_halt(target
)) != ERROR_OK
)
643 long long then
=timeval_ms();
645 while (!(timeout
=((timeval_ms()-then
)>1000)))
647 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1) == 0)
649 embeddedice_read_reg(dbg_stat
);
650 if((retval
= jtag_execute_queue()) != ERROR_OK
)
660 /* do not eat all CPU, time out after 1 se*/
669 LOG_ERROR("Failed to halt CPU after 1 sec");
670 return ERROR_TARGET_TIMEOUT
;
673 target
->state
= TARGET_HALTED
;
675 /* SVC, ARM state, IRQ and FIQ disabled */
676 buf_set_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8, 0xd3);
677 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 1;
678 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
680 /* start fetching from 0x0 */
681 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, 0x0);
682 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
683 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
685 armv4_5
->core_mode
= ARMV4_5_MODE_SVC
;
686 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
688 arm920t_disable_mmu_caches(target
, 1, 1, 1);
689 arm920t
->armv4_5_mmu
.mmu_enabled
= 0;
690 arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= 0;
691 arm920t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 0;
693 if((retval
= target_call_event_callbacks(target
, TARGET_EVENT_HALTED
)) != ERROR_OK
)
701 int arm920t_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
703 arm9tdmi_init_target(cmd_ctx
, target
);
708 int arm920t_quit(void)
713 int arm920t_init_arch_info(target_t
*target
, arm920t_common_t
*arm920t
, jtag_tap_t
*tap
)
715 arm9tdmi_common_t
*arm9tdmi
= &arm920t
->arm9tdmi_common
;
716 arm7_9_common_t
*arm7_9
= &arm9tdmi
->arm7_9_common
;
718 /* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
720 arm9tdmi_init_arch_info(target
, arm9tdmi
, tap
);
722 arm9tdmi
->arch_info
= arm920t
;
723 arm920t
->common_magic
= ARM920T_COMMON_MAGIC
;
725 arm7_9
->post_debug_entry
= arm920t_post_debug_entry
;
726 arm7_9
->pre_restore_context
= arm920t_pre_restore_context
;
728 arm920t
->armv4_5_mmu
.armv4_5_cache
.ctype
= -1;
729 arm920t
->armv4_5_mmu
.get_ttb
= arm920t_get_ttb
;
730 arm920t
->armv4_5_mmu
.read_memory
= arm7_9_read_memory
;
731 arm920t
->armv4_5_mmu
.write_memory
= arm7_9_write_memory
;
732 arm920t
->armv4_5_mmu
.disable_mmu_caches
= arm920t_disable_mmu_caches
;
733 arm920t
->armv4_5_mmu
.enable_mmu_caches
= arm920t_enable_mmu_caches
;
734 arm920t
->armv4_5_mmu
.has_tiny_pages
= 1;
735 arm920t
->armv4_5_mmu
.mmu_enabled
= 0;
737 /* disabling linefills leads to lockups, so keep them enabled for now
738 * this doesn't affect correctness, but might affect timing issues, if
739 * important data is evicted from the cache during the debug session
741 arm920t
->preserve_cache
= 0;
743 /* override hw single-step capability from ARM9TDMI */
744 arm7_9
->has_single_step
= 1;
749 int arm920t_target_create(struct target_s
*target
, Jim_Interp
*interp
)
751 arm920t_common_t
*arm920t
= calloc(1,sizeof(arm920t_common_t
));
753 arm920t_init_arch_info(target
, arm920t
, target
->tap
);
758 int arm920t_register_commands(struct command_context_s
*cmd_ctx
)
761 command_t
*arm920t_cmd
;
764 retval
= arm9tdmi_register_commands(cmd_ctx
);
766 arm920t_cmd
= register_command(cmd_ctx
, NULL
, "arm920t", NULL
, COMMAND_ANY
, "arm920t specific commands");
768 register_command(cmd_ctx
, arm920t_cmd
, "cp15", arm920t_handle_cp15_command
, COMMAND_EXEC
, "display/modify cp15 register <num> [value]");
769 register_command(cmd_ctx
, arm920t_cmd
, "cp15i", arm920t_handle_cp15i_command
, COMMAND_EXEC
, "display/modify cp15 (interpreted access) <opcode> [value] [address]");
770 register_command(cmd_ctx
, arm920t_cmd
, "cache_info", arm920t_handle_cache_info_command
, COMMAND_EXEC
, "display information about target caches");
771 register_command(cmd_ctx
, arm920t_cmd
, "virt2phys", arm920t_handle_virt2phys_command
, COMMAND_EXEC
, "translate va to pa <va>");
773 register_command(cmd_ctx
, arm920t_cmd
, "mdw_phys", arm920t_handle_md_phys_command
, COMMAND_EXEC
, "display memory words <physical addr> [count]");
774 register_command(cmd_ctx
, arm920t_cmd
, "mdh_phys", arm920t_handle_md_phys_command
, COMMAND_EXEC
, "display memory half-words <physical addr> [count]");
775 register_command(cmd_ctx
, arm920t_cmd
, "mdb_phys", arm920t_handle_md_phys_command
, COMMAND_EXEC
, "display memory bytes <physical addr> [count]");
777 register_command(cmd_ctx
, arm920t_cmd
, "mww_phys", arm920t_handle_mw_phys_command
, COMMAND_EXEC
, "write memory word <physical addr> <value>");
778 register_command(cmd_ctx
, arm920t_cmd
, "mwh_phys", arm920t_handle_mw_phys_command
, COMMAND_EXEC
, "write memory half-word <physical addr> <value>");
779 register_command(cmd_ctx
, arm920t_cmd
, "mwb_phys", arm920t_handle_mw_phys_command
, COMMAND_EXEC
, "write memory byte <physical addr> <value>");
781 register_command(cmd_ctx
, arm920t_cmd
, "read_cache", arm920t_handle_read_cache_command
, COMMAND_EXEC
, "display I/D cache content");
782 register_command(cmd_ctx
, arm920t_cmd
, "read_mmu", arm920t_handle_read_mmu_command
, COMMAND_EXEC
, "display I/D mmu content");
787 int arm920t_handle_read_cache_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
789 int retval
= ERROR_OK
;
790 target_t
*target
= get_current_target(cmd_ctx
);
791 armv4_5_common_t
*armv4_5
;
792 arm7_9_common_t
*arm7_9
;
793 arm9tdmi_common_t
*arm9tdmi
;
794 arm920t_common_t
*arm920t
;
795 arm_jtag_t
*jtag_info
;
797 u32 cp15_ctrl
, cp15_ctrl_saved
;
800 u32 C15_C_D_Ind
, C15_C_I_Ind
;
803 arm920t_cache_line_t d_cache
[8][64], i_cache
[8][64];
808 command_print(cmd_ctx
, "usage: arm920t read_cache <filename>");
812 if ((output
= fopen(args
[0], "w")) == NULL
)
814 LOG_DEBUG("error opening cache content file");
818 for (i
= 0; i
< 16; i
++)
819 regs_p
[i
] = ®s
[i
];
821 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
823 command_print(cmd_ctx
, "current target isn't an ARM920t target");
827 jtag_info
= &arm7_9
->jtag_info
;
829 /* disable MMU and Caches */
830 arm920t_read_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl
);
831 if((retval
= jtag_execute_queue()) != ERROR_OK
)
835 cp15_ctrl_saved
= cp15_ctrl
;
836 cp15_ctrl
&= ~(ARMV4_5_MMU_ENABLED
| ARMV4_5_D_U_CACHE_ENABLED
| ARMV4_5_I_CACHE_ENABLED
);
837 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl
);
839 /* read CP15 test state register */
840 arm920t_read_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15
);
841 jtag_execute_queue();
843 /* read DCache content */
844 fprintf(output
, "DCache:\n");
846 /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
847 for (segment
= 0; segment
< arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_size
.nsets
; segment
++)
849 fprintf(output
, "\nsegment: %i\n----------", segment
);
851 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
852 regs
[0] = 0x0 | (segment
<< 5);
853 arm9tdmi_write_core_regs(target
, 0x1, regs
);
855 /* set interpret mode */
857 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
859 /* D CAM Read, loads current victim into C15.C.D.Ind */
860 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(1, 0));
862 /* read current victim */
863 arm920t_read_cp15_physical(target
, 0x3d, &C15_C_D_Ind
);
865 /* clear interpret mode */
867 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
869 for (index
= 0; index
< 64; index
++)
871 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
872 regs
[0] = 0x0 | (segment
<< 5) | (index
<< 26);
873 arm9tdmi_write_core_regs(target
, 0x1, regs
);
875 /* set interpret mode */
877 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
879 /* Write DCache victim */
880 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
883 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,10,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
886 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(9, 0));
888 /* clear interpret mode */
890 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
892 /* read D RAM and CAM content */
893 arm9tdmi_read_core_regs(target
, 0x3fe, regs_p
);
894 if((retval
= jtag_execute_queue()) != ERROR_OK
)
899 d_cache
[segment
][index
].cam
= regs
[9];
902 regs
[9] &= 0xfffffffe;
903 fprintf(output
, "\nsegment: %i, index: %i, CAM: 0x%8.8x, content (%s):\n", segment
, index
, regs
[9], (regs
[9] & 0x10) ? "valid" : "invalid");
905 for (i
= 1; i
< 9; i
++)
907 d_cache
[segment
][index
].data
[i
] = regs
[i
];
908 fprintf(output
, "%i: 0x%8.8x\n", i
-1, regs
[i
]);
913 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
914 regs
[0] = 0x0 | (segment
<< 5) | (C15_C_D_Ind
<< 26);
915 arm9tdmi_write_core_regs(target
, 0x1, regs
);
917 /* set interpret mode */
919 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
921 /* Write DCache victim */
922 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
924 /* clear interpret mode */
926 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
929 /* read ICache content */
930 fprintf(output
, "ICache:\n");
932 /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
933 for (segment
= 0; segment
< arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_size
.nsets
; segment
++)
935 fprintf(output
, "segment: %i\n----------", segment
);
937 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
938 regs
[0] = 0x0 | (segment
<< 5);
939 arm9tdmi_write_core_regs(target
, 0x1, regs
);
941 /* set interpret mode */
943 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
945 /* I CAM Read, loads current victim into C15.C.I.Ind */
946 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(1, 0));
948 /* read current victim */
949 arm920t_read_cp15_physical(target
, 0x3b, &C15_C_I_Ind
);
951 /* clear interpret mode */
953 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
955 for (index
= 0; index
< 64; index
++)
957 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
958 regs
[0] = 0x0 | (segment
<< 5) | (index
<< 26);
959 arm9tdmi_write_core_regs(target
, 0x1, regs
);
961 /* set interpret mode */
963 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
965 /* Write ICache victim */
966 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
969 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,9,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
972 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(9, 0));
974 /* clear interpret mode */
976 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
978 /* read I RAM and CAM content */
979 arm9tdmi_read_core_regs(target
, 0x3fe, regs_p
);
980 if((retval
= jtag_execute_queue()) != ERROR_OK
)
985 i_cache
[segment
][index
].cam
= regs
[9];
988 regs
[9] &= 0xfffffffe;
989 fprintf(output
, "\nsegment: %i, index: %i, CAM: 0x%8.8x, content (%s):\n", segment
, index
, regs
[9], (regs
[9] & 0x10) ? "valid" : "invalid");
991 for (i
= 1; i
< 9; i
++)
993 i_cache
[segment
][index
].data
[i
] = regs
[i
];
994 fprintf(output
, "%i: 0x%8.8x\n", i
-1, regs
[i
]);
998 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
999 regs
[0] = 0x0 | (segment
<< 5) | (C15_C_D_Ind
<< 26);
1000 arm9tdmi_write_core_regs(target
, 0x1, regs
);
1002 /* set interpret mode */
1004 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1006 /* Write ICache victim */
1007 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
1009 /* clear interpret mode */
1011 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1014 /* restore CP15 MMU and Cache settings */
1015 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved
);
1017 command_print(cmd_ctx
, "cache content successfully output to %s", args
[0]);
1021 if (armv4_5_mode_to_number(armv4_5
->core_mode
)==-1)
1024 /* mark registers dirty. */
1025 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).valid
;
1026 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 1).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 1).valid
;
1027 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 2).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 2).valid
;
1028 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 3).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 3).valid
;
1029 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 4).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 4).valid
;
1030 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 5).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 5).valid
;
1031 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 6).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 6).valid
;
1032 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 7).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 7).valid
;
1033 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 8).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 8).valid
;
1034 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 9).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 9).valid
;
1039 int arm920t_handle_read_mmu_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1041 int retval
= ERROR_OK
;
1042 target_t
*target
= get_current_target(cmd_ctx
);
1043 armv4_5_common_t
*armv4_5
;
1044 arm7_9_common_t
*arm7_9
;
1045 arm9tdmi_common_t
*arm9tdmi
;
1046 arm920t_common_t
*arm920t
;
1047 arm_jtag_t
*jtag_info
;
1049 u32 cp15_ctrl
, cp15_ctrl_saved
;
1054 u32 Dlockdown
, Ilockdown
;
1055 arm920t_tlb_entry_t d_tlb
[64], i_tlb
[64];
1060 command_print(cmd_ctx
, "usage: arm920t read_mmu <filename>");
1064 if ((output
= fopen(args
[0], "w")) == NULL
)
1066 LOG_DEBUG("error opening mmu content file");
1070 for (i
= 0; i
< 16; i
++)
1071 regs_p
[i
] = ®s
[i
];
1073 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
1075 command_print(cmd_ctx
, "current target isn't an ARM920t target");
1079 jtag_info
= &arm7_9
->jtag_info
;
1081 /* disable MMU and Caches */
1082 arm920t_read_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl
);
1083 if((retval
= jtag_execute_queue()) != ERROR_OK
)
1087 cp15_ctrl_saved
= cp15_ctrl
;
1088 cp15_ctrl
&= ~(ARMV4_5_MMU_ENABLED
| ARMV4_5_D_U_CACHE_ENABLED
| ARMV4_5_I_CACHE_ENABLED
);
1089 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl
);
1091 /* read CP15 test state register */
1092 arm920t_read_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15
);
1093 if((retval
= jtag_execute_queue()) != ERROR_OK
)
1098 /* prepare reading D TLB content
1101 /* set interpret mode */
1103 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1105 /* Read D TLB lockdown */
1106 arm920t_execute_cp15(target
, ARMV4_5_MRC(15,0,0,10,0,0), ARMV4_5_LDR(1, 0));
1108 /* clear interpret mode */
1110 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1112 /* read D TLB lockdown stored to r1 */
1113 arm9tdmi_read_core_regs(target
, 0x2, regs_p
);
1114 if((retval
= jtag_execute_queue()) != ERROR_OK
)
1118 Dlockdown
= regs
[1];
1120 for (victim
= 0; victim
< 64; victim
+= 8)
1122 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1123 * base remains unchanged, victim goes through entries 0 to 63 */
1124 regs
[1] = (Dlockdown
& 0xfc000000) | (victim
<< 20);
1125 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1127 /* set interpret mode */
1129 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1131 /* Write D TLB lockdown */
1132 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1134 /* Read D TLB CAM */
1135 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,6,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1137 /* clear interpret mode */
1139 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1141 /* read D TLB CAM content stored to r2-r9 */
1142 arm9tdmi_read_core_regs(target
, 0x3fc, regs_p
);
1143 if((retval
= jtag_execute_queue()) != ERROR_OK
)
1148 for (i
= 0; i
< 8; i
++)
1149 d_tlb
[victim
+ i
].cam
= regs
[i
+ 2];
1152 for (victim
= 0; victim
< 64; victim
++)
1154 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1155 * base remains unchanged, victim goes through entries 0 to 63 */
1156 regs
[1] = (Dlockdown
& 0xfc000000) | (victim
<< 20);
1157 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1159 /* set interpret mode */
1161 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1163 /* Write D TLB lockdown */
1164 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1166 /* Read D TLB RAM1 */
1167 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,10,4), ARMV4_5_LDR(2,0));
1169 /* Read D TLB RAM2 */
1170 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,2,5), ARMV4_5_LDR(3,0));
1172 /* clear interpret mode */
1174 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1176 /* read D TLB RAM content stored to r2 and r3 */
1177 arm9tdmi_read_core_regs(target
, 0xc, regs_p
);
1178 if((retval
= jtag_execute_queue()) != ERROR_OK
)
1183 d_tlb
[victim
].ram1
= regs
[2];
1184 d_tlb
[victim
].ram2
= regs
[3];
1187 /* restore D TLB lockdown */
1188 regs
[1] = Dlockdown
;
1189 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1191 /* Write D TLB lockdown */
1192 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1194 /* prepare reading I TLB content
1197 /* set interpret mode */
1199 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1201 /* Read I TLB lockdown */
1202 arm920t_execute_cp15(target
, ARMV4_5_MRC(15,0,0,10,0,1), ARMV4_5_LDR(1, 0));
1204 /* clear interpret mode */
1206 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1208 /* read I TLB lockdown stored to r1 */
1209 arm9tdmi_read_core_regs(target
, 0x2, regs_p
);
1210 if((retval
= jtag_execute_queue()) != ERROR_OK
)
1214 Ilockdown
= regs
[1];
1216 for (victim
= 0; victim
< 64; victim
+= 8)
1218 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1219 * base remains unchanged, victim goes through entries 0 to 63 */
1220 regs
[1] = (Ilockdown
& 0xfc000000) | (victim
<< 20);
1221 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1223 /* set interpret mode */
1225 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1227 /* Write I TLB lockdown */
1228 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1230 /* Read I TLB CAM */
1231 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,5,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1233 /* clear interpret mode */
1235 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1237 /* read I TLB CAM content stored to r2-r9 */
1238 arm9tdmi_read_core_regs(target
, 0x3fc, regs_p
);
1239 if((retval
= jtag_execute_queue()) != ERROR_OK
)
1244 for (i
= 0; i
< 8; i
++)
1245 i_tlb
[i
+ victim
].cam
= regs
[i
+ 2];
1248 for (victim
= 0; victim
< 64; victim
++)
1250 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1251 * base remains unchanged, victim goes through entries 0 to 63 */
1252 regs
[1] = (Dlockdown
& 0xfc000000) | (victim
<< 20);
1253 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1255 /* set interpret mode */
1257 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1259 /* Write I TLB lockdown */
1260 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1262 /* Read I TLB RAM1 */
1263 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,9,4), ARMV4_5_LDR(2,0));
1265 /* Read I TLB RAM2 */
1266 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,1,5), ARMV4_5_LDR(3,0));
1268 /* clear interpret mode */
1270 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1272 /* read I TLB RAM content stored to r2 and r3 */
1273 arm9tdmi_read_core_regs(target
, 0xc, regs_p
);
1274 if((retval
= jtag_execute_queue()) != ERROR_OK
)
1279 i_tlb
[victim
].ram1
= regs
[2];
1280 i_tlb
[victim
].ram2
= regs
[3];
1283 /* restore I TLB lockdown */
1284 regs
[1] = Ilockdown
;
1285 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1287 /* Write I TLB lockdown */
1288 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1290 /* restore CP15 MMU and Cache settings */
1291 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved
);
1293 /* output data to file */
1294 fprintf(output
, "D TLB content:\n");
1295 for (i
= 0; i
< 64; i
++)
1297 fprintf(output
, "%i: 0x%8.8x 0x%8.8x 0x%8.8x %s\n", i
, d_tlb
[i
].cam
, d_tlb
[i
].ram1
, d_tlb
[i
].ram2
, (d_tlb
[i
].cam
& 0x20) ? "(valid)" : "(invalid)");
1300 fprintf(output
, "\n\nI TLB content:\n");
1301 for (i
= 0; i
< 64; i
++)
1303 fprintf(output
, "%i: 0x%8.8x 0x%8.8x 0x%8.8x %s\n", i
, i_tlb
[i
].cam
, i_tlb
[i
].ram1
, i_tlb
[i
].ram2
, (i_tlb
[i
].cam
& 0x20) ? "(valid)" : "(invalid)");
1306 command_print(cmd_ctx
, "mmu content successfully output to %s", args
[0]);
1310 if (armv4_5_mode_to_number(armv4_5
->core_mode
)==-1)
1313 /* mark registers dirty */
1314 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).valid
;
1315 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 1).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 1).valid
;
1316 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 2).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 2).valid
;
1317 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 3).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 3).valid
;
1318 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 4).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 4).valid
;
1319 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 5).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 5).valid
;
1320 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 6).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 6).valid
;
1321 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 7).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 7).valid
;
1322 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 8).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 8).valid
;
1323 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 9).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 9).valid
;
1327 int arm920t_handle_cp15_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1330 target_t
*target
= get_current_target(cmd_ctx
);
1331 armv4_5_common_t
*armv4_5
;
1332 arm7_9_common_t
*arm7_9
;
1333 arm9tdmi_common_t
*arm9tdmi
;
1334 arm920t_common_t
*arm920t
;
1335 arm_jtag_t
*jtag_info
;
1337 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
1339 command_print(cmd_ctx
, "current target isn't an ARM920t target");
1343 jtag_info
= &arm7_9
->jtag_info
;
1345 if (target
->state
!= TARGET_HALTED
)
1347 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
1351 /* one or more argument, access a single register (write if second argument is given */
1354 int address
= strtoul(args
[0], NULL
, 0);
1359 if ((retval
= arm920t_read_cp15_physical(target
, address
, &value
)) != ERROR_OK
)
1361 command_print(cmd_ctx
, "couldn't access reg %i", address
);
1364 if((retval
= jtag_execute_queue()) != ERROR_OK
)
1369 command_print(cmd_ctx
, "%i: %8.8x", address
, value
);
1373 u32 value
= strtoul(args
[1], NULL
, 0);
1374 if ((retval
= arm920t_write_cp15_physical(target
, address
, value
)) != ERROR_OK
)
1376 command_print(cmd_ctx
, "couldn't access reg %i", address
);
1379 command_print(cmd_ctx
, "%i: %8.8x", address
, value
);
1386 int arm920t_handle_cp15i_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1389 target_t
*target
= get_current_target(cmd_ctx
);
1390 armv4_5_common_t
*armv4_5
;
1391 arm7_9_common_t
*arm7_9
;
1392 arm9tdmi_common_t
*arm9tdmi
;
1393 arm920t_common_t
*arm920t
;
1394 arm_jtag_t
*jtag_info
;
1396 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
1398 command_print(cmd_ctx
, "current target isn't an ARM920t target");
1402 jtag_info
= &arm7_9
->jtag_info
;
1404 if (target
->state
!= TARGET_HALTED
)
1406 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
1410 /* one or more argument, access a single register (write if second argument is given */
1413 u32 opcode
= strtoul(args
[0], NULL
, 0);
1418 if ((retval
= arm920t_read_cp15_interpreted(target
, opcode
, 0x0, &value
)) != ERROR_OK
)
1420 command_print(cmd_ctx
, "couldn't execute %8.8x", opcode
);
1424 command_print(cmd_ctx
, "%8.8x: %8.8x", opcode
, value
);
1428 u32 value
= strtoul(args
[1], NULL
, 0);
1429 if ((retval
= arm920t_write_cp15_interpreted(target
, opcode
, value
, 0)) != ERROR_OK
)
1431 command_print(cmd_ctx
, "couldn't execute %8.8x", opcode
);
1434 command_print(cmd_ctx
, "%8.8x: %8.8x", opcode
, value
);
1438 u32 value
= strtoul(args
[1], NULL
, 0);
1439 u32 address
= strtoul(args
[2], NULL
, 0);
1440 if ((retval
= arm920t_write_cp15_interpreted(target
, opcode
, value
, address
)) != ERROR_OK
)
1442 command_print(cmd_ctx
, "couldn't execute %8.8x", opcode
);
1445 command_print(cmd_ctx
, "%8.8x: %8.8x %8.8x", opcode
, value
, address
);
1450 command_print(cmd_ctx
, "usage: arm920t cp15i <opcode> [value] [address]");
1456 int arm920t_handle_cache_info_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1458 target_t
*target
= get_current_target(cmd_ctx
);
1459 armv4_5_common_t
*armv4_5
;
1460 arm7_9_common_t
*arm7_9
;
1461 arm9tdmi_common_t
*arm9tdmi
;
1462 arm920t_common_t
*arm920t
;
1464 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
1466 command_print(cmd_ctx
, "current target isn't an ARM920t target");
1470 return armv4_5_handle_cache_info_command(cmd_ctx
, &arm920t
->armv4_5_mmu
.armv4_5_cache
);
1473 int arm920t_handle_virt2phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1475 target_t
*target
= get_current_target(cmd_ctx
);
1476 armv4_5_common_t
*armv4_5
;
1477 arm7_9_common_t
*arm7_9
;
1478 arm9tdmi_common_t
*arm9tdmi
;
1479 arm920t_common_t
*arm920t
;
1480 arm_jtag_t
*jtag_info
;
1482 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
1484 command_print(cmd_ctx
, "current target isn't an ARM920t target");
1488 jtag_info
= &arm7_9
->jtag_info
;
1490 if (target
->state
!= TARGET_HALTED
)
1492 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
1496 return armv4_5_mmu_handle_virt2phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm920t
->armv4_5_mmu
);
1499 int arm920t_handle_md_phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1501 target_t
*target
= get_current_target(cmd_ctx
);
1502 armv4_5_common_t
*armv4_5
;
1503 arm7_9_common_t
*arm7_9
;
1504 arm9tdmi_common_t
*arm9tdmi
;
1505 arm920t_common_t
*arm920t
;
1506 arm_jtag_t
*jtag_info
;
1508 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
1510 command_print(cmd_ctx
, "current target isn't an ARM920t target");
1514 jtag_info
= &arm7_9
->jtag_info
;
1516 if (target
->state
!= TARGET_HALTED
)
1518 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
1522 return armv4_5_mmu_handle_md_phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm920t
->armv4_5_mmu
);
1525 int arm920t_handle_mw_phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1527 target_t
*target
= get_current_target(cmd_ctx
);
1528 armv4_5_common_t
*armv4_5
;
1529 arm7_9_common_t
*arm7_9
;
1530 arm9tdmi_common_t
*arm9tdmi
;
1531 arm920t_common_t
*arm920t
;
1532 arm_jtag_t
*jtag_info
;
1534 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
1536 command_print(cmd_ctx
, "current target isn't an ARM920t target");
1540 jtag_info
= &arm7_9
->jtag_info
;
1542 if (target
->state
!= TARGET_HALTED
)
1544 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
1548 return armv4_5_mmu_handle_mw_phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm920t
->armv4_5_mmu
);
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)