1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
26 #include "arm7_9_common.h"
30 #include "embeddedice.h"
40 #define _DEBUG_INSTRUCTION_EXECUTION_
44 int arm7tdmi_register_commands(struct command_context_s
*cmd_ctx
);
46 /* forward declarations */
47 int arm7tdmi_target_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct target_s
*target
);
48 int arm7tdmi_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
);
51 /* target function declarations */
52 enum target_state
arm7tdmi_poll(struct target_s
*target
);
53 int arm7tdmi_halt(target_t
*target
);
55 target_type_t arm7tdmi_target
=
60 .arch_state
= armv4_5_arch_state
,
63 .resume
= arm7_9_resume
,
66 .assert_reset
= arm7_9_assert_reset
,
67 .deassert_reset
= arm7_9_deassert_reset
,
68 .soft_reset_halt
= arm7_9_soft_reset_halt
,
70 .get_gdb_reg_list
= armv4_5_get_gdb_reg_list
,
72 .read_memory
= arm7_9_read_memory
,
73 .write_memory
= arm7_9_write_memory
,
74 .bulk_write_memory
= arm7_9_bulk_write_memory
,
76 .run_algorithm
= armv4_5_run_algorithm
,
78 .add_breakpoint
= arm7_9_add_breakpoint
,
79 .remove_breakpoint
= arm7_9_remove_breakpoint
,
80 .add_watchpoint
= arm7_9_add_watchpoint
,
81 .remove_watchpoint
= arm7_9_remove_watchpoint
,
83 .register_commands
= arm7tdmi_register_commands
,
84 .target_command
= arm7tdmi_target_command
,
85 .init_target
= arm7tdmi_init_target
,
89 int arm7tdmi_examine_debug_reason(target_t
*target
)
91 /* get pointers to arch-specific information */
92 armv4_5_common_t
*armv4_5
= target
->arch_info
;
93 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
95 /* only check the debug reason if we don't know it already */
96 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
97 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
))
99 scan_field_t fields
[2];
103 jtag_add_end_state(TAP_PD
);
105 fields
[0].device
= arm7_9
->jtag_info
.chain_pos
;
106 fields
[0].num_bits
= 1;
107 fields
[0].out_value
= NULL
;
108 fields
[0].out_mask
= NULL
;
109 fields
[0].in_value
= &breakpoint
;
110 fields
[0].in_check_value
= NULL
;
111 fields
[0].in_check_mask
= NULL
;
112 fields
[0].in_handler
= NULL
;
113 fields
[0].in_handler_priv
= NULL
;
115 fields
[1].device
= arm7_9
->jtag_info
.chain_pos
;
116 fields
[1].num_bits
= 32;
117 fields
[1].out_value
= NULL
;
118 fields
[1].out_mask
= NULL
;
119 fields
[1].in_value
= databus
;
120 fields
[1].in_check_value
= NULL
;
121 fields
[1].in_check_mask
= NULL
;
122 fields
[1].in_handler
= NULL
;
123 fields
[1].in_handler_priv
= NULL
;
125 arm_jtag_scann(&arm7_9
->jtag_info
, 0x1);
126 arm_jtag_set_instr(&arm7_9
->jtag_info
, arm7_9
->jtag_info
.intest_instr
);
128 jtag_add_dr_scan(2, fields
, TAP_PD
);
129 jtag_execute_queue();
131 fields
[0].in_value
= NULL
;
132 fields
[0].out_value
= &breakpoint
;
133 fields
[1].in_value
= NULL
;
134 fields
[1].out_value
= databus
;
136 jtag_add_dr_scan(2, fields
, TAP_PD
);
139 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
141 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
147 /* put an instruction in the ARM7TDMI pipeline or write the data bus, and optionally read data */
148 int arm7tdmi_clock_out(arm_jtag_t
*jtag_info
, u32 out
, u32
*in
, int breakpoint
)
150 scan_field_t fields
[2];
154 buf_set_u32(out_buf
, 0, 32, flip_u32(out
, 32));
155 buf_set_u32(&breakpoint_buf
, 0, 1, breakpoint
);
157 jtag_add_end_state(TAP_PD
);
158 arm_jtag_scann(jtag_info
, 0x1);
159 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
);
161 fields
[0].device
= jtag_info
->chain_pos
;
162 fields
[0].num_bits
= 1;
163 fields
[0].out_value
= &breakpoint_buf
;
164 fields
[0].out_mask
= NULL
;
165 fields
[0].in_value
= NULL
;
166 fields
[0].in_check_value
= NULL
;
167 fields
[0].in_check_mask
= NULL
;
168 fields
[0].in_handler
= NULL
;
169 fields
[0].in_handler_priv
= NULL
;
171 fields
[1].device
= jtag_info
->chain_pos
;
172 fields
[1].num_bits
= 32;
173 fields
[1].out_value
= out_buf
;
174 fields
[1].out_mask
= NULL
;
175 fields
[1].in_value
= NULL
;
178 fields
[1].in_handler
= arm_jtag_buf_to_u32_flip
;
179 fields
[1].in_handler_priv
= in
;
183 fields
[1].in_handler
= NULL
;
184 fields
[1].in_handler_priv
= NULL
;
186 fields
[1].in_check_value
= NULL
;
187 fields
[1].in_check_mask
= NULL
;
189 jtag_add_dr_scan(2, fields
, -1);
191 jtag_add_runtest(0, -1);
193 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
195 jtag_execute_queue();
199 DEBUG("out: 0x%8.8x, in: 0x%8.8x", out
, *in
);
202 DEBUG("out: 0x%8.8x", out
);
209 /* clock the target, reading the databus */
210 int arm7tdmi_clock_data_in(arm_jtag_t
*jtag_info
, u32
*in
)
212 scan_field_t fields
[2];
214 jtag_add_end_state(TAP_PD
);
215 arm_jtag_scann(jtag_info
, 0x1);
216 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
);
218 fields
[0].device
= jtag_info
->chain_pos
;
219 fields
[0].num_bits
= 1;
220 fields
[0].out_value
= NULL
;
221 fields
[0].out_mask
= NULL
;
222 fields
[0].in_value
= NULL
;
223 fields
[0].in_check_value
= NULL
;
224 fields
[0].in_check_mask
= NULL
;
225 fields
[0].in_handler
= NULL
;
226 fields
[0].in_handler_priv
= NULL
;
228 fields
[1].device
= jtag_info
->chain_pos
;
229 fields
[1].num_bits
= 32;
230 fields
[1].out_value
= NULL
;
231 fields
[1].out_mask
= NULL
;
232 fields
[1].in_value
= NULL
;
233 fields
[1].in_handler
= arm_jtag_buf_to_u32_flip
;
234 fields
[1].in_handler_priv
= in
;
235 fields
[1].in_check_value
= NULL
;
236 fields
[1].in_check_mask
= NULL
;
238 jtag_add_dr_scan(2, fields
, -1);
240 jtag_add_runtest(0, -1);
242 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
244 jtag_execute_queue();
248 DEBUG("in: 0x%8.8x", *in
);
252 ERROR("BUG: called with in == NULL");
260 /* clock the target, and read the databus
261 * the *in pointer points to a buffer where elements of 'size' bytes
262 * are stored in big (be==1) or little (be==0) endianness
264 int arm7tdmi_clock_data_in_endianness(arm_jtag_t
*jtag_info
, void *in
, int size
, int be
)
266 scan_field_t fields
[2];
268 jtag_add_end_state(TAP_PD
);
269 arm_jtag_scann(jtag_info
, 0x1);
270 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
);
272 fields
[0].device
= jtag_info
->chain_pos
;
273 fields
[0].num_bits
= 1;
274 fields
[0].out_value
= NULL
;
275 fields
[0].out_mask
= NULL
;
276 fields
[0].in_value
= NULL
;
277 fields
[0].in_check_value
= NULL
;
278 fields
[0].in_check_mask
= NULL
;
279 fields
[0].in_handler
= NULL
;
280 fields
[0].in_handler_priv
= NULL
;
282 fields
[1].device
= jtag_info
->chain_pos
;
283 fields
[1].num_bits
= 32;
284 fields
[1].out_value
= NULL
;
285 fields
[1].out_mask
= NULL
;
286 fields
[1].in_value
= NULL
;
290 fields
[1].in_handler
= (be
) ? arm_jtag_buf_to_be32_flip
: arm_jtag_buf_to_le32_flip
;
293 fields
[1].in_handler
= (be
) ? arm_jtag_buf_to_be16_flip
: arm_jtag_buf_to_le16_flip
;
296 fields
[1].in_handler
= arm_jtag_buf_to_8_flip
;
299 fields
[1].in_handler_priv
= in
;
300 fields
[1].in_check_value
= NULL
;
301 fields
[1].in_check_mask
= NULL
;
303 jtag_add_dr_scan(2, fields
, -1);
305 jtag_add_runtest(0, -1);
307 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
309 jtag_execute_queue();
313 DEBUG("in: 0x%8.8x", *in
);
317 ERROR("BUG: called with in == NULL");
325 void arm7tdmi_change_to_arm(target_t
*target
, u32
*r0
, u32
*pc
)
327 /* get pointers to arch-specific information */
328 armv4_5_common_t
*armv4_5
= target
->arch_info
;
329 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
330 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
332 /* save r0 before using it and put system in ARM state
333 * to allow common handling of ARM and THUMB debugging */
335 /* fetch STR r0, [r0] */
336 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_STR(0, 0), NULL
, 0);
337 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
338 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
339 /* nothing fetched, STR r0, [r0] in Execute (2) */
340 arm7tdmi_clock_data_in(jtag_info
, r0
);
342 /* MOV r0, r15 fetched, STR in Decode */
343 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_MOV(0, 15), NULL
, 0);
344 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_STR(0, 0), NULL
, 0);
345 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
346 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
347 /* nothing fetched, STR r0, [r0] in Execute (2) */
348 arm7tdmi_clock_data_in(jtag_info
, pc
);
350 /* use pc-relative LDR to clear r0[1:0] (for switch to ARM mode) */
351 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_LDR_PCREL(0), NULL
, 0);
352 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
353 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
354 /* nothing fetched, data for LDR r0, [PC, #0] */
355 arm7tdmi_clock_out(jtag_info
, 0x0, NULL
, 0);
356 /* nothing fetched, data from previous cycle is written to register */
357 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
360 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_BX(0), NULL
, 0);
361 /* NOP fetched, BX in Decode, MOV in Execute */
362 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
363 /* NOP fetched, BX in Execute (1) */
364 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
366 jtag_execute_queue();
368 /* fix program counter:
369 * MOV r0, r15 was the 4th instruction (+6)
370 * reading PC in Thumb state gives address of instruction + 4
376 void arm7tdmi_read_core_regs(target_t
*target
, u32 mask
, u32
* core_regs
[16])
379 /* get pointers to arch-specific information */
380 armv4_5_common_t
*armv4_5
= target
->arch_info
;
381 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
382 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
384 /* STMIA r0-15, [r0] at debug speed
385 * register values will start to appear on 4th DCLK
387 arm7tdmi_clock_out(jtag_info
, ARMV4_5_STMIA(0, mask
& 0xffff, 0, 0), NULL
, 0);
389 /* fetch NOP, STM in DECODE stage */
390 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
391 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
392 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
394 for (i
= 0; i
<= 15; i
++)
397 /* nothing fetched, STM still in EXECUTE (1+i cycle) */
398 arm7tdmi_clock_data_in(jtag_info
, core_regs
[i
]);
403 void arm7tdmi_read_core_regs_target_buffer(target_t
*target
, u32 mask
, void* buffer
, int size
)
406 /* get pointers to arch-specific information */
407 armv4_5_common_t
*armv4_5
= target
->arch_info
;
408 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
409 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
410 int be
= (target
->endianness
== TARGET_BIG_ENDIAN
) ? 1 : 0;
411 u32
*buf_u32
= buffer
;
412 u16
*buf_u16
= buffer
;
415 /* STMIA r0-15, [r0] at debug speed
416 * register values will start to appear on 4th DCLK
418 arm7tdmi_clock_out(jtag_info
, ARMV4_5_STMIA(0, mask
& 0xffff, 0, 0), NULL
, 0);
420 /* fetch NOP, STM in DECODE stage */
421 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
422 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
423 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
425 for (i
= 0; i
<= 15; i
++)
427 /* nothing fetched, STM still in EXECUTE (1+i cycle), read databus */
433 arm7tdmi_clock_data_in_endianness(jtag_info
, buf_u32
++, 4, be
);
436 arm7tdmi_clock_data_in_endianness(jtag_info
, buf_u16
++, 2, be
);
439 arm7tdmi_clock_data_in_endianness(jtag_info
, buf_u8
++, 1, be
);
447 void arm7tdmi_read_xpsr(target_t
*target
, u32
*xpsr
, int spsr
)
449 /* get pointers to arch-specific information */
450 armv4_5_common_t
*armv4_5
= target
->arch_info
;
451 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
452 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
455 arm7tdmi_clock_out(jtag_info
, ARMV4_5_MRS(0, spsr
& 1), NULL
, 0);
458 arm7tdmi_clock_out(jtag_info
, ARMV4_5_STR(0, 15), NULL
, 0);
459 /* fetch NOP, STR in DECODE stage */
460 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
461 /* fetch NOP, STR in EXECUTE stage (1st cycle) */
462 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
463 /* nothing fetched, STR still in EXECUTE (2nd cycle) */
464 arm7tdmi_clock_data_in(jtag_info
, xpsr
);
468 void arm7tdmi_write_xpsr(target_t
*target
, u32 xpsr
, int spsr
)
470 /* get pointers to arch-specific information */
471 armv4_5_common_t
*armv4_5
= target
->arch_info
;
472 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
473 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
475 DEBUG("xpsr: %8.8x, spsr: %i", xpsr
, spsr
);
478 arm7tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM(xpsr
& 0xff, 0, 1, spsr
), NULL
, 0);
479 /* MSR2 fetched, MSR1 in DECODE */
480 arm7tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM((xpsr
& 0xff00) >> 8, 0xc, 2, spsr
), NULL
, 0);
481 /* MSR3 fetched, MSR1 in EXECUTE (1), MSR2 in DECODE */
482 arm7tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM((xpsr
& 0xff0000) >> 16, 0x8, 4, spsr
), NULL
, 0);
483 /* nothing fetched, MSR1 in EXECUTE (2) */
484 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
485 /* MSR4 fetched, MSR2 in EXECUTE (1), MSR3 in DECODE */
486 arm7tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM((xpsr
& 0xff000000) >> 24, 0x4, 8, spsr
), NULL
, 0);
487 /* nothing fetched, MSR2 in EXECUTE (2) */
488 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
489 /* NOP fetched, MSR3 in EXECUTE (1), MSR4 in DECODE */
490 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
491 /* nothing fetched, MSR3 in EXECUTE (2) */
492 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
493 /* NOP fetched, MSR4 in EXECUTE (1) */
494 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
495 /* nothing fetched, MSR4 in EXECUTE (2) */
496 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
499 void arm7tdmi_write_xpsr_im8(target_t
*target
, u8 xpsr_im
, int rot
, int spsr
)
501 /* get pointers to arch-specific information */
502 armv4_5_common_t
*armv4_5
= target
->arch_info
;
503 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
504 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
506 DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im
, rot
, spsr
);
509 arm7tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM(xpsr_im
, rot
, 1, spsr
), NULL
, 0);
510 /* NOP fetched, MSR in DECODE */
511 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
512 /* NOP fetched, MSR in EXECUTE (1) */
513 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
514 /* nothing fetched, MSR in EXECUTE (2) */
515 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
519 void arm7tdmi_write_core_regs(target_t
*target
, u32 mask
, u32 core_regs
[16])
522 /* get pointers to arch-specific information */
523 armv4_5_common_t
*armv4_5
= target
->arch_info
;
524 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
525 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
527 /* LDMIA r0-15, [r0] at debug speed
528 * register values will start to appear on 4th DCLK
530 arm7tdmi_clock_out(jtag_info
, ARMV4_5_LDMIA(0, mask
& 0xffff, 0, 0), NULL
, 0);
532 /* fetch NOP, LDM in DECODE stage */
533 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
534 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
535 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
537 for (i
= 0; i
<= 15; i
++)
540 /* nothing fetched, LDM still in EXECUTE (1+i cycle) */
541 arm7tdmi_clock_out(jtag_info
, core_regs
[i
], NULL
, 0);
543 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
547 void arm7tdmi_load_word_regs(target_t
*target
, u32 mask
)
549 /* get pointers to arch-specific information */
550 armv4_5_common_t
*armv4_5
= target
->arch_info
;
551 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
552 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
554 /* put system-speed load-multiple into the pipeline */
555 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
556 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 1);
557 arm7tdmi_clock_out(jtag_info
, ARMV4_5_LDMIA(0, mask
& 0xffff, 0, 1), NULL
, 0);
561 void arm7tdmi_load_hword_reg(target_t
*target
, int num
)
563 /* get pointers to arch-specific information */
564 armv4_5_common_t
*armv4_5
= target
->arch_info
;
565 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
566 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
568 /* put system-speed load half-word into the pipeline */
569 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
570 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 1);
571 arm7tdmi_clock_out(jtag_info
, ARMV4_5_LDRH_IP(num
, 0), NULL
, 0);
575 void arm7tdmi_load_byte_reg(target_t
*target
, int num
)
577 /* get pointers to arch-specific information */
578 armv4_5_common_t
*armv4_5
= target
->arch_info
;
579 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
580 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
582 /* put system-speed load byte into the pipeline */
583 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
584 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 1);
585 arm7tdmi_clock_out(jtag_info
, ARMV4_5_LDRB_IP(num
, 0), NULL
, 0);
589 void arm7tdmi_store_word_regs(target_t
*target
, u32 mask
)
591 /* get pointers to arch-specific information */
592 armv4_5_common_t
*armv4_5
= target
->arch_info
;
593 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
594 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
596 /* put system-speed store-multiple into the pipeline */
597 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
598 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 1);
599 arm7tdmi_clock_out(jtag_info
, ARMV4_5_STMIA(0, mask
, 0, 1), NULL
, 0);
603 void arm7tdmi_store_hword_reg(target_t
*target
, int num
)
605 /* get pointers to arch-specific information */
606 armv4_5_common_t
*armv4_5
= target
->arch_info
;
607 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
608 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
610 /* put system-speed store half-word into the pipeline */
611 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
612 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 1);
613 arm7tdmi_clock_out(jtag_info
, ARMV4_5_STRH_IP(num
, 0), NULL
, 0);
617 void arm7tdmi_store_byte_reg(target_t
*target
, int num
)
619 /* get pointers to arch-specific information */
620 armv4_5_common_t
*armv4_5
= target
->arch_info
;
621 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
622 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
624 /* put system-speed store byte into the pipeline */
625 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
626 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 1);
627 arm7tdmi_clock_out(jtag_info
, ARMV4_5_STRB_IP(num
, 0), NULL
, 0);
631 void arm7tdmi_write_pc(target_t
*target
, u32 pc
)
633 /* get pointers to arch-specific information */
634 armv4_5_common_t
*armv4_5
= target
->arch_info
;
635 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
636 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
638 /* LDMIA r0-15, [r0] at debug speed
639 * register values will start to appear on 4th DCLK
641 arm7tdmi_clock_out(jtag_info
, ARMV4_5_LDMIA(0, 0x8000, 0, 0), NULL
, 0);
642 /* fetch NOP, LDM in DECODE stage */
643 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
644 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
645 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
646 /* nothing fetched, LDM in EXECUTE stage (1st cycle) load register */
647 arm7tdmi_clock_out(jtag_info
, pc
, NULL
, 0);
648 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) load register */
649 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
650 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) load register */
651 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
652 /* fetch NOP, LDM in EXECUTE stage (4th cycle) */
653 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
654 /* fetch NOP, LDM in EXECUTE stage (5th cycle) */
655 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
658 void arm7tdmi_branch_resume(target_t
*target
)
660 /* get pointers to arch-specific information */
661 armv4_5_common_t
*armv4_5
= target
->arch_info
;
662 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
663 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
665 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 1);
666 arm7tdmi_clock_out(jtag_info
, ARMV4_5_B(0xfffffa, 0), NULL
, 0);
670 void arm7tdmi_branch_resume_thumb(target_t
*target
)
674 /* get pointers to arch-specific information */
675 armv4_5_common_t
*armv4_5
= target
->arch_info
;
676 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
677 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
678 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
680 /* LDMIA r0, [r0] at debug speed
681 * register values will start to appear on 4th DCLK
683 arm7tdmi_clock_out(jtag_info
, ARMV4_5_LDMIA(0, 0x1, 0, 0), NULL
, 0);
685 /* fetch NOP, LDM in DECODE stage */
686 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
687 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
688 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
689 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) */
690 arm7tdmi_clock_out(jtag_info
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32) | 1, NULL
, 0);
691 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
692 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
694 /* Branch and eXchange */
695 arm7tdmi_clock_out(jtag_info
, ARMV4_5_BX(0), NULL
, 0);
697 embeddedice_read_reg(dbg_stat
);
699 /* fetch NOP, BX in DECODE stage */
700 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
702 /* target is now in Thumb state */
703 embeddedice_read_reg(dbg_stat
);
705 /* fetch NOP, BX in EXECUTE stage (1st cycle) */
706 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
708 /* target is now in Thumb state */
709 embeddedice_read_reg(dbg_stat
);
712 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_LDR_PCREL(0), NULL
, 0);
713 /* fetch NOP, LDR in Decode */
714 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
715 /* fetch NOP, LDR in Execute */
716 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
717 /* nothing fetched, LDR in EXECUTE stage (2nd cycle) */
718 arm7tdmi_clock_out(jtag_info
, buf_get_u32(armv4_5
->core_cache
->reg_list
[0].value
, 0, 32), NULL
, 0);
719 /* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
720 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
722 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
723 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
725 embeddedice_read_reg(dbg_stat
);
727 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 1);
728 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_B(0x7f8), NULL
, 0);
732 void arm7tdmi_build_reg_cache(target_t
*target
)
734 reg_cache_t
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
735 /* get pointers to arch-specific information */
736 armv4_5_common_t
*armv4_5
= target
->arch_info
;
737 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
738 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
740 (*cache_p
) = armv4_5_build_reg_cache(target
, armv4_5
);
741 armv4_5
->core_cache
= (*cache_p
);
743 (*cache_p
)->next
= embeddedice_build_reg_cache(target
, arm7_9
);
744 arm7_9
->eice_cache
= (*cache_p
)->next
;
748 (*cache_p
)->next
->next
= etm_build_reg_cache(target
, jtag_info
, 0);
749 arm7_9
->etm_cache
= (*cache_p
)->next
->next
;
753 int arm7tdmi_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
756 arm7tdmi_build_reg_cache(target
);
768 int arm7tdmi_init_arch_info(target_t
*target
, arm7tdmi_common_t
*arm7tdmi
, int chain_pos
, char *variant
)
770 armv4_5_common_t
*armv4_5
;
771 arm7_9_common_t
*arm7_9
;
773 arm7_9
= &arm7tdmi
->arm7_9_common
;
774 armv4_5
= &arm7_9
->armv4_5_common
;
776 /* prepare JTAG information for the new target */
777 arm7_9
->jtag_info
.chain_pos
= chain_pos
;
778 arm7_9
->jtag_info
.scann_size
= 4;
780 /* register arch-specific functions */
781 arm7_9
->examine_debug_reason
= arm7tdmi_examine_debug_reason
;
782 arm7_9
->change_to_arm
= arm7tdmi_change_to_arm
;
783 arm7_9
->read_core_regs
= arm7tdmi_read_core_regs
;
784 arm7_9
->read_core_regs_target_buffer
= arm7tdmi_read_core_regs_target_buffer
;
785 arm7_9
->read_xpsr
= arm7tdmi_read_xpsr
;
787 arm7_9
->write_xpsr
= arm7tdmi_write_xpsr
;
788 arm7_9
->write_xpsr_im8
= arm7tdmi_write_xpsr_im8
;
789 arm7_9
->write_core_regs
= arm7tdmi_write_core_regs
;
791 arm7_9
->load_word_regs
= arm7tdmi_load_word_regs
;
792 arm7_9
->load_hword_reg
= arm7tdmi_load_hword_reg
;
793 arm7_9
->load_byte_reg
= arm7tdmi_load_byte_reg
;
795 arm7_9
->store_word_regs
= arm7tdmi_store_word_regs
;
796 arm7_9
->store_hword_reg
= arm7tdmi_store_hword_reg
;
797 arm7_9
->store_byte_reg
= arm7tdmi_store_byte_reg
;
799 arm7_9
->write_pc
= arm7tdmi_write_pc
;
800 arm7_9
->branch_resume
= arm7tdmi_branch_resume
;
801 arm7_9
->branch_resume_thumb
= arm7tdmi_branch_resume_thumb
;
803 arm7_9
->enable_single_step
= arm7_9_enable_eice_step
;
804 arm7_9
->disable_single_step
= arm7_9_disable_eice_step
;
806 arm7_9
->pre_debug_entry
= NULL
;
807 arm7_9
->post_debug_entry
= NULL
;
809 arm7_9
->pre_restore_context
= NULL
;
810 arm7_9
->post_restore_context
= NULL
;
812 /* initialize arch-specific breakpoint handling */
813 buf_set_u32((u8
*)(&arm7_9
->arm_bkpt
), 0, 32, 0xdeeedeee);
814 buf_set_u32((u8
*)(&arm7_9
->thumb_bkpt
), 0, 16, 0xdeee);
816 arm7_9
->sw_bkpts_use_wp
= 1;
817 arm7_9
->sw_bkpts_enabled
= 0;
818 arm7_9
->dbgreq_adjust_pc
= 2;
819 arm7_9
->arch_info
= arm7tdmi
;
821 arm7tdmi
->arch_info
= NULL
;
822 arm7tdmi
->common_magic
= ARM7TDMI_COMMON_MAGIC
;
826 arm7tdmi
->variant
= strdup(variant
);
830 arm7tdmi
->variant
= strdup("");
833 arm7_9_init_arch_info(target
, arm7_9
);
838 /* target arm7tdmi <endianess> <startup_mode> <chain_pos> <variant> */
839 int arm7tdmi_target_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct target_s
*target
)
842 char *variant
= NULL
;
843 arm7tdmi_common_t
*arm7tdmi
= malloc(sizeof(arm7tdmi_common_t
));
847 ERROR("'target arm7tdmi' requires at least one additional argument");
851 chain_pos
= strtoul(args
[3], NULL
, 0);
856 arm7tdmi_init_arch_info(target
, arm7tdmi
, chain_pos
, variant
);
861 int arm7tdmi_register_commands(struct command_context_s
*cmd_ctx
)
865 retval
= arm7_9_register_commands(cmd_ctx
);
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