1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2007,2008 Øyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
32 #include "arm7_9_common.h"
36 #include "embeddedice.h"
46 #define _DEBUG_INSTRUCTION_EXECUTION_
49 /* forward declarations */
51 int arm7tdmi_target_create(struct target_s
*target
,Jim_Interp
*interp
);
52 int arm7tdmi_quit(void);
54 /* target function declarations */
55 int arm7tdmi_poll(struct target_s
*target
);
56 int arm7tdmi_halt(target_t
*target
);
58 target_type_t arm7tdmi_target
=
63 .arch_state
= armv4_5_arch_state
,
65 .target_request_data
= arm7_9_target_request_data
,
68 .resume
= arm7_9_resume
,
71 .assert_reset
= arm7_9_assert_reset
,
72 .deassert_reset
= arm7_9_deassert_reset
,
73 .soft_reset_halt
= arm7_9_soft_reset_halt
,
75 .get_gdb_reg_list
= armv4_5_get_gdb_reg_list
,
77 .read_memory
= arm7_9_read_memory
,
78 .write_memory
= arm7_9_write_memory
,
79 .bulk_write_memory
= arm7_9_bulk_write_memory
,
80 .checksum_memory
= arm7_9_checksum_memory
,
81 .blank_check_memory
= arm7_9_blank_check_memory
,
83 .run_algorithm
= armv4_5_run_algorithm
,
85 .add_breakpoint
= arm7_9_add_breakpoint
,
86 .remove_breakpoint
= arm7_9_remove_breakpoint
,
87 .add_watchpoint
= arm7_9_add_watchpoint
,
88 .remove_watchpoint
= arm7_9_remove_watchpoint
,
90 .register_commands
= arm7tdmi_register_commands
,
91 .target_create
= arm7tdmi_target_create
,
92 .init_target
= arm7tdmi_init_target
,
93 .examine
= arm7tdmi_examine
,
97 int arm7tdmi_examine_debug_reason(target_t
*target
)
99 int retval
= ERROR_OK
;
100 /* get pointers to arch-specific information */
101 armv4_5_common_t
*armv4_5
= target
->arch_info
;
102 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
104 /* only check the debug reason if we don't know it already */
105 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
106 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
))
108 scan_field_t fields
[2];
112 jtag_add_end_state(TAP_DRPAUSE
);
114 fields
[0].tap
= arm7_9
->jtag_info
.tap
;
115 fields
[0].num_bits
= 1;
116 fields
[0].out_value
= NULL
;
117 fields
[0].in_value
= &breakpoint
;
119 fields
[1].tap
= arm7_9
->jtag_info
.tap
;
120 fields
[1].num_bits
= 32;
121 fields
[1].out_value
= NULL
;
122 fields
[1].in_value
= databus
;
124 if((retval
= arm_jtag_scann(&arm7_9
->jtag_info
, 0x1)) != ERROR_OK
)
128 arm_jtag_set_instr(&arm7_9
->jtag_info
, arm7_9
->jtag_info
.intest_instr
, NULL
);
130 jtag_add_dr_scan(2, fields
, TAP_DRPAUSE
);
131 if((retval
= jtag_execute_queue()) != ERROR_OK
)
136 fields
[0].in_value
= NULL
;
137 fields
[0].out_value
= &breakpoint
;
138 fields
[1].in_value
= NULL
;
139 fields
[1].out_value
= databus
;
141 jtag_add_dr_scan(2, fields
, TAP_DRPAUSE
);
144 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
146 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
152 static int arm7tdmi_num_bits
[]={1, 32};
153 static __inline
int arm7tdmi_clock_out_inner(arm_jtag_t
*jtag_info
, u32 out
, int breakpoint
)
155 u32 values
[2]={breakpoint
, flip_u32(out
, 32)};
157 jtag_add_dr_out(jtag_info
->tap
,
163 jtag_add_runtest(0, TAP_INVALID
);
168 /* put an instruction in the ARM7TDMI pipeline or write the data bus, and optionally read data */
169 static __inline
int arm7tdmi_clock_out(arm_jtag_t
*jtag_info
, u32 out
, u32
*deprecated
, int breakpoint
)
171 jtag_add_end_state(TAP_DRPAUSE
);
172 arm_jtag_scann(jtag_info
, 0x1);
173 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
175 return arm7tdmi_clock_out_inner(jtag_info
, out
, breakpoint
);
178 /* clock the target, reading the databus */
179 int arm7tdmi_clock_data_in(arm_jtag_t
*jtag_info
, u32
*in
)
181 int retval
= ERROR_OK
;
182 scan_field_t fields
[2];
184 jtag_add_end_state(TAP_DRPAUSE
);
185 if((retval
= arm_jtag_scann(jtag_info
, 0x1)) != ERROR_OK
)
189 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
191 fields
[0].tap
= jtag_info
->tap
;
192 fields
[0].num_bits
= 1;
193 fields
[0].out_value
= NULL
;
194 fields
[0].in_value
= NULL
;
196 fields
[1].tap
= jtag_info
->tap
;
197 fields
[1].num_bits
= 32;
198 fields
[1].out_value
= NULL
;
200 fields
[1].in_value
= tmp
;
202 jtag_add_dr_scan_now(2, fields
, TAP_INVALID
);
204 if (jtag_error
==ERROR_OK
)
206 *in
=flip_u32(le_to_h_u32(tmp
), 32);
209 jtag_add_runtest(0, TAP_INVALID
);
211 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
213 if((retval
= jtag_execute_queue()) != ERROR_OK
)
220 LOG_DEBUG("in: 0x%8.8x", *in
);
224 LOG_ERROR("BUG: called with in == NULL");
232 void arm_endianness(u8
*tmp
, void *in
, int size
, int be
, int flip
)
234 u32 readback
=le_to_h_u32(tmp
);
236 readback
=flip_u32(readback
, 32);
242 h_u32_to_be(((u8
*)in
), readback
);
245 h_u32_to_le(((u8
*)in
), readback
);
251 h_u16_to_be(((u8
*)in
), readback
& 0xffff);
254 h_u16_to_le(((u8
*)in
), readback
& 0xffff);
258 *((u8
*)in
)= readback
& 0xff;
264 /* clock the target, and read the databus
265 * the *in pointer points to a buffer where elements of 'size' bytes
266 * are stored in big (be==1) or little (be==0) endianness
268 int arm7tdmi_clock_data_in_endianness(arm_jtag_t
*jtag_info
, void *in
, int size
, int be
)
270 int retval
= ERROR_OK
;
271 scan_field_t fields
[2];
273 jtag_add_end_state(TAP_DRPAUSE
);
274 if((retval
= arm_jtag_scann(jtag_info
, 0x1)) != ERROR_OK
)
278 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
280 fields
[0].tap
= jtag_info
->tap
;
281 fields
[0].num_bits
= 1;
282 fields
[0].out_value
= NULL
;
283 fields
[0].in_value
= NULL
;
285 fields
[1].tap
= jtag_info
->tap
;
286 fields
[1].num_bits
= 32;
287 fields
[1].out_value
= NULL
;
289 fields
[1].in_value
= tmp
;
291 jtag_add_dr_scan_now(2, fields
, TAP_INVALID
);
293 arm_endianness(tmp
, in
, size
, be
, 1);
295 jtag_add_runtest(0, TAP_INVALID
);
297 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
299 if((retval
= jtag_execute_queue()) != ERROR_OK
)
306 LOG_DEBUG("in: 0x%8.8x", *(u32
*)in
);
310 LOG_ERROR("BUG: called with in == NULL");
318 void arm7tdmi_change_to_arm(target_t
*target
, u32
*r0
, u32
*pc
)
320 /* get pointers to arch-specific information */
321 armv4_5_common_t
*armv4_5
= target
->arch_info
;
322 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
323 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
325 /* save r0 before using it and put system in ARM state
326 * to allow common handling of ARM and THUMB debugging */
328 /* fetch STR r0, [r0] */
329 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_STR(0, 0), NULL
, 0);
330 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
331 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
332 /* nothing fetched, STR r0, [r0] in Execute (2) */
333 arm7tdmi_clock_data_in(jtag_info
, r0
);
335 /* MOV r0, r15 fetched, STR in Decode */
336 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_MOV(0, 15), NULL
, 0);
337 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_STR(0, 0), NULL
, 0);
338 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
339 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
340 /* nothing fetched, STR r0, [r0] in Execute (2) */
341 arm7tdmi_clock_data_in(jtag_info
, pc
);
343 /* use pc-relative LDR to clear r0[1:0] (for switch to ARM mode) */
344 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_LDR_PCREL(0), NULL
, 0);
345 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
346 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
347 /* nothing fetched, data for LDR r0, [PC, #0] */
348 arm7tdmi_clock_out(jtag_info
, 0x0, NULL
, 0);
349 /* nothing fetched, data from previous cycle is written to register */
350 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
353 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_BX(0), NULL
, 0);
354 /* NOP fetched, BX in Decode, MOV in Execute */
355 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
356 /* NOP fetched, BX in Execute (1) */
357 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
359 jtag_execute_queue();
361 /* fix program counter:
362 * MOV r0, r15 was the 4th instruction (+6)
363 * reading PC in Thumb state gives address of instruction + 4
369 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
370 * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
372 * The solution is to arrange for a large out/in scan in this loop and
373 * and convert data afterwards.
375 void arm7tdmi_read_core_regs(target_t
*target
, u32 mask
, u32
* core_regs
[16])
378 /* get pointers to arch-specific information */
379 armv4_5_common_t
*armv4_5
= target
->arch_info
;
380 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
381 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
383 /* STMIA r0-15, [r0] at debug speed
384 * register values will start to appear on 4th DCLK
386 arm7tdmi_clock_out(jtag_info
, ARMV4_5_STMIA(0, mask
& 0xffff, 0, 0), NULL
, 0);
388 /* fetch NOP, STM in DECODE stage */
389 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
390 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
391 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
393 for (i
= 0; i
<= 15; i
++)
396 /* nothing fetched, STM still in EXECUTE (1+i cycle) */
397 arm7tdmi_clock_data_in(jtag_info
, core_regs
[i
]);
401 void arm7tdmi_read_core_regs_target_buffer(target_t
*target
, u32 mask
, void* buffer
, int size
)
404 /* get pointers to arch-specific information */
405 armv4_5_common_t
*armv4_5
= target
->arch_info
;
406 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
407 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
408 int be
= (target
->endianness
== TARGET_BIG_ENDIAN
) ? 1 : 0;
409 u32
*buf_u32
= buffer
;
410 u16
*buf_u16
= buffer
;
413 /* STMIA r0-15, [r0] at debug speed
414 * register values will start to appear on 4th DCLK
416 arm7tdmi_clock_out(jtag_info
, ARMV4_5_STMIA(0, mask
& 0xffff, 0, 0), NULL
, 0);
418 /* fetch NOP, STM in DECODE stage */
419 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
420 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
421 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
423 for (i
= 0; i
<= 15; i
++)
425 /* nothing fetched, STM still in EXECUTE (1+i cycle), read databus */
431 arm7tdmi_clock_data_in_endianness(jtag_info
, buf_u32
++, 4, be
);
434 arm7tdmi_clock_data_in_endianness(jtag_info
, buf_u16
++, 2, be
);
437 arm7tdmi_clock_data_in_endianness(jtag_info
, buf_u8
++, 1, be
);
444 void arm7tdmi_read_xpsr(target_t
*target
, u32
*xpsr
, int spsr
)
446 /* get pointers to arch-specific information */
447 armv4_5_common_t
*armv4_5
= target
->arch_info
;
448 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
449 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
452 arm7tdmi_clock_out(jtag_info
, ARMV4_5_MRS(0, spsr
& 1), NULL
, 0);
455 arm7tdmi_clock_out(jtag_info
, ARMV4_5_STR(0, 15), NULL
, 0);
456 /* fetch NOP, STR in DECODE stage */
457 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
458 /* fetch NOP, STR in EXECUTE stage (1st cycle) */
459 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
460 /* nothing fetched, STR still in EXECUTE (2nd cycle) */
461 arm7tdmi_clock_data_in(jtag_info
, xpsr
);
464 void arm7tdmi_write_xpsr(target_t
*target
, u32 xpsr
, int spsr
)
466 /* get pointers to arch-specific information */
467 armv4_5_common_t
*armv4_5
= target
->arch_info
;
468 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
469 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
471 LOG_DEBUG("xpsr: %8.8x, spsr: %i", xpsr
, spsr
);
474 arm7tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM(xpsr
& 0xff, 0, 1, spsr
), NULL
, 0);
475 /* MSR2 fetched, MSR1 in DECODE */
476 arm7tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM((xpsr
& 0xff00) >> 8, 0xc, 2, spsr
), NULL
, 0);
477 /* MSR3 fetched, MSR1 in EXECUTE (1), MSR2 in DECODE */
478 arm7tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM((xpsr
& 0xff0000) >> 16, 0x8, 4, spsr
), NULL
, 0);
479 /* nothing fetched, MSR1 in EXECUTE (2) */
480 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
481 /* MSR4 fetched, MSR2 in EXECUTE (1), MSR3 in DECODE */
482 arm7tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM((xpsr
& 0xff000000) >> 24, 0x4, 8, spsr
), NULL
, 0);
483 /* nothing fetched, MSR2 in EXECUTE (2) */
484 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
485 /* NOP fetched, MSR3 in EXECUTE (1), MSR4 in DECODE */
486 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
487 /* nothing fetched, MSR3 in EXECUTE (2) */
488 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
489 /* NOP fetched, MSR4 in EXECUTE (1) */
490 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
491 /* nothing fetched, MSR4 in EXECUTE (2) */
492 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
495 void arm7tdmi_write_xpsr_im8(target_t
*target
, u8 xpsr_im
, int rot
, int spsr
)
497 /* get pointers to arch-specific information */
498 armv4_5_common_t
*armv4_5
= target
->arch_info
;
499 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
500 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
502 LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im
, rot
, spsr
);
505 arm7tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM(xpsr_im
, rot
, 1, spsr
), NULL
, 0);
506 /* NOP fetched, MSR in DECODE */
507 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
508 /* NOP fetched, MSR in EXECUTE (1) */
509 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
510 /* nothing fetched, MSR in EXECUTE (2) */
511 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
514 void arm7tdmi_write_core_regs(target_t
*target
, u32 mask
, u32 core_regs
[16])
517 /* get pointers to arch-specific information */
518 armv4_5_common_t
*armv4_5
= target
->arch_info
;
519 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
520 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
522 /* LDMIA r0-15, [r0] at debug speed
523 * register values will start to appear on 4th DCLK
525 arm7tdmi_clock_out(jtag_info
, ARMV4_5_LDMIA(0, mask
& 0xffff, 0, 0), NULL
, 0);
527 /* fetch NOP, LDM in DECODE stage */
528 arm7tdmi_clock_out_inner(jtag_info
, ARMV4_5_NOP
, 0);
529 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
530 arm7tdmi_clock_out_inner(jtag_info
, ARMV4_5_NOP
, 0);
532 for (i
= 0; i
<= 15; i
++)
535 /* nothing fetched, LDM still in EXECUTE (1+i cycle) */
536 arm7tdmi_clock_out_inner(jtag_info
, core_regs
[i
], 0);
538 arm7tdmi_clock_out_inner(jtag_info
, ARMV4_5_NOP
, 0);
541 void arm7tdmi_load_word_regs(target_t
*target
, u32 mask
)
543 /* get pointers to arch-specific information */
544 armv4_5_common_t
*armv4_5
= target
->arch_info
;
545 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
546 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
548 /* put system-speed load-multiple into the pipeline */
549 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
550 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 1);
551 arm7tdmi_clock_out(jtag_info
, ARMV4_5_LDMIA(0, mask
& 0xffff, 0, 1), NULL
, 0);
554 void arm7tdmi_load_hword_reg(target_t
*target
, int num
)
556 /* get pointers to arch-specific information */
557 armv4_5_common_t
*armv4_5
= target
->arch_info
;
558 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
559 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
561 /* put system-speed load half-word into the pipeline */
562 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
563 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 1);
564 arm7tdmi_clock_out(jtag_info
, ARMV4_5_LDRH_IP(num
, 0), NULL
, 0);
567 void arm7tdmi_load_byte_reg(target_t
*target
, int num
)
569 /* get pointers to arch-specific information */
570 armv4_5_common_t
*armv4_5
= target
->arch_info
;
571 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
572 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
574 /* put system-speed load byte into the pipeline */
575 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
576 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 1);
577 arm7tdmi_clock_out(jtag_info
, ARMV4_5_LDRB_IP(num
, 0), NULL
, 0);
580 void arm7tdmi_store_word_regs(target_t
*target
, u32 mask
)
582 /* get pointers to arch-specific information */
583 armv4_5_common_t
*armv4_5
= target
->arch_info
;
584 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
585 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
587 /* put system-speed store-multiple into the pipeline */
588 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
589 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 1);
590 arm7tdmi_clock_out(jtag_info
, ARMV4_5_STMIA(0, mask
, 0, 1), NULL
, 0);
593 void arm7tdmi_store_hword_reg(target_t
*target
, int num
)
595 /* get pointers to arch-specific information */
596 armv4_5_common_t
*armv4_5
= target
->arch_info
;
597 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
598 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
600 /* put system-speed store half-word into the pipeline */
601 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
602 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 1);
603 arm7tdmi_clock_out(jtag_info
, ARMV4_5_STRH_IP(num
, 0), NULL
, 0);
606 void arm7tdmi_store_byte_reg(target_t
*target
, int num
)
608 /* get pointers to arch-specific information */
609 armv4_5_common_t
*armv4_5
= target
->arch_info
;
610 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
611 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
613 /* put system-speed store byte into the pipeline */
614 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
615 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 1);
616 arm7tdmi_clock_out(jtag_info
, ARMV4_5_STRB_IP(num
, 0), NULL
, 0);
619 void arm7tdmi_write_pc(target_t
*target
, u32 pc
)
621 /* get pointers to arch-specific information */
622 armv4_5_common_t
*armv4_5
= target
->arch_info
;
623 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
624 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
626 /* LDMIA r0-15, [r0] at debug speed
627 * register values will start to appear on 4th DCLK
629 arm7tdmi_clock_out(jtag_info
, ARMV4_5_LDMIA(0, 0x8000, 0, 0), NULL
, 0);
630 /* fetch NOP, LDM in DECODE stage */
631 arm7tdmi_clock_out_inner(jtag_info
, ARMV4_5_NOP
, 0);
632 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
633 arm7tdmi_clock_out_inner(jtag_info
, ARMV4_5_NOP
, 0);
634 /* nothing fetched, LDM in EXECUTE stage (1st cycle) load register */
635 arm7tdmi_clock_out_inner(jtag_info
, pc
, 0);
636 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) load register */
637 arm7tdmi_clock_out_inner(jtag_info
, ARMV4_5_NOP
, 0);
638 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) load register */
639 arm7tdmi_clock_out_inner(jtag_info
, ARMV4_5_NOP
, 0);
640 /* fetch NOP, LDM in EXECUTE stage (4th cycle) */
641 arm7tdmi_clock_out_inner(jtag_info
, ARMV4_5_NOP
, 0);
642 /* fetch NOP, LDM in EXECUTE stage (5th cycle) */
643 arm7tdmi_clock_out_inner(jtag_info
, ARMV4_5_NOP
, 0);
646 void arm7tdmi_branch_resume(target_t
*target
)
648 /* get pointers to arch-specific information */
649 armv4_5_common_t
*armv4_5
= target
->arch_info
;
650 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
651 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
653 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 1);
654 arm7tdmi_clock_out_inner(jtag_info
, ARMV4_5_B(0xfffffa, 0), 0);
657 void arm7tdmi_branch_resume_thumb(target_t
*target
)
661 /* get pointers to arch-specific information */
662 armv4_5_common_t
*armv4_5
= target
->arch_info
;
663 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
664 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
665 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
667 /* LDMIA r0, [r0] at debug speed
668 * register values will start to appear on 4th DCLK
670 arm7tdmi_clock_out(jtag_info
, ARMV4_5_LDMIA(0, 0x1, 0, 0), NULL
, 0);
672 /* fetch NOP, LDM in DECODE stage */
673 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
674 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
675 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
676 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) */
677 arm7tdmi_clock_out(jtag_info
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32) | 1, NULL
, 0);
678 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
679 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
681 /* Branch and eXchange */
682 arm7tdmi_clock_out(jtag_info
, ARMV4_5_BX(0), NULL
, 0);
684 embeddedice_read_reg(dbg_stat
);
686 /* fetch NOP, BX in DECODE stage */
687 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
689 /* target is now in Thumb state */
690 embeddedice_read_reg(dbg_stat
);
692 /* fetch NOP, BX in EXECUTE stage (1st cycle) */
693 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
695 /* target is now in Thumb state */
696 embeddedice_read_reg(dbg_stat
);
699 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_LDR_PCREL(0), NULL
, 0);
700 /* fetch NOP, LDR in Decode */
701 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
702 /* fetch NOP, LDR in Execute */
703 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
704 /* nothing fetched, LDR in EXECUTE stage (2nd cycle) */
705 arm7tdmi_clock_out(jtag_info
, buf_get_u32(armv4_5
->core_cache
->reg_list
[0].value
, 0, 32), NULL
, 0);
706 /* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
707 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
709 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
710 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
712 embeddedice_read_reg(dbg_stat
);
714 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 1);
715 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_B(0x7f8), NULL
, 0);
718 void arm7tdmi_build_reg_cache(target_t
*target
)
720 reg_cache_t
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
721 /* get pointers to arch-specific information */
722 armv4_5_common_t
*armv4_5
= target
->arch_info
;
724 (*cache_p
) = armv4_5_build_reg_cache(target
, armv4_5
);
725 armv4_5
->core_cache
= (*cache_p
);
728 int arm7tdmi_examine(struct target_s
*target
)
731 armv4_5_common_t
*armv4_5
= target
->arch_info
;
732 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
733 if (!target
->type
->examined
)
735 /* get pointers to arch-specific information */
736 reg_cache_t
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
737 reg_cache_t
*t
=embeddedice_build_reg_cache(target
, arm7_9
);
742 arm7_9
->eice_cache
= (*cache_p
);
746 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
747 (*cache_p
)->next
= etm_build_reg_cache(target
, jtag_info
, arm7_9
->etm_ctx
);
748 arm7_9
->etm_ctx
->reg_cache
= (*cache_p
)->next
;
750 target
->type
->examined
= 1;
752 if ((retval
=embeddedice_setup(target
))!=ERROR_OK
)
754 if ((retval
=arm7_9_setup(target
))!=ERROR_OK
)
758 if ((retval
=etm_setup(target
))!=ERROR_OK
)
764 int arm7tdmi_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
766 arm7tdmi_build_reg_cache(target
);
771 int arm7tdmi_quit(void)
776 int arm7tdmi_init_arch_info(target_t
*target
, arm7tdmi_common_t
*arm7tdmi
, jtag_tap_t
*tap
)
778 armv4_5_common_t
*armv4_5
;
779 arm7_9_common_t
*arm7_9
;
781 arm7_9
= &arm7tdmi
->arm7_9_common
;
782 armv4_5
= &arm7_9
->armv4_5_common
;
784 /* prepare JTAG information for the new target */
785 arm7_9
->jtag_info
.tap
= tap
;
786 arm7_9
->jtag_info
.scann_size
= 4;
788 /* register arch-specific functions */
789 arm7_9
->examine_debug_reason
= arm7tdmi_examine_debug_reason
;
790 arm7_9
->change_to_arm
= arm7tdmi_change_to_arm
;
791 arm7_9
->read_core_regs
= arm7tdmi_read_core_regs
;
792 arm7_9
->read_core_regs_target_buffer
= arm7tdmi_read_core_regs_target_buffer
;
793 arm7_9
->read_xpsr
= arm7tdmi_read_xpsr
;
795 arm7_9
->write_xpsr
= arm7tdmi_write_xpsr
;
796 arm7_9
->write_xpsr_im8
= arm7tdmi_write_xpsr_im8
;
797 arm7_9
->write_core_regs
= arm7tdmi_write_core_regs
;
799 arm7_9
->load_word_regs
= arm7tdmi_load_word_regs
;
800 arm7_9
->load_hword_reg
= arm7tdmi_load_hword_reg
;
801 arm7_9
->load_byte_reg
= arm7tdmi_load_byte_reg
;
803 arm7_9
->store_word_regs
= arm7tdmi_store_word_regs
;
804 arm7_9
->store_hword_reg
= arm7tdmi_store_hword_reg
;
805 arm7_9
->store_byte_reg
= arm7tdmi_store_byte_reg
;
807 arm7_9
->write_pc
= arm7tdmi_write_pc
;
808 arm7_9
->branch_resume
= arm7tdmi_branch_resume
;
809 arm7_9
->branch_resume_thumb
= arm7tdmi_branch_resume_thumb
;
811 arm7_9
->enable_single_step
= arm7_9_enable_eice_step
;
812 arm7_9
->disable_single_step
= arm7_9_disable_eice_step
;
814 arm7_9
->pre_debug_entry
= NULL
;
815 arm7_9
->post_debug_entry
= NULL
;
817 arm7_9
->pre_restore_context
= NULL
;
818 arm7_9
->post_restore_context
= NULL
;
820 /* initialize arch-specific breakpoint handling */
821 arm7_9
->arm_bkpt
= 0xdeeedeee;
822 arm7_9
->thumb_bkpt
= 0xdeee;
824 arm7_9
->dbgreq_adjust_pc
= 2;
825 arm7_9
->arch_info
= arm7tdmi
;
827 arm7tdmi
->arch_info
= NULL
;
828 arm7tdmi
->common_magic
= ARM7TDMI_COMMON_MAGIC
;
830 arm7_9_init_arch_info(target
, arm7_9
);
835 int arm7tdmi_target_create( struct target_s
*target
, Jim_Interp
*interp
)
837 arm7tdmi_common_t
*arm7tdmi
;
839 arm7tdmi
= calloc(1,sizeof(arm7tdmi_common_t
));
840 arm7tdmi_init_arch_info(target
, arm7tdmi
, target
->tap
);
845 int arm7tdmi_register_commands(struct command_context_s
*cmd_ctx
)
849 retval
= arm7_9_register_commands(cmd_ctx
);
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