1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
32 #define _DEBUG_INSTRUCTION_EXECUTION_
36 int arm720t_register_commands(struct command_context_s
*cmd_ctx
);
38 int arm720t_handle_cp15_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
39 int arm720t_handle_virt2phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
40 int arm720t_handle_md_phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
41 int arm720t_handle_mw_phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
43 /* forward declarations */
44 int arm720t_target_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct target_s
*target
);
45 int arm720t_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
);
47 int arm720t_arch_state(struct target_s
*target
);
48 int arm720t_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
49 int arm720t_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
50 int arm720t_soft_reset_halt(struct target_s
*target
);
52 target_type_t arm720t_target
=
57 .arch_state
= arm720t_arch_state
,
60 .resume
= arm7_9_resume
,
63 .assert_reset
= arm7_9_assert_reset
,
64 .deassert_reset
= arm7_9_deassert_reset
,
65 .soft_reset_halt
= arm720t_soft_reset_halt
,
66 .prepare_reset_halt
= arm7_9_prepare_reset_halt
,
68 .get_gdb_reg_list
= armv4_5_get_gdb_reg_list
,
70 .read_memory
= arm720t_read_memory
,
71 .write_memory
= arm720t_write_memory
,
72 .bulk_write_memory
= arm7_9_bulk_write_memory
,
73 .checksum_memory
= arm7_9_checksum_memory
,
75 .run_algorithm
= armv4_5_run_algorithm
,
77 .add_breakpoint
= arm7_9_add_breakpoint
,
78 .remove_breakpoint
= arm7_9_remove_breakpoint
,
79 .add_watchpoint
= arm7_9_add_watchpoint
,
80 .remove_watchpoint
= arm7_9_remove_watchpoint
,
82 .register_commands
= arm720t_register_commands
,
83 .target_command
= arm720t_target_command
,
84 .init_target
= arm720t_init_target
,
88 int arm720t_scan_cp15(target_t
*target
, u32 out
, u32
*in
, int instruction
, int clock
)
90 armv4_5_common_t
*armv4_5
= target
->arch_info
;
91 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
92 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
93 scan_field_t fields
[2];
95 u8 instruction_buf
= instruction
;
97 buf_set_u32(out_buf
, 0, 32, flip_u32(out
, 32));
99 jtag_add_end_state(TAP_PD
);
100 arm_jtag_scann(jtag_info
, 0xf);
101 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
103 fields
[0].device
= jtag_info
->chain_pos
;
104 fields
[0].num_bits
= 1;
105 fields
[0].out_value
= &instruction_buf
;
106 fields
[0].out_mask
= NULL
;
107 fields
[0].in_value
= NULL
;
108 fields
[0].in_check_value
= NULL
;
109 fields
[0].in_check_mask
= NULL
;
110 fields
[0].in_handler
= NULL
;
111 fields
[0].in_handler_priv
= NULL
;
113 fields
[1].device
= jtag_info
->chain_pos
;
114 fields
[1].num_bits
= 32;
115 fields
[1].out_value
= out_buf
;
116 fields
[1].out_mask
= NULL
;
117 fields
[1].in_value
= NULL
;
120 fields
[1].in_handler
= arm_jtag_buf_to_u32_flip
;
121 fields
[1].in_handler_priv
= in
;
124 fields
[1].in_handler
= NULL
;
125 fields
[1].in_handler_priv
= NULL
;
127 fields
[1].in_check_value
= NULL
;
128 fields
[1].in_check_mask
= NULL
;
130 jtag_add_dr_scan(2, fields
, -1);
133 jtag_add_runtest(0, -1);
135 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
136 jtag_execute_queue();
139 DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out
, *in
, instruction
, clock
);
141 DEBUG("out: %8.8x, instruction: %i, clock: %i", out
, instruction
, clock
);
143 DEBUG("out: %8.8x, instruction: %i, clock: %i", out
, instruction
, clock
);
149 int arm720t_read_cp15(target_t
*target
, u32 opcode
, u32
*value
)
151 /* fetch CP15 opcode */
152 arm720t_scan_cp15(target
, opcode
, NULL
, 1, 1);
154 arm720t_scan_cp15(target
, ARMV4_5_NOP
, NULL
, 1, 1);
155 /* "EXECUTE" stage (1) */
156 arm720t_scan_cp15(target
, ARMV4_5_NOP
, NULL
, 1, 0);
157 arm720t_scan_cp15(target
, 0x0, NULL
, 0, 1);
158 /* "EXECUTE" stage (2) */
159 arm720t_scan_cp15(target
, 0x0, NULL
, 0, 1);
160 /* "EXECUTE" stage (3), CDATA is read */
161 arm720t_scan_cp15(target
, ARMV4_5_NOP
, value
, 1, 1);
166 int arm720t_write_cp15(target_t
*target
, u32 opcode
, u32 value
)
168 /* fetch CP15 opcode */
169 arm720t_scan_cp15(target
, opcode
, NULL
, 1, 1);
171 arm720t_scan_cp15(target
, ARMV4_5_NOP
, NULL
, 1, 1);
172 /* "EXECUTE" stage (1) */
173 arm720t_scan_cp15(target
, ARMV4_5_NOP
, NULL
, 1, 0);
174 arm720t_scan_cp15(target
, 0x0, NULL
, 0, 1);
175 /* "EXECUTE" stage (2) */
176 arm720t_scan_cp15(target
, value
, NULL
, 0, 1);
177 arm720t_scan_cp15(target
, ARMV4_5_NOP
, NULL
, 1, 1);
182 u32
arm720t_get_ttb(target_t
*target
)
186 arm720t_read_cp15(target
, 0xee120f10, &ttb
);
187 jtag_execute_queue();
194 void arm720t_disable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
198 /* read cp15 control register */
199 arm720t_read_cp15(target
, 0xee110f10, &cp15_control
);
200 jtag_execute_queue();
203 cp15_control
&= ~0x1U
;
205 if (d_u_cache
|| i_cache
)
206 cp15_control
&= ~0x4U
;
208 arm720t_write_cp15(target
, 0xee010f10, cp15_control
);
211 void arm720t_enable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
215 /* read cp15 control register */
216 arm720t_read_cp15(target
, 0xee110f10, &cp15_control
);
217 jtag_execute_queue();
220 cp15_control
|= 0x1U
;
222 if (d_u_cache
|| i_cache
)
223 cp15_control
|= 0x4U
;
225 arm720t_write_cp15(target
, 0xee010f10, cp15_control
);
228 void arm720t_post_debug_entry(target_t
*target
)
230 armv4_5_common_t
*armv4_5
= target
->arch_info
;
231 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
232 arm7tdmi_common_t
*arm7tdmi
= arm7_9
->arch_info
;
233 arm720t_common_t
*arm720t
= arm7tdmi
->arch_info
;
235 /* examine cp15 control reg */
236 arm720t_read_cp15(target
, 0xee110f10, &arm720t
->cp15_control_reg
);
237 jtag_execute_queue();
238 DEBUG("cp15_control_reg: %8.8x", arm720t
->cp15_control_reg
);
240 arm720t
->armv4_5_mmu
.mmu_enabled
= (arm720t
->cp15_control_reg
& 0x1U
) ? 1 : 0;
241 arm720t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= (arm720t
->cp15_control_reg
& 0x4U
) ? 1 : 0;
242 arm720t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 0;
244 /* save i/d fault status and address register */
245 arm720t_read_cp15(target
, 0xee150f10, &arm720t
->fsr_reg
);
246 arm720t_read_cp15(target
, 0xee160f10, &arm720t
->far_reg
);
247 jtag_execute_queue();
250 void arm720t_pre_restore_context(target_t
*target
)
252 armv4_5_common_t
*armv4_5
= target
->arch_info
;
253 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
254 arm7tdmi_common_t
*arm7tdmi
= arm7_9
->arch_info
;
255 arm720t_common_t
*arm720t
= arm7tdmi
->arch_info
;
257 /* restore i/d fault status and address register */
258 arm720t_write_cp15(target
, 0xee050f10, arm720t
->fsr_reg
);
259 arm720t_write_cp15(target
, 0xee060f10, arm720t
->far_reg
);
262 int arm720t_get_arch_pointers(target_t
*target
, armv4_5_common_t
**armv4_5_p
, arm7_9_common_t
**arm7_9_p
, arm7tdmi_common_t
**arm7tdmi_p
, arm720t_common_t
**arm720t_p
)
264 armv4_5_common_t
*armv4_5
= target
->arch_info
;
265 arm7_9_common_t
*arm7_9
;
266 arm7tdmi_common_t
*arm7tdmi
;
267 arm720t_common_t
*arm720t
;
269 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
274 arm7_9
= armv4_5
->arch_info
;
275 if (arm7_9
->common_magic
!= ARM7_9_COMMON_MAGIC
)
280 arm7tdmi
= arm7_9
->arch_info
;
281 if (arm7tdmi
->common_magic
!= ARM7TDMI_COMMON_MAGIC
)
286 arm720t
= arm7tdmi
->arch_info
;
287 if (arm720t
->common_magic
!= ARM720T_COMMON_MAGIC
)
292 *armv4_5_p
= armv4_5
;
294 *arm7tdmi_p
= arm7tdmi
;
295 *arm720t_p
= arm720t
;
300 int arm720t_arch_state(struct target_s
*target
)
302 armv4_5_common_t
*armv4_5
= target
->arch_info
;
303 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
304 arm7tdmi_common_t
*arm7tdmi
= arm7_9
->arch_info
;
305 arm720t_common_t
*arm720t
= arm7tdmi
->arch_info
;
309 "disabled", "enabled"
312 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
314 ERROR("BUG: called for a non-ARMv4/5 target");
318 USER("target halted in %s state due to %s, current mode: %s\n"
319 "cpsr: 0x%8.8x pc: 0x%8.8x\n"
320 "MMU: %s, Cache: %s",
321 armv4_5_state_strings
[armv4_5
->core_state
],
322 target_debug_reason_strings
[target
->debug_reason
],
323 armv4_5_mode_strings
[armv4_5_mode_to_number(armv4_5
->core_mode
)],
324 buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32),
325 buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32),
326 state
[arm720t
->armv4_5_mmu
.mmu_enabled
],
327 state
[arm720t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
]);
332 int arm720t_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
335 armv4_5_common_t
*armv4_5
= target
->arch_info
;
336 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
337 arm7tdmi_common_t
*arm7tdmi
= arm7_9
->arch_info
;
338 arm720t_common_t
*arm720t
= arm7tdmi
->arch_info
;
340 /* disable cache, but leave MMU enabled */
341 if (arm720t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
)
342 arm720t_disable_mmu_caches(target
, 0, 1, 0);
344 retval
= arm7_9_read_memory(target
, address
, size
, count
, buffer
);
346 if (arm720t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
)
347 arm720t_enable_mmu_caches(target
, 0, 1, 0);
352 int arm720t_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
356 if ((retval
= arm7_9_write_memory(target
, address
, size
, count
, buffer
)) != ERROR_OK
)
362 int arm720t_soft_reset_halt(struct target_s
*target
)
364 armv4_5_common_t
*armv4_5
= target
->arch_info
;
365 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
366 arm7tdmi_common_t
*arm7tdmi
= arm7_9
->arch_info
;
367 arm720t_common_t
*arm720t
= arm7tdmi
->arch_info
;
368 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
370 if (target
->state
== TARGET_RUNNING
)
372 target
->type
->halt(target
);
375 while (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1) == 0)
377 embeddedice_read_reg(dbg_stat
);
378 jtag_execute_queue();
381 target
->state
= TARGET_HALTED
;
383 /* SVC, ARM state, IRQ and FIQ disabled */
384 buf_set_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8, 0xd3);
385 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 1;
386 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
388 /* start fetching from 0x0 */
389 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, 0x0);
390 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
391 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
393 armv4_5
->core_mode
= ARMV4_5_MODE_SVC
;
394 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
396 arm720t_disable_mmu_caches(target
, 1, 1, 1);
397 arm720t
->armv4_5_mmu
.mmu_enabled
= 0;
398 arm720t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= 0;
399 arm720t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 0;
401 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
406 int arm720t_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
408 arm7tdmi_init_target(cmd_ctx
, target
);
420 int arm720t_init_arch_info(target_t
*target
, arm720t_common_t
*arm720t
, int chain_pos
, char *variant
)
422 arm7tdmi_common_t
*arm7tdmi
= &arm720t
->arm7tdmi_common
;
423 arm7_9_common_t
*arm7_9
= &arm7tdmi
->arm7_9_common
;
425 arm7tdmi_init_arch_info(target
, arm7tdmi
, chain_pos
, variant
);
427 arm7tdmi
->arch_info
= arm720t
;
428 arm720t
->common_magic
= ARM720T_COMMON_MAGIC
;
430 arm7_9
->post_debug_entry
= arm720t_post_debug_entry
;
431 arm7_9
->pre_restore_context
= arm720t_pre_restore_context
;
433 arm720t
->armv4_5_mmu
.armv4_5_cache
.ctype
= -1;
434 arm720t
->armv4_5_mmu
.get_ttb
= arm720t_get_ttb
;
435 arm720t
->armv4_5_mmu
.read_memory
= arm7_9_read_memory
;
436 arm720t
->armv4_5_mmu
.write_memory
= arm7_9_write_memory
;
437 arm720t
->armv4_5_mmu
.disable_mmu_caches
= arm720t_disable_mmu_caches
;
438 arm720t
->armv4_5_mmu
.enable_mmu_caches
= arm720t_enable_mmu_caches
;
439 arm720t
->armv4_5_mmu
.has_tiny_pages
= 0;
440 arm720t
->armv4_5_mmu
.mmu_enabled
= 0;
445 int arm720t_target_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct target_s
*target
)
448 char *variant
= NULL
;
449 arm720t_common_t
*arm720t
= malloc(sizeof(arm720t_common_t
));
453 ERROR("'target arm720t' requires at least one additional argument");
457 chain_pos
= strtoul(args
[3], NULL
, 0);
462 DEBUG("chain_pos: %i, variant: %s", chain_pos
, variant
);
464 arm720t_init_arch_info(target
, arm720t
, chain_pos
, variant
);
469 int arm720t_register_commands(struct command_context_s
*cmd_ctx
)
472 command_t
*arm720t_cmd
;
475 retval
= arm7tdmi_register_commands(cmd_ctx
);
477 arm720t_cmd
= register_command(cmd_ctx
, NULL
, "arm720t", NULL
, COMMAND_ANY
, "arm720t specific commands");
479 register_command(cmd_ctx
, arm720t_cmd
, "cp15", arm720t_handle_cp15_command
, COMMAND_EXEC
, "display/modify cp15 register <opcode> [value]");
480 register_command(cmd_ctx
, arm720t_cmd
, "virt2phys", arm720t_handle_virt2phys_command
, COMMAND_EXEC
, "translate va to pa <va>");
482 register_command(cmd_ctx
, arm720t_cmd
, "mdw_phys", arm720t_handle_md_phys_command
, COMMAND_EXEC
, "display memory words <physical addr> [count]");
483 register_command(cmd_ctx
, arm720t_cmd
, "mdh_phys", arm720t_handle_md_phys_command
, COMMAND_EXEC
, "display memory half-words <physical addr> [count]");
484 register_command(cmd_ctx
, arm720t_cmd
, "mdb_phys", arm720t_handle_md_phys_command
, COMMAND_EXEC
, "display memory bytes <physical addr> [count]");
486 register_command(cmd_ctx
, arm720t_cmd
, "mww_phys", arm720t_handle_mw_phys_command
, COMMAND_EXEC
, "write memory word <physical addr> <value>");
487 register_command(cmd_ctx
, arm720t_cmd
, "mwh_phys", arm720t_handle_mw_phys_command
, COMMAND_EXEC
, "write memory half-word <physical addr> <value>");
488 register_command(cmd_ctx
, arm720t_cmd
, "mwb_phys", arm720t_handle_mw_phys_command
, COMMAND_EXEC
, "write memory byte <physical addr> <value>");
493 int arm720t_handle_cp15_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
496 target_t
*target
= get_current_target(cmd_ctx
);
497 armv4_5_common_t
*armv4_5
;
498 arm7_9_common_t
*arm7_9
;
499 arm7tdmi_common_t
*arm7tdmi
;
500 arm720t_common_t
*arm720t
;
501 arm_jtag_t
*jtag_info
;
503 if (arm720t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm7tdmi
, &arm720t
) != ERROR_OK
)
505 command_print(cmd_ctx
, "current target isn't an ARM720t target");
509 jtag_info
= &arm7_9
->jtag_info
;
511 if (target
->state
!= TARGET_HALTED
)
513 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
517 /* one or more argument, access a single register (write if second argument is given */
520 u32 opcode
= strtoul(args
[0], NULL
, 0);
525 if ((retval
= arm720t_read_cp15(target
, opcode
, &value
)) != ERROR_OK
)
527 command_print(cmd_ctx
, "couldn't access cp15 with opcode 0x%8.8x", opcode
);
530 jtag_execute_queue();
532 command_print(cmd_ctx
, "0x%8.8x: 0x%8.8x", opcode
, value
);
536 u32 value
= strtoul(args
[1], NULL
, 0);
537 if ((retval
= arm720t_write_cp15(target
, opcode
, value
)) != ERROR_OK
)
539 command_print(cmd_ctx
, "couldn't access cp15 with opcode 0x%8.8x", opcode
);
542 command_print(cmd_ctx
, "0x%8.8x: 0x%8.8x", opcode
, value
);
549 int arm720t_handle_virt2phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
551 target_t
*target
= get_current_target(cmd_ctx
);
552 armv4_5_common_t
*armv4_5
;
553 arm7_9_common_t
*arm7_9
;
554 arm7tdmi_common_t
*arm7tdmi
;
555 arm720t_common_t
*arm720t
;
556 arm_jtag_t
*jtag_info
;
558 if (arm720t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm7tdmi
, &arm720t
) != ERROR_OK
)
560 command_print(cmd_ctx
, "current target isn't an ARM720t target");
564 jtag_info
= &arm7_9
->jtag_info
;
566 if (target
->state
!= TARGET_HALTED
)
568 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
572 return armv4_5_mmu_handle_virt2phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm720t
->armv4_5_mmu
);
575 int arm720t_handle_md_phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
577 target_t
*target
= get_current_target(cmd_ctx
);
578 armv4_5_common_t
*armv4_5
;
579 arm7_9_common_t
*arm7_9
;
580 arm7tdmi_common_t
*arm7tdmi
;
581 arm720t_common_t
*arm720t
;
582 arm_jtag_t
*jtag_info
;
584 if (arm720t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm7tdmi
, &arm720t
) != ERROR_OK
)
586 command_print(cmd_ctx
, "current target isn't an ARM720t target");
590 jtag_info
= &arm7_9
->jtag_info
;
592 if (target
->state
!= TARGET_HALTED
)
594 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
598 return armv4_5_mmu_handle_md_phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm720t
->armv4_5_mmu
);
601 int arm720t_handle_mw_phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
603 target_t
*target
= get_current_target(cmd_ctx
);
604 armv4_5_common_t
*armv4_5
;
605 arm7_9_common_t
*arm7_9
;
606 arm7tdmi_common_t
*arm7tdmi
;
607 arm720t_common_t
*arm720t
;
608 arm_jtag_t
*jtag_info
;
610 if (arm720t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm7tdmi
, &arm720t
) != ERROR_OK
)
612 command_print(cmd_ctx
, "current target isn't an ARM720t target");
616 jtag_info
= &arm7_9
->jtag_info
;
618 if (target
->state
!= TARGET_HALTED
)
620 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
624 return armv4_5_mmu_handle_mw_phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm720t
->armv4_5_mmu
);
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)