1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
4 * Copyright (C) 2008 Oyvind Harboe oyvind.harboe@zylin.com *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program; if not, write to the *
18 * Free Software Foundation, Inc., *
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
20 ***************************************************************************/
34 #define JTAG_DEBUG(expr ...) DEBUG(expr)
36 #define JTAG_DEBUG(expr ...) do {} while(0)
39 enum tap_state arm11_move_pi_to_si_via_ci
[] =
41 TAP_E2I
, TAP_UI
, TAP_SDS
, TAP_SIS
, TAP_CI
, TAP_SI
45 int arm11_add_ir_scan_vc(int num_fields
, scan_field_t
*fields
, enum tap_state state
)
47 if (cmd_queue_cur_state
== TAP_PI
)
48 jtag_add_pathmove(asizeof(arm11_move_pi_to_si_via_ci
), arm11_move_pi_to_si_via_ci
);
50 jtag_add_ir_scan(num_fields
, fields
, state
);
54 enum tap_state arm11_move_pd_to_sd_via_cd
[] =
56 TAP_E2D
, TAP_UD
, TAP_SDS
, TAP_CD
, TAP_SD
59 int arm11_add_dr_scan_vc(int num_fields
, scan_field_t
*fields
, enum tap_state state
)
61 if (cmd_queue_cur_state
== TAP_PD
)
62 jtag_add_pathmove(asizeof(arm11_move_pd_to_sd_via_cd
), arm11_move_pd_to_sd_via_cd
);
64 jtag_add_dr_scan(num_fields
, fields
, state
);
69 /** Code de-clutter: Construct scan_field_t to write out a value
71 * \param arm11 Target state variable.
72 * \param num_bits Length of the data field
73 * \param out_data pointer to the data that will be sent out
74 * <em>(data is read when it is added to the JTAG queue)</em>
75 * \param in_data pointer to the memory that will receive data that was clocked in
76 * <em>(data is written when the JTAG queue is executed)</em>
77 * \param field target data structure that will be initialized
79 void arm11_setup_field(arm11_common_t
* arm11
, int num_bits
, void * out_data
, void * in_data
, scan_field_t
* field
)
81 field
->device
= arm11
->jtag_info
.chain_pos
;
82 field
->num_bits
= num_bits
;
83 field
->out_mask
= NULL
;
84 field
->in_check_mask
= NULL
;
85 field
->in_check_value
= NULL
;
86 field
->in_handler
= NULL
;
87 field
->in_handler_priv
= NULL
;
89 field
->out_value
= out_data
;
90 field
->in_value
= in_data
;
94 /** Write JTAG instruction register
96 * \param arm11 Target state variable.
97 * \param instr An ARM11 DBGTAP instruction. Use enum #arm11_instructions.
98 * \param state Pass the final TAP state or -1 for the default value (Pause-IR).
100 * \remarks This adds to the JTAG command queue but does \em not execute it.
102 void arm11_add_IR(arm11_common_t
* arm11
, u8 instr
, enum tap_state state
)
104 jtag_device_t
*device
= jtag_get_device(arm11
->jtag_info
.chain_pos
);
106 if (buf_get_u32(device
->cur_instr
, 0, 5) == instr
)
108 JTAG_DEBUG("IR <= 0x%02x SKIPPED", instr
);
112 JTAG_DEBUG("IR <= 0x%02x", instr
);
116 arm11_setup_field(arm11
, 5, &instr
, NULL
, &field
);
118 arm11_add_ir_scan_vc(1, &field
, state
== -1 ? TAP_PI
: state
);
121 /** Verify shifted out data from Scan Chain Register (SCREG)
122 * Used as parameter to scan_field_t::in_handler in
123 * arm11_add_debug_SCAN_N().
126 static int arm11_in_handler_SCAN_N(u8
*in_value
, void *priv
, struct scan_field_s
*field
)
128 /** \todo TODO: clarify why this isnt properly masked in jtag.c jtag_read_buffer() */
129 u8 v
= *in_value
& 0x1F;
133 LOG_ERROR("'arm11 target' JTAG communication error SCREG SCAN OUT 0x%02x (expected 0x10)", v
);
137 JTAG_DEBUG("SCREG SCAN OUT 0x%02x", v
);
141 /** Select and write to Scan Chain Register (SCREG)
143 * This function sets the instruction register to SCAN_N and writes
144 * the data register with the selected chain number.
146 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/Cacbjhfg.html
148 * \param arm11 Target state variable.
149 * \param chain Scan chain that will be selected.
150 * \param state Pass the final TAP state or -1 for the default
153 * The chain takes effect when Update-DR is passed (usually when subsequently
154 * the INTEXT/EXTEST instructions are written).
156 * \warning (Obsolete) Using this twice in a row will \em fail. The first call will end
157 * in Pause-DR. The second call, due to the IR caching, will not
158 * go through Capture-DR when shifting in the new scan chain number.
159 * As a result the verification in arm11_in_handler_SCAN_N() must
162 * \remarks This adds to the JTAG command queue but does \em not execute it.
165 void arm11_add_debug_SCAN_N(arm11_common_t
* arm11
, u8 chain
, enum tap_state state
)
167 JTAG_DEBUG("SCREG <= 0x%02x", chain
);
169 arm11_add_IR(arm11
, ARM11_SCAN_N
, -1);
173 arm11_setup_field(arm11
, 5, &chain
, NULL
, &field
);
175 field
.in_handler
= arm11_in_handler_SCAN_N
;
177 arm11_add_dr_scan_vc(1, &field
, state
== -1 ? TAP_PD
: state
);
180 /** Write an instruction into the ITR register
182 * \param arm11 Target state variable.
183 * \param inst An ARM11 processor instruction/opcode.
184 * \param flag Optional parameter to retrieve the InstCompl flag
185 * (this will be written when the JTAG chain is executed).
186 * \param state Pass the final TAP state or -1 for the default
187 * value (Run-Test/Idle).
189 * \remarks By default this ends with Run-Test/Idle state
190 * and causes the instruction to be executed. If
191 * a subsequent write to DTR is needed before
192 * executing the instruction then TAP_PD should be
193 * passed to \p state.
195 * \remarks This adds to the JTAG command queue but does \em not execute it.
197 void arm11_add_debug_INST(arm11_common_t
* arm11
, u32 inst
, u8
* flag
, enum tap_state state
)
199 JTAG_DEBUG("INST <= 0x%08x", inst
);
203 arm11_setup_field(arm11
, 32, &inst
, NULL
, itr
+ 0);
204 arm11_setup_field(arm11
, 1, NULL
, flag
, itr
+ 1);
206 arm11_add_dr_scan_vc(asizeof(itr
), itr
, state
== -1 ? TAP_RTI
: state
);
209 /** Read the Debug Status and Control Register (DSCR)
213 * \param arm11 Target state variable.
214 * \return DSCR content
216 * \remarks This is a stand-alone function that executes the JTAG command queue.
218 u32
arm11_read_DSCR(arm11_common_t
* arm11
)
220 arm11_add_debug_SCAN_N(arm11
, 0x01, -1);
222 arm11_add_IR(arm11
, ARM11_INTEST
, -1);
225 scan_field_t chain1_field
;
227 arm11_setup_field(arm11
, 32, NULL
, &dscr
, &chain1_field
);
229 arm11_add_dr_scan_vc(1, &chain1_field
, TAP_PD
);
231 jtag_execute_queue();
233 if (arm11
->last_dscr
!= dscr
)
234 JTAG_DEBUG("DSCR = %08x (OLD %08x)", dscr
, arm11
->last_dscr
);
236 arm11
->last_dscr
= dscr
;
241 /** Write the Debug Status and Control Register (DSCR)
245 * \param arm11 Target state variable.
246 * \param dscr DSCR content
248 * \remarks This is a stand-alone function that executes the JTAG command queue.
250 void arm11_write_DSCR(arm11_common_t
* arm11
, u32 dscr
)
252 arm11_add_debug_SCAN_N(arm11
, 0x01, -1);
254 arm11_add_IR(arm11
, ARM11_EXTEST
, -1);
256 scan_field_t chain1_field
;
258 arm11_setup_field(arm11
, 32, &dscr
, NULL
, &chain1_field
);
260 arm11_add_dr_scan_vc(1, &chain1_field
, TAP_PD
);
262 jtag_execute_queue();
264 JTAG_DEBUG("DSCR <= %08x (OLD %08x)", dscr
, arm11
->last_dscr
);
266 arm11
->last_dscr
= dscr
;
271 /** Get the debug reason from Debug Status and Control Register (DSCR)
273 * \param dscr DSCR value to analyze
274 * \return Debug reason
277 enum target_debug_reason
arm11_get_DSCR_debug_reason(u32 dscr
)
279 switch (dscr
& ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK
)
281 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT
:
282 LOG_INFO("Debug entry: JTAG HALT");
283 return DBG_REASON_DBGRQ
;
285 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT
:
286 LOG_INFO("Debug entry: breakpoint");
287 return DBG_REASON_BREAKPOINT
;
289 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT
:
290 LOG_INFO("Debug entry: watchpoint");
291 return DBG_REASON_WATCHPOINT
;
293 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION
:
294 LOG_INFO("Debug entry: BKPT instruction");
295 return DBG_REASON_BREAKPOINT
;
297 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ
:
298 LOG_INFO("Debug entry: EDBGRQ signal");
299 return DBG_REASON_DBGRQ
;
301 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH
:
302 LOG_INFO("Debug entry: VCR vector catch");
303 return DBG_REASON_BREAKPOINT
;
306 LOG_INFO("Debug entry: unknown");
307 return DBG_REASON_DBGRQ
;
313 /** Prepare the stage for ITR/DTR operations
314 * from the arm11_run_instr... group of functions.
316 * Put arm11_run_instr_data_prepare() and arm11_run_instr_data_finish()
317 * around a block of arm11_run_instr_... calls.
319 * Select scan chain 5 to allow quick access to DTR. When scan
320 * chain 4 is needed to put in a register the ITRSel instruction
321 * shortcut is used instead of actually changing the Scan_N
324 * \param arm11 Target state variable.
327 void arm11_run_instr_data_prepare(arm11_common_t
* arm11
)
329 arm11_add_debug_SCAN_N(arm11
, 0x05, -1);
332 /** Cleanup after ITR/DTR operations
333 * from the arm11_run_instr... group of functions
335 * Put arm11_run_instr_data_prepare() and arm11_run_instr_data_finish()
336 * around a block of arm11_run_instr_... calls.
338 * Any RTI can lead to an instruction execution when
339 * scan chains 4 or 5 are selected and the IR holds
340 * INTEST or EXTEST. So we must disable that before
341 * any following activities lead to an RTI.
343 * \param arm11 Target state variable.
346 void arm11_run_instr_data_finish(arm11_common_t
* arm11
)
348 arm11_add_debug_SCAN_N(arm11
, 0x00, -1);
352 /** Execute one or multiple instructions via ITR
354 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
356 * \param arm11 Target state variable.
357 * \param opcode Pointer to sequence of ARM opcodes
358 * \param count Number of opcodes to execute
361 void arm11_run_instr_no_data(arm11_common_t
* arm11
, u32
* opcode
, size_t count
)
363 arm11_add_IR(arm11
, ARM11_ITRSEL
, -1);
367 arm11_add_debug_INST(arm11
, *opcode
++, NULL
, TAP_RTI
);
373 arm11_add_debug_INST(arm11
, 0, &flag
, count
? TAP_RTI
: TAP_PD
);
375 jtag_execute_queue();
383 /** Execute one instruction via ITR
385 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
387 * \param arm11 Target state variable.
388 * \param opcode ARM opcode
391 void arm11_run_instr_no_data1(arm11_common_t
* arm11
, u32 opcode
)
393 arm11_run_instr_no_data(arm11
, &opcode
, 1);
397 /** Execute one instruction via ITR repeatedly while
398 * passing data to the core via DTR on each execution.
400 * The executed instruction \em must read data from DTR.
402 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
404 * \param arm11 Target state variable.
405 * \param opcode ARM opcode
406 * \param data Pointer to the data words to be passed to the core
407 * \param count Number of data words and instruction repetitions
410 void arm11_run_instr_data_to_core(arm11_common_t
* arm11
, u32 opcode
, u32
* data
, size_t count
)
412 arm11_add_IR(arm11
, ARM11_ITRSEL
, -1);
414 arm11_add_debug_INST(arm11
, opcode
, NULL
, TAP_PD
);
416 arm11_add_IR(arm11
, ARM11_EXTEST
, -1);
418 scan_field_t chain5_fields
[3];
424 arm11_setup_field(arm11
, 32, &Data
, NULL
, chain5_fields
+ 0);
425 arm11_setup_field(arm11
, 1, NULL
, &Ready
, chain5_fields
+ 1);
426 arm11_setup_field(arm11
, 1, NULL
, &nRetry
, chain5_fields
+ 2);
434 arm11_add_dr_scan_vc(asizeof(chain5_fields
), chain5_fields
, TAP_RTI
);
435 jtag_execute_queue();
437 JTAG_DEBUG("DTR Ready %d nRetry %d", Ready
, nRetry
);
444 arm11_add_IR(arm11
, ARM11_INTEST
, -1);
450 arm11_add_dr_scan_vc(asizeof(chain5_fields
), chain5_fields
, TAP_PD
);
451 jtag_execute_queue();
453 JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data
, Ready
, nRetry
);
458 /** JTAG path for arm11_run_instr_data_to_core_noack
460 * The repeated TAP_RTI's do not cause a repeated execution
461 * if passed without leaving the state.
463 * Since this is more than 7 bits (adjustable via adding more
464 * TAP_RTI's) it produces an artificial delay in the lower
465 * layer (FT2232) that is long enough to finish execution on
466 * the core but still shorter than any manually inducible delays.
469 enum tap_state arm11_MOVE_PD_RTI_PD_with_delay
[] =
471 TAP_E2D
, TAP_UD
, TAP_RTI
, TAP_RTI
, TAP_RTI
, TAP_SDS
, TAP_CD
, TAP_SD
476 /** Execute one instruction via ITR repeatedly while
477 * passing data to the core via DTR on each execution.
479 * No Ready check during transmission.
481 * The executed instruction \em must read data from DTR.
483 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
485 * \param arm11 Target state variable.
486 * \param opcode ARM opcode
487 * \param data Pointer to the data words to be passed to the core
488 * \param count Number of data words and instruction repetitions
491 void arm11_run_instr_data_to_core_noack(arm11_common_t
* arm11
, u32 opcode
, u32
* data
, size_t count
)
493 arm11_add_IR(arm11
, ARM11_ITRSEL
, -1);
495 arm11_add_debug_INST(arm11
, opcode
, NULL
, TAP_PD
);
497 arm11_add_IR(arm11
, ARM11_EXTEST
, -1);
499 scan_field_t chain5_fields
[3];
501 arm11_setup_field(arm11
, 32, NULL
/*&Data*/, NULL
, chain5_fields
+ 0);
502 arm11_setup_field(arm11
, 1, NULL
, NULL
/*&Ready*/, chain5_fields
+ 1);
503 arm11_setup_field(arm11
, 1, NULL
, NULL
, chain5_fields
+ 2);
505 u8 Readies
[count
+ 1];
506 u8
* ReadyPos
= Readies
;
510 chain5_fields
[0].out_value
= (void *)(data
++);
511 chain5_fields
[1].in_value
= ReadyPos
++;
515 jtag_add_dr_scan(asizeof(chain5_fields
), chain5_fields
, TAP_PD
);
516 jtag_add_pathmove(asizeof(arm11_MOVE_PD_RTI_PD_with_delay
),
517 arm11_MOVE_PD_RTI_PD_with_delay
);
521 jtag_add_dr_scan(asizeof(chain5_fields
), chain5_fields
, TAP_RTI
);
525 arm11_add_IR(arm11
, ARM11_INTEST
, -1);
527 chain5_fields
[0].out_value
= 0;
528 chain5_fields
[1].in_value
= ReadyPos
++;
530 arm11_add_dr_scan_vc(asizeof(chain5_fields
), chain5_fields
, TAP_PD
);
532 jtag_execute_queue();
534 size_t error_count
= 0;
537 for (i
= 0; i
< asizeof(Readies
); i
++)
546 LOG_ERROR("Transfer errors " ZU
, error_count
);
550 /** Execute an instruction via ITR while handing data into the core via DTR.
552 * The executed instruction \em must read data from DTR.
554 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
556 * \param arm11 Target state variable.
557 * \param opcode ARM opcode
558 * \param data Data word to be passed to the core via DTR
561 void arm11_run_instr_data_to_core1(arm11_common_t
* arm11
, u32 opcode
, u32 data
)
563 arm11_run_instr_data_to_core(arm11
, opcode
, &data
, 1);
567 /** Execute one instruction via ITR repeatedly while
568 * reading data from the core via DTR on each execution.
570 * The executed instruction \em must write data to DTR.
572 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
574 * \param arm11 Target state variable.
575 * \param opcode ARM opcode
576 * \param data Pointer to an array that receives the data words from the core
577 * \param count Number of data words and instruction repetitions
580 void arm11_run_instr_data_from_core(arm11_common_t
* arm11
, u32 opcode
, u32
* data
, size_t count
)
582 arm11_add_IR(arm11
, ARM11_ITRSEL
, -1);
584 arm11_add_debug_INST(arm11
, opcode
, NULL
, TAP_RTI
);
586 arm11_add_IR(arm11
, ARM11_INTEST
, -1);
588 scan_field_t chain5_fields
[3];
594 arm11_setup_field(arm11
, 32, NULL
, &Data
, chain5_fields
+ 0);
595 arm11_setup_field(arm11
, 1, NULL
, &Ready
, chain5_fields
+ 1);
596 arm11_setup_field(arm11
, 1, NULL
, &nRetry
, chain5_fields
+ 2);
602 arm11_add_dr_scan_vc(asizeof(chain5_fields
), chain5_fields
, count
? TAP_RTI
: TAP_PD
);
603 jtag_execute_queue();
605 JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data
, Ready
, nRetry
);
613 /** Execute one instruction via ITR
614 * then load r0 into DTR and read DTR from core.
616 * The first executed instruction (\p opcode) should write data to r0.
618 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
620 * \param arm11 Target state variable.
621 * \param opcode ARM opcode to write r0 with the value of interest
622 * \param data Pointer to a data word that receives the value from r0 after \p opcode was executed.
625 void arm11_run_instr_data_from_core_via_r0(arm11_common_t
* arm11
, u32 opcode
, u32
* data
)
627 arm11_run_instr_no_data1(arm11
, opcode
);
629 /* MCR p14,0,R0,c0,c5,0 (move r0 -> wDTR -> local var) */
630 arm11_run_instr_data_from_core(arm11
, 0xEE000E15, data
, 1);
633 /** Load data into core via DTR then move it to r0 then
634 * execute one instruction via ITR
636 * The final executed instruction (\p opcode) should read data from r0.
638 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
640 * \param arm11 Target state variable.
641 * \param opcode ARM opcode to read r0 act upon it
642 * \param data Data word that will be written to r0 before \p opcode is executed
645 void arm11_run_instr_data_to_core_via_r0(arm11_common_t
* arm11
, u32 opcode
, u32 data
)
647 /* MRC p14,0,r0,c0,c5,0 */
648 arm11_run_instr_data_to_core1(arm11
, 0xEE100E15, data
);
650 arm11_run_instr_no_data1(arm11
, opcode
);
653 /** Apply reads and writes to scan chain 7
655 * \see arm11_sc7_action_t
657 * \param arm11 Target state variable.
658 * \param actions A list of read and/or write instructions
659 * \param count Number of instructions in the list.
662 void arm11_sc7_run(arm11_common_t
* arm11
, arm11_sc7_action_t
* actions
, size_t count
)
664 arm11_add_debug_SCAN_N(arm11
, 0x07, -1);
666 arm11_add_IR(arm11
, ARM11_EXTEST
, -1);
668 scan_field_t chain7_fields
[3];
677 arm11_setup_field(arm11
, 1, &nRW
, &Ready
, chain7_fields
+ 0);
678 arm11_setup_field(arm11
, 32, &DataOut
, &DataIn
, chain7_fields
+ 1);
679 arm11_setup_field(arm11
, 7, &AddressOut
, &AddressIn
, chain7_fields
+ 2);
682 for (i
= 0; i
< count
+ 1; i
++)
686 nRW
= actions
[i
].write
? 1 : 0;
687 DataOut
= actions
[i
].value
;
688 AddressOut
= actions
[i
].address
;
699 JTAG_DEBUG("SC7 <= Address %02x Data %08x nRW %d", AddressOut
, DataOut
, nRW
);
701 arm11_add_dr_scan_vc(asizeof(chain7_fields
), chain7_fields
, TAP_PD
);
702 jtag_execute_queue();
704 JTAG_DEBUG("SC7 => Address %02x Data %08x Ready %d", AddressIn
, DataIn
, Ready
);
706 while (!Ready
); /* 'nRW' is 'Ready' on read out */
710 if (actions
[i
- 1].address
!= AddressIn
)
712 LOG_WARNING("Scan chain 7 shifted out unexpected address");
715 if (!actions
[i
- 1].write
)
717 actions
[i
- 1].value
= DataIn
;
721 if (actions
[i
- 1].value
!= DataIn
)
723 LOG_WARNING("Scan chain 7 shifted out unexpected data");
730 for (i
= 0; i
< count
; i
++)
732 JTAG_DEBUG("SC7 %02d: %02x %s %08x", i
, actions
[i
].address
, actions
[i
].write
? "<=" : "=>", actions
[i
].value
);
736 /** Clear VCR and all breakpoints and watchpoints via scan chain 7
738 * \param arm11 Target state variable.
741 void arm11_sc7_clear_vbw(arm11_common_t
* arm11
)
743 arm11_sc7_action_t clear_bw
[arm11
->brp
+ arm11
->wrp
+ 1];
744 arm11_sc7_action_t
* pos
= clear_bw
;
747 for (i
= 0; i
< asizeof(clear_bw
); i
++)
749 clear_bw
[i
].write
= true;
750 clear_bw
[i
].value
= 0;
754 for (i
= 0; i
< arm11
->brp
; i
++)
755 (pos
++)->address
= ARM11_SC7_BCR0
+ i
;
759 for (i
= 0; i
< arm11
->wrp
; i
++)
760 (pos
++)->address
= ARM11_SC7_WCR0
+ i
;
763 (pos
++)->address
= ARM11_SC7_VCR
;
765 arm11_sc7_run(arm11
, clear_bw
, asizeof(clear_bw
));
768 /** Write VCR register
770 * \param arm11 Target state variable.
771 * \param value Value to be written
773 void arm11_sc7_set_vcr(arm11_common_t
* arm11
, u32 value
)
775 arm11_sc7_action_t set_vcr
;
777 set_vcr
.write
= true;
778 set_vcr
.address
= ARM11_SC7_VCR
;
779 set_vcr
.value
= value
;
782 arm11_sc7_run(arm11
, &set_vcr
, 1);
787 /** Read word from address
789 * \param arm11 Target state variable.
790 * \param address Memory address to be read
791 * \param result Pointer where to store result
794 void arm11_read_memory_word(arm11_common_t
* arm11
, u32 address
, u32
* result
)
796 arm11_run_instr_data_prepare(arm11
);
798 /* MRC p14,0,r0,c0,c5,0 (r0 = address) */
799 arm11_run_instr_data_to_core1(arm11
, 0xee100e15, address
);
801 /* LDC p14,c5,[R0],#4 (DTR = [r0]) */
802 arm11_run_instr_data_from_core(arm11
, 0xecb05e01, result
, 1);
804 arm11_run_instr_data_finish(arm11
);
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