1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
5 * Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
28 #define asizeof(x) (sizeof(x) / sizeof((x)[0]))
30 #define NEW(type, variable, items) \
31 type * variable = calloc(1, sizeof(type) * items)
33 /* For MinGW use 'I' prefix to print size_t (instead of 'z') */
34 /* Except if __USE_MINGW_ANSI_STDIO is defined with MinGW */
36 #if (!defined(__MSVCRT__) || defined(__USE_MINGW_ANSI_STDIO))
42 #define ARM11_REGCACHE_MODEREGS 0
43 #define ARM11_REGCACHE_FREGS 0
45 #define ARM11_REGCACHE_COUNT (20 + \
46 23 * ARM11_REGCACHE_MODEREGS + \
47 9 * ARM11_REGCACHE_FREGS)
49 #define ARM11_TAP_DEFAULT TAP_INVALID
52 #define CHECK_RETVAL(action) \
54 int __retval = (action); \
56 if (__retval != ERROR_OK) \
58 LOG_DEBUG("error while calling \"" # action "\""); \
65 struct arm11_register_history
71 enum arm11_debug_version
73 ARM11_DEBUG_V6
= 0x01,
74 ARM11_DEBUG_V61
= 0x02,
75 ARM11_DEBUG_V7
= 0x03,
76 ARM11_DEBUG_V7_CP14
= 0x04,
82 struct target
* target
; /**< Reference back to the owner */
84 /** \name Processor type detection */
87 uint32_t device_id
; /**< IDCODE readout */
88 uint32_t didr
; /**< DIDR readout (debug capabilities) */
89 uint8_t implementor
; /**< DIDR Implementor readout */
91 size_t brp
; /**< Number of Breakpoint Register Pairs from DIDR */
92 size_t wrp
; /**< Number of Watchpoint Register Pairs from DIDR */
94 enum arm11_debug_version
95 debug_version
; /**< ARM debug architecture from DIDR */
98 uint32_t last_dscr
; /**< Last retrieved DSCR value;
99 Use only for debug message generation */
101 bool simulate_reset_on_next_halt
; /**< Perform cleanups of the ARM state on next halt */
103 /** \name Shadow registers to save processor state */
106 struct reg
* reg_list
; /**< target register list */
107 uint32_t reg_values
[ARM11_REGCACHE_COUNT
]; /**< data for registers */
111 struct arm11_register_history
112 reg_history
[ARM11_REGCACHE_COUNT
]; /**< register state before last resume */
114 size_t free_brps
; /**< keep track of breakpoints allocated by arm11_add_breakpoint() */
115 size_t free_wrps
; /**< keep track of breakpoints allocated by arm11_add_watchpoint() */
118 struct reg_cache
*core_cache
;
120 struct arm_jtag jtag_info
;
123 static inline struct arm11_common
*target_to_arm11(struct target
*target
)
125 return container_of(target
->arch_info
, struct arm11_common
,
130 * ARM11 DBGTAP instructions
132 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/I1006229.html
134 enum arm11_instructions
138 ARM11_RESTART
= 0x04,
148 ARM11_DSCR_CORE_HALTED
= 1 << 0,
149 ARM11_DSCR_CORE_RESTARTED
= 1 << 1,
151 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK
= 0x0F << 2,
152 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT
= 0x00 << 2,
153 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT
= 0x01 << 2,
154 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT
= 0x02 << 2,
155 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION
= 0x03 << 2,
156 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ
= 0x04 << 2,
157 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH
= 0x05 << 2,
159 ARM11_DSCR_STICKY_PRECISE_DATA_ABORT
= 1 << 6,
160 ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT
= 1 << 7,
161 ARM11_DSCR_INTERRUPTS_DISABLE
= 1 << 11,
162 ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE
= 1 << 13,
163 ARM11_DSCR_MODE_SELECT
= 1 << 14,
164 ARM11_DSCR_WDTR_FULL
= 1 << 29,
165 ARM11_DSCR_RDTR_FULL
= 1 << 30,
170 ARM11_CPSR_T
= 1 << 5,
171 ARM11_CPSR_J
= 1 << 24,
182 ARM11_SC7_WCR0
= 112,
185 struct arm11_reg_state
188 struct target
* target
;
191 int arm11_register_commands(struct command_context
*cmd_ctx
);
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)