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Michael Bruck:
[openocd.git] / src / target / arm11.c
1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
3 * *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
8 * *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
13 * *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
18 ***************************************************************************/
19
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "arm11.h"
25 #include "jtag.h"
26 #include "log.h"
27
28 #include <stdlib.h>
29 #include <string.h>
30
31 #if 0
32 #define _DEBUG_INSTRUCTION_EXECUTION_
33 #endif
34
35
36 #if 0
37 #define FNC_INFO DEBUG("-")
38 #else
39 #define FNC_INFO
40 #endif
41
42 #if 1
43 #define FNC_INFO_NOTIMPLEMENTED do { DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
44 #else
45 #define FNC_INFO_NOTIMPLEMENTED
46 #endif
47
48 static void arm11_on_enter_debug_state(arm11_common_t * arm11);
49
50
51 bool arm11_config_memwrite_burst = true;
52 bool arm11_config_memwrite_error_fatal = true;
53 u32 arm11_vcr = 0;
54
55
56 #define ARM11_HANDLER(x) \
57 .x = arm11_##x
58
59 target_type_t arm11_target =
60 {
61 .name = "arm11",
62
63 ARM11_HANDLER(poll),
64 ARM11_HANDLER(arch_state),
65
66 ARM11_HANDLER(target_request_data),
67
68 ARM11_HANDLER(halt),
69 ARM11_HANDLER(resume),
70 ARM11_HANDLER(step),
71
72 ARM11_HANDLER(assert_reset),
73 ARM11_HANDLER(deassert_reset),
74 ARM11_HANDLER(soft_reset_halt),
75 ARM11_HANDLER(prepare_reset_halt),
76
77 ARM11_HANDLER(get_gdb_reg_list),
78
79 ARM11_HANDLER(read_memory),
80 ARM11_HANDLER(write_memory),
81
82 ARM11_HANDLER(bulk_write_memory),
83
84 ARM11_HANDLER(checksum_memory),
85
86 ARM11_HANDLER(add_breakpoint),
87 ARM11_HANDLER(remove_breakpoint),
88 ARM11_HANDLER(add_watchpoint),
89 ARM11_HANDLER(remove_watchpoint),
90
91 ARM11_HANDLER(run_algorithm),
92
93 ARM11_HANDLER(register_commands),
94 ARM11_HANDLER(target_command),
95 ARM11_HANDLER(init_target),
96 ARM11_HANDLER(quit),
97 };
98
99 int arm11_regs_arch_type = -1;
100
101
102 enum arm11_regtype
103 {
104 ARM11_REGISTER_CORE,
105 ARM11_REGISTER_CPSR,
106
107 ARM11_REGISTER_FX,
108 ARM11_REGISTER_FPS,
109
110 ARM11_REGISTER_FIQ,
111 ARM11_REGISTER_SVC,
112 ARM11_REGISTER_ABT,
113 ARM11_REGISTER_IRQ,
114 ARM11_REGISTER_UND,
115 ARM11_REGISTER_MON,
116
117 ARM11_REGISTER_SPSR_FIQ,
118 ARM11_REGISTER_SPSR_SVC,
119 ARM11_REGISTER_SPSR_ABT,
120 ARM11_REGISTER_SPSR_IRQ,
121 ARM11_REGISTER_SPSR_UND,
122 ARM11_REGISTER_SPSR_MON,
123
124 /* debug regs */
125 ARM11_REGISTER_DSCR,
126 ARM11_REGISTER_WDTR,
127 ARM11_REGISTER_RDTR,
128 };
129
130
131 typedef struct arm11_reg_defs_s
132 {
133 char * name;
134 u32 num;
135 int gdb_num;
136 enum arm11_regtype type;
137 } arm11_reg_defs_t;
138
139 /* update arm11_regcache_ids when changing this */
140 static const arm11_reg_defs_t arm11_reg_defs[] =
141 {
142 {"r0", 0, 0, ARM11_REGISTER_CORE},
143 {"r1", 1, 1, ARM11_REGISTER_CORE},
144 {"r2", 2, 2, ARM11_REGISTER_CORE},
145 {"r3", 3, 3, ARM11_REGISTER_CORE},
146 {"r4", 4, 4, ARM11_REGISTER_CORE},
147 {"r5", 5, 5, ARM11_REGISTER_CORE},
148 {"r6", 6, 6, ARM11_REGISTER_CORE},
149 {"r7", 7, 7, ARM11_REGISTER_CORE},
150 {"r8", 8, 8, ARM11_REGISTER_CORE},
151 {"r9", 9, 9, ARM11_REGISTER_CORE},
152 {"r10", 10, 10, ARM11_REGISTER_CORE},
153 {"r11", 11, 11, ARM11_REGISTER_CORE},
154 {"r12", 12, 12, ARM11_REGISTER_CORE},
155 {"sp", 13, 13, ARM11_REGISTER_CORE},
156 {"lr", 14, 14, ARM11_REGISTER_CORE},
157 {"pc", 15, 15, ARM11_REGISTER_CORE},
158
159 #if ARM11_REGCACHE_FREGS
160 {"f0", 0, 16, ARM11_REGISTER_FX},
161 {"f1", 1, 17, ARM11_REGISTER_FX},
162 {"f2", 2, 18, ARM11_REGISTER_FX},
163 {"f3", 3, 19, ARM11_REGISTER_FX},
164 {"f4", 4, 20, ARM11_REGISTER_FX},
165 {"f5", 5, 21, ARM11_REGISTER_FX},
166 {"f6", 6, 22, ARM11_REGISTER_FX},
167 {"f7", 7, 23, ARM11_REGISTER_FX},
168 {"fps", 0, 24, ARM11_REGISTER_FPS},
169 #endif
170
171 {"cpsr", 0, 25, ARM11_REGISTER_CPSR},
172
173 #if ARM11_REGCACHE_MODEREGS
174 {"r8_fiq", 8, -1, ARM11_REGISTER_FIQ},
175 {"r9_fiq", 9, -1, ARM11_REGISTER_FIQ},
176 {"r10_fiq", 10, -1, ARM11_REGISTER_FIQ},
177 {"r11_fiq", 11, -1, ARM11_REGISTER_FIQ},
178 {"r12_fiq", 12, -1, ARM11_REGISTER_FIQ},
179 {"r13_fiq", 13, -1, ARM11_REGISTER_FIQ},
180 {"r14_fiq", 14, -1, ARM11_REGISTER_FIQ},
181 {"spsr_fiq", 0, -1, ARM11_REGISTER_SPSR_FIQ},
182
183 {"r13_svc", 13, -1, ARM11_REGISTER_SVC},
184 {"r14_svc", 14, -1, ARM11_REGISTER_SVC},
185 {"spsr_svc", 0, -1, ARM11_REGISTER_SPSR_SVC},
186
187 {"r13_abt", 13, -1, ARM11_REGISTER_ABT},
188 {"r14_abt", 14, -1, ARM11_REGISTER_ABT},
189 {"spsr_abt", 0, -1, ARM11_REGISTER_SPSR_ABT},
190
191 {"r13_irq", 13, -1, ARM11_REGISTER_IRQ},
192 {"r14_irq", 14, -1, ARM11_REGISTER_IRQ},
193 {"spsr_irq", 0, -1, ARM11_REGISTER_SPSR_IRQ},
194
195 {"r13_und", 13, -1, ARM11_REGISTER_UND},
196 {"r14_und", 14, -1, ARM11_REGISTER_UND},
197 {"spsr_und", 0, -1, ARM11_REGISTER_SPSR_UND},
198
199 /* ARM1176 only */
200 {"r13_mon", 13, -1, ARM11_REGISTER_MON},
201 {"r14_mon", 14, -1, ARM11_REGISTER_MON},
202 {"spsr_mon", 0, -1, ARM11_REGISTER_SPSR_MON},
203 #endif
204
205 /* Debug Registers */
206 {"dscr", 0, -1, ARM11_REGISTER_DSCR},
207 {"wdtr", 0, -1, ARM11_REGISTER_WDTR},
208 {"rdtr", 0, -1, ARM11_REGISTER_RDTR},
209 };
210
211 enum arm11_regcache_ids
212 {
213 ARM11_RC_R0,
214 ARM11_RC_RX = ARM11_RC_R0,
215
216 ARM11_RC_R1,
217 ARM11_RC_R2,
218 ARM11_RC_R3,
219 ARM11_RC_R4,
220 ARM11_RC_R5,
221 ARM11_RC_R6,
222 ARM11_RC_R7,
223 ARM11_RC_R8,
224 ARM11_RC_R9,
225 ARM11_RC_R10,
226 ARM11_RC_R11,
227 ARM11_RC_R12,
228 ARM11_RC_R13,
229 ARM11_RC_SP = ARM11_RC_R13,
230 ARM11_RC_R14,
231 ARM11_RC_LR = ARM11_RC_R14,
232 ARM11_RC_R15,
233 ARM11_RC_PC = ARM11_RC_R15,
234
235 #if ARM11_REGCACHE_FREGS
236 ARM11_RC_F0,
237 ARM11_RC_FX = ARM11_RC_F0,
238 ARM11_RC_F1,
239 ARM11_RC_F2,
240 ARM11_RC_F3,
241 ARM11_RC_F4,
242 ARM11_RC_F5,
243 ARM11_RC_F6,
244 ARM11_RC_F7,
245 ARM11_RC_FPS,
246 #endif
247
248 ARM11_RC_CPSR,
249
250 #if ARM11_REGCACHE_MODEREGS
251 ARM11_RC_R8_FIQ,
252 ARM11_RC_R9_FIQ,
253 ARM11_RC_R10_FIQ,
254 ARM11_RC_R11_FIQ,
255 ARM11_RC_R12_FIQ,
256 ARM11_RC_R13_FIQ,
257 ARM11_RC_R14_FIQ,
258 ARM11_RC_SPSR_FIQ,
259
260 ARM11_RC_R13_SVC,
261 ARM11_RC_R14_SVC,
262 ARM11_RC_SPSR_SVC,
263
264 ARM11_RC_R13_ABT,
265 ARM11_RC_R14_ABT,
266 ARM11_RC_SPSR_ABT,
267
268 ARM11_RC_R13_IRQ,
269 ARM11_RC_R14_IRQ,
270 ARM11_RC_SPSR_IRQ,
271
272 ARM11_RC_R13_UND,
273 ARM11_RC_R14_UND,
274 ARM11_RC_SPSR_UND,
275
276 ARM11_RC_R13_MON,
277 ARM11_RC_R14_MON,
278 ARM11_RC_SPSR_MON,
279 #endif
280
281 ARM11_RC_DSCR,
282 ARM11_RC_WDTR,
283 ARM11_RC_RDTR,
284
285
286 ARM11_RC_MAX,
287 };
288
289 #define ARM11_GDB_REGISTER_COUNT 26
290
291 u8 arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
292
293 reg_t arm11_gdb_dummy_fp_reg =
294 {
295 "GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
296 };
297
298 u8 arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};
299
300 reg_t arm11_gdb_dummy_fps_reg =
301 {
302 "GDB dummy floating-point status register", arm11_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
303 };
304
305
306
307 /** Check and if necessary take control of the system
308 *
309 * \param arm11 Target state variable.
310 * \param dscr If the current DSCR content is
311 * available a pointer to a word holding the
312 * DSCR can be passed. Otherwise use NULL.
313 */
314 void arm11_check_init(arm11_common_t * arm11, u32 * dscr)
315 {
316 FNC_INFO;
317
318 u32 dscr_local_tmp_copy;
319
320 if (!dscr)
321 {
322 dscr = &dscr_local_tmp_copy;
323 *dscr = arm11_read_DSCR(arm11);
324 }
325
326 if (!(*dscr & ARM11_DSCR_MODE_SELECT))
327 {
328 DEBUG("Bringing target into debug mode");
329
330 *dscr |= ARM11_DSCR_MODE_SELECT; /* Halt debug-mode */
331 arm11_write_DSCR(arm11, *dscr);
332
333 /* add further reset initialization here */
334
335 if (*dscr & ARM11_DSCR_CORE_HALTED)
336 {
337 arm11->target->state = TARGET_HALTED;
338 arm11->target->debug_reason = arm11_get_DSCR_debug_reason(*dscr);
339 }
340 else
341 {
342 arm11->target->state = TARGET_RUNNING;
343 arm11->target->debug_reason = DBG_REASON_NOTHALTED;
344 }
345
346 arm11_sc7_clear_vbw(arm11);
347 }
348 }
349
350
351
352 #define R(x) \
353 (arm11->reg_values[ARM11_RC_##x])
354
355 /** Save processor state.
356 *
357 * This is called when the HALT instruction has succeeded
358 * or on other occasions that stop the processor.
359 *
360 */
361 static void arm11_on_enter_debug_state(arm11_common_t * arm11)
362 {
363 FNC_INFO;
364
365 {size_t i;
366 for(i = 0; i < asizeof(arm11->reg_values); i++)
367 {
368 arm11->reg_list[i].valid = 1;
369 arm11->reg_list[i].dirty = 0;
370 }}
371
372 /* Save DSCR */
373
374 R(DSCR) = arm11_read_DSCR(arm11);
375
376 /* Save wDTR */
377
378 if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
379 {
380 arm11_add_debug_SCAN_N(arm11, 0x05, -1);
381
382 arm11_add_IR(arm11, ARM11_INTEST, -1);
383
384 scan_field_t chain5_fields[3];
385
386 arm11_setup_field(arm11, 32, NULL, &R(WDTR), chain5_fields + 0);
387 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
388 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
389
390 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD);
391 }
392 else
393 {
394 arm11->reg_list[ARM11_RC_WDTR].valid = 0;
395 }
396
397
398 /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */
399 /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
400 ARM1136 seems to require this to issue ITR's as well */
401
402 u32 new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
403
404 /* this executes JTAG queue: */
405
406 arm11_write_DSCR(arm11, new_dscr);
407
408
409 /* From the spec:
410 Before executing any instruction in debug state you have to drain the write buffer.
411 This ensures that no imprecise Data Aborts can return at a later point:*/
412
413 /** \todo TODO: Test drain write buffer. */
414
415 #if 0
416 while (1)
417 {
418 /* MRC p14,0,R0,c5,c10,0 */
419 // arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
420
421 /* mcr 15, 0, r0, cr7, cr10, {4} */
422 arm11_run_instr_no_data1(arm11, 0xee070f9a);
423
424 u32 dscr = arm11_read_DSCR(arm11);
425
426 DEBUG("DRAIN, DSCR %08x", dscr);
427
428 if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)
429 {
430 arm11_run_instr_no_data1(arm11, 0xe320f000);
431
432 dscr = arm11_read_DSCR(arm11);
433
434 DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
435
436 break;
437 }
438 }
439 #endif
440
441
442 arm11_run_instr_data_prepare(arm11);
443
444 /* save r0 - r14 */
445
446
447 /** \todo TODO: handle other mode registers */
448
449 {size_t i;
450 for (i = 0; i < 15; i++)
451 {
452 /* MCR p14,0,R?,c0,c5,0 */
453 arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);
454 }}
455
456
457 /* save rDTR */
458
459 /* check rDTRfull in DSCR */
460
461 if (R(DSCR) & ARM11_DSCR_RDTR_FULL)
462 {
463 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
464 arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR));
465 }
466 else
467 {
468 arm11->reg_list[ARM11_RC_RDTR].valid = 0;
469 }
470
471 /* save CPSR */
472
473 /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */
474 arm11_run_instr_data_from_core_via_r0(arm11, 0xE10F0000, &R(CPSR));
475
476 /* save PC */
477
478 /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
479 arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC));
480
481 /* adjust PC depending on ARM state */
482
483 if (R(CPSR) & ARM11_CPSR_J) /* Java state */
484 {
485 arm11->reg_values[ARM11_RC_PC] -= 0;
486 }
487 else if (R(CPSR) & ARM11_CPSR_T) /* Thumb state */
488 {
489 arm11->reg_values[ARM11_RC_PC] -= 4;
490 }
491 else /* ARM state */
492 {
493 arm11->reg_values[ARM11_RC_PC] -= 8;
494 }
495
496 if (arm11->simulate_reset_on_next_halt)
497 {
498 arm11->simulate_reset_on_next_halt = false;
499
500 DEBUG("Reset c1 Control Register");
501
502 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
503
504 /* MCR p15,0,R0,c1,c0,0 */
505 arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
506
507 }
508
509
510
511 arm11_run_instr_data_finish(arm11);
512
513 arm11_dump_reg_changes(arm11);
514 }
515
516 void arm11_dump_reg_changes(arm11_common_t * arm11)
517 {
518 {size_t i;
519 for(i = 0; i < ARM11_REGCACHE_COUNT; i++)
520 {
521 if (!arm11->reg_list[i].valid)
522 {
523 if (arm11->reg_history[i].valid)
524 INFO("%8s INVALID (%08x)", arm11_reg_defs[i].name, arm11->reg_history[i].value);
525 }
526 else
527 {
528 if (arm11->reg_history[i].valid)
529 {
530 if (arm11->reg_history[i].value != arm11->reg_values[i])
531 INFO("%8s %08x (%08x)", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
532 }
533 else
534 {
535 INFO("%8s %08x (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
536 }
537 }
538 }}
539 }
540
541
542 /** Restore processor state
543 *
544 * This is called in preparation for the RESTART function.
545 *
546 */
547 void arm11_leave_debug_state(arm11_common_t * arm11)
548 {
549 FNC_INFO;
550
551 arm11_run_instr_data_prepare(arm11);
552
553 /** \todo TODO: handle other mode registers */
554
555 /* restore R1 - R14 */
556 {size_t i;
557 for (i = 1; i < 15; i++)
558 {
559 if (!arm11->reg_list[ARM11_RC_RX + i].dirty)
560 continue;
561
562 /* MRC p14,0,r?,c0,c5,0 */
563 arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));
564
565 // DEBUG("RESTORE R%d %08x", i, R(RX + i));
566 }}
567
568 arm11_run_instr_data_finish(arm11);
569
570
571 /* spec says clear wDTR and rDTR; we assume they are clear as
572 otherwise our programming would be sloppy */
573
574 {
575 u32 DSCR = arm11_read_DSCR(arm11);
576
577 if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
578 {
579 ERROR("wDTR/rDTR inconsistent (DSCR %08x)", DSCR);
580 }
581 }
582
583 arm11_run_instr_data_prepare(arm11);
584
585 /* restore original wDTR */
586
587 if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty)
588 {
589 /* MCR p14,0,R0,c0,c5,0 */
590 arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR));
591 }
592
593 /* restore CPSR */
594
595 /* MSR CPSR,R0*/
596 arm11_run_instr_data_to_core_via_r0(arm11, 0xe129f000, R(CPSR));
597
598
599 /* restore PC */
600
601 /* MOV PC,R0 */
602 arm11_run_instr_data_to_core_via_r0(arm11, 0xe1a0f000, R(PC));
603
604
605 /* restore R0 */
606
607 /* MRC p14,0,r0,c0,c5,0 */
608 arm11_run_instr_data_to_core1(arm11, 0xee100e15, R(R0));
609
610 arm11_run_instr_data_finish(arm11);
611
612
613 /* restore DSCR */
614
615 arm11_write_DSCR(arm11, R(DSCR));
616
617
618 /* restore rDTR */
619
620 if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty)
621 {
622 arm11_add_debug_SCAN_N(arm11, 0x05, -1);
623
624 arm11_add_IR(arm11, ARM11_EXTEST, -1);
625
626 scan_field_t chain5_fields[3];
627
628 u8 Ready = 0; /* ignored */
629 u8 Valid = 0; /* ignored */
630
631 arm11_setup_field(arm11, 32, &R(RDTR), NULL, chain5_fields + 0);
632 arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
633 arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
634
635 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD);
636 }
637
638 arm11_record_register_history(arm11);
639 }
640
641 void arm11_record_register_history(arm11_common_t * arm11)
642 {
643 {size_t i;
644 for(i = 0; i < ARM11_REGCACHE_COUNT; i++)
645 {
646 arm11->reg_history[i].value = arm11->reg_values[i];
647 arm11->reg_history[i].valid = arm11->reg_list[i].valid;
648
649 arm11->reg_list[i].valid = 0;
650 arm11->reg_list[i].dirty = 0;
651 }}
652 }
653
654
655 /* poll current target status */
656 int arm11_poll(struct target_s *target)
657 {
658 FNC_INFO;
659
660 arm11_common_t * arm11 = target->arch_info;
661
662 if (arm11->trst_active)
663 return ERROR_OK;
664
665 u32 dscr = arm11_read_DSCR(arm11);
666
667 DEBUG("DSCR %08x", dscr);
668
669 arm11_check_init(arm11, &dscr);
670
671 if (dscr & ARM11_DSCR_CORE_HALTED)
672 {
673 if (target->state != TARGET_HALTED)
674 {
675 enum target_state old_state = target->state;
676
677 DEBUG("enter TARGET_HALTED");
678 target->state = TARGET_HALTED;
679 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
680 arm11_on_enter_debug_state(arm11);
681
682 target_call_event_callbacks(target,
683 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
684 }
685 }
686 else
687 {
688 if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
689 {
690 DEBUG("enter TARGET_RUNNING");
691 target->state = TARGET_RUNNING;
692 target->debug_reason = DBG_REASON_NOTHALTED;
693 }
694 }
695
696 return ERROR_OK;
697 }
698 /* architecture specific status reply */
699 int arm11_arch_state(struct target_s *target)
700 {
701 FNC_INFO_NOTIMPLEMENTED;
702
703 return ERROR_OK;
704 }
705
706
707 /* target request support */
708 int arm11_target_request_data(struct target_s *target, u32 size, u8 *buffer)
709 {
710 FNC_INFO_NOTIMPLEMENTED;
711
712 return ERROR_OK;
713 }
714
715
716
717 /* target execution control */
718 int arm11_halt(struct target_s *target)
719 {
720 FNC_INFO;
721
722 arm11_common_t * arm11 = target->arch_info;
723
724 DEBUG("target->state: %s", target_state_strings[target->state]);
725
726 if (target->state == TARGET_UNKNOWN)
727 {
728 arm11->simulate_reset_on_next_halt = true;
729 }
730
731 if (target->state == TARGET_HALTED)
732 {
733 WARNING("target was already halted");
734 return ERROR_TARGET_ALREADY_HALTED;
735 }
736
737 if (arm11->trst_active)
738 {
739 arm11->halt_requested = true;
740 return ERROR_OK;
741 }
742
743 arm11_add_IR(arm11, ARM11_HALT, TAP_RTI);
744
745 jtag_execute_queue();
746
747 u32 dscr;
748
749 while (1)
750 {
751 dscr = arm11_read_DSCR(arm11);
752
753 if (dscr & ARM11_DSCR_CORE_HALTED)
754 break;
755 }
756
757 arm11_on_enter_debug_state(arm11);
758
759 enum target_state old_state = target->state;
760
761 target->state = TARGET_HALTED;
762 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
763
764 target_call_event_callbacks(target,
765 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
766
767 return ERROR_OK;
768 }
769
770
771 int arm11_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
772 {
773 FNC_INFO;
774
775 // DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
776 // current, address, handle_breakpoints, debug_execution);
777
778 arm11_common_t * arm11 = target->arch_info;
779
780 DEBUG("target->state: %s", target_state_strings[target->state]);
781
782 if (target->state != TARGET_HALTED)
783 {
784 WARNING("target was not halted");
785 return ERROR_TARGET_NOT_HALTED;
786 }
787
788 if (!current)
789 R(PC) = address;
790
791 INFO("RESUME PC %08x", R(PC));
792
793 /* clear breakpoints/watchpoints and VCR*/
794 arm11_sc7_clear_vbw(arm11);
795
796 /* Set up breakpoints */
797 if (!debug_execution)
798 {
799 /* check if one matches PC and step over it if necessary */
800
801 breakpoint_t * bp;
802
803 for (bp = target->breakpoints; bp; bp = bp->next)
804 {
805 if (bp->address == R(PC))
806 {
807 DEBUG("must step over %08x", bp->address);
808 arm11_step(target, 1, 0, 0);
809 break;
810 }
811 }
812
813 /* set all breakpoints */
814
815 size_t brp_num = 0;
816
817 for (bp = target->breakpoints; bp; bp = bp->next)
818 {
819 arm11_sc7_action_t brp[2];
820
821 brp[0].write = 1;
822 brp[0].address = ARM11_SC7_BVR0 + brp_num;
823 brp[0].value = bp->address;
824 brp[1].write = 1;
825 brp[1].address = ARM11_SC7_BCR0 + brp_num;
826 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
827
828 arm11_sc7_run(arm11, brp, asizeof(brp));
829
830 DEBUG("Add BP %zd at %08x", brp_num, bp->address);
831
832 brp_num++;
833 }
834
835 arm11_sc7_set_vcr(arm11, arm11_vcr);
836 }
837
838
839 arm11_leave_debug_state(arm11);
840
841 arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI);
842
843 jtag_execute_queue();
844
845 while (1)
846 {
847 u32 dscr = arm11_read_DSCR(arm11);
848
849 DEBUG("DSCR %08x", dscr);
850
851 if (dscr & ARM11_DSCR_CORE_RESTARTED)
852 break;
853 }
854
855 if (!debug_execution)
856 {
857 target->state = TARGET_RUNNING;
858 target->debug_reason = DBG_REASON_NOTHALTED;
859 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
860 }
861 else
862 {
863 target->state = TARGET_DEBUG_RUNNING;
864 target->debug_reason = DBG_REASON_NOTHALTED;
865 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
866 }
867
868 return ERROR_OK;
869 }
870
871 int arm11_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
872 {
873 FNC_INFO;
874
875 DEBUG("target->state: %s", target_state_strings[target->state]);
876
877 if (target->state != TARGET_HALTED)
878 {
879 WARNING("target was not halted");
880 return ERROR_TARGET_NOT_HALTED;
881 }
882
883 arm11_common_t * arm11 = target->arch_info;
884
885 if (!current)
886 R(PC) = address;
887
888 INFO("STEP PC %08x", R(PC));
889
890 /** \todo TODO: Thumb not supported here */
891
892 u32 next_instruction;
893
894 arm11_read_memory_word(arm11, R(PC), &next_instruction);
895
896 /* skip over BKPT */
897 if ((next_instruction & 0xFFF00070) == 0xe1200070)
898 {
899 R(PC) += 4;
900 arm11->reg_list[ARM11_RC_PC].valid = 1;
901 arm11->reg_list[ARM11_RC_PC].dirty = 0;
902 INFO("Skipping BKPT");
903 }
904 /* skip over Wait for interrupt / Standby */
905 /* mcr 15, 0, r?, cr7, cr0, {4} */
906 else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90)
907 {
908 R(PC) += 4;
909 arm11->reg_list[ARM11_RC_PC].valid = 1;
910 arm11->reg_list[ARM11_RC_PC].dirty = 0;
911 INFO("Skipping WFI");
912 }
913 /* ignore B to self */
914 else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
915 {
916 INFO("Not stepping jump to self");
917 }
918 else
919 {
920 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
921 * with this. */
922
923 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
924 * the VCR might be something worth looking into. */
925
926
927 /* Set up breakpoint for stepping */
928
929 arm11_sc7_action_t brp[2];
930
931 brp[0].write = 1;
932 brp[0].address = ARM11_SC7_BVR0;
933 brp[0].value = R(PC);
934 brp[1].write = 1;
935 brp[1].address = ARM11_SC7_BCR0;
936 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
937
938 arm11_sc7_run(arm11, brp, asizeof(brp));
939
940 /* resume */
941
942 arm11_leave_debug_state(arm11);
943
944 arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI);
945
946 jtag_execute_queue();
947
948 /** \todo TODO: add a timeout */
949
950 /* wait for halt */
951
952 while (1)
953 {
954 u32 dscr = arm11_read_DSCR(arm11);
955
956 DEBUG("DSCR %08x", dscr);
957
958 if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
959 (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))
960 break;
961 }
962
963 /* clear breakpoint */
964 arm11_sc7_clear_vbw(arm11);
965
966 /* save state */
967 arm11_on_enter_debug_state(arm11);
968 }
969
970 // target->state = TARGET_HALTED;
971 target->debug_reason = DBG_REASON_SINGLESTEP;
972
973 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
974
975 return ERROR_OK;
976 }
977
978
979 /* target reset control */
980 int arm11_assert_reset(struct target_s *target)
981 {
982 FNC_INFO;
983
984 #if 0
985 /* assert reset lines */
986 /* resets only the DBGTAP, not the ARM */
987
988 jtag_add_reset(1, 0);
989 jtag_add_sleep(5000);
990
991 arm11_common_t * arm11 = target->arch_info;
992 arm11->trst_active = true;
993 #endif
994
995 return ERROR_OK;
996 }
997
998 int arm11_deassert_reset(struct target_s *target)
999 {
1000 FNC_INFO;
1001
1002 #if 0
1003 DEBUG("target->state: %s", target_state_strings[target->state]);
1004
1005 /* deassert reset lines */
1006 jtag_add_reset(0, 0);
1007
1008 arm11_common_t * arm11 = target->arch_info;
1009 arm11->trst_active = false;
1010
1011 if (arm11->halt_requested)
1012 return arm11_halt(target);
1013 #endif
1014
1015 return ERROR_OK;
1016 }
1017
1018 int arm11_soft_reset_halt(struct target_s *target)
1019 {
1020 FNC_INFO_NOTIMPLEMENTED;
1021
1022 return ERROR_OK;
1023 }
1024
1025 int arm11_prepare_reset_halt(struct target_s *target)
1026 {
1027 FNC_INFO_NOTIMPLEMENTED;
1028
1029 return ERROR_OK;
1030 }
1031
1032
1033 /* target register access for gdb */
1034 int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size)
1035 {
1036 FNC_INFO;
1037
1038 arm11_common_t * arm11 = target->arch_info;
1039
1040 if (target->state != TARGET_HALTED)
1041 {
1042 return ERROR_TARGET_NOT_HALTED;
1043 }
1044
1045 *reg_list_size = ARM11_GDB_REGISTER_COUNT;
1046 *reg_list = malloc(sizeof(reg_t*) * ARM11_GDB_REGISTER_COUNT);
1047
1048 {size_t i;
1049 for (i = 16; i < 24; i++)
1050 {
1051 (*reg_list)[i] = &arm11_gdb_dummy_fp_reg;
1052 }}
1053
1054 (*reg_list)[24] = &arm11_gdb_dummy_fps_reg;
1055
1056
1057 {size_t i;
1058 for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1059 {
1060 if (arm11_reg_defs[i].gdb_num == -1)
1061 continue;
1062
1063 (*reg_list)[arm11_reg_defs[i].gdb_num] = arm11->reg_list + i;
1064 }}
1065
1066 return ERROR_OK;
1067 }
1068
1069
1070 /* target memory access
1071 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
1072 * count: number of items of <size>
1073 */
1074 int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1075 {
1076 /** \todo TODO: check if buffer cast to u32* and u16* might cause alignment problems */
1077
1078 FNC_INFO;
1079
1080 DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count);
1081
1082 arm11_common_t * arm11 = target->arch_info;
1083
1084 arm11_run_instr_data_prepare(arm11);
1085
1086 /* MRC p14,0,r0,c0,c5,0 */
1087 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1088
1089 switch (size)
1090 {
1091 case 1:
1092 /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
1093 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1094
1095 {size_t i;
1096 for (i = 0; i < count; i++)
1097 {
1098 /* ldrb r1, [r0], #1 */
1099 arm11_run_instr_no_data1(arm11, 0xe4d01001);
1100
1101 u32 res;
1102 /* MCR p14,0,R1,c0,c5,0 */
1103 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1104
1105 *buffer++ = res;
1106 }}
1107
1108 break;
1109
1110 case 2:
1111 {
1112 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1113
1114 u16 * buf16 = (u16*)buffer;
1115
1116 {size_t i;
1117 for (i = 0; i < count; i++)
1118 {
1119 /* ldrh r1, [r0], #2 */
1120 arm11_run_instr_no_data1(arm11, 0xe0d010b2);
1121
1122 u32 res;
1123
1124 /* MCR p14,0,R1,c0,c5,0 */
1125 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1126
1127 *buf16++ = res;
1128 }}
1129
1130 break;
1131 }
1132
1133 case 4:
1134
1135 /* LDC p14,c5,[R0],#4 */
1136 arm11_run_instr_data_from_core(arm11, 0xecb05e01, (u32 *)buffer, count);
1137 break;
1138 }
1139
1140 arm11_run_instr_data_finish(arm11);
1141
1142 return ERROR_OK;
1143 }
1144
1145 int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1146 {
1147 FNC_INFO;
1148
1149 DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count);
1150
1151 arm11_common_t * arm11 = target->arch_info;
1152
1153 arm11_run_instr_data_prepare(arm11);
1154
1155 /* MRC p14,0,r0,c0,c5,0 */
1156 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1157
1158 switch (size)
1159 {
1160 case 1:
1161 {
1162 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1163
1164 {size_t i;
1165 for (i = 0; i < count; i++)
1166 {
1167 /* MRC p14,0,r1,c0,c5,0 */
1168 arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
1169
1170 /* strb r1, [r0], #1 */
1171 arm11_run_instr_no_data1(arm11, 0xe4c01001);
1172 }}
1173
1174 break;
1175 }
1176
1177 case 2:
1178 {
1179 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1180
1181 u16 * buf16 = (u16*)buffer;
1182
1183 {size_t i;
1184 for (i = 0; i < count; i++)
1185 {
1186 /* MRC p14,0,r1,c0,c5,0 */
1187 arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buf16++);
1188
1189 /* strh r1, [r0], #2 */
1190 arm11_run_instr_no_data1(arm11, 0xe0c010b2);
1191 }}
1192
1193 break;
1194 }
1195
1196 case 4:
1197 /** \todo TODO: check if buffer cast to u32* might cause alignment problems */
1198
1199 if (!arm11_config_memwrite_burst)
1200 {
1201 /* STC p14,c5,[R0],#4 */
1202 arm11_run_instr_data_to_core(arm11, 0xeca05e01, (u32 *)buffer, count);
1203 }
1204 else
1205 {
1206 /* STC p14,c5,[R0],#4 */
1207 arm11_run_instr_data_to_core_noack(arm11, 0xeca05e01, (u32 *)buffer, count);
1208 }
1209
1210 break;
1211 }
1212
1213 #if 1
1214 /* r0 verification */
1215 {
1216 u32 r0;
1217
1218 /* MCR p14,0,R0,c0,c5,0 */
1219 arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
1220
1221 if (address + size * count != r0)
1222 {
1223 ERROR("Data transfer failed. (%d)", (r0 - address) - size * count);
1224
1225 if (arm11_config_memwrite_burst)
1226 ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1227
1228 if (arm11_config_memwrite_error_fatal)
1229 exit(-1);
1230 }
1231 }
1232 #endif
1233
1234
1235 arm11_run_instr_data_finish(arm11);
1236
1237
1238
1239
1240 return ERROR_OK;
1241 }
1242
1243
1244 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1245 int arm11_bulk_write_memory(struct target_s *target, u32 address, u32 count, u8 *buffer)
1246 {
1247 FNC_INFO;
1248
1249 return arm11_write_memory(target, address, 4, count, buffer);
1250 }
1251
1252
1253 int arm11_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
1254 {
1255 FNC_INFO_NOTIMPLEMENTED;
1256
1257 return ERROR_OK;
1258 }
1259
1260
1261 /* target break-/watchpoint control
1262 * rw: 0 = write, 1 = read, 2 = access
1263 */
1264 int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1265 {
1266 FNC_INFO;
1267
1268 arm11_common_t * arm11 = target->arch_info;
1269
1270 #if 0
1271 if (breakpoint->type == BKPT_SOFT)
1272 {
1273 INFO("sw breakpoint requested, but software breakpoints not enabled");
1274 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1275 }
1276 #endif
1277
1278 if (!arm11->free_brps)
1279 {
1280 INFO("no breakpoint unit available for hardware breakpoint");
1281 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1282 }
1283
1284 if (breakpoint->length != 4)
1285 {
1286 INFO("only breakpoints of four bytes length supported");
1287 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1288 }
1289
1290 arm11->free_brps--;
1291
1292 return ERROR_OK;
1293 }
1294
1295 int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1296 {
1297 FNC_INFO;
1298
1299 arm11_common_t * arm11 = target->arch_info;
1300
1301 arm11->free_brps++;
1302
1303 return ERROR_OK;
1304 }
1305
1306 int arm11_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1307 {
1308 FNC_INFO_NOTIMPLEMENTED;
1309
1310 return ERROR_OK;
1311 }
1312
1313 int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1314 {
1315 FNC_INFO_NOTIMPLEMENTED;
1316
1317 return ERROR_OK;
1318 }
1319
1320
1321 /* target algorithm support */
1322 int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_param, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info)
1323 {
1324 FNC_INFO_NOTIMPLEMENTED;
1325
1326 return ERROR_OK;
1327 }
1328
1329 int arm11_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
1330 {
1331 FNC_INFO;
1332
1333 if (argc < 4)
1334 {
1335 ERROR("'target arm11' 4th argument <jtag chain pos>");
1336 exit(-1);
1337 }
1338
1339 int chain_pos = strtoul(args[3], NULL, 0);
1340
1341 NEW(arm11_common_t, arm11, 1);
1342
1343 arm11->target = target;
1344
1345 /* prepare JTAG information for the new target */
1346 arm11->jtag_info.chain_pos = chain_pos;
1347 arm11->jtag_info.scann_size = 5;
1348
1349 arm_jtag_setup_connection(&arm11->jtag_info);
1350
1351 jtag_device_t *device = jtag_get_device(chain_pos);
1352
1353 if (device->ir_length != 5)
1354 {
1355 ERROR("'target arm11' expects 'jtag_device 5 0x01 0x1F 0x1E'");
1356 exit(-1);
1357 }
1358
1359 target->arch_info = arm11;
1360
1361 return ERROR_OK;
1362 }
1363
1364 int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
1365 {
1366 FNC_INFO;
1367
1368 arm11_common_t * arm11 = target->arch_info;
1369
1370 /* check IDCODE */
1371
1372 arm11_add_IR(arm11, ARM11_IDCODE, -1);
1373
1374 scan_field_t idcode_field;
1375
1376 arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field);
1377
1378 arm11_add_dr_scan_vc(1, &idcode_field, TAP_PD);
1379
1380 /* check DIDR */
1381
1382 arm11_add_debug_SCAN_N(arm11, 0x00, -1);
1383
1384 arm11_add_IR(arm11, ARM11_INTEST, -1);
1385
1386 scan_field_t chain0_fields[2];
1387
1388 arm11_setup_field(arm11, 32, NULL, &arm11->didr, chain0_fields + 0);
1389 arm11_setup_field(arm11, 8, NULL, &arm11->implementor, chain0_fields + 1);
1390
1391 arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_RTI);
1392
1393 jtag_execute_queue();
1394
1395
1396 switch (arm11->device_id & 0x0FFFF000)
1397 {
1398 case 0x07B36000: INFO("found ARM1136"); break;
1399 case 0x07B56000: INFO("found ARM1156"); break;
1400 case 0x07B76000: INFO("found ARM1176"); break;
1401 default:
1402 {
1403 ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1404 exit(-1);
1405 }
1406 }
1407
1408 arm11->debug_version = (arm11->didr >> 16) & 0x0F;
1409
1410 if (arm11->debug_version != ARM11_DEBUG_V6 &&
1411 arm11->debug_version != ARM11_DEBUG_V61)
1412 {
1413 ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
1414 exit(-1);
1415 }
1416
1417
1418 arm11->brp = ((arm11->didr >> 24) & 0x0F) + 1;
1419 arm11->wrp = ((arm11->didr >> 28) & 0x0F) + 1;
1420
1421 /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1422 arm11->free_brps = arm11->brp;
1423 arm11->free_wrps = arm11->wrp;
1424
1425 DEBUG("IDCODE %08x IMPLEMENTOR %02x DIDR %08x",
1426 arm11->device_id,
1427 arm11->implementor,
1428 arm11->didr);
1429
1430 arm11_build_reg_cache(target);
1431
1432
1433 /* as a side-effect this reads DSCR and thus
1434 * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1435 * as suggested by the spec.
1436 */
1437
1438 arm11_check_init(arm11, NULL);
1439
1440 return ERROR_OK;
1441 }
1442
1443 int arm11_quit(void)
1444 {
1445 FNC_INFO_NOTIMPLEMENTED;
1446
1447 return ERROR_OK;
1448 }
1449
1450 /** Load a register that is marked !valid in the register cache */
1451 int arm11_get_reg(reg_t *reg)
1452 {
1453 FNC_INFO;
1454
1455 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1456
1457 if (target->state != TARGET_HALTED)
1458 {
1459 return ERROR_TARGET_NOT_HALTED;
1460 }
1461
1462 /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
1463
1464 #if 0
1465 arm11_common_t *arm11 = target->arch_info;
1466 const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1467 #endif
1468
1469 return ERROR_OK;
1470 }
1471
1472 /** Change a value in the register cache */
1473 int arm11_set_reg(reg_t *reg, u8 *buf)
1474 {
1475 FNC_INFO;
1476
1477 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1478 arm11_common_t *arm11 = target->arch_info;
1479 // const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1480
1481 arm11->reg_values[((arm11_reg_state_t *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
1482 reg->valid = 1;
1483 reg->dirty = 1;
1484
1485 return ERROR_OK;
1486 }
1487
1488
1489 void arm11_build_reg_cache(target_t *target)
1490 {
1491 arm11_common_t *arm11 = target->arch_info;
1492
1493 NEW(reg_cache_t, cache, 1);
1494 NEW(reg_t, reg_list, ARM11_REGCACHE_COUNT);
1495 NEW(arm11_reg_state_t, arm11_reg_states, ARM11_REGCACHE_COUNT);
1496
1497 if (arm11_regs_arch_type == -1)
1498 arm11_regs_arch_type = register_reg_arch_type(arm11_get_reg, arm11_set_reg);
1499
1500 arm11->reg_list = reg_list;
1501
1502 /* Build the process context cache */
1503 cache->name = "arm11 registers";
1504 cache->next = NULL;
1505 cache->reg_list = reg_list;
1506 cache->num_regs = ARM11_REGCACHE_COUNT;
1507
1508 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
1509 (*cache_p) = cache;
1510
1511 // armv7m->core_cache = cache;
1512 // armv7m->process_context = cache;
1513
1514 size_t i;
1515
1516 /* Not very elegant assertion */
1517 if (ARM11_REGCACHE_COUNT != asizeof(arm11->reg_values) ||
1518 ARM11_REGCACHE_COUNT != asizeof(arm11_reg_defs) ||
1519 ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
1520 {
1521 ERROR("arm11->reg_values inconsistent (%d %zd %zd %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX);
1522 exit(-1);
1523 }
1524
1525 for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1526 {
1527 reg_t * r = reg_list + i;
1528 const arm11_reg_defs_t * rd = arm11_reg_defs + i;
1529 arm11_reg_state_t * rs = arm11_reg_states + i;
1530
1531 r->name = rd->name;
1532 r->size = 32;
1533 r->value = (u8 *)(arm11->reg_values + i);
1534 r->dirty = 0;
1535 r->valid = 0;
1536 r->bitfield_desc = NULL;
1537 r->num_bitfields = 0;
1538 r->arch_type = arm11_regs_arch_type;
1539 r->arch_info = rs;
1540
1541 rs->def_index = i;
1542 rs->target = target;
1543 }
1544 }
1545
1546
1547
1548 int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool * var, char * name)
1549 {
1550 if (argc == 0)
1551 {
1552 INFO("%s is %s.", name, *var ? "enabled" : "disabled");
1553 return ERROR_OK;
1554 }
1555
1556 if (argc != 1)
1557 return ERROR_COMMAND_SYNTAX_ERROR;
1558
1559 switch (args[0][0])
1560 {
1561 case '0': /* 0 */
1562 case 'f': /* false */
1563 case 'F':
1564 case 'd': /* disable */
1565 case 'D':
1566 *var = false;
1567 break;
1568
1569 case '1': /* 1 */
1570 case 't': /* true */
1571 case 'T':
1572 case 'e': /* enable */
1573 case 'E':
1574 *var = true;
1575 break;
1576 }
1577
1578 INFO("%s %s.", *var ? "Enabled" : "Disabled", name);
1579
1580 return ERROR_OK;
1581 }
1582
1583
1584 #define BOOL_WRAPPER(name, print_name) \
1585 int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) \
1586 { \
1587 return arm11_handle_bool(cmd_ctx, cmd, args, argc, &arm11_config_##name, print_name); \
1588 }
1589
1590 #define RC_TOP(name, descr, more) \
1591 { \
1592 command_t * new_cmd = register_command(cmd_ctx, top_cmd, name, NULL, COMMAND_ANY, descr); \
1593 command_t * top_cmd = new_cmd; \
1594 more \
1595 }
1596
1597 #define RC_FINAL(name, descr, handler) \
1598 register_command(cmd_ctx, top_cmd, name, handler, COMMAND_ANY, descr);
1599
1600 #define RC_FINAL_BOOL(name, descr, var) \
1601 register_command(cmd_ctx, top_cmd, name, arm11_handle_bool_##var, COMMAND_ANY, descr);
1602
1603
1604 BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
1605 BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
1606
1607
1608 int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1609 {
1610 if (argc == 1)
1611 {
1612 arm11_vcr = strtoul(args[0], NULL, 0);
1613 }
1614 else if (argc != 0)
1615 {
1616 return ERROR_COMMAND_SYNTAX_ERROR;
1617 }
1618
1619 INFO("VCR 0x%08X", arm11_vcr);
1620 return ERROR_OK;
1621 }
1622
1623
1624 int arm11_register_commands(struct command_context_s *cmd_ctx)
1625 {
1626 FNC_INFO;
1627
1628 command_t * top_cmd = NULL;
1629
1630 RC_TOP( "arm11", "arm11 specific commands",
1631
1632 RC_TOP( "memwrite", "Control memory write transfer mode",
1633
1634 RC_FINAL_BOOL( "burst", "Enable/Disable non-standard but fast burst mode (default: enabled)",
1635 memwrite_burst)
1636
1637 RC_FINAL_BOOL( "error_fatal",
1638 "Terminate program if transfer error was found (default: enabled)",
1639 memwrite_error_fatal)
1640 )
1641
1642 RC_FINAL( "vcr", "Control (Interrupt) Vector Catch Register",
1643 arm11_handle_vcr)
1644 )
1645
1646 return ERROR_OK;
1647 }
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