1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
5 * Copyright (C) 2008,2009 Oyvind Harboe oyvind.harboe@zylin.com *
7 * Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
23 ***************************************************************************/
30 #include "breakpoints.h"
31 #include "arm11_dbgtap.h"
32 #include "arm_simulator.h"
33 #include "time_support.h"
34 #include "target_type.h"
35 #include "algorithm.h"
40 #define _DEBUG_INSTRUCTION_EXECUTION_
44 #define FNC_INFO LOG_DEBUG("-")
50 #define FNC_INFO_NOTIMPLEMENTED do { LOG_DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
52 #define FNC_INFO_NOTIMPLEMENTED
55 static bool arm11_config_memwrite_burst
= true;
56 static bool arm11_config_memwrite_error_fatal
= true;
57 static uint32_t arm11_vcr
= 0;
58 static bool arm11_config_step_irq_enable
= false;
59 static bool arm11_config_hardware_step
= false;
76 ARM11_REGISTER_SPSR_FIQ
,
77 ARM11_REGISTER_SPSR_SVC
,
78 ARM11_REGISTER_SPSR_ABT
,
79 ARM11_REGISTER_SPSR_IRQ
,
80 ARM11_REGISTER_SPSR_UND
,
81 ARM11_REGISTER_SPSR_MON
,
95 enum arm11_regtype type
;
98 /* update arm11_regcache_ids when changing this */
99 static const struct arm11_reg_defs arm11_reg_defs
[] =
101 {"r0", 0, 0, ARM11_REGISTER_CORE
},
102 {"r1", 1, 1, ARM11_REGISTER_CORE
},
103 {"r2", 2, 2, ARM11_REGISTER_CORE
},
104 {"r3", 3, 3, ARM11_REGISTER_CORE
},
105 {"r4", 4, 4, ARM11_REGISTER_CORE
},
106 {"r5", 5, 5, ARM11_REGISTER_CORE
},
107 {"r6", 6, 6, ARM11_REGISTER_CORE
},
108 {"r7", 7, 7, ARM11_REGISTER_CORE
},
109 {"r8", 8, 8, ARM11_REGISTER_CORE
},
110 {"r9", 9, 9, ARM11_REGISTER_CORE
},
111 {"r10", 10, 10, ARM11_REGISTER_CORE
},
112 {"r11", 11, 11, ARM11_REGISTER_CORE
},
113 {"r12", 12, 12, ARM11_REGISTER_CORE
},
114 {"sp", 13, 13, ARM11_REGISTER_CORE
},
115 {"lr", 14, 14, ARM11_REGISTER_CORE
},
116 {"pc", 15, 15, ARM11_REGISTER_CORE
},
118 #if ARM11_REGCACHE_FREGS
119 {"f0", 0, 16, ARM11_REGISTER_FX
},
120 {"f1", 1, 17, ARM11_REGISTER_FX
},
121 {"f2", 2, 18, ARM11_REGISTER_FX
},
122 {"f3", 3, 19, ARM11_REGISTER_FX
},
123 {"f4", 4, 20, ARM11_REGISTER_FX
},
124 {"f5", 5, 21, ARM11_REGISTER_FX
},
125 {"f6", 6, 22, ARM11_REGISTER_FX
},
126 {"f7", 7, 23, ARM11_REGISTER_FX
},
127 {"fps", 0, 24, ARM11_REGISTER_FPS
},
130 {"cpsr", 0, 25, ARM11_REGISTER_CPSR
},
132 #if ARM11_REGCACHE_MODEREGS
133 {"r8_fiq", 8, -1, ARM11_REGISTER_FIQ
},
134 {"r9_fiq", 9, -1, ARM11_REGISTER_FIQ
},
135 {"r10_fiq", 10, -1, ARM11_REGISTER_FIQ
},
136 {"r11_fiq", 11, -1, ARM11_REGISTER_FIQ
},
137 {"r12_fiq", 12, -1, ARM11_REGISTER_FIQ
},
138 {"r13_fiq", 13, -1, ARM11_REGISTER_FIQ
},
139 {"r14_fiq", 14, -1, ARM11_REGISTER_FIQ
},
140 {"spsr_fiq", 0, -1, ARM11_REGISTER_SPSR_FIQ
},
142 {"r13_svc", 13, -1, ARM11_REGISTER_SVC
},
143 {"r14_svc", 14, -1, ARM11_REGISTER_SVC
},
144 {"spsr_svc", 0, -1, ARM11_REGISTER_SPSR_SVC
},
146 {"r13_abt", 13, -1, ARM11_REGISTER_ABT
},
147 {"r14_abt", 14, -1, ARM11_REGISTER_ABT
},
148 {"spsr_abt", 0, -1, ARM11_REGISTER_SPSR_ABT
},
150 {"r13_irq", 13, -1, ARM11_REGISTER_IRQ
},
151 {"r14_irq", 14, -1, ARM11_REGISTER_IRQ
},
152 {"spsr_irq", 0, -1, ARM11_REGISTER_SPSR_IRQ
},
154 {"r13_und", 13, -1, ARM11_REGISTER_UND
},
155 {"r14_und", 14, -1, ARM11_REGISTER_UND
},
156 {"spsr_und", 0, -1, ARM11_REGISTER_SPSR_UND
},
159 {"r13_mon", 13, -1, ARM11_REGISTER_MON
},
160 {"r14_mon", 14, -1, ARM11_REGISTER_MON
},
161 {"spsr_mon", 0, -1, ARM11_REGISTER_SPSR_MON
},
164 /* Debug Registers */
165 {"dscr", 0, -1, ARM11_REGISTER_DSCR
},
166 {"wdtr", 0, -1, ARM11_REGISTER_WDTR
},
167 {"rdtr", 0, -1, ARM11_REGISTER_RDTR
},
170 enum arm11_regcache_ids
173 ARM11_RC_RX
= ARM11_RC_R0
,
188 ARM11_RC_SP
= ARM11_RC_R13
,
190 ARM11_RC_LR
= ARM11_RC_R14
,
192 ARM11_RC_PC
= ARM11_RC_R15
,
194 #if ARM11_REGCACHE_FREGS
196 ARM11_RC_FX
= ARM11_RC_F0
,
209 #if ARM11_REGCACHE_MODEREGS
247 #define ARM11_GDB_REGISTER_COUNT 26
249 static int arm11_on_enter_debug_state(struct arm11_common
*arm11
);
250 static int arm11_step(struct target
*target
, int current
,
251 uint32_t address
, int handle_breakpoints
);
253 static int arm11_build_reg_cache(struct target
*target
);
254 static int arm11_set_reg(struct reg
*reg
, uint8_t *buf
);
255 static int arm11_get_reg(struct reg
*reg
);
257 static void arm11_record_register_history(struct arm11_common
* arm11
);
258 static void arm11_dump_reg_changes(struct arm11_common
* arm11
);
261 /** Check and if necessary take control of the system
263 * \param arm11 Target state variable.
264 * \param dscr If the current DSCR content is
265 * available a pointer to a word holding the
266 * DSCR can be passed. Otherwise use NULL.
268 static int arm11_check_init(struct arm11_common
*arm11
, uint32_t *dscr
)
272 uint32_t dscr_local_tmp_copy
;
276 dscr
= &dscr_local_tmp_copy
;
278 CHECK_RETVAL(arm11_read_DSCR(arm11
, dscr
));
281 if (!(*dscr
& ARM11_DSCR_MODE_SELECT
))
283 LOG_DEBUG("Bringing target into debug mode");
285 *dscr
|= ARM11_DSCR_MODE_SELECT
; /* Halt debug-mode */
286 arm11_write_DSCR(arm11
, *dscr
);
288 /* add further reset initialization here */
290 arm11
->simulate_reset_on_next_halt
= true;
292 if (*dscr
& ARM11_DSCR_CORE_HALTED
)
294 /** \todo TODO: this needs further scrutiny because
295 * arm11_on_enter_debug_state() never gets properly called.
296 * As a result we don't read the actual register states from
300 arm11
->target
->state
= TARGET_HALTED
;
301 arm11
->target
->debug_reason
= arm11_get_DSCR_debug_reason(*dscr
);
305 arm11
->target
->state
= TARGET_RUNNING
;
306 arm11
->target
->debug_reason
= DBG_REASON_NOTHALTED
;
309 arm11_sc7_clear_vbw(arm11
);
318 (arm11->reg_values[ARM11_RC_##x])
320 /** Save processor state.
322 * This is called when the HALT instruction has succeeded
323 * or on other occasions that stop the processor.
326 static int arm11_on_enter_debug_state(struct arm11_common
*arm11
)
331 for (size_t i
= 0; i
< ARRAY_SIZE(arm11
->reg_values
); i
++)
333 arm11
->reg_list
[i
].valid
= 1;
334 arm11
->reg_list
[i
].dirty
= 0;
338 CHECK_RETVAL(arm11_read_DSCR(arm11
, &R(DSCR
)));
342 if (R(DSCR
) & ARM11_DSCR_WDTR_FULL
)
344 arm11_add_debug_SCAN_N(arm11
, 0x05, ARM11_TAP_DEFAULT
);
346 arm11_add_IR(arm11
, ARM11_INTEST
, ARM11_TAP_DEFAULT
);
348 struct scan_field chain5_fields
[3];
350 arm11_setup_field(arm11
, 32, NULL
, &R(WDTR
), chain5_fields
+ 0);
351 arm11_setup_field(arm11
, 1, NULL
, NULL
, chain5_fields
+ 1);
352 arm11_setup_field(arm11
, 1, NULL
, NULL
, chain5_fields
+ 2);
354 arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields
), chain5_fields
, TAP_DRPAUSE
);
358 arm11
->reg_list
[ARM11_RC_WDTR
].valid
= 0;
362 /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */
363 /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
364 ARM1136 seems to require this to issue ITR's as well */
366 uint32_t new_dscr
= R(DSCR
) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE
;
368 /* this executes JTAG queue: */
370 arm11_write_DSCR(arm11
, new_dscr
);
374 Before executing any instruction in debug state you have to drain the write buffer.
375 This ensures that no imprecise Data Aborts can return at a later point:*/
377 /** \todo TODO: Test drain write buffer. */
382 /* MRC p14,0,R0,c5,c10,0 */
383 // arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
385 /* mcr 15, 0, r0, cr7, cr10, {4} */
386 arm11_run_instr_no_data1(arm11
, 0xee070f9a);
388 uint32_t dscr
= arm11_read_DSCR(arm11
);
390 LOG_DEBUG("DRAIN, DSCR %08x", dscr
);
392 if (dscr
& ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT
)
394 arm11_run_instr_no_data1(arm11
, 0xe320f000);
396 dscr
= arm11_read_DSCR(arm11
);
398 LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr
);
405 retval
= arm11_run_instr_data_prepare(arm11
);
406 if (retval
!= ERROR_OK
)
411 /** \todo TODO: handle other mode registers */
413 for (size_t i
= 0; i
< 15; i
++)
415 /* MCR p14,0,R?,c0,c5,0 */
416 retval
= arm11_run_instr_data_from_core(arm11
, 0xEE000E15 | (i
<< 12), &R(RX
+ i
), 1);
417 if (retval
!= ERROR_OK
)
423 /* check rDTRfull in DSCR */
425 if (R(DSCR
) & ARM11_DSCR_RDTR_FULL
)
427 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
428 retval
= arm11_run_instr_data_from_core_via_r0(arm11
, 0xEE100E15, &R(RDTR
));
429 if (retval
!= ERROR_OK
)
434 arm11
->reg_list
[ARM11_RC_RDTR
].valid
= 0;
439 /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */
440 retval
= arm11_run_instr_data_from_core_via_r0(arm11
, 0xE10F0000, &R(CPSR
));
441 if (retval
!= ERROR_OK
)
446 /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
447 retval
= arm11_run_instr_data_from_core_via_r0(arm11
, 0xE1A0000F, &R(PC
));
448 if (retval
!= ERROR_OK
)
451 /* adjust PC depending on ARM state */
453 if (R(CPSR
) & ARM11_CPSR_J
) /* Java state */
455 arm11
->reg_values
[ARM11_RC_PC
] -= 0;
457 else if (R(CPSR
) & ARM11_CPSR_T
) /* Thumb state */
459 arm11
->reg_values
[ARM11_RC_PC
] -= 4;
463 arm11
->reg_values
[ARM11_RC_PC
] -= 8;
466 if (arm11
->simulate_reset_on_next_halt
)
468 arm11
->simulate_reset_on_next_halt
= false;
470 LOG_DEBUG("Reset c1 Control Register");
472 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
474 /* MCR p15,0,R0,c1,c0,0 */
475 retval
= arm11_run_instr_data_to_core_via_r0(arm11
, 0xee010f10, 0);
476 if (retval
!= ERROR_OK
)
481 retval
= arm11_run_instr_data_finish(arm11
);
482 if (retval
!= ERROR_OK
)
485 arm11_dump_reg_changes(arm11
);
490 void arm11_dump_reg_changes(struct arm11_common
* arm11
)
493 if (!(debug_level
>= LOG_LVL_DEBUG
))
498 for (size_t i
= 0; i
< ARM11_REGCACHE_COUNT
; i
++)
500 if (!arm11
->reg_list
[i
].valid
)
502 if (arm11
->reg_history
[i
].valid
)
503 LOG_DEBUG("%8s INVALID (%08" PRIx32
")", arm11_reg_defs
[i
].name
, arm11
->reg_history
[i
].value
);
507 if (arm11
->reg_history
[i
].valid
)
509 if (arm11
->reg_history
[i
].value
!= arm11
->reg_values
[i
])
510 LOG_DEBUG("%8s %08" PRIx32
" (%08" PRIx32
")", arm11_reg_defs
[i
].name
, arm11
->reg_values
[i
], arm11
->reg_history
[i
].value
);
514 LOG_DEBUG("%8s %08" PRIx32
" (INVALID)", arm11_reg_defs
[i
].name
, arm11
->reg_values
[i
]);
520 /** Restore processor state
522 * This is called in preparation for the RESTART function.
525 static int arm11_leave_debug_state(struct arm11_common
*arm11
)
530 retval
= arm11_run_instr_data_prepare(arm11
);
531 if (retval
!= ERROR_OK
)
534 /** \todo TODO: handle other mode registers */
536 /* restore R1 - R14 */
538 for (size_t i
= 1; i
< 15; i
++)
540 if (!arm11
->reg_list
[ARM11_RC_RX
+ i
].dirty
)
543 /* MRC p14,0,r?,c0,c5,0 */
544 arm11_run_instr_data_to_core1(arm11
, 0xee100e15 | (i
<< 12), R(RX
+ i
));
546 // LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
549 retval
= arm11_run_instr_data_finish(arm11
);
550 if (retval
!= ERROR_OK
)
553 /* spec says clear wDTR and rDTR; we assume they are clear as
554 otherwise our programming would be sloppy */
558 CHECK_RETVAL(arm11_read_DSCR(arm11
, &DSCR
));
560 if (DSCR
& (ARM11_DSCR_RDTR_FULL
| ARM11_DSCR_WDTR_FULL
))
563 The wDTR/rDTR two registers that are used to send/receive data to/from
564 the core in tandem with corresponding instruction codes that are
565 written into the core. The RDTR FULL/WDTR FULL flag indicates that the
566 registers hold data that was written by one side (CPU or JTAG) and not
567 read out by the other side.
569 LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08" PRIx32
")", DSCR
);
574 retval
= arm11_run_instr_data_prepare(arm11
);
575 if (retval
!= ERROR_OK
)
578 /* restore original wDTR */
580 if ((R(DSCR
) & ARM11_DSCR_WDTR_FULL
) || arm11
->reg_list
[ARM11_RC_WDTR
].dirty
)
582 /* MCR p14,0,R0,c0,c5,0 */
583 retval
= arm11_run_instr_data_to_core_via_r0(arm11
, 0xee000e15, R(WDTR
));
584 if (retval
!= ERROR_OK
)
591 retval
= arm11_run_instr_data_to_core_via_r0(arm11
, 0xe129f000, R(CPSR
));
592 if (retval
!= ERROR_OK
)
599 retval
= arm11_run_instr_data_to_core_via_r0(arm11
, 0xe1a0f000, R(PC
));
600 if (retval
!= ERROR_OK
)
606 /* MRC p14,0,r0,c0,c5,0 */
607 arm11_run_instr_data_to_core1(arm11
, 0xee100e15, R(R0
));
609 retval
= arm11_run_instr_data_finish(arm11
);
610 if (retval
!= ERROR_OK
)
615 arm11_write_DSCR(arm11
, R(DSCR
));
619 if (R(DSCR
) & ARM11_DSCR_RDTR_FULL
|| arm11
->reg_list
[ARM11_RC_RDTR
].dirty
)
621 arm11_add_debug_SCAN_N(arm11
, 0x05, ARM11_TAP_DEFAULT
);
623 arm11_add_IR(arm11
, ARM11_EXTEST
, ARM11_TAP_DEFAULT
);
625 struct scan_field chain5_fields
[3];
627 uint8_t Ready
= 0; /* ignored */
628 uint8_t Valid
= 0; /* ignored */
630 arm11_setup_field(arm11
, 32, &R(RDTR
), NULL
, chain5_fields
+ 0);
631 arm11_setup_field(arm11
, 1, &Ready
, NULL
, chain5_fields
+ 1);
632 arm11_setup_field(arm11
, 1, &Valid
, NULL
, chain5_fields
+ 2);
634 arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields
), chain5_fields
, TAP_DRPAUSE
);
637 arm11_record_register_history(arm11
);
642 static void arm11_record_register_history(struct arm11_common
*arm11
)
644 for (size_t i
= 0; i
< ARM11_REGCACHE_COUNT
; i
++)
646 arm11
->reg_history
[i
].value
= arm11
->reg_values
[i
];
647 arm11
->reg_history
[i
].valid
= arm11
->reg_list
[i
].valid
;
649 arm11
->reg_list
[i
].valid
= 0;
650 arm11
->reg_list
[i
].dirty
= 0;
655 /* poll current target status */
656 static int arm11_poll(struct target
*target
)
660 struct arm11_common
*arm11
= target_to_arm11(target
);
663 CHECK_RETVAL(arm11_read_DSCR(arm11
, &dscr
));
665 LOG_DEBUG("DSCR %08" PRIx32
"", dscr
);
667 CHECK_RETVAL(arm11_check_init(arm11
, &dscr
));
669 if (dscr
& ARM11_DSCR_CORE_HALTED
)
671 if (target
->state
!= TARGET_HALTED
)
673 enum target_state old_state
= target
->state
;
675 LOG_DEBUG("enter TARGET_HALTED");
676 target
->state
= TARGET_HALTED
;
677 target
->debug_reason
= arm11_get_DSCR_debug_reason(dscr
);
678 retval
= arm11_on_enter_debug_state(arm11
);
679 if (retval
!= ERROR_OK
)
682 target_call_event_callbacks(target
,
683 old_state
== TARGET_DEBUG_RUNNING
? TARGET_EVENT_DEBUG_HALTED
: TARGET_EVENT_HALTED
);
688 if (target
->state
!= TARGET_RUNNING
&& target
->state
!= TARGET_DEBUG_RUNNING
)
690 LOG_DEBUG("enter TARGET_RUNNING");
691 target
->state
= TARGET_RUNNING
;
692 target
->debug_reason
= DBG_REASON_NOTHALTED
;
698 /* architecture specific status reply */
699 static int arm11_arch_state(struct target
*target
)
701 struct arm11_common
*arm11
= target_to_arm11(target
);
703 LOG_USER("target halted due to %s\ncpsr: 0x%8.8" PRIx32
" pc: 0x%8.8" PRIx32
"",
704 Jim_Nvp_value2name_simple(nvp_target_debug_reason
, target
->debug_reason
)->name
,
711 /* target request support */
712 static int arm11_target_request_data(struct target
*target
,
713 uint32_t size
, uint8_t *buffer
)
715 FNC_INFO_NOTIMPLEMENTED
;
720 /* target execution control */
721 static int arm11_halt(struct target
*target
)
724 struct arm11_common
*arm11
= target_to_arm11(target
);
726 LOG_DEBUG("target->state: %s",
727 target_state_name(target
));
729 if (target
->state
== TARGET_UNKNOWN
)
731 arm11
->simulate_reset_on_next_halt
= true;
734 if (target
->state
== TARGET_HALTED
)
736 LOG_DEBUG("target was already halted");
740 arm11_add_IR(arm11
, ARM11_HALT
, TAP_IDLE
);
742 CHECK_RETVAL(jtag_execute_queue());
749 CHECK_RETVAL(arm11_read_DSCR(arm11
, &dscr
));
751 if (dscr
& ARM11_DSCR_CORE_HALTED
)
762 if ((timeval_ms()-then
) > 1000)
764 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
771 arm11_on_enter_debug_state(arm11
);
773 enum target_state old_state
= target
->state
;
775 target
->state
= TARGET_HALTED
;
776 target
->debug_reason
= arm11_get_DSCR_debug_reason(dscr
);
779 target_call_event_callbacks(target
,
780 old_state
== TARGET_DEBUG_RUNNING
? TARGET_EVENT_DEBUG_HALTED
: TARGET_EVENT_HALTED
));
785 static int arm11_resume(struct target
*target
, int current
,
786 uint32_t address
, int handle_breakpoints
, int debug_execution
)
790 // LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
791 // current, address, handle_breakpoints, debug_execution);
793 struct arm11_common
*arm11
= target_to_arm11(target
);
795 LOG_DEBUG("target->state: %s",
796 target_state_name(target
));
799 if (target
->state
!= TARGET_HALTED
)
801 LOG_ERROR("Target not halted");
802 return ERROR_TARGET_NOT_HALTED
;
808 LOG_DEBUG("RESUME PC %08" PRIx32
"%s", R(PC
), !current
? "!" : "");
810 /* clear breakpoints/watchpoints and VCR*/
811 arm11_sc7_clear_vbw(arm11
);
813 /* Set up breakpoints */
814 if (!debug_execution
)
816 /* check if one matches PC and step over it if necessary */
818 struct breakpoint
* bp
;
820 for (bp
= target
->breakpoints
; bp
; bp
= bp
->next
)
822 if (bp
->address
== R(PC
))
824 LOG_DEBUG("must step over %08" PRIx32
"", bp
->address
);
825 arm11_step(target
, 1, 0, 0);
830 /* set all breakpoints */
834 for (bp
= target
->breakpoints
; bp
; bp
= bp
->next
)
836 struct arm11_sc7_action brp
[2];
839 brp
[0].address
= ARM11_SC7_BVR0
+ brp_num
;
840 brp
[0].value
= bp
->address
;
842 brp
[1].address
= ARM11_SC7_BCR0
+ brp_num
;
843 brp
[1].value
= 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
845 arm11_sc7_run(arm11
, brp
, ARRAY_SIZE(brp
));
847 LOG_DEBUG("Add BP " ZU
" at %08" PRIx32
"", brp_num
, bp
->address
);
852 arm11_sc7_set_vcr(arm11
, arm11_vcr
);
855 arm11_leave_debug_state(arm11
);
857 arm11_add_IR(arm11
, ARM11_RESTART
, TAP_IDLE
);
859 CHECK_RETVAL(jtag_execute_queue());
866 CHECK_RETVAL(arm11_read_DSCR(arm11
, &dscr
));
868 LOG_DEBUG("DSCR %08" PRIx32
"", dscr
);
870 if (dscr
& ARM11_DSCR_CORE_RESTARTED
)
881 if ((timeval_ms()-then
) > 1000)
883 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
890 if (!debug_execution
)
892 target
->state
= TARGET_RUNNING
;
893 target
->debug_reason
= DBG_REASON_NOTHALTED
;
895 CHECK_RETVAL(target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
));
899 target
->state
= TARGET_DEBUG_RUNNING
;
900 target
->debug_reason
= DBG_REASON_NOTHALTED
;
902 CHECK_RETVAL(target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
));
909 static int armv4_5_to_arm11(int reg
)
916 return ARM11_RC_CPSR
;
918 /* FIX!!! handle thumb better! */
919 return ARM11_RC_CPSR
;
921 LOG_ERROR("BUG: register translation from armv4_5 to arm11 not supported %d", reg
);
927 static uint32_t arm11_sim_get_reg(struct arm_sim_interface
*sim
, int reg
)
929 struct arm11_common
* arm11
= (struct arm11_common
*)sim
->user_data
;
931 reg
=armv4_5_to_arm11(reg
);
933 return buf_get_u32(arm11
->reg_list
[reg
].value
, 0, 32);
936 static void arm11_sim_set_reg(struct arm_sim_interface
*sim
,
937 int reg
, uint32_t value
)
939 struct arm11_common
* arm11
= (struct arm11_common
*)sim
->user_data
;
941 reg
=armv4_5_to_arm11(reg
);
943 buf_set_u32(arm11
->reg_list
[reg
].value
, 0, 32, value
);
946 static uint32_t arm11_sim_get_cpsr(struct arm_sim_interface
*sim
,
949 struct arm11_common
* arm11
= (struct arm11_common
*)sim
->user_data
;
951 return buf_get_u32(arm11
->reg_list
[ARM11_RC_CPSR
].value
, pos
, bits
);
954 static enum armv4_5_state
arm11_sim_get_state(struct arm_sim_interface
*sim
)
956 // struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
958 /* FIX!!!! we should implement thumb for arm11 */
959 return ARMV4_5_STATE_ARM
;
962 static void arm11_sim_set_state(struct arm_sim_interface
*sim
,
963 enum armv4_5_state mode
)
965 // struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
967 /* FIX!!!! we should implement thumb for arm11 */
968 LOG_ERROR("Not implemetned!");
972 static enum armv4_5_mode
arm11_sim_get_mode(struct arm_sim_interface
*sim
)
974 //struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
976 /* FIX!!!! we should implement something that returns the current mode here!!! */
977 return ARMV4_5_MODE_USR
;
980 static int arm11_simulate_step(struct target
*target
, uint32_t *dry_run_pc
)
982 struct arm_sim_interface sim
;
984 sim
.user_data
=target
->arch_info
;
985 sim
.get_reg
=&arm11_sim_get_reg
;
986 sim
.set_reg
=&arm11_sim_set_reg
;
987 sim
.get_reg_mode
=&arm11_sim_get_reg
;
988 sim
.set_reg_mode
=&arm11_sim_set_reg
;
989 sim
.get_cpsr
=&arm11_sim_get_cpsr
;
990 sim
.get_mode
=&arm11_sim_get_mode
;
991 sim
.get_state
=&arm11_sim_get_state
;
992 sim
.set_state
=&arm11_sim_set_state
;
994 return arm_simulate_step_core(target
, dry_run_pc
, &sim
);
998 static int arm11_step(struct target
*target
, int current
,
999 uint32_t address
, int handle_breakpoints
)
1003 LOG_DEBUG("target->state: %s",
1004 target_state_name(target
));
1006 if (target
->state
!= TARGET_HALTED
)
1008 LOG_WARNING("target was not halted");
1009 return ERROR_TARGET_NOT_HALTED
;
1012 struct arm11_common
*arm11
= target_to_arm11(target
);
1017 LOG_DEBUG("STEP PC %08" PRIx32
"%s", R(PC
), !current
? "!" : "");
1020 /** \todo TODO: Thumb not supported here */
1022 uint32_t next_instruction
;
1024 CHECK_RETVAL(arm11_read_memory_word(arm11
, R(PC
), &next_instruction
));
1026 /* skip over BKPT */
1027 if ((next_instruction
& 0xFFF00070) == 0xe1200070)
1030 arm11
->reg_list
[ARM11_RC_PC
].valid
= 1;
1031 arm11
->reg_list
[ARM11_RC_PC
].dirty
= 0;
1032 LOG_DEBUG("Skipping BKPT");
1034 /* skip over Wait for interrupt / Standby */
1035 /* mcr 15, 0, r?, cr7, cr0, {4} */
1036 else if ((next_instruction
& 0xFFFF0FFF) == 0xee070f90)
1039 arm11
->reg_list
[ARM11_RC_PC
].valid
= 1;
1040 arm11
->reg_list
[ARM11_RC_PC
].dirty
= 0;
1041 LOG_DEBUG("Skipping WFI");
1043 /* ignore B to self */
1044 else if ((next_instruction
& 0xFEFFFFFF) == 0xeafffffe)
1046 LOG_DEBUG("Not stepping jump to self");
1050 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
1053 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
1054 * the VCR might be something worth looking into. */
1057 /* Set up breakpoint for stepping */
1059 struct arm11_sc7_action brp
[2];
1062 brp
[0].address
= ARM11_SC7_BVR0
;
1064 brp
[1].address
= ARM11_SC7_BCR0
;
1066 if (arm11_config_hardware_step
)
1068 /* hardware single stepping be used if possible or is it better to
1069 * always use the same code path? Hardware single stepping is not supported
1072 brp
[0].value
= R(PC
);
1073 brp
[1].value
= 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
1076 /* sets a breakpoint on the next PC(calculated by simulation),
1080 retval
= arm11_simulate_step(target
, &next_pc
);
1081 if (retval
!= ERROR_OK
)
1084 brp
[0].value
= next_pc
;
1085 brp
[1].value
= 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
1088 CHECK_RETVAL(arm11_sc7_run(arm11
, brp
, ARRAY_SIZE(brp
)));
1093 if (arm11_config_step_irq_enable
)
1094 R(DSCR
) &= ~ARM11_DSCR_INTERRUPTS_DISABLE
; /* should be redundant */
1096 R(DSCR
) |= ARM11_DSCR_INTERRUPTS_DISABLE
;
1099 CHECK_RETVAL(arm11_leave_debug_state(arm11
));
1101 arm11_add_IR(arm11
, ARM11_RESTART
, TAP_IDLE
);
1103 CHECK_RETVAL(jtag_execute_queue());
1111 CHECK_RETVAL(arm11_read_DSCR(arm11
, &dscr
));
1113 LOG_DEBUG("DSCR %08" PRIx32
"e", dscr
);
1115 if ((dscr
& (ARM11_DSCR_CORE_RESTARTED
| ARM11_DSCR_CORE_HALTED
)) ==
1116 (ARM11_DSCR_CORE_RESTARTED
| ARM11_DSCR_CORE_HALTED
))
1122 then
= timeval_ms();
1126 if ((timeval_ms()-then
) > 1000)
1128 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
1135 /* clear breakpoint */
1136 arm11_sc7_clear_vbw(arm11
);
1139 CHECK_RETVAL(arm11_on_enter_debug_state(arm11
));
1141 /* restore default state */
1142 R(DSCR
) &= ~ARM11_DSCR_INTERRUPTS_DISABLE
;
1146 // target->state = TARGET_HALTED;
1147 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1149 CHECK_RETVAL(target_call_event_callbacks(target
, TARGET_EVENT_HALTED
));
1154 static int arm11_assert_reset(struct target
*target
)
1158 struct arm11_common
*arm11
= target_to_arm11(target
);
1160 retval
= arm11_check_init(arm11
, NULL
);
1161 if (retval
!= ERROR_OK
)
1164 target
->state
= TARGET_UNKNOWN
;
1166 /* we would very much like to reset into the halted, state,
1167 * but resetting and halting is second best... */
1168 if (target
->reset_halt
)
1170 CHECK_RETVAL(target_halt(target
));
1174 /* srst is funny. We can not do *anything* else while it's asserted
1175 * and it has unkonwn side effects. Make sure no other code runs
1178 * Code below assumes srst:
1180 * - Causes power-on-reset (but of what parts of the system?). Bug
1183 * - Messes us TAP state without asserting trst.
1185 * - There is another bug in the arm11 core. When you generate an access to
1186 * external logic (for example ddr controller via AHB bus) and that block
1187 * is not configured (perhaps it is still held in reset), that transaction
1188 * will never complete. This will hang arm11 core but it will also hang
1189 * JTAG controller. Nothing, short of srst assertion will bring it out of
1194 * - What should the PC be after an srst reset when starting in the halted
1198 jtag_add_reset(0, 1);
1199 jtag_add_reset(0, 0);
1201 /* How long do we have to wait? */
1202 jtag_add_sleep(5000);
1204 /* un-mess up TAP state */
1207 retval
= jtag_execute_queue();
1208 if (retval
!= ERROR_OK
)
1216 static int arm11_deassert_reset(struct target
*target
)
1221 static int arm11_soft_reset_halt(struct target
*target
)
1223 FNC_INFO_NOTIMPLEMENTED
;
1228 /* target register access for gdb */
1229 static int arm11_get_gdb_reg_list(struct target
*target
,
1230 struct reg
**reg_list
[], int *reg_list_size
)
1233 struct arm11_common
*arm11
= target_to_arm11(target
);
1235 *reg_list_size
= ARM11_GDB_REGISTER_COUNT
;
1236 *reg_list
= malloc(sizeof(struct reg
*) * ARM11_GDB_REGISTER_COUNT
);
1238 /* nine unused legacy FPA registers are expected by GDB */
1239 for (size_t i
= 16; i
< 24; i
++)
1240 (*reg_list
)[i
] = &arm_gdb_dummy_fp_reg
;
1241 (*reg_list
)[24] = &arm_gdb_dummy_fps_reg
;
1243 for (size_t i
= 0; i
< ARM11_REGCACHE_COUNT
; i
++)
1245 if (arm11_reg_defs
[i
].gdb_num
== -1)
1248 (*reg_list
)[arm11_reg_defs
[i
].gdb_num
] = arm11
->reg_list
+ i
;
1254 /* target memory access
1255 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
1256 * count: number of items of <size>
1258 * arm11_config_memrw_no_increment - in the future we may want to be able
1259 * to read/write a range of data to a "port". a "port" is an action on
1260 * read memory address for some peripheral.
1262 static int arm11_read_memory_inner(struct target
*target
,
1263 uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
,
1264 bool arm11_config_memrw_no_increment
)
1266 /** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment problems */
1271 if (target
->state
!= TARGET_HALTED
)
1273 LOG_WARNING("target was not halted");
1274 return ERROR_TARGET_NOT_HALTED
;
1277 LOG_DEBUG("ADDR %08" PRIx32
" SIZE %08" PRIx32
" COUNT %08" PRIx32
"", address
, size
, count
);
1279 struct arm11_common
*arm11
= target_to_arm11(target
);
1281 retval
= arm11_run_instr_data_prepare(arm11
);
1282 if (retval
!= ERROR_OK
)
1285 /* MRC p14,0,r0,c0,c5,0 */
1286 retval
= arm11_run_instr_data_to_core1(arm11
, 0xee100e15, address
);
1287 if (retval
!= ERROR_OK
)
1293 /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
1294 arm11
->reg_list
[ARM11_RC_R1
].dirty
= 1;
1296 for (size_t i
= 0; i
< count
; i
++)
1298 /* ldrb r1, [r0], #1 */
1300 arm11_run_instr_no_data1(arm11
,
1301 !arm11_config_memrw_no_increment
? 0xe4d01001 : 0xe5d01000);
1304 /* MCR p14,0,R1,c0,c5,0 */
1305 arm11_run_instr_data_from_core(arm11
, 0xEE001E15, &res
, 1);
1314 arm11
->reg_list
[ARM11_RC_R1
].dirty
= 1;
1316 for (size_t i
= 0; i
< count
; i
++)
1318 /* ldrh r1, [r0], #2 */
1319 arm11_run_instr_no_data1(arm11
,
1320 !arm11_config_memrw_no_increment
? 0xe0d010b2 : 0xe1d010b0);
1324 /* MCR p14,0,R1,c0,c5,0 */
1325 arm11_run_instr_data_from_core(arm11
, 0xEE001E15, &res
, 1);
1327 uint16_t svalue
= res
;
1328 memcpy(buffer
+ i
* sizeof(uint16_t), &svalue
, sizeof(uint16_t));
1336 uint32_t instr
= !arm11_config_memrw_no_increment
? 0xecb05e01 : 0xed905e00;
1337 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1338 uint32_t *words
= (uint32_t *)buffer
;
1340 /* LDC p14,c5,[R0],#4 */
1341 /* LDC p14,c5,[R0] */
1342 arm11_run_instr_data_from_core(arm11
, instr
, words
, count
);
1347 return arm11_run_instr_data_finish(arm11
);
1350 static int arm11_read_memory(struct target
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
1352 return arm11_read_memory_inner(target
, address
, size
, count
, buffer
, false);
1356 * arm11_config_memrw_no_increment - in the future we may want to be able
1357 * to read/write a range of data to a "port". a "port" is an action on
1358 * read memory address for some peripheral.
1360 static int arm11_write_memory_inner(struct target
*target
,
1361 uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
,
1362 bool arm11_config_memrw_no_increment
)
1367 if (target
->state
!= TARGET_HALTED
)
1369 LOG_WARNING("target was not halted");
1370 return ERROR_TARGET_NOT_HALTED
;
1373 LOG_DEBUG("ADDR %08" PRIx32
" SIZE %08" PRIx32
" COUNT %08" PRIx32
"", address
, size
, count
);
1375 struct arm11_common
*arm11
= target_to_arm11(target
);
1377 retval
= arm11_run_instr_data_prepare(arm11
);
1378 if (retval
!= ERROR_OK
)
1381 /* MRC p14,0,r0,c0,c5,0 */
1382 retval
= arm11_run_instr_data_to_core1(arm11
, 0xee100e15, address
);
1383 if (retval
!= ERROR_OK
)
1386 /* burst writes are not used for single words as those may well be
1387 * reset init script writes.
1389 * The other advantage is that as burst writes are default, we'll
1390 * now exercise both burst and non-burst code paths with the
1391 * default settings, increasing code coverage.
1393 bool burst
= arm11_config_memwrite_burst
&& (count
> 1);
1399 arm11
->reg_list
[ARM11_RC_R1
].dirty
= 1;
1401 for (size_t i
= 0; i
< count
; i
++)
1403 /* MRC p14,0,r1,c0,c5,0 */
1404 retval
= arm11_run_instr_data_to_core1(arm11
, 0xee101e15, *buffer
++);
1405 if (retval
!= ERROR_OK
)
1408 /* strb r1, [r0], #1 */
1410 retval
= arm11_run_instr_no_data1(arm11
,
1411 !arm11_config_memrw_no_increment
? 0xe4c01001 : 0xe5c01000);
1412 if (retval
!= ERROR_OK
)
1421 arm11
->reg_list
[ARM11_RC_R1
].dirty
= 1;
1423 for (size_t i
= 0; i
< count
; i
++)
1426 memcpy(&value
, buffer
+ i
* sizeof(uint16_t), sizeof(uint16_t));
1428 /* MRC p14,0,r1,c0,c5,0 */
1429 retval
= arm11_run_instr_data_to_core1(arm11
, 0xee101e15, value
);
1430 if (retval
!= ERROR_OK
)
1433 /* strh r1, [r0], #2 */
1435 retval
= arm11_run_instr_no_data1(arm11
,
1436 !arm11_config_memrw_no_increment
? 0xe0c010b2 : 0xe1c010b0);
1437 if (retval
!= ERROR_OK
)
1445 uint32_t instr
= !arm11_config_memrw_no_increment
? 0xeca05e01 : 0xed805e00;
1447 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1448 uint32_t *words
= (uint32_t*)buffer
;
1452 /* STC p14,c5,[R0],#4 */
1453 /* STC p14,c5,[R0]*/
1454 retval
= arm11_run_instr_data_to_core(arm11
, instr
, words
, count
);
1455 if (retval
!= ERROR_OK
)
1460 /* STC p14,c5,[R0],#4 */
1461 /* STC p14,c5,[R0]*/
1462 retval
= arm11_run_instr_data_to_core_noack(arm11
, instr
, words
, count
);
1463 if (retval
!= ERROR_OK
)
1471 /* r0 verification */
1472 if (!arm11_config_memrw_no_increment
)
1476 /* MCR p14,0,R0,c0,c5,0 */
1477 retval
= arm11_run_instr_data_from_core(arm11
, 0xEE000E15, &r0
, 1);
1478 if (retval
!= ERROR_OK
)
1481 if (address
+ size
* count
!= r0
)
1483 LOG_ERROR("Data transfer failed. Expected end "
1484 "address 0x%08x, got 0x%08x",
1485 (unsigned) (address
+ size
* count
),
1489 LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1491 if (arm11_config_memwrite_error_fatal
)
1496 return arm11_run_instr_data_finish(arm11
);
1499 static int arm11_write_memory(struct target
*target
,
1500 uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
1502 return arm11_write_memory_inner(target
, address
, size
, count
, buffer
, false);
1505 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1506 static int arm11_bulk_write_memory(struct target
*target
,
1507 uint32_t address
, uint32_t count
, uint8_t *buffer
)
1511 if (target
->state
!= TARGET_HALTED
)
1513 LOG_WARNING("target was not halted");
1514 return ERROR_TARGET_NOT_HALTED
;
1517 return arm11_write_memory(target
, address
, 4, count
, buffer
);
1520 /* target break-/watchpoint control
1521 * rw: 0 = write, 1 = read, 2 = access
1523 static int arm11_add_breakpoint(struct target
*target
,
1524 struct breakpoint
*breakpoint
)
1527 struct arm11_common
*arm11
= target_to_arm11(target
);
1530 if (breakpoint
->type
== BKPT_SOFT
)
1532 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
1533 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1537 if (!arm11
->free_brps
)
1539 LOG_DEBUG("no breakpoint unit available for hardware breakpoint");
1540 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1543 if (breakpoint
->length
!= 4)
1545 LOG_DEBUG("only breakpoints of four bytes length supported");
1546 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1554 static int arm11_remove_breakpoint(struct target
*target
,
1555 struct breakpoint
*breakpoint
)
1558 struct arm11_common
*arm11
= target_to_arm11(target
);
1565 static int arm11_add_watchpoint(struct target
*target
,
1566 struct watchpoint
*watchpoint
)
1568 FNC_INFO_NOTIMPLEMENTED
;
1573 static int arm11_remove_watchpoint(struct target
*target
,
1574 struct watchpoint
*watchpoint
)
1576 FNC_INFO_NOTIMPLEMENTED
;
1581 // HACKHACKHACK - FIXME mode/state
1582 /* target algorithm support */
1583 static int arm11_run_algorithm(struct target
*target
,
1584 int num_mem_params
, struct mem_param
*mem_params
,
1585 int num_reg_params
, struct reg_param
*reg_params
,
1586 uint32_t entry_point
, uint32_t exit_point
,
1587 int timeout_ms
, void *arch_info
)
1589 struct arm11_common
*arm11
= target_to_arm11(target
);
1590 // enum armv4_5_state core_state = arm11->core_state;
1591 // enum armv4_5_mode core_mode = arm11->core_mode;
1592 uint32_t context
[16];
1594 int exit_breakpoint_size
= 0;
1595 int retval
= ERROR_OK
;
1596 LOG_DEBUG("Running algorithm");
1599 if (target
->state
!= TARGET_HALTED
)
1601 LOG_WARNING("target not halted");
1602 return ERROR_TARGET_NOT_HALTED
;
1606 // if (!is_arm_mode(arm11->core_mode))
1607 // return ERROR_FAIL;
1610 for (unsigned i
= 0; i
< 16; i
++)
1612 context
[i
] = buf_get_u32((uint8_t*)(&arm11
->reg_values
[i
]),0,32);
1613 LOG_DEBUG("Save %u: 0x%" PRIx32
"", i
, context
[i
]);
1616 cpsr
= buf_get_u32((uint8_t*)(arm11
->reg_values
+ ARM11_RC_CPSR
),0,32);
1617 LOG_DEBUG("Save CPSR: 0x%" PRIx32
"", cpsr
);
1619 for (int i
= 0; i
< num_mem_params
; i
++)
1621 target_write_buffer(target
, mem_params
[i
].address
, mem_params
[i
].size
, mem_params
[i
].value
);
1624 // Set register parameters
1625 for (int i
= 0; i
< num_reg_params
; i
++)
1627 struct reg
*reg
= register_get_by_name(arm11
->core_cache
, reg_params
[i
].reg_name
, 0);
1630 LOG_ERROR("BUG: register '%s' not found", reg_params
[i
].reg_name
);
1631 return ERROR_INVALID_ARGUMENTS
;
1634 if (reg
->size
!= reg_params
[i
].size
)
1636 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params
[i
].reg_name
);
1637 return ERROR_INVALID_ARGUMENTS
;
1639 arm11_set_reg(reg
,reg_params
[i
].value
);
1640 // printf("%i: Set %s =%08x\n", i, reg_params[i].reg_name,val);
1643 exit_breakpoint_size
= 4;
1645 /* arm11->core_state = arm11_algorithm_info->core_state;
1646 if (arm11->core_state == ARMV4_5_STATE_ARM)
1647 exit_breakpoint_size = 4;
1648 else if (arm11->core_state == ARMV4_5_STATE_THUMB)
1649 exit_breakpoint_size = 2;
1652 LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
1658 /* arm11 at this point only supports ARM not THUMB mode
1659 however if this test needs to be reactivated the current state can be read back
1662 if (arm11_algorithm_info
->core_mode
!= ARMV4_5_MODE_ANY
)
1664 LOG_DEBUG("setting core_mode: 0x%2.2x", arm11_algorithm_info
->core_mode
);
1665 buf_set_u32(arm11
->reg_list
[ARM11_RC_CPSR
].value
, 0, 5, arm11_algorithm_info
->core_mode
);
1666 arm11
->reg_list
[ARM11_RC_CPSR
].dirty
= 1;
1667 arm11
->reg_list
[ARM11_RC_CPSR
].valid
= 1;
1671 if ((retval
= breakpoint_add(target
, exit_point
, exit_breakpoint_size
, BKPT_HARD
)) != ERROR_OK
)
1673 LOG_ERROR("can't add breakpoint to finish algorithm execution");
1674 retval
= ERROR_TARGET_FAILURE
;
1678 // no debug, otherwise breakpoint is not set
1679 CHECK_RETVAL(target_resume(target
, 0, entry_point
, 1, 0));
1681 CHECK_RETVAL(target_wait_state(target
, TARGET_HALTED
, timeout_ms
));
1683 if (target
->state
!= TARGET_HALTED
)
1685 CHECK_RETVAL(target_halt(target
));
1687 CHECK_RETVAL(target_wait_state(target
, TARGET_HALTED
, 500));
1689 retval
= ERROR_TARGET_TIMEOUT
;
1691 goto del_breakpoint
;
1694 if (buf_get_u32(arm11
->reg_list
[15].value
, 0, 32) != exit_point
)
1696 LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32
"",
1697 buf_get_u32(arm11
->reg_list
[15].value
, 0, 32));
1698 retval
= ERROR_TARGET_TIMEOUT
;
1699 goto del_breakpoint
;
1702 for (int i
= 0; i
< num_mem_params
; i
++)
1704 if (mem_params
[i
].direction
!= PARAM_OUT
)
1705 target_read_buffer(target
, mem_params
[i
].address
, mem_params
[i
].size
, mem_params
[i
].value
);
1708 for (int i
= 0; i
< num_reg_params
; i
++)
1710 if (reg_params
[i
].direction
!= PARAM_OUT
)
1712 struct reg
*reg
= register_get_by_name(arm11
->core_cache
, reg_params
[i
].reg_name
, 0);
1715 LOG_ERROR("BUG: register '%s' not found", reg_params
[i
].reg_name
);
1716 retval
= ERROR_INVALID_ARGUMENTS
;
1717 goto del_breakpoint
;
1720 if (reg
->size
!= reg_params
[i
].size
)
1722 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params
[i
].reg_name
);
1723 retval
= ERROR_INVALID_ARGUMENTS
;
1724 goto del_breakpoint
;
1727 buf_set_u32(reg_params
[i
].value
, 0, 32, buf_get_u32(reg
->value
, 0, 32));
1732 breakpoint_remove(target
, exit_point
);
1736 for (size_t i
= 0; i
< 16; i
++)
1738 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32
"",
1739 arm11
->reg_list
[i
].name
, context
[i
]);
1740 arm11_set_reg(&arm11
->reg_list
[i
], (uint8_t*)&context
[i
]);
1742 LOG_DEBUG("restoring CPSR with value 0x%8.8" PRIx32
"", cpsr
);
1743 arm11_set_reg(&arm11
->reg_list
[ARM11_RC_CPSR
], (uint8_t*)&cpsr
);
1745 // arm11->core_state = core_state;
1746 // arm11->core_mode = core_mode;
1751 static int arm11_target_create(struct target
*target
, Jim_Interp
*interp
)
1755 NEW(struct arm11_common
, arm11
, 1);
1757 arm11
->target
= target
;
1759 if (target
->tap
== NULL
)
1762 if (target
->tap
->ir_length
!= 5)
1764 LOG_ERROR("'target arm11' expects IR LENGTH = 5");
1765 return ERROR_COMMAND_SYNTAX_ERROR
;
1768 armv4_5_init_arch_info(target
, &arm11
->arm
);
1770 arm11
->jtag_info
.tap
= target
->tap
;
1771 arm11
->jtag_info
.scann_size
= 5;
1772 arm11
->jtag_info
.scann_instr
= ARM11_SCAN_N
;
1773 /* cur_scan_chain == 0 */
1774 arm11
->jtag_info
.intest_instr
= ARM11_INTEST
;
1779 static int arm11_init_target(struct command_context
*cmd_ctx
,
1780 struct target
*target
)
1782 /* Initialize anything we can set up without talking to the target */
1784 /* FIXME Switch to use the standard build_reg_cache() not custom
1785 * code. Do it from examine(), after we check whether we're
1786 * an arm1176 and thus support the Secure Monitor mode.
1788 return arm11_build_reg_cache(target
);
1791 /* talk to the target and set things up */
1792 static int arm11_examine(struct target
*target
)
1797 struct arm11_common
*arm11
= target_to_arm11(target
);
1801 arm11_add_IR(arm11
, ARM11_IDCODE
, ARM11_TAP_DEFAULT
);
1803 struct scan_field idcode_field
;
1805 arm11_setup_field(arm11
, 32, NULL
, &arm11
->device_id
, &idcode_field
);
1807 arm11_add_dr_scan_vc(1, &idcode_field
, TAP_DRPAUSE
);
1811 arm11_add_debug_SCAN_N(arm11
, 0x00, ARM11_TAP_DEFAULT
);
1813 arm11_add_IR(arm11
, ARM11_INTEST
, ARM11_TAP_DEFAULT
);
1815 struct scan_field chain0_fields
[2];
1817 arm11_setup_field(arm11
, 32, NULL
, &arm11
->didr
, chain0_fields
+ 0);
1818 arm11_setup_field(arm11
, 8, NULL
, &arm11
->implementor
, chain0_fields
+ 1);
1820 arm11_add_dr_scan_vc(ARRAY_SIZE(chain0_fields
), chain0_fields
, TAP_IDLE
);
1822 CHECK_RETVAL(jtag_execute_queue());
1824 switch (arm11
->device_id
& 0x0FFFF000)
1833 arm11
->arm
.core_type
= ARM_MODE_MON
;
1837 LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1840 LOG_INFO("found %s", type
);
1842 arm11
->debug_version
= (arm11
->didr
>> 16) & 0x0F;
1844 if (arm11
->debug_version
!= ARM11_DEBUG_V6
&&
1845 arm11
->debug_version
!= ARM11_DEBUG_V61
)
1847 LOG_ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
1851 arm11
->brp
= ((arm11
->didr
>> 24) & 0x0F) + 1;
1852 arm11
->wrp
= ((arm11
->didr
>> 28) & 0x0F) + 1;
1854 /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1855 arm11
->free_brps
= arm11
->brp
;
1856 arm11
->free_wrps
= arm11
->wrp
;
1858 LOG_DEBUG("IDCODE %08" PRIx32
" IMPLEMENTOR %02x DIDR %08" PRIx32
"",
1860 (int)(arm11
->implementor
),
1863 /* as a side-effect this reads DSCR and thus
1864 * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1865 * as suggested by the spec.
1868 retval
= arm11_check_init(arm11
, NULL
);
1869 if (retval
!= ERROR_OK
)
1872 /* ETM on ARM11 still uses original scanchain 6 access mode */
1873 if (arm11
->arm
.etm
&& !target_was_examined(target
)) {
1874 *register_get_last_cache_p(&target
->reg_cache
) =
1875 etm_build_reg_cache(target
, &arm11
->jtag_info
,
1877 retval
= etm_setup(target
);
1880 target_set_examined(target
);
1886 /** Load a register that is marked !valid in the register cache */
1887 static int arm11_get_reg(struct reg
*reg
)
1891 struct target
* target
= ((struct arm11_reg_state
*)reg
->arch_info
)->target
;
1893 if (target
->state
!= TARGET_HALTED
)
1895 LOG_WARNING("target was not halted");
1896 return ERROR_TARGET_NOT_HALTED
;
1899 /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
1902 struct arm11_common
*arm11
= target_to_arm11(target
);
1903 const struct arm11_reg_defs
*arm11_reg_info
= arm11_reg_defs
+ ((struct arm11_reg_state
*)reg
->arch_info
)->def_index
;
1909 /** Change a value in the register cache */
1910 static int arm11_set_reg(struct reg
*reg
, uint8_t *buf
)
1914 struct target
*target
= ((struct arm11_reg_state
*)reg
->arch_info
)->target
;
1915 struct arm11_common
*arm11
= target_to_arm11(target
);
1916 // const struct arm11_reg_defs *arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index;
1918 arm11
->reg_values
[((struct arm11_reg_state
*)reg
->arch_info
)->def_index
] = buf_get_u32(buf
, 0, 32);
1925 static const struct reg_arch_type arm11_reg_type
= {
1926 .get
= arm11_get_reg
,
1927 .set
= arm11_set_reg
,
1930 static int arm11_build_reg_cache(struct target
*target
)
1932 struct arm11_common
*arm11
= target_to_arm11(target
);
1934 NEW(struct reg_cache
, cache
, 1);
1935 NEW(struct reg
, reg_list
, ARM11_REGCACHE_COUNT
);
1936 NEW(struct arm11_reg_state
, arm11_reg_states
, ARM11_REGCACHE_COUNT
);
1938 arm11
->reg_list
= reg_list
;
1940 /* Build the process context cache */
1941 cache
->name
= "arm11 registers";
1943 cache
->reg_list
= reg_list
;
1944 cache
->num_regs
= ARM11_REGCACHE_COUNT
;
1946 struct reg_cache
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
1949 arm11
->core_cache
= cache
;
1950 // armv7m->process_context = cache;
1954 /* Not very elegant assertion */
1955 if (ARM11_REGCACHE_COUNT
!= ARRAY_SIZE(arm11
->reg_values
) ||
1956 ARM11_REGCACHE_COUNT
!= ARRAY_SIZE(arm11_reg_defs
) ||
1957 ARM11_REGCACHE_COUNT
!= ARM11_RC_MAX
)
1959 LOG_ERROR("BUG: arm11->reg_values inconsistent (%d " ZU
" " ZU
" %d)", ARM11_REGCACHE_COUNT
, ARRAY_SIZE(arm11
->reg_values
), ARRAY_SIZE(arm11_reg_defs
), ARM11_RC_MAX
);
1963 for (i
= 0; i
< ARM11_REGCACHE_COUNT
; i
++)
1965 struct reg
* r
= reg_list
+ i
;
1966 const struct arm11_reg_defs
* rd
= arm11_reg_defs
+ i
;
1967 struct arm11_reg_state
* rs
= arm11_reg_states
+ i
;
1971 r
->value
= (uint8_t *)(arm11
->reg_values
+ i
);
1974 r
->type
= &arm11_reg_type
;
1978 rs
->target
= target
;
1984 #define ARM11_BOOL_WRAPPER(name, print_name) \
1985 COMMAND_HANDLER(arm11_handle_bool_##name) \
1987 return CALL_COMMAND_HANDLER(handle_command_parse_bool, \
1988 &arm11_config_##name, print_name); \
1991 ARM11_BOOL_WRAPPER(memwrite_burst
, "memory write burst mode")
1992 ARM11_BOOL_WRAPPER(memwrite_error_fatal
, "fatal error mode for memory writes")
1993 ARM11_BOOL_WRAPPER(step_irq_enable
, "IRQs while stepping")
1994 ARM11_BOOL_WRAPPER(hardware_step
, "hardware single step")
1996 COMMAND_HANDLER(arm11_handle_vcr
)
2002 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], arm11_vcr
);
2005 return ERROR_COMMAND_SYNTAX_ERROR
;
2008 LOG_INFO("VCR 0x%08" PRIx32
"", arm11_vcr
);
2012 static const uint32_t arm11_coproc_instruction_limits
[] =
2014 15, /* coprocessor */
2019 0xFFFFFFFF, /* value */
2022 static int arm11_mrc_inner(struct target
*target
, int cpnum
,
2023 uint32_t op1
, uint32_t op2
, uint32_t CRn
, uint32_t CRm
,
2024 uint32_t *value
, bool read
)
2027 struct arm11_common
*arm11
= target_to_arm11(target
);
2029 if (target
->state
!= TARGET_HALTED
)
2031 LOG_ERROR("Target not halted");
2035 uint32_t instr
= 0xEE000010 |
2043 instr
|= 0x00100000;
2045 retval
= arm11_run_instr_data_prepare(arm11
);
2046 if (retval
!= ERROR_OK
)
2051 retval
= arm11_run_instr_data_from_core_via_r0(arm11
, instr
, value
);
2052 if (retval
!= ERROR_OK
)
2057 retval
= arm11_run_instr_data_to_core_via_r0(arm11
, instr
, *value
);
2058 if (retval
!= ERROR_OK
)
2062 return arm11_run_instr_data_finish(arm11
);
2065 static int arm11_mrc(struct target
*target
, int cpnum
,
2066 uint32_t op1
, uint32_t op2
, uint32_t CRn
, uint32_t CRm
, uint32_t *value
)
2068 return arm11_mrc_inner(target
, cpnum
, op1
, op2
, CRn
, CRm
, value
, true);
2071 static int arm11_mcr(struct target
*target
, int cpnum
,
2072 uint32_t op1
, uint32_t op2
, uint32_t CRn
, uint32_t CRm
, uint32_t value
)
2074 return arm11_mrc_inner(target
, cpnum
, op1
, op2
, CRn
, CRm
, &value
, false);
2077 static int arm11_register_commands(struct command_context
*cmd_ctx
)
2081 struct command
*top_cmd
, *mw_cmd
;
2083 armv4_5_register_commands(cmd_ctx
);
2085 top_cmd
= register_command(cmd_ctx
, NULL
, "arm11",
2086 NULL
, COMMAND_ANY
, NULL
);
2088 /* "hardware_step" is only here to check if the default
2089 * simulate + breakpoint implementation is broken.
2090 * TEMPORARY! NOT DOCUMENTED!
2092 register_command(cmd_ctx
, top_cmd
, "hardware_step",
2093 arm11_handle_bool_hardware_step
, COMMAND_ANY
,
2094 "DEBUG ONLY - Hardware single stepping"
2095 " (default: disabled)");
2097 mw_cmd
= register_command(cmd_ctx
, top_cmd
, "memwrite",
2098 NULL
, COMMAND_ANY
, NULL
);
2099 register_command(cmd_ctx
, mw_cmd
, "burst",
2100 arm11_handle_bool_memwrite_burst
, COMMAND_ANY
,
2101 "Enable/Disable non-standard but fast burst mode"
2102 " (default: enabled)");
2103 register_command(cmd_ctx
, mw_cmd
, "error_fatal",
2104 arm11_handle_bool_memwrite_error_fatal
, COMMAND_ANY
,
2105 "Terminate program if transfer error was found"
2106 " (default: enabled)");
2108 register_command(cmd_ctx
, top_cmd
, "step_irq_enable",
2109 arm11_handle_bool_step_irq_enable
, COMMAND_ANY
,
2110 "Enable interrupts while stepping"
2111 " (default: disabled)");
2112 register_command(cmd_ctx
, top_cmd
, "vcr",
2113 arm11_handle_vcr
, COMMAND_ANY
,
2114 "Control (Interrupt) Vector Catch Register");
2116 return etm_register_commands(cmd_ctx
);
2119 /** Holds methods for ARM11xx targets. */
2120 struct target_type arm11_target
= {
2124 .arch_state
= arm11_arch_state
,
2126 .target_request_data
= arm11_target_request_data
,
2129 .resume
= arm11_resume
,
2132 .assert_reset
= arm11_assert_reset
,
2133 .deassert_reset
= arm11_deassert_reset
,
2134 .soft_reset_halt
= arm11_soft_reset_halt
,
2136 .get_gdb_reg_list
= arm11_get_gdb_reg_list
,
2138 .read_memory
= arm11_read_memory
,
2139 .write_memory
= arm11_write_memory
,
2141 .bulk_write_memory
= arm11_bulk_write_memory
,
2143 .checksum_memory
= arm_checksum_memory
,
2144 .blank_check_memory
= arm_blank_check_memory
,
2146 .add_breakpoint
= arm11_add_breakpoint
,
2147 .remove_breakpoint
= arm11_remove_breakpoint
,
2148 .add_watchpoint
= arm11_add_watchpoint
,
2149 .remove_watchpoint
= arm11_remove_watchpoint
,
2151 .run_algorithm
= arm11_run_algorithm
,
2153 .register_commands
= arm11_register_commands
,
2154 .target_create
= arm11_target_create
,
2155 .init_target
= arm11_init_target
,
2156 .examine
= arm11_examine
,
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)