1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
4 * Copyright (C) 2008 Oyvind Harboe oyvind.harboe@zylin.com *
6 * Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
36 #define _DEBUG_INSTRUCTION_EXECUTION_
40 #define FNC_INFO LOG_DEBUG("-")
46 #define FNC_INFO_NOTIMPLEMENTED do { LOG_DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
48 #define FNC_INFO_NOTIMPLEMENTED
51 static int arm11_on_enter_debug_state(arm11_common_t
* arm11
);
53 bool arm11_config_memwrite_burst
= true;
54 bool arm11_config_memwrite_error_fatal
= true;
56 bool arm11_config_memrw_no_increment
= false;
57 bool arm11_config_step_irq_enable
= false;
59 #define ARM11_HANDLER(x) \
62 target_type_t arm11_target
=
67 ARM11_HANDLER(arch_state
),
69 ARM11_HANDLER(target_request_data
),
72 ARM11_HANDLER(resume
),
75 ARM11_HANDLER(assert_reset
),
76 ARM11_HANDLER(deassert_reset
),
77 ARM11_HANDLER(soft_reset_halt
),
79 ARM11_HANDLER(get_gdb_reg_list
),
81 ARM11_HANDLER(read_memory
),
82 ARM11_HANDLER(write_memory
),
84 ARM11_HANDLER(bulk_write_memory
),
86 ARM11_HANDLER(checksum_memory
),
88 ARM11_HANDLER(add_breakpoint
),
89 ARM11_HANDLER(remove_breakpoint
),
90 ARM11_HANDLER(add_watchpoint
),
91 ARM11_HANDLER(remove_watchpoint
),
93 ARM11_HANDLER(run_algorithm
),
95 ARM11_HANDLER(register_commands
),
96 ARM11_HANDLER(target_create
),
97 ARM11_HANDLER(init_target
),
98 ARM11_HANDLER(examine
),
102 int arm11_regs_arch_type
= -1;
120 ARM11_REGISTER_SPSR_FIQ
,
121 ARM11_REGISTER_SPSR_SVC
,
122 ARM11_REGISTER_SPSR_ABT
,
123 ARM11_REGISTER_SPSR_IRQ
,
124 ARM11_REGISTER_SPSR_UND
,
125 ARM11_REGISTER_SPSR_MON
,
134 typedef struct arm11_reg_defs_s
139 enum arm11_regtype type
;
142 /* update arm11_regcache_ids when changing this */
143 static const arm11_reg_defs_t arm11_reg_defs
[] =
145 {"r0", 0, 0, ARM11_REGISTER_CORE
},
146 {"r1", 1, 1, ARM11_REGISTER_CORE
},
147 {"r2", 2, 2, ARM11_REGISTER_CORE
},
148 {"r3", 3, 3, ARM11_REGISTER_CORE
},
149 {"r4", 4, 4, ARM11_REGISTER_CORE
},
150 {"r5", 5, 5, ARM11_REGISTER_CORE
},
151 {"r6", 6, 6, ARM11_REGISTER_CORE
},
152 {"r7", 7, 7, ARM11_REGISTER_CORE
},
153 {"r8", 8, 8, ARM11_REGISTER_CORE
},
154 {"r9", 9, 9, ARM11_REGISTER_CORE
},
155 {"r10", 10, 10, ARM11_REGISTER_CORE
},
156 {"r11", 11, 11, ARM11_REGISTER_CORE
},
157 {"r12", 12, 12, ARM11_REGISTER_CORE
},
158 {"sp", 13, 13, ARM11_REGISTER_CORE
},
159 {"lr", 14, 14, ARM11_REGISTER_CORE
},
160 {"pc", 15, 15, ARM11_REGISTER_CORE
},
162 #if ARM11_REGCACHE_FREGS
163 {"f0", 0, 16, ARM11_REGISTER_FX
},
164 {"f1", 1, 17, ARM11_REGISTER_FX
},
165 {"f2", 2, 18, ARM11_REGISTER_FX
},
166 {"f3", 3, 19, ARM11_REGISTER_FX
},
167 {"f4", 4, 20, ARM11_REGISTER_FX
},
168 {"f5", 5, 21, ARM11_REGISTER_FX
},
169 {"f6", 6, 22, ARM11_REGISTER_FX
},
170 {"f7", 7, 23, ARM11_REGISTER_FX
},
171 {"fps", 0, 24, ARM11_REGISTER_FPS
},
174 {"cpsr", 0, 25, ARM11_REGISTER_CPSR
},
176 #if ARM11_REGCACHE_MODEREGS
177 {"r8_fiq", 8, -1, ARM11_REGISTER_FIQ
},
178 {"r9_fiq", 9, -1, ARM11_REGISTER_FIQ
},
179 {"r10_fiq", 10, -1, ARM11_REGISTER_FIQ
},
180 {"r11_fiq", 11, -1, ARM11_REGISTER_FIQ
},
181 {"r12_fiq", 12, -1, ARM11_REGISTER_FIQ
},
182 {"r13_fiq", 13, -1, ARM11_REGISTER_FIQ
},
183 {"r14_fiq", 14, -1, ARM11_REGISTER_FIQ
},
184 {"spsr_fiq", 0, -1, ARM11_REGISTER_SPSR_FIQ
},
186 {"r13_svc", 13, -1, ARM11_REGISTER_SVC
},
187 {"r14_svc", 14, -1, ARM11_REGISTER_SVC
},
188 {"spsr_svc", 0, -1, ARM11_REGISTER_SPSR_SVC
},
190 {"r13_abt", 13, -1, ARM11_REGISTER_ABT
},
191 {"r14_abt", 14, -1, ARM11_REGISTER_ABT
},
192 {"spsr_abt", 0, -1, ARM11_REGISTER_SPSR_ABT
},
194 {"r13_irq", 13, -1, ARM11_REGISTER_IRQ
},
195 {"r14_irq", 14, -1, ARM11_REGISTER_IRQ
},
196 {"spsr_irq", 0, -1, ARM11_REGISTER_SPSR_IRQ
},
198 {"r13_und", 13, -1, ARM11_REGISTER_UND
},
199 {"r14_und", 14, -1, ARM11_REGISTER_UND
},
200 {"spsr_und", 0, -1, ARM11_REGISTER_SPSR_UND
},
203 {"r13_mon", 13, -1, ARM11_REGISTER_MON
},
204 {"r14_mon", 14, -1, ARM11_REGISTER_MON
},
205 {"spsr_mon", 0, -1, ARM11_REGISTER_SPSR_MON
},
208 /* Debug Registers */
209 {"dscr", 0, -1, ARM11_REGISTER_DSCR
},
210 {"wdtr", 0, -1, ARM11_REGISTER_WDTR
},
211 {"rdtr", 0, -1, ARM11_REGISTER_RDTR
},
214 enum arm11_regcache_ids
217 ARM11_RC_RX
= ARM11_RC_R0
,
232 ARM11_RC_SP
= ARM11_RC_R13
,
234 ARM11_RC_LR
= ARM11_RC_R14
,
236 ARM11_RC_PC
= ARM11_RC_R15
,
238 #if ARM11_REGCACHE_FREGS
240 ARM11_RC_FX
= ARM11_RC_F0
,
253 #if ARM11_REGCACHE_MODEREGS
291 #define ARM11_GDB_REGISTER_COUNT 26
293 u8 arm11_gdb_dummy_fp_value
[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
295 reg_t arm11_gdb_dummy_fp_reg
=
297 "GDB dummy floating-point register", arm11_gdb_dummy_fp_value
, 0, 1, 96, NULL
, 0, NULL
, 0
300 u8 arm11_gdb_dummy_fps_value
[] = {0, 0, 0, 0};
302 reg_t arm11_gdb_dummy_fps_reg
=
304 "GDB dummy floating-point status register", arm11_gdb_dummy_fps_value
, 0, 1, 32, NULL
, 0, NULL
, 0
309 /** Check and if necessary take control of the system
311 * \param arm11 Target state variable.
312 * \param dscr If the current DSCR content is
313 * available a pointer to a word holding the
314 * DSCR can be passed. Otherwise use NULL.
316 int arm11_check_init(arm11_common_t
* arm11
, u32
* dscr
)
321 u32 dscr_local_tmp_copy
;
325 dscr
= &dscr_local_tmp_copy
;
326 if ((retval
=arm11_read_DSCR(arm11
, dscr
))!=ERROR_OK
)
330 if (!(*dscr
& ARM11_DSCR_MODE_SELECT
))
332 LOG_DEBUG("Bringing target into debug mode");
334 *dscr
|= ARM11_DSCR_MODE_SELECT
; /* Halt debug-mode */
335 arm11_write_DSCR(arm11
, *dscr
);
337 /* add further reset initialization here */
339 arm11
->simulate_reset_on_next_halt
= true;
341 if (*dscr
& ARM11_DSCR_CORE_HALTED
)
343 /** \todo TODO: this needs further scrutiny because
344 * arm11_on_enter_debug_state() never gets properly called
347 arm11
->target
->state
= TARGET_HALTED
;
348 arm11
->target
->debug_reason
= arm11_get_DSCR_debug_reason(*dscr
);
352 arm11
->target
->state
= TARGET_RUNNING
;
353 arm11
->target
->debug_reason
= DBG_REASON_NOTHALTED
;
356 arm11_sc7_clear_vbw(arm11
);
365 (arm11->reg_values[ARM11_RC_##x])
367 /** Save processor state.
369 * This is called when the HALT instruction has succeeded
370 * or on other occasions that stop the processor.
373 static int arm11_on_enter_debug_state(arm11_common_t
* arm11
)
378 for(i
= 0; i
< asizeof(arm11
->reg_values
); i
++)
380 arm11
->reg_list
[i
].valid
= 1;
381 arm11
->reg_list
[i
].dirty
= 0;
386 if ((retval
=arm11_read_DSCR(arm11
, &R(DSCR
)))!=ERROR_OK
)
391 if (R(DSCR
) & ARM11_DSCR_WDTR_FULL
)
393 arm11_add_debug_SCAN_N(arm11
, 0x05, ARM11_TAP_DEFAULT
);
395 arm11_add_IR(arm11
, ARM11_INTEST
, ARM11_TAP_DEFAULT
);
397 scan_field_t chain5_fields
[3];
399 arm11_setup_field(arm11
, 32, NULL
, &R(WDTR
), chain5_fields
+ 0);
400 arm11_setup_field(arm11
, 1, NULL
, NULL
, chain5_fields
+ 1);
401 arm11_setup_field(arm11
, 1, NULL
, NULL
, chain5_fields
+ 2);
403 arm11_add_dr_scan_vc(asizeof(chain5_fields
), chain5_fields
, TAP_DRPAUSE
);
407 arm11
->reg_list
[ARM11_RC_WDTR
].valid
= 0;
411 /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */
412 /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
413 ARM1136 seems to require this to issue ITR's as well */
415 u32 new_dscr
= R(DSCR
) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE
;
417 /* this executes JTAG queue: */
419 arm11_write_DSCR(arm11
, new_dscr
);
423 Before executing any instruction in debug state you have to drain the write buffer.
424 This ensures that no imprecise Data Aborts can return at a later point:*/
426 /** \todo TODO: Test drain write buffer. */
431 /* MRC p14,0,R0,c5,c10,0 */
432 // arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
434 /* mcr 15, 0, r0, cr7, cr10, {4} */
435 arm11_run_instr_no_data1(arm11
, 0xee070f9a);
437 u32 dscr
= arm11_read_DSCR(arm11
);
439 LOG_DEBUG("DRAIN, DSCR %08x", dscr
);
441 if (dscr
& ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT
)
443 arm11_run_instr_no_data1(arm11
, 0xe320f000);
445 dscr
= arm11_read_DSCR(arm11
);
447 LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr
);
454 arm11_run_instr_data_prepare(arm11
);
458 /** \todo TODO: handle other mode registers */
461 for (i
= 0; i
< 15; i
++)
463 /* MCR p14,0,R?,c0,c5,0 */
464 arm11_run_instr_data_from_core(arm11
, 0xEE000E15 | (i
<< 12), &R(RX
+ i
), 1);
469 /* check rDTRfull in DSCR */
471 if (R(DSCR
) & ARM11_DSCR_RDTR_FULL
)
473 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
474 arm11_run_instr_data_from_core_via_r0(arm11
, 0xEE100E15, &R(RDTR
));
478 arm11
->reg_list
[ARM11_RC_RDTR
].valid
= 0;
483 /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */
484 arm11_run_instr_data_from_core_via_r0(arm11
, 0xE10F0000, &R(CPSR
));
488 /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
489 arm11_run_instr_data_from_core_via_r0(arm11
, 0xE1A0000F, &R(PC
));
491 /* adjust PC depending on ARM state */
493 if (R(CPSR
) & ARM11_CPSR_J
) /* Java state */
495 arm11
->reg_values
[ARM11_RC_PC
] -= 0;
497 else if (R(CPSR
) & ARM11_CPSR_T
) /* Thumb state */
499 arm11
->reg_values
[ARM11_RC_PC
] -= 4;
503 arm11
->reg_values
[ARM11_RC_PC
] -= 8;
506 if (arm11
->simulate_reset_on_next_halt
)
508 arm11
->simulate_reset_on_next_halt
= false;
510 LOG_DEBUG("Reset c1 Control Register");
512 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
514 /* MCR p15,0,R0,c1,c0,0 */
515 arm11_run_instr_data_to_core_via_r0(arm11
, 0xee010f10, 0);
519 arm11_run_instr_data_finish(arm11
);
521 arm11_dump_reg_changes(arm11
);
526 void arm11_dump_reg_changes(arm11_common_t
* arm11
)
529 if (!(debug_level
>= LOG_LVL_DEBUG
))
535 for(i
= 0; i
< ARM11_REGCACHE_COUNT
; i
++)
537 if (!arm11
->reg_list
[i
].valid
)
539 if (arm11
->reg_history
[i
].valid
)
540 LOG_DEBUG("%8s INVALID (%08x)", arm11_reg_defs
[i
].name
, arm11
->reg_history
[i
].value
);
544 if (arm11
->reg_history
[i
].valid
)
546 if (arm11
->reg_history
[i
].value
!= arm11
->reg_values
[i
])
547 LOG_DEBUG("%8s %08x (%08x)", arm11_reg_defs
[i
].name
, arm11
->reg_values
[i
], arm11
->reg_history
[i
].value
);
551 LOG_DEBUG("%8s %08x (INVALID)", arm11_reg_defs
[i
].name
, arm11
->reg_values
[i
]);
557 /** Restore processor state
559 * This is called in preparation for the RESTART function.
562 int arm11_leave_debug_state(arm11_common_t
* arm11
)
566 arm11_run_instr_data_prepare(arm11
);
568 /** \todo TODO: handle other mode registers */
570 /* restore R1 - R14 */
572 for (i
= 1; i
< 15; i
++)
574 if (!arm11
->reg_list
[ARM11_RC_RX
+ i
].dirty
)
577 /* MRC p14,0,r?,c0,c5,0 */
578 arm11_run_instr_data_to_core1(arm11
, 0xee100e15 | (i
<< 12), R(RX
+ i
));
580 // LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
583 arm11_run_instr_data_finish(arm11
);
585 /* spec says clear wDTR and rDTR; we assume they are clear as
586 otherwise our programming would be sloppy */
590 if ((retval
=arm11_read_DSCR(arm11
, &DSCR
))!=ERROR_OK
)
595 if (DSCR
& (ARM11_DSCR_RDTR_FULL
| ARM11_DSCR_WDTR_FULL
))
597 LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08x)", DSCR
);
601 arm11_run_instr_data_prepare(arm11
);
603 /* restore original wDTR */
605 if ((R(DSCR
) & ARM11_DSCR_WDTR_FULL
) || arm11
->reg_list
[ARM11_RC_WDTR
].dirty
)
607 /* MCR p14,0,R0,c0,c5,0 */
608 arm11_run_instr_data_to_core_via_r0(arm11
, 0xee000e15, R(WDTR
));
614 arm11_run_instr_data_to_core_via_r0(arm11
, 0xe129f000, R(CPSR
));
619 arm11_run_instr_data_to_core_via_r0(arm11
, 0xe1a0f000, R(PC
));
623 /* MRC p14,0,r0,c0,c5,0 */
624 arm11_run_instr_data_to_core1(arm11
, 0xee100e15, R(R0
));
626 arm11_run_instr_data_finish(arm11
);
630 arm11_write_DSCR(arm11
, R(DSCR
));
634 if (R(DSCR
) & ARM11_DSCR_RDTR_FULL
|| arm11
->reg_list
[ARM11_RC_RDTR
].dirty
)
636 arm11_add_debug_SCAN_N(arm11
, 0x05, ARM11_TAP_DEFAULT
);
638 arm11_add_IR(arm11
, ARM11_EXTEST
, ARM11_TAP_DEFAULT
);
640 scan_field_t chain5_fields
[3];
642 u8 Ready
= 0; /* ignored */
643 u8 Valid
= 0; /* ignored */
645 arm11_setup_field(arm11
, 32, &R(RDTR
), NULL
, chain5_fields
+ 0);
646 arm11_setup_field(arm11
, 1, &Ready
, NULL
, chain5_fields
+ 1);
647 arm11_setup_field(arm11
, 1, &Valid
, NULL
, chain5_fields
+ 2);
649 arm11_add_dr_scan_vc(asizeof(chain5_fields
), chain5_fields
, TAP_DRPAUSE
);
652 arm11_record_register_history(arm11
);
657 void arm11_record_register_history(arm11_common_t
* arm11
)
660 for(i
= 0; i
< ARM11_REGCACHE_COUNT
; i
++)
662 arm11
->reg_history
[i
].value
= arm11
->reg_values
[i
];
663 arm11
->reg_history
[i
].valid
= arm11
->reg_list
[i
].valid
;
665 arm11
->reg_list
[i
].valid
= 0;
666 arm11
->reg_list
[i
].dirty
= 0;
671 /* poll current target status */
672 int arm11_poll(struct target_s
*target
)
676 arm11_common_t
* arm11
= target
->arch_info
;
678 if (arm11
->trst_active
)
683 if ((retval
=arm11_read_DSCR(arm11
, &dscr
))!=ERROR_OK
)
686 LOG_DEBUG("DSCR %08x", dscr
);
688 if ((retval
=arm11_check_init(arm11
, &dscr
))!=ERROR_OK
)
691 if (dscr
& ARM11_DSCR_CORE_HALTED
)
693 if (target
->state
!= TARGET_HALTED
)
695 enum target_state old_state
= target
->state
;
697 LOG_DEBUG("enter TARGET_HALTED");
698 target
->state
= TARGET_HALTED
;
699 target
->debug_reason
= arm11_get_DSCR_debug_reason(dscr
);
700 arm11_on_enter_debug_state(arm11
);
702 target_call_event_callbacks(target
,
703 old_state
== TARGET_DEBUG_RUNNING
? TARGET_EVENT_DEBUG_HALTED
: TARGET_EVENT_HALTED
);
708 if (target
->state
!= TARGET_RUNNING
&& target
->state
!= TARGET_DEBUG_RUNNING
)
710 LOG_DEBUG("enter TARGET_RUNNING");
711 target
->state
= TARGET_RUNNING
;
712 target
->debug_reason
= DBG_REASON_NOTHALTED
;
718 /* architecture specific status reply */
719 int arm11_arch_state(struct target_s
*target
)
721 arm11_common_t
* arm11
= target
->arch_info
;
723 LOG_USER("target halted due to %s\ncpsr: 0x%8.8x pc: 0x%8.8x",
724 Jim_Nvp_value2name_simple( nvp_target_debug_reason
, target
->debug_reason
)->name
,
731 /* target request support */
732 int arm11_target_request_data(struct target_s
*target
, u32 size
, u8
*buffer
)
734 FNC_INFO_NOTIMPLEMENTED
;
739 /* target execution control */
740 int arm11_halt(struct target_s
*target
)
742 int retval
= ERROR_OK
;
746 arm11_common_t
* arm11
= target
->arch_info
;
748 LOG_DEBUG("target->state: %s",
749 Jim_Nvp_value2name_simple( nvp_target_state
, target
->state
)->name
);
751 if (target
->state
== TARGET_UNKNOWN
)
753 arm11
->simulate_reset_on_next_halt
= true;
756 if (target
->state
== TARGET_HALTED
)
758 LOG_DEBUG("target was already halted");
762 if (arm11
->trst_active
)
764 arm11
->halt_requested
= true;
768 arm11_add_IR(arm11
, ARM11_HALT
, TAP_IDLE
);
770 if((retval
= jtag_execute_queue()) != ERROR_OK
)
780 retval
= arm11_read_DSCR(arm11
, &dscr
);
781 if (retval
!=ERROR_OK
)
784 if (dscr
& ARM11_DSCR_CORE_HALTED
)
788 arm11_on_enter_debug_state(arm11
);
790 enum target_state old_state
= target
->state
;
792 target
->state
= TARGET_HALTED
;
793 target
->debug_reason
= arm11_get_DSCR_debug_reason(dscr
);
795 if((retval
= target_call_event_callbacks(target
,
796 old_state
== TARGET_DEBUG_RUNNING
? TARGET_EVENT_DEBUG_HALTED
: TARGET_EVENT_HALTED
)) != ERROR_OK
)
804 int arm11_resume(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
, int debug_execution
)
806 int retval
= ERROR_OK
;
810 // LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
811 // current, address, handle_breakpoints, debug_execution);
813 arm11_common_t
* arm11
= target
->arch_info
;
815 LOG_DEBUG("target->state: %s",
816 Jim_Nvp_value2name_simple( nvp_target_state
, target
->state
)->name
);
819 if (target
->state
!= TARGET_HALTED
)
821 LOG_ERROR("Target not halted");
822 return ERROR_TARGET_NOT_HALTED
;
828 LOG_DEBUG("RESUME PC %08x%s", R(PC
), !current
? "!" : "");
830 /* clear breakpoints/watchpoints and VCR*/
831 arm11_sc7_clear_vbw(arm11
);
833 /* Set up breakpoints */
834 if (!debug_execution
)
836 /* check if one matches PC and step over it if necessary */
840 for (bp
= target
->breakpoints
; bp
; bp
= bp
->next
)
842 if (bp
->address
== R(PC
))
844 LOG_DEBUG("must step over %08x", bp
->address
);
845 arm11_step(target
, 1, 0, 0);
850 /* set all breakpoints */
854 for (bp
= target
->breakpoints
; bp
; bp
= bp
->next
)
856 arm11_sc7_action_t brp
[2];
859 brp
[0].address
= ARM11_SC7_BVR0
+ brp_num
;
860 brp
[0].value
= bp
->address
;
862 brp
[1].address
= ARM11_SC7_BCR0
+ brp_num
;
863 brp
[1].value
= 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
865 arm11_sc7_run(arm11
, brp
, asizeof(brp
));
867 LOG_DEBUG("Add BP " ZU
" at %08x", brp_num
, bp
->address
);
872 arm11_sc7_set_vcr(arm11
, arm11_vcr
);
875 arm11_leave_debug_state(arm11
);
877 arm11_add_IR(arm11
, ARM11_RESTART
, TAP_IDLE
);
879 if((retval
= jtag_execute_queue()) != ERROR_OK
)
887 retval
= arm11_read_DSCR(arm11
, &dscr
);
888 if (retval
!=ERROR_OK
)
891 LOG_DEBUG("DSCR %08x", dscr
);
893 if (dscr
& ARM11_DSCR_CORE_RESTARTED
)
897 if (!debug_execution
)
899 target
->state
= TARGET_RUNNING
;
900 target
->debug_reason
= DBG_REASON_NOTHALTED
;
902 if((retval
= target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
)) != ERROR_OK
)
909 target
->state
= TARGET_DEBUG_RUNNING
;
910 target
->debug_reason
= DBG_REASON_NOTHALTED
;
911 if((retval
= target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
)) != ERROR_OK
)
920 int arm11_step(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
)
922 int retval
= ERROR_OK
;
926 LOG_DEBUG("target->state: %s",
927 Jim_Nvp_value2name_simple( nvp_target_state
, target
->state
)->name
);
929 if (target
->state
!= TARGET_HALTED
)
931 LOG_WARNING("target was not halted");
932 return ERROR_TARGET_NOT_HALTED
;
935 arm11_common_t
* arm11
= target
->arch_info
;
940 LOG_INFO("STEP PC %08x%s", R(PC
), !current
? "!" : "");
942 /** \todo TODO: Thumb not supported here */
944 u32 next_instruction
;
946 if ((arm11_read_memory_word(arm11
, R(PC
), &next_instruction
))!=ERROR_OK
)
950 if ((next_instruction
& 0xFFF00070) == 0xe1200070)
953 arm11
->reg_list
[ARM11_RC_PC
].valid
= 1;
954 arm11
->reg_list
[ARM11_RC_PC
].dirty
= 0;
955 LOG_INFO("Skipping BKPT");
957 /* skip over Wait for interrupt / Standby */
958 /* mcr 15, 0, r?, cr7, cr0, {4} */
959 else if ((next_instruction
& 0xFFFF0FFF) == 0xee070f90)
962 arm11
->reg_list
[ARM11_RC_PC
].valid
= 1;
963 arm11
->reg_list
[ARM11_RC_PC
].dirty
= 0;
964 LOG_INFO("Skipping WFI");
966 /* ignore B to self */
967 else if ((next_instruction
& 0xFEFFFFFF) == 0xeafffffe)
969 LOG_INFO("Not stepping jump to self");
973 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
976 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
977 * the VCR might be something worth looking into. */
980 /* Set up breakpoint for stepping */
982 arm11_sc7_action_t brp
[2];
985 brp
[0].address
= ARM11_SC7_BVR0
;
986 brp
[0].value
= R(PC
);
988 brp
[1].address
= ARM11_SC7_BCR0
;
989 brp
[1].value
= 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
991 if ((retval
=arm11_sc7_run(arm11
, brp
, asizeof(brp
)))!=ERROR_OK
)
997 if (arm11_config_step_irq_enable
)
998 R(DSCR
) &= ~ARM11_DSCR_INTERRUPTS_DISABLE
; /* should be redundant */
1000 R(DSCR
) |= ARM11_DSCR_INTERRUPTS_DISABLE
;
1003 if ((retval
=arm11_leave_debug_state(arm11
))!=ERROR_OK
)
1006 arm11_add_IR(arm11
, ARM11_RESTART
, TAP_IDLE
);
1008 if((retval
= jtag_execute_queue()) != ERROR_OK
)
1013 /** \todo TODO: add a timeout */
1020 retval
= arm11_read_DSCR(arm11
, &dscr
);
1021 if (retval
!=ERROR_OK
)
1024 LOG_DEBUG("DSCR %08x", dscr
);
1026 if ((dscr
& (ARM11_DSCR_CORE_RESTARTED
| ARM11_DSCR_CORE_HALTED
)) ==
1027 (ARM11_DSCR_CORE_RESTARTED
| ARM11_DSCR_CORE_HALTED
))
1031 /* clear breakpoint */
1032 arm11_sc7_clear_vbw(arm11
);
1035 if((retval
= arm11_on_enter_debug_state(arm11
))!=ERROR_OK
)
1038 /* restore default state */
1039 R(DSCR
) &= ~ARM11_DSCR_INTERRUPTS_DISABLE
;
1043 // target->state = TARGET_HALTED;
1044 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1046 if((retval
= target_call_event_callbacks(target
, TARGET_EVENT_HALTED
)) != ERROR_OK
)
1054 /* target reset control */
1055 int arm11_assert_reset(struct target_s
*target
)
1060 /* assert reset lines */
1061 /* resets only the DBGTAP, not the ARM */
1063 jtag_add_reset(1, 0);
1064 jtag_add_sleep(5000);
1066 arm11_common_t
* arm11
= target
->arch_info
;
1067 arm11
->trst_active
= true;
1070 if (target
->reset_halt
)
1073 if ((retval
= target_halt(target
))!=ERROR_OK
)
1080 int arm11_deassert_reset(struct target_s
*target
)
1085 LOG_DEBUG("target->state: %s",
1086 Jim_Nvp_value2name_simple( nvp_target_state
, target
->state
)->name
);
1089 /* deassert reset lines */
1090 jtag_add_reset(0, 0);
1092 arm11_common_t
* arm11
= target
->arch_info
;
1093 arm11
->trst_active
= false;
1095 if (arm11
->halt_requested
)
1096 return arm11_halt(target
);
1102 int arm11_soft_reset_halt(struct target_s
*target
)
1104 FNC_INFO_NOTIMPLEMENTED
;
1109 /* target register access for gdb */
1110 int arm11_get_gdb_reg_list(struct target_s
*target
, struct reg_s
**reg_list
[], int *reg_list_size
)
1114 arm11_common_t
* arm11
= target
->arch_info
;
1116 *reg_list_size
= ARM11_GDB_REGISTER_COUNT
;
1117 *reg_list
= malloc(sizeof(reg_t
*) * ARM11_GDB_REGISTER_COUNT
);
1120 for (i
= 16; i
< 24; i
++)
1122 (*reg_list
)[i
] = &arm11_gdb_dummy_fp_reg
;
1125 (*reg_list
)[24] = &arm11_gdb_dummy_fps_reg
;
1128 for (i
= 0; i
< ARM11_REGCACHE_COUNT
; i
++)
1130 if (arm11_reg_defs
[i
].gdb_num
== -1)
1133 (*reg_list
)[arm11_reg_defs
[i
].gdb_num
] = arm11
->reg_list
+ i
;
1139 /* target memory access
1140 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
1141 * count: number of items of <size>
1143 int arm11_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
1145 /** \todo TODO: check if buffer cast to u32* and u16* might cause alignment problems */
1149 if (target
->state
!= TARGET_HALTED
)
1151 LOG_WARNING("target was not halted");
1152 return ERROR_TARGET_NOT_HALTED
;
1155 LOG_DEBUG("ADDR %08x SIZE %08x COUNT %08x", address
, size
, count
);
1157 arm11_common_t
* arm11
= target
->arch_info
;
1159 arm11_run_instr_data_prepare(arm11
);
1161 /* MRC p14,0,r0,c0,c5,0 */
1162 arm11_run_instr_data_to_core1(arm11
, 0xee100e15, address
);
1167 /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
1168 arm11
->reg_list
[ARM11_RC_R1
].dirty
= 1;
1171 for (i
= 0; i
< count
; i
++)
1173 /* ldrb r1, [r0], #1 */
1175 arm11_run_instr_no_data1(arm11
,
1176 !arm11_config_memrw_no_increment
? 0xe4d01001 : 0xe5d01000);
1179 /* MCR p14,0,R1,c0,c5,0 */
1180 arm11_run_instr_data_from_core(arm11
, 0xEE001E15, &res
, 1);
1189 arm11
->reg_list
[ARM11_RC_R1
].dirty
= 1;
1191 u16
* buf16
= (u16
*)buffer
;
1194 for (i
= 0; i
< count
; i
++)
1196 /* ldrh r1, [r0], #2 */
1197 arm11_run_instr_no_data1(arm11
,
1198 !arm11_config_memrw_no_increment
? 0xe0d010b2 : 0xe1d010b0);
1202 /* MCR p14,0,R1,c0,c5,0 */
1203 arm11_run_instr_data_from_core(arm11
, 0xEE001E15, &res
, 1);
1213 /* LDC p14,c5,[R0],#4 */
1214 /* LDC p14,c5,[R0] */
1215 arm11_run_instr_data_from_core(arm11
,
1216 (!arm11_config_memrw_no_increment
? 0xecb05e01 : 0xed905e00),
1217 (u32
*)buffer
, count
);
1221 arm11_run_instr_data_finish(arm11
);
1226 int arm11_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
1230 if (target
->state
!= TARGET_HALTED
)
1232 LOG_WARNING("target was not halted");
1233 return ERROR_TARGET_NOT_HALTED
;
1236 LOG_DEBUG("ADDR %08x SIZE %08x COUNT %08x", address
, size
, count
);
1238 arm11_common_t
* arm11
= target
->arch_info
;
1240 arm11_run_instr_data_prepare(arm11
);
1242 /* MRC p14,0,r0,c0,c5,0 */
1243 arm11_run_instr_data_to_core1(arm11
, 0xee100e15, address
);
1249 arm11
->reg_list
[ARM11_RC_R1
].dirty
= 1;
1252 for (i
= 0; i
< count
; i
++)
1254 /* MRC p14,0,r1,c0,c5,0 */
1255 arm11_run_instr_data_to_core1(arm11
, 0xee101e15, *buffer
++);
1257 /* strb r1, [r0], #1 */
1259 arm11_run_instr_no_data1(arm11
,
1260 !arm11_config_memrw_no_increment
? 0xe4c01001 : 0xe5c01000);
1268 arm11
->reg_list
[ARM11_RC_R1
].dirty
= 1;
1270 u16
* buf16
= (u16
*)buffer
;
1273 for (i
= 0; i
< count
; i
++)
1275 /* MRC p14,0,r1,c0,c5,0 */
1276 arm11_run_instr_data_to_core1(arm11
, 0xee101e15, *buf16
++);
1278 /* strh r1, [r0], #2 */
1280 arm11_run_instr_no_data1(arm11
,
1281 !arm11_config_memrw_no_increment
? 0xe0c010b2 : 0xe1c010b0);
1288 /** \todo TODO: check if buffer cast to u32* might cause alignment problems */
1290 if (!arm11_config_memwrite_burst
)
1292 /* STC p14,c5,[R0],#4 */
1293 /* STC p14,c5,[R0]*/
1294 arm11_run_instr_data_to_core(arm11
,
1295 (!arm11_config_memrw_no_increment
? 0xeca05e01 : 0xed805e00),
1296 (u32
*)buffer
, count
);
1300 /* STC p14,c5,[R0],#4 */
1301 /* STC p14,c5,[R0]*/
1302 arm11_run_instr_data_to_core_noack(arm11
,
1303 (!arm11_config_memrw_no_increment
? 0xeca05e01 : 0xed805e00),
1304 (u32
*)buffer
, count
);
1311 /* r0 verification */
1312 if (!arm11_config_memrw_no_increment
)
1316 /* MCR p14,0,R0,c0,c5,0 */
1317 arm11_run_instr_data_from_core(arm11
, 0xEE000E15, &r0
, 1);
1319 if (address
+ size
* count
!= r0
)
1321 LOG_ERROR("Data transfer failed. (%d)", (r0
- address
) - size
* count
);
1323 if (arm11_config_memwrite_burst
)
1324 LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1326 if (arm11_config_memwrite_error_fatal
)
1332 arm11_run_instr_data_finish(arm11
);
1338 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1339 int arm11_bulk_write_memory(struct target_s
*target
, u32 address
, u32 count
, u8
*buffer
)
1343 if (target
->state
!= TARGET_HALTED
)
1345 LOG_WARNING("target was not halted");
1346 return ERROR_TARGET_NOT_HALTED
;
1349 return arm11_write_memory(target
, address
, 4, count
, buffer
);
1352 int arm11_checksum_memory(struct target_s
*target
, u32 address
, u32 count
, u32
* checksum
)
1354 FNC_INFO_NOTIMPLEMENTED
;
1359 /* target break-/watchpoint control
1360 * rw: 0 = write, 1 = read, 2 = access
1362 int arm11_add_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
1366 arm11_common_t
* arm11
= target
->arch_info
;
1369 if (breakpoint
->type
== BKPT_SOFT
)
1371 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
1372 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1376 if (!arm11
->free_brps
)
1378 LOG_INFO("no breakpoint unit available for hardware breakpoint");
1379 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1382 if (breakpoint
->length
!= 4)
1384 LOG_INFO("only breakpoints of four bytes length supported");
1385 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1393 int arm11_remove_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
1397 arm11_common_t
* arm11
= target
->arch_info
;
1404 int arm11_add_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
1406 FNC_INFO_NOTIMPLEMENTED
;
1411 int arm11_remove_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
1413 FNC_INFO_NOTIMPLEMENTED
;
1418 // HACKHACKHACK - FIXME mode/state
1419 /* target algorithm support */
1420 int arm11_run_algorithm(struct target_s
*target
, int num_mem_params
, mem_param_t
*mem_params
,
1421 int num_reg_params
, reg_param_t
*reg_params
, u32 entry_point
, u32 exit_point
,
1422 int timeout_ms
, void *arch_info
)
1424 arm11_common_t
*arm11
= target
->arch_info
;
1425 armv4_5_algorithm_t
*arm11_algorithm_info
= arch_info
;
1426 // enum armv4_5_state core_state = arm11->core_state;
1427 // enum armv4_5_mode core_mode = arm11->core_mode;
1430 int exit_breakpoint_size
= 0;
1432 int retval
= ERROR_OK
;
1433 LOG_DEBUG("Running algorithm");
1435 if (arm11_algorithm_info
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
1437 LOG_ERROR("current target isn't an ARMV4/5 target");
1438 return ERROR_TARGET_INVALID
;
1441 if (target
->state
!= TARGET_HALTED
)
1443 LOG_WARNING("target not halted");
1444 return ERROR_TARGET_NOT_HALTED
;
1448 // if (armv4_5_mode_to_number(arm11->core_mode)==-1)
1449 // return ERROR_FAIL;
1452 for (i
= 0; i
< 16; i
++)
1454 context
[i
] = buf_get_u32((u8
*)(&arm11
->reg_values
[i
]),0,32);
1455 LOG_DEBUG("Save %i: 0x%x",i
,context
[i
]);
1458 cpsr
= buf_get_u32((u8
*)(arm11
->reg_values
+ARM11_RC_CPSR
),0,32);
1459 LOG_DEBUG("Save CPSR: 0x%x", cpsr
);
1461 for (i
= 0; i
< num_mem_params
; i
++)
1463 target_write_buffer(target
, mem_params
[i
].address
, mem_params
[i
].size
, mem_params
[i
].value
);
1466 // Set register parameters
1467 for (i
= 0; i
< num_reg_params
; i
++)
1469 reg_t
*reg
= register_get_by_name(arm11
->core_cache
, reg_params
[i
].reg_name
, 0);
1472 LOG_ERROR("BUG: register '%s' not found", reg_params
[i
].reg_name
);
1476 if (reg
->size
!= reg_params
[i
].size
)
1478 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params
[i
].reg_name
);
1481 arm11_set_reg(reg
,reg_params
[i
].value
);
1482 // printf("%i: Set %s =%08x\n", i, reg_params[i].reg_name,val);
1485 exit_breakpoint_size
= 4;
1487 /* arm11->core_state = arm11_algorithm_info->core_state;
1488 if (arm11->core_state == ARMV4_5_STATE_ARM)
1489 exit_breakpoint_size = 4;
1490 else if (arm11->core_state == ARMV4_5_STATE_THUMB)
1491 exit_breakpoint_size = 2;
1494 LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
1498 if (arm11_algorithm_info
->core_mode
!= ARMV4_5_MODE_ANY
)
1500 LOG_DEBUG("setting core_mode: 0x%2.2x", arm11_algorithm_info
->core_mode
);
1501 buf_set_u32(arm11
->reg_list
[ARM11_RC_CPSR
].value
, 0, 5, arm11_algorithm_info
->core_mode
);
1502 arm11
->reg_list
[ARM11_RC_CPSR
].dirty
= 1;
1503 arm11
->reg_list
[ARM11_RC_CPSR
].valid
= 1;
1506 if ((retval
= breakpoint_add(target
, exit_point
, exit_breakpoint_size
, BKPT_HARD
)) != ERROR_OK
)
1508 LOG_ERROR("can't add breakpoint to finish algorithm execution");
1509 retval
= ERROR_TARGET_FAILURE
;
1513 // no debug, otherwise breakpoint is not set
1514 if((retval
= target_resume(target
, 0, entry_point
, 1, 0)) != ERROR_OK
)
1519 if((retval
= target_wait_state(target
, TARGET_HALTED
, timeout_ms
)) != ERROR_OK
)
1524 if (target
->state
!= TARGET_HALTED
)
1526 if ((retval
=target_halt(target
))!=ERROR_OK
)
1528 if ((retval
=target_wait_state(target
, TARGET_HALTED
, 500))!=ERROR_OK
)
1532 retval
= ERROR_TARGET_TIMEOUT
;
1533 goto del_breakpoint
;
1536 if (buf_get_u32(arm11
->reg_list
[15].value
, 0, 32) != exit_point
)
1538 LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4x",
1539 buf_get_u32(arm11
->reg_list
[15].value
, 0, 32));
1540 retval
= ERROR_TARGET_TIMEOUT
;
1541 goto del_breakpoint
;
1544 for (i
= 0; i
< num_mem_params
; i
++)
1546 if (mem_params
[i
].direction
!= PARAM_OUT
)
1547 target_read_buffer(target
, mem_params
[i
].address
, mem_params
[i
].size
, mem_params
[i
].value
);
1550 for (i
= 0; i
< num_reg_params
; i
++)
1552 if (reg_params
[i
].direction
!= PARAM_OUT
)
1554 reg_t
*reg
= register_get_by_name(arm11
->core_cache
, reg_params
[i
].reg_name
, 0);
1557 LOG_ERROR("BUG: register '%s' not found", reg_params
[i
].reg_name
);
1561 if (reg
->size
!= reg_params
[i
].size
)
1563 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params
[i
].reg_name
);
1567 buf_set_u32(reg_params
[i
].value
, 0, 32, buf_get_u32(reg
->value
, 0, 32));
1572 breakpoint_remove(target
, exit_point
);
1576 for (i
= 0; i
< 16; i
++)
1578 LOG_DEBUG("restoring register %s with value 0x%8.8x",
1579 arm11
->reg_list
[i
].name
, context
[i
]);
1580 arm11_set_reg(&arm11
->reg_list
[i
], (u8
*)&context
[i
]);
1582 LOG_DEBUG("restoring CPSR with value 0x%8.8x", cpsr
);
1583 arm11_set_reg(&arm11
->reg_list
[ARM11_RC_CPSR
], (u8
*)&cpsr
);
1585 // arm11->core_state = core_state;
1586 // arm11->core_mode = core_mode;
1591 int arm11_target_create(struct target_s
*target
, Jim_Interp
*interp
)
1593 int retval
= ERROR_OK
;
1596 NEW(arm11_common_t
, arm11
, 1);
1598 arm11
->target
= target
;
1600 /* prepare JTAG information for the new target */
1601 arm11
->jtag_info
.tap
= target
->tap
;
1602 arm11
->jtag_info
.scann_size
= 5;
1604 if((retval
= arm_jtag_setup_connection(&arm11
->jtag_info
)) != ERROR_OK
)
1609 if (target
->tap
==NULL
)
1612 if (target
->tap
->ir_length
!= 5)
1614 LOG_ERROR("'target arm11' expects IR LENGTH = 5");
1615 return ERROR_COMMAND_SYNTAX_ERROR
;
1618 target
->arch_info
= arm11
;
1623 int arm11_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
1625 /* Initialize anything we can set up without talking to the target */
1626 return arm11_build_reg_cache(target
);
1629 /* talk to the target and set things up */
1630 int arm11_examine(struct target_s
*target
)
1635 arm11_common_t
* arm11
= target
->arch_info
;
1639 arm11_add_IR(arm11
, ARM11_IDCODE
, ARM11_TAP_DEFAULT
);
1641 scan_field_t idcode_field
;
1643 arm11_setup_field(arm11
, 32, NULL
, &arm11
->device_id
, &idcode_field
);
1645 arm11_add_dr_scan_vc(1, &idcode_field
, TAP_DRPAUSE
);
1649 arm11_add_debug_SCAN_N(arm11
, 0x00, ARM11_TAP_DEFAULT
);
1651 arm11_add_IR(arm11
, ARM11_INTEST
, ARM11_TAP_DEFAULT
);
1653 scan_field_t chain0_fields
[2];
1655 arm11_setup_field(arm11
, 32, NULL
, &arm11
->didr
, chain0_fields
+ 0);
1656 arm11_setup_field(arm11
, 8, NULL
, &arm11
->implementor
, chain0_fields
+ 1);
1658 arm11_add_dr_scan_vc(asizeof(chain0_fields
), chain0_fields
, TAP_IDLE
);
1660 if ((retval
=jtag_execute_queue())!=ERROR_OK
)
1664 switch (arm11
->device_id
& 0x0FFFF000)
1666 case 0x07B36000: LOG_INFO("found ARM1136"); break;
1667 case 0x07B56000: LOG_INFO("found ARM1156"); break;
1668 case 0x07B76000: LOG_INFO("found ARM1176"); break;
1671 LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1676 arm11
->debug_version
= (arm11
->didr
>> 16) & 0x0F;
1678 if (arm11
->debug_version
!= ARM11_DEBUG_V6
&&
1679 arm11
->debug_version
!= ARM11_DEBUG_V61
)
1681 LOG_ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
1685 arm11
->brp
= ((arm11
->didr
>> 24) & 0x0F) + 1;
1686 arm11
->wrp
= ((arm11
->didr
>> 28) & 0x0F) + 1;
1688 /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1689 arm11
->free_brps
= arm11
->brp
;
1690 arm11
->free_wrps
= arm11
->wrp
;
1692 LOG_DEBUG("IDCODE %08x IMPLEMENTOR %02x DIDR %08x",
1697 /* as a side-effect this reads DSCR and thus
1698 * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1699 * as suggested by the spec.
1702 arm11_check_init(arm11
, NULL
);
1704 target
->type
->examined
= 1;
1709 int arm11_quit(void)
1711 FNC_INFO_NOTIMPLEMENTED
;
1716 /** Load a register that is marked !valid in the register cache */
1717 int arm11_get_reg(reg_t
*reg
)
1721 target_t
* target
= ((arm11_reg_state_t
*)reg
->arch_info
)->target
;
1723 if (target
->state
!= TARGET_HALTED
)
1725 LOG_WARNING("target was not halted");
1726 return ERROR_TARGET_NOT_HALTED
;
1729 /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
1732 arm11_common_t
*arm11
= target
->arch_info
;
1733 const arm11_reg_defs_t
* arm11_reg_info
= arm11_reg_defs
+ ((arm11_reg_state_t
*)reg
->arch_info
)->def_index
;
1739 /** Change a value in the register cache */
1740 int arm11_set_reg(reg_t
*reg
, u8
*buf
)
1744 target_t
* target
= ((arm11_reg_state_t
*)reg
->arch_info
)->target
;
1745 arm11_common_t
*arm11
= target
->arch_info
;
1746 // const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1748 arm11
->reg_values
[((arm11_reg_state_t
*)reg
->arch_info
)->def_index
] = buf_get_u32(buf
, 0, 32);
1755 int arm11_build_reg_cache(target_t
*target
)
1757 arm11_common_t
*arm11
= target
->arch_info
;
1759 NEW(reg_cache_t
, cache
, 1);
1760 NEW(reg_t
, reg_list
, ARM11_REGCACHE_COUNT
);
1761 NEW(arm11_reg_state_t
, arm11_reg_states
, ARM11_REGCACHE_COUNT
);
1763 if (arm11_regs_arch_type
== -1)
1764 arm11_regs_arch_type
= register_reg_arch_type(arm11_get_reg
, arm11_set_reg
);
1766 register_init_dummy(&arm11_gdb_dummy_fp_reg
);
1767 register_init_dummy(&arm11_gdb_dummy_fps_reg
);
1769 arm11
->reg_list
= reg_list
;
1771 /* Build the process context cache */
1772 cache
->name
= "arm11 registers";
1774 cache
->reg_list
= reg_list
;
1775 cache
->num_regs
= ARM11_REGCACHE_COUNT
;
1777 reg_cache_t
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
1780 arm11
->core_cache
= cache
;
1781 // armv7m->process_context = cache;
1785 /* Not very elegant assertion */
1786 if (ARM11_REGCACHE_COUNT
!= asizeof(arm11
->reg_values
) ||
1787 ARM11_REGCACHE_COUNT
!= asizeof(arm11_reg_defs
) ||
1788 ARM11_REGCACHE_COUNT
!= ARM11_RC_MAX
)
1790 LOG_ERROR("BUG: arm11->reg_values inconsistent (%d " ZU
" " ZU
" %d)", ARM11_REGCACHE_COUNT
, asizeof(arm11
->reg_values
), asizeof(arm11_reg_defs
), ARM11_RC_MAX
);
1794 for (i
= 0; i
< ARM11_REGCACHE_COUNT
; i
++)
1796 reg_t
* r
= reg_list
+ i
;
1797 const arm11_reg_defs_t
* rd
= arm11_reg_defs
+ i
;
1798 arm11_reg_state_t
* rs
= arm11_reg_states
+ i
;
1802 r
->value
= (u8
*)(arm11
->reg_values
+ i
);
1805 r
->bitfield_desc
= NULL
;
1806 r
->num_bitfields
= 0;
1807 r
->arch_type
= arm11_regs_arch_type
;
1811 rs
->target
= target
;
1817 int arm11_handle_bool(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, bool * var
, char * name
)
1821 LOG_INFO("%s is %s.", name
, *var
? "enabled" : "disabled");
1826 return ERROR_COMMAND_SYNTAX_ERROR
;
1831 case 'f': /* false */
1833 case 'd': /* disable */
1839 case 't': /* true */
1841 case 'e': /* enable */
1847 LOG_INFO("%s %s.", *var
? "Enabled" : "Disabled", name
);
1852 #define BOOL_WRAPPER(name, print_name) \
1853 int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) \
1855 return arm11_handle_bool(cmd_ctx, cmd, args, argc, &arm11_config_##name, print_name); \
1858 #define RC_TOP(name, descr, more) \
1860 command_t * new_cmd = register_command(cmd_ctx, top_cmd, name, NULL, COMMAND_ANY, descr); \
1861 command_t * top_cmd = new_cmd; \
1865 #define RC_FINAL(name, descr, handler) \
1866 register_command(cmd_ctx, top_cmd, name, handler, COMMAND_ANY, descr);
1868 #define RC_FINAL_BOOL(name, descr, var) \
1869 register_command(cmd_ctx, top_cmd, name, arm11_handle_bool_##var, COMMAND_ANY, descr);
1871 BOOL_WRAPPER(memwrite_burst
, "memory write burst mode")
1872 BOOL_WRAPPER(memwrite_error_fatal
, "fatal error mode for memory writes")
1873 BOOL_WRAPPER(memrw_no_increment
, "\"no increment\" mode for memory transfers")
1874 BOOL_WRAPPER(step_irq_enable
, "IRQs while stepping")
1876 int arm11_handle_vcr(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1880 arm11_vcr
= strtoul(args
[0], NULL
, 0);
1884 return ERROR_COMMAND_SYNTAX_ERROR
;
1887 LOG_INFO("VCR 0x%08X", arm11_vcr
);
1891 const u32 arm11_coproc_instruction_limits
[] =
1893 15, /* coprocessor */
1898 0xFFFFFFFF, /* value */
1901 const char arm11_mrc_syntax
[] = "Syntax: mrc <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2>. All parameters are numbers only.";
1902 const char arm11_mcr_syntax
[] = "Syntax: mcr <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2> <32bit value to write>. All parameters are numbers only.";
1904 arm11_common_t
* arm11_find_target(const char * arg
)
1909 tap
= jtag_TapByString(arg
);
1914 for (t
= all_targets
; t
; t
= t
->next
)
1919 /* if (t->type == arm11_target) */
1920 if (0 == strcmp(t
->type
->name
, "arm11"))
1921 return t
->arch_info
;
1927 int arm11_handle_mrc_mcr(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, bool read
)
1929 if (argc
!= (read
? 6 : 7))
1931 LOG_ERROR("Invalid number of arguments. %s", read
? arm11_mrc_syntax
: arm11_mcr_syntax
);
1935 arm11_common_t
* arm11
= arm11_find_target(args
[0]);
1939 LOG_ERROR("Parameter 1 is not a the JTAG chain position of an ARM11 device. %s",
1940 read
? arm11_mrc_syntax
: arm11_mcr_syntax
);
1945 if (arm11
->target
->state
!= TARGET_HALTED
)
1947 LOG_WARNING("target was not halted");
1948 return ERROR_TARGET_NOT_HALTED
;
1954 for (i
= 0; i
< (read
? 5 : 6); i
++)
1956 values
[i
] = strtoul(args
[i
+ 1], NULL
, 0);
1958 if (values
[i
] > arm11_coproc_instruction_limits
[i
])
1960 LOG_ERROR("Parameter %ld out of bounds (%d max). %s",
1961 (long)(i
+ 2), arm11_coproc_instruction_limits
[i
],
1962 read
? arm11_mrc_syntax
: arm11_mcr_syntax
);
1967 u32 instr
= 0xEE000010 |
1975 instr
|= 0x00100000;
1977 arm11_run_instr_data_prepare(arm11
);
1982 arm11_run_instr_data_from_core_via_r0(arm11
, instr
, &result
);
1984 LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08x (%d)",
1985 values
[0], values
[1], values
[2], values
[3], values
[4], result
, result
);
1989 arm11_run_instr_data_to_core_via_r0(arm11
, instr
, values
[5]);
1991 LOG_INFO("MRC p%d, %d, R0 (#0x%08x), c%d, c%d, %d",
1992 values
[0], values
[1],
1994 values
[2], values
[3], values
[4]);
1997 arm11_run_instr_data_finish(arm11
);
2003 int arm11_handle_mrc(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
2005 return arm11_handle_mrc_mcr(cmd_ctx
, cmd
, args
, argc
, true);
2008 int arm11_handle_mcr(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
2010 return arm11_handle_mrc_mcr(cmd_ctx
, cmd
, args
, argc
, false);
2013 int arm11_register_commands(struct command_context_s
*cmd_ctx
)
2017 command_t
* top_cmd
= NULL
;
2019 RC_TOP( "arm11", "arm11 specific commands",
2021 RC_TOP( "memwrite", "Control memory write transfer mode",
2023 RC_FINAL_BOOL( "burst", "Enable/Disable non-standard but fast burst mode (default: enabled)",
2026 RC_FINAL_BOOL( "error_fatal", "Terminate program if transfer error was found (default: enabled)",
2027 memwrite_error_fatal
)
2030 RC_FINAL_BOOL( "no_increment", "Don't increment address on multi-read/-write (default: disabled)",
2033 RC_FINAL_BOOL( "step_irq_enable", "Enable interrupts while stepping (default: disabled)",
2036 RC_FINAL( "vcr", "Control (Interrupt) Vector Catch Register",
2039 RC_FINAL( "mrc", "Read Coprocessor register",
2042 RC_FINAL( "mcr", "Write Coprocessor register",
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)