1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
25 #include <jtag/interface.h>
38 static uint8_t output_value
;
39 static int dev_mem_fd
;
40 static void *gpio_controller
;
41 static volatile uint8_t *gpio_data_register
;
42 static volatile uint8_t *gpio_data_direction_register
;
44 /* low level command set
46 static int ep93xx_read(void);
47 static void ep93xx_write(int tck
, int tms
, int tdi
);
48 static void ep93xx_reset(int trst
, int srst
);
50 static int ep93xx_speed(int speed
);
51 static int ep93xx_init(void);
52 static int ep93xx_quit(void);
54 struct timespec ep93xx_zzzz
;
56 struct jtag_interface ep93xx_interface
= {
59 .supported
= DEBUG_CAP_TMS_SEQ
,
60 .execute_queue
= bitbang_execute_queue
,
62 .speed
= ep93xx_speed
,
67 static struct bitbang_interface ep93xx_bitbang
= {
69 .write
= ep93xx_write
,
70 .reset
= ep93xx_reset
,
74 static int ep93xx_read(void)
76 return !!(*gpio_data_register
& TDO_BIT
);
79 static void ep93xx_write(int tck
, int tms
, int tdi
)
82 output_value
|= TCK_BIT
;
84 output_value
&= ~TCK_BIT
;
87 output_value
|= TMS_BIT
;
89 output_value
&= ~TMS_BIT
;
92 output_value
|= TDI_BIT
;
94 output_value
&= ~TDI_BIT
;
96 *gpio_data_register
= output_value
;
97 nanosleep(&ep93xx_zzzz
, NULL
);
100 /* (1) assert or (0) deassert reset lines */
101 static void ep93xx_reset(int trst
, int srst
)
104 output_value
|= TRST_BIT
;
106 output_value
&= ~TRST_BIT
;
109 output_value
|= SRST_BIT
;
111 output_value
&= ~SRST_BIT
;
113 *gpio_data_register
= output_value
;
114 nanosleep(&ep93xx_zzzz
, NULL
);
117 static int ep93xx_speed(int speed
)
123 static int set_gonk_mode(void)
128 syscon
= mmap(NULL
, 4096, PROT_READ
| PROT_WRITE
,
129 MAP_SHARED
, dev_mem_fd
, 0x80930000);
130 if (syscon
== MAP_FAILED
) {
132 return ERROR_JTAG_INIT_FAILED
;
135 devicecfg
= *((volatile int *)(syscon
+ 0x80));
136 *((volatile int *)(syscon
+ 0xc0)) = 0xaa;
137 *((volatile int *)(syscon
+ 0x80)) = devicecfg
| 0x08000000;
139 munmap(syscon
, 4096);
144 static int ep93xx_init(void)
148 bitbang_interface
= &ep93xx_bitbang
;
150 ep93xx_zzzz
.tv_sec
= 0;
151 ep93xx_zzzz
.tv_nsec
= 10000000;
153 dev_mem_fd
= open("/dev/mem", O_RDWR
| O_SYNC
);
154 if (dev_mem_fd
< 0) {
156 return ERROR_JTAG_INIT_FAILED
;
159 gpio_controller
= mmap(NULL
, 4096, PROT_READ
| PROT_WRITE
,
160 MAP_SHARED
, dev_mem_fd
, 0x80840000);
161 if (gpio_controller
== MAP_FAILED
) {
164 return ERROR_JTAG_INIT_FAILED
;
167 ret
= set_gonk_mode();
168 if (ret
!= ERROR_OK
) {
169 munmap(gpio_controller
, 4096);
175 /* Use GPIO port A. */
176 gpio_data_register
= gpio_controller
+ 0x00;
177 gpio_data_direction_register
= gpio_controller
+ 0x10;
180 /* Use GPIO port B. */
181 gpio_data_register
= gpio_controller
+ 0x04;
182 gpio_data_direction_register
= gpio_controller
+ 0x14;
184 /* Use GPIO port C. */
185 gpio_data_register
= gpio_controller
+ 0x08;
186 gpio_data_direction_register
= gpio_controller
+ 0x18;
188 /* Use GPIO port D. */
189 gpio_data_register
= gpio_controller
+ 0x0c;
190 gpio_data_direction_register
= gpio_controller
+ 0x1c;
193 /* Use GPIO port C. */
194 gpio_data_register
= gpio_controller
+ 0x08;
195 gpio_data_direction_register
= gpio_controller
+ 0x18;
197 LOG_INFO("gpio_data_register = %p", gpio_data_register
);
198 LOG_INFO("gpio_data_direction_reg = %p", gpio_data_direction_register
);
200 * Configure bit 0 (TDO) as an input, and bits 1-5 (TDI, TCK
201 * TMS, TRST, SRST) as outputs. Drive TDI and TCK low, and
202 * TMS/TRST/SRST high.
204 output_value
= TMS_BIT
| TRST_BIT
| SRST_BIT
| VCC_BIT
;
205 *gpio_data_register
= output_value
;
206 nanosleep(&ep93xx_zzzz
, NULL
);
209 * Configure the direction register. 1 = output, 0 = input.
211 *gpio_data_direction_register
=
212 TDI_BIT
| TCK_BIT
| TMS_BIT
| TRST_BIT
| SRST_BIT
| VCC_BIT
;
214 nanosleep(&ep93xx_zzzz
, NULL
);
218 static int ep93xx_quit(void)
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