1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
17 ***************************************************************************/
23 #include <jtag/interface.h>
36 static uint8_t output_value
;
37 static int dev_mem_fd
;
38 static void *gpio_controller
;
39 static volatile uint8_t *gpio_data_register
;
40 static volatile uint8_t *gpio_data_direction_register
;
42 /* low level command set
44 static bb_value_t
ep93xx_read(void);
45 static int ep93xx_write(int tck
, int tms
, int tdi
);
46 static int ep93xx_reset(int trst
, int srst
);
48 static int ep93xx_init(void);
49 static int ep93xx_quit(void);
51 struct timespec ep93xx_zzzz
;
53 static struct jtag_interface ep93xx_interface
= {
54 .supported
= DEBUG_CAP_TMS_SEQ
,
55 .execute_queue
= bitbang_execute_queue
,
58 struct adapter_driver ep93xx_adapter_driver
= {
60 .transports
= jtag_only
,
64 .reset
= ep93xx_reset
,
66 .jtag_ops
= &ep93xx_interface
,
69 static struct bitbang_interface ep93xx_bitbang
= {
71 .write
= ep93xx_write
,
75 static bb_value_t
ep93xx_read(void)
77 return (*gpio_data_register
& TDO_BIT
) ? BB_HIGH
: BB_LOW
;
80 static int ep93xx_write(int tck
, int tms
, int tdi
)
83 output_value
|= TCK_BIT
;
85 output_value
&= ~TCK_BIT
;
88 output_value
|= TMS_BIT
;
90 output_value
&= ~TMS_BIT
;
93 output_value
|= TDI_BIT
;
95 output_value
&= ~TDI_BIT
;
97 *gpio_data_register
= output_value
;
98 nanosleep(&ep93xx_zzzz
, NULL
);
103 /* (1) assert or (0) deassert reset lines */
104 static int ep93xx_reset(int trst
, int srst
)
107 output_value
|= TRST_BIT
;
109 output_value
&= ~TRST_BIT
;
112 output_value
|= SRST_BIT
;
114 output_value
&= ~SRST_BIT
;
116 *gpio_data_register
= output_value
;
117 nanosleep(&ep93xx_zzzz
, NULL
);
122 static int set_gonk_mode(void)
127 syscon
= mmap(NULL
, 4096, PROT_READ
| PROT_WRITE
,
128 MAP_SHARED
, dev_mem_fd
, 0x80930000);
129 if (syscon
== MAP_FAILED
) {
131 return ERROR_JTAG_INIT_FAILED
;
134 devicecfg
= *((volatile int *)(syscon
+ 0x80));
135 *((volatile int *)(syscon
+ 0xc0)) = 0xaa;
136 *((volatile int *)(syscon
+ 0x80)) = devicecfg
| 0x08000000;
138 munmap(syscon
, 4096);
143 static int ep93xx_init(void)
147 bitbang_interface
= &ep93xx_bitbang
;
149 ep93xx_zzzz
.tv_sec
= 0;
150 ep93xx_zzzz
.tv_nsec
= 10000000;
152 dev_mem_fd
= open("/dev/mem", O_RDWR
| O_SYNC
);
153 if (dev_mem_fd
< 0) {
155 return ERROR_JTAG_INIT_FAILED
;
158 gpio_controller
= mmap(NULL
, 4096, PROT_READ
| PROT_WRITE
,
159 MAP_SHARED
, dev_mem_fd
, 0x80840000);
160 if (gpio_controller
== MAP_FAILED
) {
163 return ERROR_JTAG_INIT_FAILED
;
166 ret
= set_gonk_mode();
167 if (ret
!= ERROR_OK
) {
168 munmap(gpio_controller
, 4096);
174 /* Use GPIO port A. */
175 gpio_data_register
= gpio_controller
+ 0x00;
176 gpio_data_direction_register
= gpio_controller
+ 0x10;
179 /* Use GPIO port B. */
180 gpio_data_register
= gpio_controller
+ 0x04;
181 gpio_data_direction_register
= gpio_controller
+ 0x14;
183 /* Use GPIO port C. */
184 gpio_data_register
= gpio_controller
+ 0x08;
185 gpio_data_direction_register
= gpio_controller
+ 0x18;
187 /* Use GPIO port D. */
188 gpio_data_register
= gpio_controller
+ 0x0c;
189 gpio_data_direction_register
= gpio_controller
+ 0x1c;
192 /* Use GPIO port C. */
193 gpio_data_register
= gpio_controller
+ 0x08;
194 gpio_data_direction_register
= gpio_controller
+ 0x18;
196 LOG_INFO("gpio_data_register = %p", gpio_data_register
);
197 LOG_INFO("gpio_data_direction_reg = %p", gpio_data_direction_register
);
199 * Configure bit 0 (TDO) as an input, and bits 1-5 (TDI, TCK
200 * TMS, TRST, SRST) as outputs. Drive TDI and TCK low, and
201 * TMS/TRST/SRST high.
203 output_value
= TMS_BIT
| TRST_BIT
| SRST_BIT
| VCC_BIT
;
204 *gpio_data_register
= output_value
;
205 nanosleep(&ep93xx_zzzz
, NULL
);
208 * Configure the direction register. 1 = output, 0 = input.
210 *gpio_data_direction_register
=
211 TDI_BIT
| TCK_BIT
| TMS_BIT
| TRST_BIT
| SRST_BIT
| VCC_BIT
;
213 nanosleep(&ep93xx_zzzz
, NULL
);
217 static int ep93xx_quit(void)
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)