1 /***************************************************************************
2 * Copyright (C) 2013 by Andes Technology *
3 * Hsiangkai Wang <hkwang@andestech.com> *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
19 ***************************************************************************/
24 #include <jtag/drivers/libusb_common.h>
25 #include <helper/log.h>
26 #include <helper/time_support.h>
27 #include <target/target.h>
28 #include <jtag/jtag.h>
29 #include <target/nds32_insn.h>
30 #include <target/nds32_reg.h>
34 /* Global USB buffers */
35 static uint8_t usb_in_buffer
[AICE_IN_BUFFER_SIZE
];
36 static uint8_t usb_out_buffer
[AICE_OUT_BUFFER_SIZE
];
37 static uint8_t current_target_id
;
38 static uint32_t jtag_clock
;
39 static struct aice_usb_handler_s aice_handler
;
40 /* AICE max retry times. If AICE command timeout, retry it. */
41 static int aice_max_retry_times
= 10;
42 /* Default endian is little endian. */
43 static enum aice_target_endian data_endian
;
46 /***************************************************************************/
47 /* AICE commands' pack/unpack functions */
48 static void aice_pack_htda(uint8_t cmd_code
, uint8_t extra_word_length
,
51 usb_out_buffer
[0] = cmd_code
;
52 usb_out_buffer
[1] = extra_word_length
;
53 usb_out_buffer
[2] = (uint8_t)(address
& 0xFF);
56 static void aice_pack_htdc(uint8_t cmd_code
, uint8_t extra_word_length
,
57 uint32_t address
, uint32_t word
, enum aice_target_endian access_endian
)
59 usb_out_buffer
[0] = cmd_code
;
60 usb_out_buffer
[1] = extra_word_length
;
61 usb_out_buffer
[2] = (uint8_t)(address
& 0xFF);
62 if (access_endian
== AICE_BIG_ENDIAN
) {
63 *(uint32_t *)(usb_out_buffer
+ 3) = word
;
65 usb_out_buffer
[3] = (uint8_t)((word
>> 24) & 0xFF);
66 usb_out_buffer
[4] = (uint8_t)((word
>> 16) & 0xFF);
67 usb_out_buffer
[5] = (uint8_t)((word
>> 8) & 0xFF);
68 usb_out_buffer
[6] = (uint8_t)(word
& 0xFF);
72 static void aice_pack_htdma(uint8_t cmd_code
, uint8_t target_id
,
73 uint8_t extra_word_length
, uint32_t address
)
75 usb_out_buffer
[0] = cmd_code
;
76 usb_out_buffer
[1] = target_id
;
77 usb_out_buffer
[2] = extra_word_length
;
78 usb_out_buffer
[3] = (uint8_t)(address
& 0xFF);
81 static void aice_pack_htdmb(uint8_t cmd_code
, uint8_t target_id
,
82 uint8_t extra_word_length
, uint32_t address
)
84 usb_out_buffer
[0] = cmd_code
;
85 usb_out_buffer
[1] = target_id
;
86 usb_out_buffer
[2] = extra_word_length
;
87 usb_out_buffer
[3] = 0;
88 usb_out_buffer
[4] = (uint8_t)((address
>> 24) & 0xFF);
89 usb_out_buffer
[5] = (uint8_t)((address
>> 16) & 0xFF);
90 usb_out_buffer
[6] = (uint8_t)((address
>> 8) & 0xFF);
91 usb_out_buffer
[7] = (uint8_t)(address
& 0xFF);
94 static void aice_pack_htdmc(uint8_t cmd_code
, uint8_t target_id
,
95 uint8_t extra_word_length
, uint32_t address
, uint32_t word
,
96 enum aice_target_endian access_endian
)
98 usb_out_buffer
[0] = cmd_code
;
99 usb_out_buffer
[1] = target_id
;
100 usb_out_buffer
[2] = extra_word_length
;
101 usb_out_buffer
[3] = (uint8_t)(address
& 0xFF);
102 if (access_endian
== AICE_BIG_ENDIAN
) {
103 *(uint32_t *)(usb_out_buffer
+ 4) = word
;
105 usb_out_buffer
[4] = (uint8_t)((word
>> 24) & 0xFF);
106 usb_out_buffer
[5] = (uint8_t)((word
>> 16) & 0xFF);
107 usb_out_buffer
[6] = (uint8_t)((word
>> 8) & 0xFF);
108 usb_out_buffer
[7] = (uint8_t)(word
& 0xFF);
112 static void aice_pack_htdmc_multiple_data(uint8_t cmd_code
, uint8_t target_id
,
113 uint8_t extra_word_length
, uint32_t address
, uint32_t *word
,
114 uint8_t num_of_words
, enum aice_target_endian access_endian
)
116 usb_out_buffer
[0] = cmd_code
;
117 usb_out_buffer
[1] = target_id
;
118 usb_out_buffer
[2] = extra_word_length
;
119 usb_out_buffer
[3] = (uint8_t)(address
& 0xFF);
122 for (i
= 0 ; i
< num_of_words
; i
++, word
++) {
123 if (access_endian
== AICE_BIG_ENDIAN
) {
124 *(uint32_t *)(usb_out_buffer
+ 4 + i
* 4) = *word
;
126 usb_out_buffer
[4 + i
* 4] = (uint8_t)((*word
>> 24) & 0xFF);
127 usb_out_buffer
[5 + i
* 4] = (uint8_t)((*word
>> 16) & 0xFF);
128 usb_out_buffer
[6 + i
* 4] = (uint8_t)((*word
>> 8) & 0xFF);
129 usb_out_buffer
[7 + i
* 4] = (uint8_t)(*word
& 0xFF);
134 static void aice_pack_htdmd(uint8_t cmd_code
, uint8_t target_id
,
135 uint8_t extra_word_length
, uint32_t address
, uint32_t word
,
136 enum aice_target_endian access_endian
)
138 usb_out_buffer
[0] = cmd_code
;
139 usb_out_buffer
[1] = target_id
;
140 usb_out_buffer
[2] = extra_word_length
;
141 usb_out_buffer
[3] = 0;
142 usb_out_buffer
[4] = (uint8_t)((address
>> 24) & 0xFF);
143 usb_out_buffer
[5] = (uint8_t)((address
>> 16) & 0xFF);
144 usb_out_buffer
[6] = (uint8_t)((address
>> 8) & 0xFF);
145 usb_out_buffer
[7] = (uint8_t)(address
& 0xFF);
146 if (access_endian
== AICE_BIG_ENDIAN
) {
147 *(uint32_t *)(usb_out_buffer
+ 8) = word
;
149 usb_out_buffer
[8] = (uint8_t)((word
>> 24) & 0xFF);
150 usb_out_buffer
[9] = (uint8_t)((word
>> 16) & 0xFF);
151 usb_out_buffer
[10] = (uint8_t)((word
>> 8) & 0xFF);
152 usb_out_buffer
[11] = (uint8_t)(word
& 0xFF);
156 static void aice_pack_htdmd_multiple_data(uint8_t cmd_code
, uint8_t target_id
,
157 uint8_t extra_word_length
, uint32_t address
, const uint32_t *word
,
158 enum aice_target_endian access_endian
)
160 usb_out_buffer
[0] = cmd_code
;
161 usb_out_buffer
[1] = target_id
;
162 usb_out_buffer
[2] = extra_word_length
;
163 usb_out_buffer
[3] = 0;
164 usb_out_buffer
[4] = (uint8_t)((address
>> 24) & 0xFF);
165 usb_out_buffer
[5] = (uint8_t)((address
>> 16) & 0xFF);
166 usb_out_buffer
[6] = (uint8_t)((address
>> 8) & 0xFF);
167 usb_out_buffer
[7] = (uint8_t)(address
& 0xFF);
170 /* num_of_words may be over 0xFF, so use uint32_t */
171 uint32_t num_of_words
= extra_word_length
+ 1;
173 for (i
= 0 ; i
< num_of_words
; i
++, word
++) {
174 if (access_endian
== AICE_BIG_ENDIAN
) {
175 *(uint32_t *)(usb_out_buffer
+ 8 + i
* 4) = *word
;
177 usb_out_buffer
[8 + i
* 4] = (uint8_t)((*word
>> 24) & 0xFF);
178 usb_out_buffer
[9 + i
* 4] = (uint8_t)((*word
>> 16) & 0xFF);
179 usb_out_buffer
[10 + i
* 4] = (uint8_t)((*word
>> 8) & 0xFF);
180 usb_out_buffer
[11 + i
* 4] = (uint8_t)(*word
& 0xFF);
185 static void aice_unpack_dtha(uint8_t *cmd_ack_code
, uint8_t *extra_word_length
,
186 uint32_t *word
, enum aice_target_endian access_endian
)
188 *cmd_ack_code
= usb_in_buffer
[0];
189 *extra_word_length
= usb_in_buffer
[1];
191 if (access_endian
== AICE_BIG_ENDIAN
) {
192 *word
= *(uint32_t *)(usb_in_buffer
+ 2);
194 *word
= (usb_in_buffer
[2] << 24) |
195 (usb_in_buffer
[3] << 16) |
196 (usb_in_buffer
[4] << 8) |
201 static void aice_unpack_dtha_multiple_data(uint8_t *cmd_ack_code
,
202 uint8_t *extra_word_length
, uint32_t *word
, uint8_t num_of_words
,
203 enum aice_target_endian access_endian
)
205 *cmd_ack_code
= usb_in_buffer
[0];
206 *extra_word_length
= usb_in_buffer
[1];
209 for (i
= 0 ; i
< num_of_words
; i
++, word
++) {
210 if (access_endian
== AICE_BIG_ENDIAN
) {
211 *word
= *(uint32_t *)(usb_in_buffer
+ 2 + i
* 4);
213 *word
= (usb_in_buffer
[2 + i
* 4] << 24) |
214 (usb_in_buffer
[3 + i
* 4] << 16) |
215 (usb_in_buffer
[4 + i
* 4] << 8) |
216 (usb_in_buffer
[5 + i
* 4]);
221 static void aice_unpack_dthb(uint8_t *cmd_ack_code
, uint8_t *extra_word_length
)
223 *cmd_ack_code
= usb_in_buffer
[0];
224 *extra_word_length
= usb_in_buffer
[1];
227 static void aice_unpack_dthma(uint8_t *cmd_ack_code
, uint8_t *target_id
,
228 uint8_t *extra_word_length
, uint32_t *word
,
229 enum aice_target_endian access_endian
)
231 *cmd_ack_code
= usb_in_buffer
[0];
232 *target_id
= usb_in_buffer
[1];
233 *extra_word_length
= usb_in_buffer
[2];
234 if (access_endian
== AICE_BIG_ENDIAN
) {
235 *word
= *(uint32_t *)(usb_in_buffer
+ 4);
237 *word
= (usb_in_buffer
[4] << 24) |
238 (usb_in_buffer
[5] << 16) |
239 (usb_in_buffer
[6] << 8) |
244 static void aice_unpack_dthma_multiple_data(uint8_t *cmd_ack_code
,
245 uint8_t *target_id
, uint8_t *extra_word_length
, uint32_t *word
,
246 enum aice_target_endian access_endian
)
248 *cmd_ack_code
= usb_in_buffer
[0];
249 *target_id
= usb_in_buffer
[1];
250 *extra_word_length
= usb_in_buffer
[2];
251 if (access_endian
== AICE_BIG_ENDIAN
) {
252 *word
= *(uint32_t *)(usb_in_buffer
+ 4);
254 *word
= (usb_in_buffer
[4] << 24) |
255 (usb_in_buffer
[5] << 16) |
256 (usb_in_buffer
[6] << 8) |
262 for (i
= 0; i
< *extra_word_length
; i
++) {
263 if (access_endian
== AICE_BIG_ENDIAN
) {
264 *word
= *(uint32_t *)(usb_in_buffer
+ 8 + i
* 4);
266 *word
= (usb_in_buffer
[8 + i
* 4] << 24) |
267 (usb_in_buffer
[9 + i
* 4] << 16) |
268 (usb_in_buffer
[10 + i
* 4] << 8) |
269 (usb_in_buffer
[11 + i
* 4]);
275 static void aice_unpack_dthmb(uint8_t *cmd_ack_code
, uint8_t *target_id
,
276 uint8_t *extra_word_length
)
278 *cmd_ack_code
= usb_in_buffer
[0];
279 *target_id
= usb_in_buffer
[1];
280 *extra_word_length
= usb_in_buffer
[2];
283 /***************************************************************************/
284 /* End of AICE commands' pack/unpack functions */
286 /* calls the given usb_bulk_* function, allowing for the data to
287 * trickle in with some timeouts */
288 static int usb_bulk_with_retries(
289 int (*f
)(jtag_libusb_device_handle
*, int, char *, int, int),
290 jtag_libusb_device_handle
*dev
, int ep
,
291 char *bytes
, int size
, int timeout
)
293 int tries
= 3, count
= 0;
295 while (tries
&& (count
< size
)) {
296 int result
= f(dev
, ep
, bytes
+ count
, size
- count
, timeout
);
299 else if ((-ETIMEDOUT
!= result
) || !--tries
)
305 static int wrap_usb_bulk_write(jtag_libusb_device_handle
*dev
, int ep
,
306 char *buff
, int size
, int timeout
)
308 /* usb_bulk_write() takes const char *buff */
309 return jtag_libusb_bulk_write(dev
, ep
, buff
, size
, timeout
);
312 static inline int usb_bulk_write_ex(jtag_libusb_device_handle
*dev
, int ep
,
313 char *bytes
, int size
, int timeout
)
315 return usb_bulk_with_retries(&wrap_usb_bulk_write
,
316 dev
, ep
, bytes
, size
, timeout
);
319 static inline int usb_bulk_read_ex(jtag_libusb_device_handle
*dev
, int ep
,
320 char *bytes
, int size
, int timeout
)
322 return usb_bulk_with_retries(&jtag_libusb_bulk_read
,
323 dev
, ep
, bytes
, size
, timeout
);
326 /* Write data from out_buffer to USB. */
327 static int aice_usb_write(uint8_t *out_buffer
, int out_length
)
331 if (out_length
> AICE_OUT_BUFFER_SIZE
) {
332 LOG_ERROR("aice_write illegal out_length=%d (max=%d)",
333 out_length
, AICE_OUT_BUFFER_SIZE
);
337 result
= usb_bulk_write_ex(aice_handler
.usb_handle
, aice_handler
.usb_write_ep
,
338 (char *)out_buffer
, out_length
, AICE_USB_TIMEOUT
);
340 DEBUG_JTAG_IO("aice_usb_write, out_length = %d, result = %d",
346 /* Read data from USB into in_buffer. */
347 static int aice_usb_read(uint8_t *in_buffer
, int expected_size
)
349 int result
= usb_bulk_read_ex(aice_handler
.usb_handle
, aice_handler
.usb_read_ep
,
350 (char *)in_buffer
, expected_size
, AICE_USB_TIMEOUT
);
352 DEBUG_JTAG_IO("aice_usb_read, result = %d", result
);
357 static uint8_t usb_out_packets_buffer
[AICE_OUT_PACKETS_BUFFER_SIZE
];
358 static uint8_t usb_in_packets_buffer
[AICE_IN_PACKETS_BUFFER_SIZE
];
359 static uint32_t usb_out_packets_buffer_length
;
360 static uint32_t usb_in_packets_buffer_length
;
361 static bool usb_pack_command
;
363 static int aice_usb_packet_flush(void)
365 if (usb_out_packets_buffer_length
== 0)
368 LOG_DEBUG("Flush usb packets");
372 aice_usb_write(usb_out_packets_buffer
, usb_out_packets_buffer_length
);
373 result
= aice_usb_read(usb_in_packets_buffer
, usb_in_packets_buffer_length
);
375 usb_out_packets_buffer_length
= 0;
376 usb_in_packets_buffer_length
= 0;
381 static void aice_usb_packet_append(uint8_t *out_buffer
, int out_length
,
384 if (usb_out_packets_buffer_length
+ out_length
> AICE_OUT_PACKETS_BUFFER_SIZE
)
385 aice_usb_packet_flush();
387 LOG_DEBUG("Append usb packets 0x%02x", out_buffer
[0]);
389 memcpy(usb_out_packets_buffer
+ usb_out_packets_buffer_length
,
392 usb_out_packets_buffer_length
+= out_length
;
393 usb_in_packets_buffer_length
+= in_length
;
396 /***************************************************************************/
398 static int aice_scan_chain(uint32_t *id_codes
, uint8_t *num_of_ids
)
403 if (usb_pack_command
)
404 aice_usb_packet_flush();
407 aice_pack_htda(AICE_CMD_SCAN_CHAIN
, 0x0F, 0x0);
409 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDA
);
411 LOG_DEBUG("SCAN_CHAIN, length: 0x0F");
413 /** TODO: modify receive length */
414 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHA
);
415 if (AICE_FORMAT_DTHA
!= result
) {
416 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
417 AICE_FORMAT_DTHA
, result
);
421 uint8_t cmd_ack_code
;
422 aice_unpack_dtha_multiple_data(&cmd_ack_code
, num_of_ids
, id_codes
,
423 0x10, AICE_LITTLE_ENDIAN
);
425 LOG_DEBUG("SCAN_CHAIN response, # of IDs: %d", *num_of_ids
);
427 if (cmd_ack_code
!= AICE_CMD_SCAN_CHAIN
) {
428 LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
429 AICE_CMD_SCAN_CHAIN
, cmd_ack_code
);
431 if (retry_times
> aice_max_retry_times
)
434 /* clear timeout and retry */
435 if (aice_write_ctrl(AICE_WRITE_CTRL_CLEAR_TIMEOUT_STATUS
, 0x1) != ERROR_OK
)
442 if (*num_of_ids
== 0xFF) {
443 LOG_ERROR("No target connected");
445 } else if (*num_of_ids
== 0x10) {
446 LOG_INFO("The ice chain over 16 targets");
456 int aice_read_ctrl(uint32_t address
, uint32_t *data
)
460 if (usb_pack_command
)
461 aice_usb_packet_flush();
463 aice_pack_htda(AICE_CMD_READ_CTRL
, 0, address
);
465 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDA
);
467 LOG_DEBUG("READ_CTRL, address: 0x%x", address
);
469 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHA
);
470 if (AICE_FORMAT_DTHA
!= result
) {
471 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
472 AICE_FORMAT_DTHA
, result
);
476 uint8_t cmd_ack_code
;
477 uint8_t extra_length
;
478 aice_unpack_dtha(&cmd_ack_code
, &extra_length
, data
, AICE_LITTLE_ENDIAN
);
480 LOG_DEBUG("READ_CTRL response, data: 0x%x", *data
);
482 if (cmd_ack_code
!= AICE_CMD_READ_CTRL
) {
483 LOG_ERROR("aice command error (command=0x%x, response=0x%x)",
484 AICE_CMD_READ_CTRL
, cmd_ack_code
);
491 int aice_write_ctrl(uint32_t address
, uint32_t data
)
495 if (usb_pack_command
)
496 aice_usb_packet_flush();
498 aice_pack_htdc(AICE_CMD_WRITE_CTRL
, 0, address
, data
, AICE_LITTLE_ENDIAN
);
500 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDC
);
502 LOG_DEBUG("WRITE_CTRL, address: 0x%x, data: 0x%x", address
, data
);
504 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHB
);
505 if (AICE_FORMAT_DTHB
!= result
) {
506 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
507 AICE_FORMAT_DTHB
, result
);
511 uint8_t cmd_ack_code
;
512 uint8_t extra_length
;
513 aice_unpack_dthb(&cmd_ack_code
, &extra_length
);
515 LOG_DEBUG("WRITE_CTRL response");
517 if (cmd_ack_code
!= AICE_CMD_WRITE_CTRL
) {
518 LOG_ERROR("aice command error (command=0x%x, response=0x%x)",
519 AICE_CMD_WRITE_CTRL
, cmd_ack_code
);
526 int aice_read_dtr(uint8_t target_id
, uint32_t *data
)
531 if (usb_pack_command
)
532 aice_usb_packet_flush();
535 aice_pack_htdma(AICE_CMD_T_READ_DTR
, target_id
, 0, 0);
537 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMA
);
539 LOG_DEBUG("READ_DTR");
541 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMA
);
542 if (AICE_FORMAT_DTHMA
!= result
) {
543 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
544 AICE_FORMAT_DTHMA
, result
);
548 uint8_t cmd_ack_code
;
549 uint8_t extra_length
;
550 uint8_t res_target_id
;
551 aice_unpack_dthma(&cmd_ack_code
, &res_target_id
, &extra_length
,
552 data
, AICE_LITTLE_ENDIAN
);
554 LOG_DEBUG("READ_DTR response, data: 0x%x", *data
);
556 if (cmd_ack_code
== AICE_CMD_T_READ_DTR
) {
559 LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
560 AICE_CMD_T_READ_DTR
, cmd_ack_code
);
562 if (retry_times
> aice_max_retry_times
)
565 /* clear timeout and retry */
566 if (aice_write_ctrl(AICE_WRITE_CTRL_CLEAR_TIMEOUT_STATUS
, 0x1) != ERROR_OK
)
576 int aice_write_dtr(uint8_t target_id
, uint32_t data
)
581 if (usb_pack_command
)
582 aice_usb_packet_flush();
585 aice_pack_htdmc(AICE_CMD_T_WRITE_DTR
, target_id
, 0, 0, data
,
588 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMC
);
590 LOG_DEBUG("WRITE_DTR, data: 0x%x", data
);
592 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMB
);
593 if (AICE_FORMAT_DTHMB
!= result
) {
594 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
595 AICE_FORMAT_DTHMB
, result
);
599 uint8_t cmd_ack_code
;
600 uint8_t extra_length
;
601 uint8_t res_target_id
;
602 aice_unpack_dthmb(&cmd_ack_code
, &res_target_id
, &extra_length
);
604 LOG_DEBUG("WRITE_DTR response");
606 if (cmd_ack_code
== AICE_CMD_T_WRITE_DTR
) {
609 LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
610 AICE_CMD_T_WRITE_DTR
, cmd_ack_code
);
612 if (retry_times
> aice_max_retry_times
)
615 /* clear timeout and retry */
616 if (aice_write_ctrl(AICE_WRITE_CTRL_CLEAR_TIMEOUT_STATUS
, 0x1) != ERROR_OK
)
626 int aice_read_misc(uint8_t target_id
, uint32_t address
, uint32_t *data
)
631 if (usb_pack_command
)
632 aice_usb_packet_flush();
635 aice_pack_htdma(AICE_CMD_T_READ_MISC
, target_id
, 0, address
);
637 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMA
);
639 LOG_DEBUG("READ_MISC, address: 0x%x", address
);
641 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMA
);
642 if (AICE_FORMAT_DTHMA
!= result
) {
643 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
644 AICE_FORMAT_DTHMA
, result
);
645 return ERROR_AICE_DISCONNECT
;
648 uint8_t cmd_ack_code
;
649 uint8_t extra_length
;
650 uint8_t res_target_id
;
651 aice_unpack_dthma(&cmd_ack_code
, &res_target_id
, &extra_length
,
652 data
, AICE_LITTLE_ENDIAN
);
654 LOG_DEBUG("READ_MISC response, data: 0x%x", *data
);
656 if (cmd_ack_code
== AICE_CMD_T_READ_MISC
) {
659 LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
660 AICE_CMD_T_READ_MISC
, cmd_ack_code
);
662 if (retry_times
> aice_max_retry_times
)
665 /* clear timeout and retry */
666 if (aice_write_ctrl(AICE_WRITE_CTRL_CLEAR_TIMEOUT_STATUS
, 0x1) != ERROR_OK
)
676 int aice_write_misc(uint8_t target_id
, uint32_t address
, uint32_t data
)
681 if (usb_pack_command
)
682 aice_usb_packet_flush();
685 aice_pack_htdmc(AICE_CMD_T_WRITE_MISC
, target_id
, 0, address
,
686 data
, AICE_LITTLE_ENDIAN
);
688 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMC
);
690 LOG_DEBUG("WRITE_MISC, address: 0x%x, data: 0x%x", address
, data
);
692 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMB
);
693 if (AICE_FORMAT_DTHMB
!= result
) {
694 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
695 AICE_FORMAT_DTHMB
, result
);
699 uint8_t cmd_ack_code
;
700 uint8_t extra_length
;
701 uint8_t res_target_id
;
702 aice_unpack_dthmb(&cmd_ack_code
, &res_target_id
, &extra_length
);
704 LOG_DEBUG("WRITE_MISC response");
706 if (cmd_ack_code
== AICE_CMD_T_WRITE_MISC
) {
709 LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
710 AICE_CMD_T_WRITE_MISC
, cmd_ack_code
);
712 if (retry_times
> aice_max_retry_times
)
715 /* clear timeout and retry */
716 if (aice_write_ctrl(AICE_WRITE_CTRL_CLEAR_TIMEOUT_STATUS
, 0x1) != ERROR_OK
)
726 int aice_read_edmsr(uint8_t target_id
, uint32_t address
, uint32_t *data
)
731 if (usb_pack_command
)
732 aice_usb_packet_flush();
735 aice_pack_htdma(AICE_CMD_T_READ_EDMSR
, target_id
, 0, address
);
737 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMA
);
739 LOG_DEBUG("READ_EDMSR, address: 0x%x", address
);
741 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMA
);
742 if (AICE_FORMAT_DTHMA
!= result
) {
743 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
744 AICE_FORMAT_DTHMA
, result
);
748 uint8_t cmd_ack_code
;
749 uint8_t extra_length
;
750 uint8_t res_target_id
;
751 aice_unpack_dthma(&cmd_ack_code
, &res_target_id
, &extra_length
,
752 data
, AICE_LITTLE_ENDIAN
);
754 LOG_DEBUG("READ_EDMSR response, data: 0x%x", *data
);
756 if (cmd_ack_code
== AICE_CMD_T_READ_EDMSR
) {
759 LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
760 AICE_CMD_T_READ_EDMSR
, cmd_ack_code
);
762 if (retry_times
> aice_max_retry_times
)
765 /* clear timeout and retry */
766 if (aice_write_ctrl(AICE_WRITE_CTRL_CLEAR_TIMEOUT_STATUS
, 0x1) != ERROR_OK
)
776 int aice_write_edmsr(uint8_t target_id
, uint32_t address
, uint32_t data
)
781 if (usb_pack_command
)
782 aice_usb_packet_flush();
785 aice_pack_htdmc(AICE_CMD_T_WRITE_EDMSR
, target_id
, 0, address
,
786 data
, AICE_LITTLE_ENDIAN
);
788 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMC
);
790 LOG_DEBUG("WRITE_EDMSR, address: 0x%x, data: 0x%x", address
, data
);
792 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMB
);
793 if (AICE_FORMAT_DTHMB
!= result
) {
794 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
795 AICE_FORMAT_DTHMB
, result
);
799 uint8_t cmd_ack_code
;
800 uint8_t extra_length
;
801 uint8_t res_target_id
;
802 aice_unpack_dthmb(&cmd_ack_code
, &res_target_id
, &extra_length
);
804 LOG_DEBUG("WRITE_EDMSR response");
806 if (cmd_ack_code
== AICE_CMD_T_WRITE_EDMSR
) {
809 LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
810 AICE_CMD_T_WRITE_EDMSR
, cmd_ack_code
);
812 if (retry_times
> aice_max_retry_times
)
815 /* clear timeout and retry */
816 if (aice_write_ctrl(AICE_WRITE_CTRL_CLEAR_TIMEOUT_STATUS
, 0x1) != ERROR_OK
)
826 static int aice_switch_to_big_endian(uint32_t *word
, uint8_t num_of_words
)
830 for (uint8_t i
= 0 ; i
< num_of_words
; i
++) {
831 tmp
= ((word
[i
] >> 24) & 0x000000FF) |
832 ((word
[i
] >> 8) & 0x0000FF00) |
833 ((word
[i
] << 8) & 0x00FF0000) |
834 ((word
[i
] << 24) & 0xFF000000);
841 static int aice_write_dim(uint8_t target_id
, uint32_t *word
, uint8_t num_of_words
)
844 uint32_t big_endian_word
[4];
847 if (usb_pack_command
)
848 aice_usb_packet_flush();
850 memcpy(big_endian_word
, word
, sizeof(big_endian_word
));
852 /** instruction is big-endian */
853 aice_switch_to_big_endian(big_endian_word
, num_of_words
);
856 aice_pack_htdmc_multiple_data(AICE_CMD_T_WRITE_DIM
, target_id
,
858 big_endian_word
, num_of_words
, AICE_LITTLE_ENDIAN
);
860 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMC
+ (num_of_words
- 1) * 4);
862 LOG_DEBUG("WRITE_DIM, data: 0x%08x, 0x%08x, 0x%08x, 0x%08x",
868 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMB
);
869 if (AICE_FORMAT_DTHMB
!= result
) {
870 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
871 AICE_FORMAT_DTHMB
, result
);
875 uint8_t cmd_ack_code
;
876 uint8_t extra_length
;
877 uint8_t res_target_id
;
878 aice_unpack_dthmb(&cmd_ack_code
, &res_target_id
, &extra_length
);
880 LOG_DEBUG("WRITE_DIM response");
882 if (cmd_ack_code
== AICE_CMD_T_WRITE_DIM
) {
885 LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
886 AICE_CMD_T_WRITE_DIM
, cmd_ack_code
);
888 if (retry_times
> aice_max_retry_times
)
891 /* clear timeout and retry */
892 if (aice_write_ctrl(AICE_WRITE_CTRL_CLEAR_TIMEOUT_STATUS
, 0x1) != ERROR_OK
)
902 static int aice_do_execute(uint8_t target_id
)
907 if (usb_pack_command
)
908 aice_usb_packet_flush();
911 aice_pack_htdmc(AICE_CMD_T_EXECUTE
, target_id
, 0, 0, 0, AICE_LITTLE_ENDIAN
);
913 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMC
);
915 LOG_DEBUG("EXECUTE");
917 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMB
);
918 if (AICE_FORMAT_DTHMB
!= result
) {
919 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
920 AICE_FORMAT_DTHMB
, result
);
924 uint8_t cmd_ack_code
;
925 uint8_t extra_length
;
926 uint8_t res_target_id
;
927 aice_unpack_dthmb(&cmd_ack_code
, &res_target_id
, &extra_length
);
929 LOG_DEBUG("EXECUTE response");
931 if (cmd_ack_code
== AICE_CMD_T_EXECUTE
) {
934 LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
935 AICE_CMD_T_EXECUTE
, cmd_ack_code
);
937 if (retry_times
> aice_max_retry_times
)
940 /* clear timeout and retry */
941 if (aice_write_ctrl(AICE_WRITE_CTRL_CLEAR_TIMEOUT_STATUS
, 0x1) != ERROR_OK
)
951 int aice_write_mem_b(uint8_t target_id
, uint32_t address
, uint32_t data
)
956 LOG_DEBUG("WRITE_MEM_B, ADDRESS %08" PRIx32
" VALUE %08" PRIx32
,
960 if (usb_pack_command
) {
961 aice_pack_htdmd(AICE_CMD_T_WRITE_MEM_B
, target_id
, 0, address
,
962 data
& 0x000000FF, data_endian
);
963 aice_usb_packet_append(usb_out_buffer
, AICE_FORMAT_HTDMD
, AICE_FORMAT_DTHMB
);
966 aice_pack_htdmd(AICE_CMD_T_WRITE_MEM_B
, target_id
, 0,
967 address
, data
& 0x000000FF, data_endian
);
968 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMD
);
970 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMB
);
971 if (AICE_FORMAT_DTHMB
!= result
) {
972 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
973 AICE_FORMAT_DTHMB
, result
);
977 uint8_t cmd_ack_code
;
978 uint8_t extra_length
;
979 uint8_t res_target_id
;
980 aice_unpack_dthmb(&cmd_ack_code
, &res_target_id
, &extra_length
);
982 if (cmd_ack_code
== AICE_CMD_T_WRITE_MEM_B
) {
985 LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
986 AICE_CMD_T_WRITE_MEM_B
, cmd_ack_code
);
988 if (retry_times
> aice_max_retry_times
)
991 /* clear timeout and retry */
992 if (aice_write_ctrl(AICE_WRITE_CTRL_CLEAR_TIMEOUT_STATUS
, 0x1) != ERROR_OK
)
1003 int aice_write_mem_h(uint8_t target_id
, uint32_t address
, uint32_t data
)
1006 int retry_times
= 0;
1008 LOG_DEBUG("WRITE_MEM_H, ADDRESS %08" PRIx32
" VALUE %08" PRIx32
,
1012 if (usb_pack_command
) {
1013 aice_pack_htdmd(AICE_CMD_T_WRITE_MEM_H
, target_id
, 0,
1014 (address
>> 1) & 0x7FFFFFFF, data
& 0x0000FFFF, data_endian
);
1015 aice_usb_packet_append(usb_out_buffer
, AICE_FORMAT_HTDMD
, AICE_FORMAT_DTHMB
);
1018 aice_pack_htdmd(AICE_CMD_T_WRITE_MEM_H
, target_id
, 0,
1019 (address
>> 1) & 0x7FFFFFFF, data
& 0x0000FFFF, data_endian
);
1020 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMD
);
1022 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMB
);
1023 if (AICE_FORMAT_DTHMB
!= result
) {
1024 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
1025 AICE_FORMAT_DTHMB
, result
);
1029 uint8_t cmd_ack_code
;
1030 uint8_t extra_length
;
1031 uint8_t res_target_id
;
1032 aice_unpack_dthmb(&cmd_ack_code
, &res_target_id
, &extra_length
);
1034 if (cmd_ack_code
== AICE_CMD_T_WRITE_MEM_H
) {
1037 LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
1038 AICE_CMD_T_WRITE_MEM_H
, cmd_ack_code
);
1040 if (retry_times
> aice_max_retry_times
)
1043 /* clear timeout and retry */
1044 if (aice_write_ctrl(AICE_WRITE_CTRL_CLEAR_TIMEOUT_STATUS
, 0x1) != ERROR_OK
)
1055 int aice_write_mem(uint8_t target_id
, uint32_t address
, uint32_t data
)
1058 int retry_times
= 0;
1060 LOG_DEBUG("WRITE_MEM, ADDRESS %08" PRIx32
" VALUE %08" PRIx32
,
1064 if (usb_pack_command
) {
1065 aice_pack_htdmd(AICE_CMD_T_WRITE_MEM
, target_id
, 0,
1066 (address
>> 2) & 0x3FFFFFFF, data
, data_endian
);
1067 aice_usb_packet_append(usb_out_buffer
, AICE_FORMAT_HTDMD
, AICE_FORMAT_DTHMB
);
1070 aice_pack_htdmd(AICE_CMD_T_WRITE_MEM
, target_id
, 0,
1071 (address
>> 2) & 0x3FFFFFFF, data
, data_endian
);
1072 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMD
);
1074 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMB
);
1075 if (AICE_FORMAT_DTHMB
!= result
) {
1076 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
1077 AICE_FORMAT_DTHMB
, result
);
1081 uint8_t cmd_ack_code
;
1082 uint8_t extra_length
;
1083 uint8_t res_target_id
;
1084 aice_unpack_dthmb(&cmd_ack_code
, &res_target_id
, &extra_length
);
1086 if (cmd_ack_code
== AICE_CMD_T_WRITE_MEM
) {
1089 LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
1090 AICE_CMD_T_WRITE_MEM
, cmd_ack_code
);
1092 if (retry_times
> aice_max_retry_times
)
1095 /* clear timeout and retry */
1096 if (aice_write_ctrl(AICE_WRITE_CTRL_CLEAR_TIMEOUT_STATUS
, 0x1) != ERROR_OK
)
1107 int aice_fastread_mem(uint8_t target_id
, uint32_t *word
, uint32_t num_of_words
)
1110 int retry_times
= 0;
1112 if (usb_pack_command
)
1113 aice_usb_packet_flush();
1116 aice_pack_htdmb(AICE_CMD_T_FASTREAD_MEM
, target_id
, num_of_words
- 1, 0);
1118 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMB
);
1120 LOG_DEBUG("FASTREAD_MEM, # of DATA %08" PRIx32
, num_of_words
);
1122 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMA
+ (num_of_words
- 1) * 4);
1124 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
1125 AICE_FORMAT_DTHMA
+ (num_of_words
- 1) * 4, result
);
1129 uint8_t cmd_ack_code
;
1130 uint8_t extra_length
;
1131 uint8_t res_target_id
;
1132 aice_unpack_dthma_multiple_data(&cmd_ack_code
, &res_target_id
,
1133 &extra_length
, word
, data_endian
);
1135 if (cmd_ack_code
== AICE_CMD_T_FASTREAD_MEM
) {
1138 LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
1139 AICE_CMD_T_FASTREAD_MEM
, cmd_ack_code
);
1141 if (retry_times
> aice_max_retry_times
)
1144 /* clear timeout and retry */
1145 if (aice_write_ctrl(AICE_WRITE_CTRL_CLEAR_TIMEOUT_STATUS
, 0x1) != ERROR_OK
)
1155 int aice_fastwrite_mem(uint8_t target_id
, const uint32_t *word
, uint32_t num_of_words
)
1158 int retry_times
= 0;
1160 if (usb_pack_command
)
1161 aice_usb_packet_flush();
1164 aice_pack_htdmd_multiple_data(AICE_CMD_T_FASTWRITE_MEM
, target_id
,
1165 num_of_words
- 1, 0, word
, data_endian
);
1167 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMD
+ (num_of_words
- 1) * 4);
1169 LOG_DEBUG("FASTWRITE_MEM, # of DATA %08" PRIx32
, num_of_words
);
1171 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMB
);
1172 if (AICE_FORMAT_DTHMB
!= result
) {
1173 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
1174 AICE_FORMAT_DTHMB
, result
);
1178 uint8_t cmd_ack_code
;
1179 uint8_t extra_length
;
1180 uint8_t res_target_id
;
1181 aice_unpack_dthmb(&cmd_ack_code
, &res_target_id
, &extra_length
);
1183 if (cmd_ack_code
== AICE_CMD_T_FASTWRITE_MEM
) {
1186 LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
1187 AICE_CMD_T_FASTWRITE_MEM
, cmd_ack_code
);
1189 if (retry_times
> aice_max_retry_times
)
1192 /* clear timeout and retry */
1193 if (aice_write_ctrl(AICE_WRITE_CTRL_CLEAR_TIMEOUT_STATUS
, 0x1) != ERROR_OK
)
1203 int aice_read_mem_b(uint8_t target_id
, uint32_t address
, uint32_t *data
)
1206 int retry_times
= 0;
1208 if (usb_pack_command
)
1209 aice_usb_packet_flush();
1212 aice_pack_htdmb(AICE_CMD_T_READ_MEM_B
, target_id
, 0, address
);
1214 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMB
);
1216 LOG_DEBUG("READ_MEM_B");
1218 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMA
);
1219 if (AICE_FORMAT_DTHMA
!= result
) {
1220 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
1221 AICE_FORMAT_DTHMA
, result
);
1225 uint8_t cmd_ack_code
;
1226 uint8_t extra_length
;
1227 uint8_t res_target_id
;
1228 aice_unpack_dthma(&cmd_ack_code
, &res_target_id
, &extra_length
,
1231 LOG_DEBUG("READ_MEM_B response, data: 0x%x", *data
);
1233 if (cmd_ack_code
== AICE_CMD_T_READ_MEM_B
) {
1236 LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
1237 AICE_CMD_T_READ_MEM_B
, cmd_ack_code
);
1239 if (retry_times
> aice_max_retry_times
)
1242 /* clear timeout and retry */
1243 if (aice_write_ctrl(AICE_WRITE_CTRL_CLEAR_TIMEOUT_STATUS
, 0x1) != ERROR_OK
)
1253 int aice_read_mem_h(uint8_t target_id
, uint32_t address
, uint32_t *data
)
1256 int retry_times
= 0;
1258 if (usb_pack_command
)
1259 aice_usb_packet_flush();
1262 aice_pack_htdmb(AICE_CMD_T_READ_MEM_H
, target_id
, 0, (address
>> 1) & 0x7FFFFFFF);
1264 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMB
);
1266 LOG_DEBUG("READ_MEM_H");
1268 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMA
);
1269 if (AICE_FORMAT_DTHMA
!= result
) {
1270 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
1271 AICE_FORMAT_DTHMA
, result
);
1275 uint8_t cmd_ack_code
;
1276 uint8_t extra_length
;
1277 uint8_t res_target_id
;
1278 aice_unpack_dthma(&cmd_ack_code
, &res_target_id
, &extra_length
,
1281 LOG_DEBUG("READ_MEM_H response, data: 0x%x", *data
);
1283 if (cmd_ack_code
== AICE_CMD_T_READ_MEM_H
) {
1286 LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
1287 AICE_CMD_T_READ_MEM_H
, cmd_ack_code
);
1289 if (retry_times
> aice_max_retry_times
)
1292 /* clear timeout and retry */
1293 if (aice_write_ctrl(AICE_WRITE_CTRL_CLEAR_TIMEOUT_STATUS
, 0x1) != ERROR_OK
)
1303 int aice_read_mem(uint8_t target_id
, uint32_t address
, uint32_t *data
)
1306 int retry_times
= 0;
1308 if (usb_pack_command
)
1309 aice_usb_packet_flush();
1312 aice_pack_htdmb(AICE_CMD_T_READ_MEM
, target_id
, 0,
1313 (address
>> 2) & 0x3FFFFFFF);
1315 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMB
);
1317 LOG_DEBUG("READ_MEM");
1319 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMA
);
1320 if (AICE_FORMAT_DTHMA
!= result
) {
1321 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
1322 AICE_FORMAT_DTHMA
, result
);
1326 uint8_t cmd_ack_code
;
1327 uint8_t extra_length
;
1328 uint8_t res_target_id
;
1329 aice_unpack_dthma(&cmd_ack_code
, &res_target_id
, &extra_length
,
1332 LOG_DEBUG("READ_MEM response, data: 0x%x", *data
);
1334 if (cmd_ack_code
== AICE_CMD_T_READ_MEM
) {
1337 LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
1338 AICE_CMD_T_READ_MEM
, cmd_ack_code
);
1340 if (retry_times
> aice_max_retry_times
)
1343 /* clear timeout and retry */
1344 if (aice_write_ctrl(AICE_WRITE_CTRL_CLEAR_TIMEOUT_STATUS
, 0x1) != ERROR_OK
)
1354 /***************************************************************************/
1355 /* End of AICE commands */
1357 typedef int (*read_mem_func_t
)(uint32_t address
, uint32_t *data
);
1358 typedef int (*write_mem_func_t
)(uint32_t address
, uint32_t data
);
1365 uint32_t log2_line_size
;
1368 static uint32_t r0_backup
;
1369 static uint32_t r1_backup
;
1370 static uint32_t host_dtr_backup
;
1371 static uint32_t target_dtr_backup
;
1372 static uint32_t edmsw_backup
;
1373 static uint32_t edm_ctl_backup
;
1374 static bool debug_under_dex_on
;
1375 static bool dex_use_psw_on
;
1376 static bool host_dtr_valid
;
1377 static bool target_dtr_valid
;
1378 static enum nds_memory_access access_channel
= NDS_MEMORY_ACC_CPU
;
1379 static enum nds_memory_select memory_select
= NDS_MEMORY_SELECT_AUTO
;
1380 static enum aice_target_state_s core_state
= AICE_TARGET_UNKNOWN
;
1381 static uint32_t edm_version
;
1382 static struct cache_info icache
= {0, 0, 0, 0, 0};
1383 static struct cache_info dcache
= {0, 0, 0, 0, 0};
1384 static bool cache_init
;
1385 static char *custom_srst_script
;
1386 static char *custom_trst_script
;
1387 static char *custom_restart_script
;
1388 static uint32_t aice_count_to_check_dbger
= 30;
1390 static int aice_read_reg(uint32_t num
, uint32_t *val
);
1391 static int aice_write_reg(uint32_t num
, uint32_t val
);
1393 static int check_suppressed_exception(uint32_t dbger_value
)
1397 /* the default value of handling_suppressed_exception is false */
1398 static bool handling_suppressed_exception
;
1400 if (handling_suppressed_exception
)
1403 if ((dbger_value
& NDS_DBGER_ALL_SUPRS_EX
) == NDS_DBGER_ALL_SUPRS_EX
) {
1404 LOG_ERROR("<-- TARGET WARNING! Exception is detected and suppressed. -->");
1405 handling_suppressed_exception
= true;
1407 aice_read_reg(IR4
, &ir4_value
);
1408 /* Clear IR6.SUPRS_EXC, IR6.IMP_EXC */
1409 aice_read_reg(IR6
, &ir6_value
);
1411 * For MCU version(MSC_CFG.MCU == 1) like V3m
1412 * | SWID[30:16] | Reserved[15:10] | SUPRS_EXC[9] | IMP_EXC[8]
1413 * |VECTOR[7:5] | INST[4] | Exc Type[3:0] |
1415 * For non-MCU version(MSC_CFG.MCU == 0) like V3
1416 * | SWID[30:16] | Reserved[15:14] | SUPRS_EXC[13] | IMP_EXC[12]
1417 * | VECTOR[11:5] | INST[4] | Exc Type[3:0] |
1419 LOG_INFO("EVA: 0x%08x", ir4_value
);
1420 LOG_INFO("ITYPE: 0x%08x", ir6_value
);
1422 ir6_value
= ir6_value
& (~0x300); /* for MCU */
1423 ir6_value
= ir6_value
& (~0x3000); /* for non-MCU */
1424 aice_write_reg(IR6
, ir6_value
);
1426 handling_suppressed_exception
= false;
1432 static int check_privilege(uint32_t dbger_value
)
1434 if ((dbger_value
& NDS_DBGER_ILL_SEC_ACC
) == NDS_DBGER_ILL_SEC_ACC
) {
1435 LOG_ERROR("<-- TARGET ERROR! Insufficient security privilege "
1436 "to execute the debug operations. -->");
1438 /* Clear DBGER.ILL_SEC_ACC */
1439 if (aice_write_misc(current_target_id
, NDS_EDM_MISC_DBGER
,
1440 NDS_DBGER_ILL_SEC_ACC
) != ERROR_OK
)
1447 static int aice_check_dbger(uint32_t expect_status
)
1450 uint32_t value_dbger
;
1453 aice_read_misc(current_target_id
, NDS_EDM_MISC_DBGER
, &value_dbger
);
1455 if ((value_dbger
& expect_status
) == expect_status
) {
1456 if (ERROR_OK
!= check_suppressed_exception(value_dbger
))
1458 if (ERROR_OK
!= check_privilege(value_dbger
))
1464 if (i
== aice_count_to_check_dbger
)
1465 then
= timeval_ms();
1466 if (i
>= aice_count_to_check_dbger
) {
1467 if ((timeval_ms() - then
) > 1000) {
1468 LOG_ERROR("Timeout (1000ms) waiting for $DBGER status "
1469 "being 0x%08x", expect_status
);
1479 static int aice_execute_dim(uint32_t *insts
, uint8_t n_inst
)
1482 if (aice_write_dim(current_target_id
, insts
, n_inst
) != ERROR_OK
)
1485 /** clear DBGER.DPED */
1486 if (aice_write_misc(current_target_id
, NDS_EDM_MISC_DBGER
, NDS_DBGER_DPED
) != ERROR_OK
)
1490 if (aice_do_execute(current_target_id
) != ERROR_OK
)
1493 /** read DBGER.DPED */
1494 if (aice_check_dbger(NDS_DBGER_DPED
) != ERROR_OK
) {
1495 LOG_ERROR("<-- TARGET ERROR! Debug operations do not finish properly: "
1496 "0x%08x 0x%08x 0x%08x 0x%08x. -->",
1507 static int aice_read_reg(uint32_t num
, uint32_t *val
)
1509 LOG_DEBUG("aice_read_reg, reg_no: 0x%08x", num
);
1511 uint32_t instructions
[4]; /** execute instructions in DIM */
1513 if (NDS32_REG_TYPE_GPR
== nds32_reg_type(num
)) { /* general registers */
1514 instructions
[0] = MTSR_DTR(num
);
1515 instructions
[1] = DSB
;
1516 instructions
[2] = NOP
;
1517 instructions
[3] = BEQ_MINUS_12
;
1518 } else if (NDS32_REG_TYPE_SPR
== nds32_reg_type(num
)) { /* user special registers */
1519 instructions
[0] = MFUSR_G0(0, nds32_reg_sr_index(num
));
1520 instructions
[1] = MTSR_DTR(0);
1521 instructions
[2] = DSB
;
1522 instructions
[3] = BEQ_MINUS_12
;
1523 } else if (NDS32_REG_TYPE_AUMR
== nds32_reg_type(num
)) { /* audio registers */
1524 if ((CB_CTL
<= num
) && (num
<= CBE3
)) {
1525 instructions
[0] = AMFAR2(0, nds32_reg_sr_index(num
));
1526 instructions
[1] = MTSR_DTR(0);
1527 instructions
[2] = DSB
;
1528 instructions
[3] = BEQ_MINUS_12
;
1530 instructions
[0] = AMFAR(0, nds32_reg_sr_index(num
));
1531 instructions
[1] = MTSR_DTR(0);
1532 instructions
[2] = DSB
;
1533 instructions
[3] = BEQ_MINUS_12
;
1535 } else if (NDS32_REG_TYPE_FPU
== nds32_reg_type(num
)) { /* fpu registers */
1537 instructions
[0] = FMFCSR
;
1538 instructions
[1] = MTSR_DTR(0);
1539 instructions
[2] = DSB
;
1540 instructions
[3] = BEQ_MINUS_12
;
1541 } else if (FPCFG
== num
) {
1542 instructions
[0] = FMFCFG
;
1543 instructions
[1] = MTSR_DTR(0);
1544 instructions
[2] = DSB
;
1545 instructions
[3] = BEQ_MINUS_12
;
1547 if (FS0
<= num
&& num
<= FS31
) { /* single precision */
1548 instructions
[0] = FMFSR(0, nds32_reg_sr_index(num
));
1549 instructions
[1] = MTSR_DTR(0);
1550 instructions
[2] = DSB
;
1551 instructions
[3] = BEQ_MINUS_12
;
1552 } else if (FD0
<= num
&& num
<= FD31
) { /* double precision */
1553 instructions
[0] = FMFDR(0, nds32_reg_sr_index(num
));
1554 instructions
[1] = MTSR_DTR(0);
1555 instructions
[2] = DSB
;
1556 instructions
[3] = BEQ_MINUS_12
;
1559 } else { /* system registers */
1560 instructions
[0] = MFSR(0, nds32_reg_sr_index(num
));
1561 instructions
[1] = MTSR_DTR(0);
1562 instructions
[2] = DSB
;
1563 instructions
[3] = BEQ_MINUS_12
;
1566 aice_execute_dim(instructions
, 4);
1568 uint32_t value_edmsw
;
1569 aice_read_edmsr(current_target_id
, NDS_EDM_SR_EDMSW
, &value_edmsw
);
1570 if (value_edmsw
& NDS_EDMSW_WDV
)
1571 aice_read_dtr(current_target_id
, val
);
1573 LOG_ERROR("<-- TARGET ERROR! The debug target failed to update "
1574 "the DTR register. -->");
1581 static int aice_usb_read_reg(uint32_t num
, uint32_t *val
)
1583 LOG_DEBUG("aice_usb_read_reg");
1587 } else if (num
== R1
) {
1589 } else if (num
== DR41
) {
1590 /* As target is halted, OpenOCD will backup DR41/DR42/DR43.
1591 * As user wants to read these registers, OpenOCD should return
1592 * the backup values, instead of reading the real values.
1593 * As user wants to write these registers, OpenOCD should write
1594 * to the backup values, instead of writing to real registers. */
1595 *val
= edmsw_backup
;
1596 } else if (num
== DR42
) {
1597 *val
= edm_ctl_backup
;
1598 } else if ((target_dtr_valid
== true) && (num
== DR43
)) {
1599 *val
= target_dtr_backup
;
1601 if (ERROR_OK
!= aice_read_reg(num
, val
))
1608 static int aice_write_reg(uint32_t num
, uint32_t val
)
1610 LOG_DEBUG("aice_write_reg, reg_no: 0x%08x, value: 0x%08x", num
, val
);
1612 uint32_t instructions
[4]; /** execute instructions in DIM */
1613 uint32_t value_edmsw
;
1615 aice_write_dtr(current_target_id
, val
);
1616 aice_read_edmsr(current_target_id
, NDS_EDM_SR_EDMSW
, &value_edmsw
);
1617 if (0 == (value_edmsw
& NDS_EDMSW_RDV
)) {
1618 LOG_ERROR("<-- TARGET ERROR! AICE failed to write to the DTR register. -->");
1622 if (NDS32_REG_TYPE_GPR
== nds32_reg_type(num
)) { /* general registers */
1623 instructions
[0] = MFSR_DTR(num
);
1624 instructions
[1] = DSB
;
1625 instructions
[2] = NOP
;
1626 instructions
[3] = BEQ_MINUS_12
;
1627 } else if (NDS32_REG_TYPE_SPR
== nds32_reg_type(num
)) { /* user special registers */
1628 instructions
[0] = MFSR_DTR(0);
1629 instructions
[1] = MTUSR_G0(0, nds32_reg_sr_index(num
));
1630 instructions
[2] = DSB
;
1631 instructions
[3] = BEQ_MINUS_12
;
1632 } else if (NDS32_REG_TYPE_AUMR
== nds32_reg_type(num
)) { /* audio registers */
1633 if ((CB_CTL
<= num
) && (num
<= CBE3
)) {
1634 instructions
[0] = MFSR_DTR(0);
1635 instructions
[1] = AMTAR2(0, nds32_reg_sr_index(num
));
1636 instructions
[2] = DSB
;
1637 instructions
[3] = BEQ_MINUS_12
;
1639 instructions
[0] = MFSR_DTR(0);
1640 instructions
[1] = AMTAR(0, nds32_reg_sr_index(num
));
1641 instructions
[2] = DSB
;
1642 instructions
[3] = BEQ_MINUS_12
;
1644 } else if (NDS32_REG_TYPE_FPU
== nds32_reg_type(num
)) { /* fpu registers */
1646 instructions
[0] = MFSR_DTR(0);
1647 instructions
[1] = FMTCSR
;
1648 instructions
[2] = DSB
;
1649 instructions
[3] = BEQ_MINUS_12
;
1650 } else if (FPCFG
== num
) {
1651 /* FPCFG is readonly */
1653 if (FS0
<= num
&& num
<= FS31
) { /* single precision */
1654 instructions
[0] = MFSR_DTR(0);
1655 instructions
[1] = FMTSR(0, nds32_reg_sr_index(num
));
1656 instructions
[2] = DSB
;
1657 instructions
[3] = BEQ_MINUS_12
;
1658 } else if (FD0
<= num
&& num
<= FD31
) { /* double precision */
1659 instructions
[0] = MFSR_DTR(0);
1660 instructions
[1] = FMTDR(0, nds32_reg_sr_index(num
));
1661 instructions
[2] = DSB
;
1662 instructions
[3] = BEQ_MINUS_12
;
1666 instructions
[0] = MFSR_DTR(0);
1667 instructions
[1] = MTSR(0, nds32_reg_sr_index(num
));
1668 instructions
[2] = DSB
;
1669 instructions
[3] = BEQ_MINUS_12
;
1672 return aice_execute_dim(instructions
, 4);
1675 static int aice_usb_write_reg(uint32_t num
, uint32_t val
)
1677 LOG_DEBUG("aice_usb_write_reg");
1683 else if (num
== DR42
)
1684 /* As target is halted, OpenOCD will backup DR41/DR42/DR43.
1685 * As user wants to read these registers, OpenOCD should return
1686 * the backup values, instead of reading the real values.
1687 * As user wants to write these registers, OpenOCD should write
1688 * to the backup values, instead of writing to real registers. */
1689 edm_ctl_backup
= val
;
1690 else if ((target_dtr_valid
== true) && (num
== DR43
))
1691 target_dtr_backup
= val
;
1693 return aice_write_reg(num
, val
);
1698 static int aice_usb_open(struct aice_port_param_s
*param
)
1700 const uint16_t vids
[] = { param
->vid
, 0 };
1701 const uint16_t pids
[] = { param
->pid
, 0 };
1702 struct jtag_libusb_device_handle
*devh
;
1704 if (jtag_libusb_open(vids
, pids
, &devh
) != ERROR_OK
)
1707 /* BE ***VERY CAREFUL*** ABOUT MAKING CHANGES IN THIS
1708 * AREA!!!!!!!!!!! The behavior of libusb is not completely
1709 * consistent across Windows, Linux, and Mac OS X platforms.
1710 * The actions taken in the following compiler conditionals may
1711 * not agree with published documentation for libusb, but were
1712 * found to be necessary through trials and tribulations. Even
1713 * little tweaks can break one or more platforms, so if you do
1714 * make changes test them carefully on all platforms before
1720 jtag_libusb_reset_device(devh
);
1725 /* reopen jlink after usb_reset
1726 * on win32 this may take a second or two to re-enumerate */
1728 while ((retval
= jtag_libusb_open(vids
, pids
, &devh
)) != ERROR_OK
) {
1734 if (ERROR_OK
!= retval
)
1740 /* usb_set_configuration required under win32 */
1741 struct jtag_libusb_device
*udev
= jtag_libusb_get_device(devh
);
1742 jtag_libusb_set_configuration(devh
, 0);
1743 jtag_libusb_claim_interface(devh
, 0);
1745 unsigned int aice_read_ep
;
1746 unsigned int aice_write_ep
;
1747 jtag_libusb_get_endpoints(udev
, &aice_read_ep
, &aice_write_ep
);
1749 aice_handler
.usb_read_ep
= aice_read_ep
;
1750 aice_handler
.usb_write_ep
= aice_write_ep
;
1751 aice_handler
.usb_handle
= devh
;
1756 static int aice_usb_read_reg_64(uint32_t num
, uint64_t *val
)
1758 LOG_DEBUG("aice_usb_read_reg_64, %s", nds32_reg_simple_name(num
));
1761 uint32_t high_value
;
1763 if (ERROR_OK
!= aice_read_reg(num
, &value
))
1766 aice_read_reg(R1
, &high_value
);
1768 LOG_DEBUG("low: 0x%08x, high: 0x%08x\n", value
, high_value
);
1770 if (data_endian
== AICE_BIG_ENDIAN
)
1771 *val
= (((uint64_t)high_value
) << 32) | value
;
1773 *val
= (((uint64_t)value
) << 32) | high_value
;
1778 static int aice_usb_write_reg_64(uint32_t num
, uint64_t val
)
1781 uint32_t high_value
;
1783 if (data_endian
== AICE_BIG_ENDIAN
) {
1784 value
= val
& 0xFFFFFFFF;
1785 high_value
= (val
>> 32) & 0xFFFFFFFF;
1787 high_value
= val
& 0xFFFFFFFF;
1788 value
= (val
>> 32) & 0xFFFFFFFF;
1791 LOG_DEBUG("aice_usb_write_reg_64, %s, low: 0x%08x, high: 0x%08x\n",
1792 nds32_reg_simple_name(num
), value
, high_value
);
1794 aice_write_reg(R1
, high_value
);
1795 return aice_write_reg(num
, value
);
1798 static int aice_get_version_info(void)
1800 uint32_t hardware_version
;
1801 uint32_t firmware_version
;
1802 uint32_t fpga_version
;
1804 if (aice_read_ctrl(AICE_READ_CTRL_GET_HARDWARE_VERSION
, &hardware_version
) != ERROR_OK
)
1807 if (aice_read_ctrl(AICE_READ_CTRL_GET_FIRMWARE_VERSION
, &firmware_version
) != ERROR_OK
)
1810 if (aice_read_ctrl(AICE_READ_CTRL_GET_FPGA_VERSION
, &fpga_version
) != ERROR_OK
)
1813 LOG_INFO("AICE version: hw_ver = 0x%x, fw_ver = 0x%x, fpga_ver = 0x%x",
1814 hardware_version
, firmware_version
, fpga_version
);
1819 #define LINE_BUFFER_SIZE 1024
1821 static int aice_execute_custom_script(const char *script
)
1824 char line_buffer
[LINE_BUFFER_SIZE
];
1828 uint32_t write_ctrl_value
;
1831 script_fd
= fopen(script
, "r");
1832 if (script_fd
== NULL
) {
1835 while (fgets(line_buffer
, LINE_BUFFER_SIZE
, script_fd
) != NULL
) {
1836 /* execute operations */
1838 op_str
= strstr(line_buffer
, "set");
1839 if (op_str
!= NULL
) {
1841 goto get_reset_type
;
1844 op_str
= strstr(line_buffer
, "clear");
1848 reset_str
= strstr(op_str
, "srst");
1849 if (reset_str
!= NULL
) {
1851 write_ctrl_value
= AICE_CUSTOM_DELAY_SET_SRST
;
1853 write_ctrl_value
= AICE_CUSTOM_DELAY_CLEAN_SRST
;
1856 reset_str
= strstr(op_str
, "dbgi");
1857 if (reset_str
!= NULL
) {
1859 write_ctrl_value
= AICE_CUSTOM_DELAY_SET_DBGI
;
1861 write_ctrl_value
= AICE_CUSTOM_DELAY_CLEAN_DBGI
;
1864 reset_str
= strstr(op_str
, "trst");
1865 if (reset_str
!= NULL
) {
1867 write_ctrl_value
= AICE_CUSTOM_DELAY_SET_TRST
;
1869 write_ctrl_value
= AICE_CUSTOM_DELAY_CLEAN_TRST
;
1875 delay
= strtoul(reset_str
+ 4, NULL
, 0);
1876 write_ctrl_value
|= (delay
<< 16);
1878 if (aice_write_ctrl(AICE_WRITE_CTRL_CUSTOM_DELAY
,
1879 write_ctrl_value
) != ERROR_OK
) {
1890 static int aice_edm_reset(void)
1892 if (aice_write_ctrl(AICE_WRITE_CTRL_CLEAR_TIMEOUT_STATUS
, 0x1) != ERROR_OK
)
1898 static int aice_usb_set_clock(int set_clock
)
1900 if (aice_write_ctrl(AICE_WRITE_CTRL_TCK_CONTROL
,
1901 AICE_TCK_CONTROL_TCK_SCAN
) != ERROR_OK
)
1904 /* Read out TCK_SCAN clock value */
1905 uint32_t scan_clock
;
1906 if (aice_read_ctrl(AICE_READ_CTRL_GET_ICE_STATE
, &scan_clock
) != ERROR_OK
)
1911 uint32_t scan_base_freq
;
1912 if (scan_clock
& 0x8)
1913 scan_base_freq
= 48000; /* 48 MHz */
1915 scan_base_freq
= 30000; /* 30 MHz */
1917 uint32_t set_base_freq
;
1918 if (set_clock
& 0x8)
1919 set_base_freq
= 48000;
1921 set_base_freq
= 30000;
1925 set_freq
= set_base_freq
>> (set_clock
& 0x7);
1926 scan_freq
= scan_base_freq
>> (scan_clock
& 0x7);
1928 if (scan_freq
< set_freq
) {
1929 LOG_ERROR("User specifies higher jtag clock than TCK_SCAN clock");
1933 if (aice_write_ctrl(AICE_WRITE_CTRL_TCK_CONTROL
, set_clock
) != ERROR_OK
)
1936 uint32_t check_speed
;
1937 if (aice_read_ctrl(AICE_READ_CTRL_GET_ICE_STATE
, &check_speed
) != ERROR_OK
)
1940 if (((int)check_speed
& 0x0F) != set_clock
) {
1941 LOG_ERROR("Set jtag clock failed");
1948 static int aice_edm_init(void)
1950 aice_write_edmsr(current_target_id
, NDS_EDM_SR_DIMBR
, 0xFFFF0000);
1952 /* unconditionally try to turn on V3_EDM_MODE */
1953 uint32_t edm_ctl_value
;
1954 aice_read_edmsr(current_target_id
, NDS_EDM_SR_EDM_CTL
, &edm_ctl_value
);
1955 aice_write_edmsr(current_target_id
, NDS_EDM_SR_EDM_CTL
, edm_ctl_value
| 0x00000040);
1957 aice_write_misc(current_target_id
, NDS_EDM_MISC_DBGER
,
1958 NDS_DBGER_DPED
| NDS_DBGER_CRST
| NDS_DBGER_AT_MAX
);
1959 aice_write_misc(current_target_id
, NDS_EDM_MISC_DIMIR
, 0);
1961 /* get EDM version */
1962 uint32_t value_edmcfg
;
1963 aice_read_edmsr(current_target_id
, NDS_EDM_SR_EDM_CFG
, &value_edmcfg
);
1964 edm_version
= (value_edmcfg
>> 16) & 0xFFFF;
1969 static bool is_v2_edm(void)
1971 if ((edm_version
& 0x1000) == 0)
1977 static int aice_init_edm_registers(bool clear_dex_use_psw
)
1979 /* enable DEH_SEL & MAX_STOP & V3_EDM_MODE & DBGI_MASK */
1980 uint32_t host_edm_ctl
= edm_ctl_backup
| 0xA000004F;
1981 if (clear_dex_use_psw
)
1982 /* After entering debug mode, OpenOCD may set
1983 * DEX_USE_PSW accidentally through backup value
1984 * of target EDM_CTL.
1985 * So, clear DEX_USE_PSW by force. */
1986 host_edm_ctl
&= ~(0x40000000);
1988 LOG_DEBUG("aice_init_edm_registers - EDM_CTL: 0x%08x", host_edm_ctl
);
1990 int result
= aice_write_edmsr(current_target_id
, NDS_EDM_SR_EDM_CTL
, host_edm_ctl
);
1996 * EDM_CTL will be modified by OpenOCD as debugging. OpenOCD has the
1997 * responsibility to keep EDM_CTL untouched after debugging.
1999 * There are two scenarios to consider:
2000 * 1. single step/running as debugging (running under debug session)
2001 * 2. detached from gdb (exit debug session)
2003 * So, we need to bakcup EDM_CTL before halted and restore it after
2004 * running. The difference of these two scenarios is EDM_CTL.DEH_SEL
2005 * is on for scenario 1, and off for scenario 2.
2007 static int aice_backup_edm_registers(void)
2009 int result
= aice_read_edmsr(current_target_id
, NDS_EDM_SR_EDM_CTL
, &edm_ctl_backup
);
2011 /* To call aice_backup_edm_registers() after DEX on, DEX_USE_PSW
2012 * may be not correct. (For example, hit breakpoint, then backup
2013 * EDM_CTL. EDM_CTL.DEX_USE_PSW will be cleared.) Because debug
2014 * interrupt will clear DEX_USE_PSW, DEX_USE_PSW is always off after
2015 * DEX is on. It only backups correct value before OpenOCD issues DBGI.
2016 * (Backup EDM_CTL, then issue DBGI actively (refer aice_usb_halt())) */
2017 if (edm_ctl_backup
& 0x40000000)
2018 dex_use_psw_on
= true;
2020 dex_use_psw_on
= false;
2022 LOG_DEBUG("aice_backup_edm_registers - EDM_CTL: 0x%08x, DEX_USE_PSW: %s",
2023 edm_ctl_backup
, dex_use_psw_on
? "on" : "off");
2028 static int aice_restore_edm_registers(void)
2030 LOG_DEBUG("aice_restore_edm_registers -");
2032 /* set DEH_SEL, because target still under EDM control */
2033 int result
= aice_write_edmsr(current_target_id
, NDS_EDM_SR_EDM_CTL
,
2034 edm_ctl_backup
| 0x80000000);
2039 static int aice_backup_tmp_registers(void)
2041 LOG_DEBUG("backup_tmp_registers -");
2043 /* backup target DTR first(if the target DTR is valid) */
2044 uint32_t value_edmsw
;
2045 aice_read_edmsr(current_target_id
, NDS_EDM_SR_EDMSW
, &value_edmsw
);
2046 edmsw_backup
= value_edmsw
;
2047 if (value_edmsw
& 0x1) { /* EDMSW.WDV == 1 */
2048 aice_read_dtr(current_target_id
, &target_dtr_backup
);
2049 target_dtr_valid
= true;
2051 LOG_DEBUG("Backup target DTR: 0x%08x", target_dtr_backup
);
2053 target_dtr_valid
= false;
2056 /* Target DTR has been backup, then backup $R0 and $R1 */
2057 aice_read_reg(R0
, &r0_backup
);
2058 aice_read_reg(R1
, &r1_backup
);
2060 /* backup host DTR(if the host DTR is valid) */
2061 if (value_edmsw
& 0x2) { /* EDMSW.RDV == 1*/
2062 /* read out host DTR and write into target DTR, then use aice_read_edmsr to
2064 uint32_t instructions
[4] = {
2065 MFSR_DTR(R0
), /* R0 has already been backup */
2070 aice_execute_dim(instructions
, 4);
2072 aice_read_dtr(current_target_id
, &host_dtr_backup
);
2073 host_dtr_valid
= true;
2075 LOG_DEBUG("Backup host DTR: 0x%08x", host_dtr_backup
);
2077 host_dtr_valid
= false;
2080 LOG_DEBUG("r0: 0x%08x, r1: 0x%08x", r0_backup
, r1_backup
);
2085 static int aice_restore_tmp_registers(void)
2087 LOG_DEBUG("restore_tmp_registers - r0: 0x%08x, r1: 0x%08x", r0_backup
, r1_backup
);
2089 if (target_dtr_valid
) {
2090 uint32_t instructions
[4] = {
2091 SETHI(R0
, target_dtr_backup
>> 12),
2092 ORI(R0
, R0
, target_dtr_backup
& 0x00000FFF),
2096 aice_execute_dim(instructions
, 4);
2098 instructions
[0] = MTSR_DTR(R0
);
2099 instructions
[1] = DSB
;
2100 instructions
[2] = NOP
;
2101 instructions
[3] = BEQ_MINUS_12
;
2102 aice_execute_dim(instructions
, 4);
2104 LOG_DEBUG("Restore target DTR: 0x%08x", target_dtr_backup
);
2107 aice_write_reg(R0
, r0_backup
);
2108 aice_write_reg(R1
, r1_backup
);
2110 if (host_dtr_valid
) {
2111 aice_write_dtr(current_target_id
, host_dtr_backup
);
2113 LOG_DEBUG("Restore host DTR: 0x%08x", host_dtr_backup
);
2119 static int aice_open_device(struct aice_port_param_s
*param
)
2121 if (ERROR_OK
!= aice_usb_open(param
))
2124 if (ERROR_FAIL
== aice_get_version_info()) {
2125 LOG_ERROR("Cannot get AICE version!");
2129 LOG_INFO("AICE initialization started");
2131 /* attempt to reset Andes EDM */
2132 if (ERROR_FAIL
== aice_edm_reset()) {
2133 LOG_ERROR("Cannot initial AICE Interface!");
2137 if (ERROR_OK
!= aice_edm_init()) {
2138 LOG_ERROR("Cannot initial EDM!");
2145 static int aice_usb_set_jtag_clock(uint32_t a_clock
)
2147 jtag_clock
= a_clock
;
2149 if (ERROR_OK
!= aice_usb_set_clock(a_clock
)) {
2150 LOG_ERROR("Cannot set AICE JTAG clock!");
2157 static int aice_usb_close(void)
2159 jtag_libusb_close(aice_handler
.usb_handle
);
2161 if (custom_srst_script
)
2162 free(custom_srst_script
);
2164 if (custom_trst_script
)
2165 free(custom_trst_script
);
2167 if (custom_restart_script
)
2168 free(custom_restart_script
);
2173 static int aice_usb_idcode(uint32_t *idcode
, uint8_t *num_of_idcode
)
2175 return aice_scan_chain(idcode
, num_of_idcode
);
2178 static int aice_usb_halt(void)
2180 if (core_state
== AICE_TARGET_HALTED
) {
2181 LOG_DEBUG("aice_usb_halt check halted");
2185 LOG_DEBUG("aice_usb_halt");
2187 /** backup EDM registers */
2188 aice_backup_edm_registers();
2189 /** init EDM for host debugging */
2190 /** no need to clear dex_use_psw, because dbgi will clear it */
2191 aice_init_edm_registers(false);
2193 /** Clear EDM_CTL.DBGIM & EDM_CTL.DBGACKM */
2194 uint32_t edm_ctl_value
;
2195 aice_read_edmsr(current_target_id
, NDS_EDM_SR_EDM_CTL
, &edm_ctl_value
);
2196 if (edm_ctl_value
& 0x3)
2197 aice_write_edmsr(current_target_id
, NDS_EDM_SR_EDM_CTL
, edm_ctl_value
& ~(0x3));
2200 uint32_t acc_ctl_value
;
2202 debug_under_dex_on
= false;
2203 aice_read_misc(current_target_id
, NDS_EDM_MISC_DBGER
, &dbger
);
2205 if (dbger
& NDS_DBGER_AT_MAX
)
2206 LOG_ERROR("<-- TARGET ERROR! Reaching the max interrupt stack level. -->");
2208 if (dbger
& NDS_DBGER_DEX
) {
2209 if (is_v2_edm() == false) {
2210 /** debug 'debug mode'. use force_debug to issue dbgi */
2211 aice_read_misc(current_target_id
, NDS_EDM_MISC_ACC_CTL
, &acc_ctl_value
);
2212 acc_ctl_value
|= 0x8;
2213 aice_write_misc(current_target_id
, NDS_EDM_MISC_ACC_CTL
, acc_ctl_value
);
2214 debug_under_dex_on
= true;
2216 aice_write_misc(current_target_id
, NDS_EDM_MISC_EDM_CMDR
, 0);
2217 /* If CPU stalled due to AT_MAX, clear AT_MAX status. */
2218 if (dbger
& NDS_DBGER_AT_MAX
)
2219 aice_write_misc(current_target_id
, NDS_EDM_MISC_DBGER
, NDS_DBGER_AT_MAX
);
2222 /** Issue DBGI normally */
2223 aice_write_misc(current_target_id
, NDS_EDM_MISC_EDM_CMDR
, 0);
2224 /* If CPU stalled due to AT_MAX, clear AT_MAX status. */
2225 if (dbger
& NDS_DBGER_AT_MAX
)
2226 aice_write_misc(current_target_id
, NDS_EDM_MISC_DBGER
, NDS_DBGER_AT_MAX
);
2229 if (aice_check_dbger(NDS_DBGER_DEX
) != ERROR_OK
) {
2230 LOG_ERROR("<-- TARGET ERROR! Unable to stop the debug target through DBGI. -->");
2234 if (debug_under_dex_on
) {
2235 if (dex_use_psw_on
== false) {
2236 /* under debug 'debug mode', force $psw to 'debug mode' bahavior */
2237 /* !!!NOTICE!!! this is workaround for debug 'debug mode'.
2238 * it is only for debugging 'debug exception handler' purpose.
2239 * after openocd detaches from target, target behavior is
2242 uint32_t debug_mode_ir0_value
;
2243 aice_read_reg(IR0
, &ir0_value
);
2244 debug_mode_ir0_value
= ir0_value
| 0x408; /* turn on DEX, set POM = 1 */
2245 debug_mode_ir0_value
&= ~(0x000000C1); /* turn off DT/IT/GIE */
2246 aice_write_reg(IR0
, debug_mode_ir0_value
);
2250 /** set EDM_CTL.DBGIM & EDM_CTL.DBGACKM after halt */
2251 if (edm_ctl_value
& 0x3)
2252 aice_write_edmsr(current_target_id
, NDS_EDM_SR_EDM_CTL
, edm_ctl_value
);
2254 /* backup r0 & r1 */
2255 aice_backup_tmp_registers();
2256 core_state
= AICE_TARGET_HALTED
;
2261 static int aice_usb_state(enum aice_target_state_s
*state
)
2263 uint32_t dbger_value
;
2266 int result
= aice_read_misc(current_target_id
, NDS_EDM_MISC_DBGER
, &dbger_value
);
2268 if (ERROR_AICE_TIMEOUT
== result
) {
2269 if (aice_read_ctrl(AICE_READ_CTRL_GET_ICE_STATE
, &ice_state
) != ERROR_OK
) {
2270 LOG_ERROR("<-- AICE ERROR! AICE is unplugged. -->");
2274 if ((ice_state
& 0x20) == 0) {
2275 LOG_ERROR("<-- TARGET ERROR! Target is disconnected with AICE. -->");
2280 } else if (ERROR_AICE_DISCONNECT
== result
) {
2281 LOG_ERROR("<-- AICE ERROR! AICE is unplugged. -->");
2285 if ((dbger_value
& NDS_DBGER_ILL_SEC_ACC
) == NDS_DBGER_ILL_SEC_ACC
) {
2286 LOG_ERROR("<-- TARGET ERROR! Insufficient security privilege. -->");
2288 /* Clear ILL_SEC_ACC */
2289 aice_write_misc(current_target_id
, NDS_EDM_MISC_DBGER
, NDS_DBGER_ILL_SEC_ACC
);
2291 *state
= AICE_TARGET_RUNNING
;
2292 core_state
= AICE_TARGET_RUNNING
;
2293 } else if ((dbger_value
& NDS_DBGER_AT_MAX
) == NDS_DBGER_AT_MAX
) {
2294 /* Issue DBGI to exit cpu stall */
2297 /* Read OIPC to find out the trigger point */
2298 uint32_t ir11_value
;
2299 aice_read_reg(IR11
, &ir11_value
);
2301 LOG_ERROR("<-- TARGET ERROR! Reaching the max interrupt stack level; "
2302 "CPU is stalled at 0x%08x for debugging. -->", ir11_value
);
2304 *state
= AICE_TARGET_HALTED
;
2305 } else if ((dbger_value
& NDS_DBGER_CRST
) == NDS_DBGER_CRST
) {
2306 LOG_DEBUG("DBGER.CRST is on.");
2308 *state
= AICE_TARGET_RESET
;
2309 core_state
= AICE_TARGET_RUNNING
;
2312 aice_write_misc(current_target_id
, NDS_EDM_MISC_DBGER
, NDS_DBGER_CRST
);
2313 } else if ((dbger_value
& NDS_DBGER_DEX
) == NDS_DBGER_DEX
) {
2314 if (AICE_TARGET_RUNNING
== core_state
) {
2315 /* enter debug mode, init EDM registers */
2316 /* backup EDM registers */
2317 aice_backup_edm_registers();
2318 /* init EDM for host debugging */
2319 aice_init_edm_registers(true);
2320 aice_backup_tmp_registers();
2321 core_state
= AICE_TARGET_HALTED
;
2322 } else if (AICE_TARGET_UNKNOWN
== core_state
) {
2323 /* debug 'debug mode', use force debug to halt core */
2326 *state
= AICE_TARGET_HALTED
;
2328 *state
= AICE_TARGET_RUNNING
;
2329 core_state
= AICE_TARGET_RUNNING
;
2335 static int aice_usb_reset(void)
2337 if (aice_write_ctrl(AICE_WRITE_CTRL_CLEAR_TIMEOUT_STATUS
, 0x1) != ERROR_OK
)
2340 if (custom_trst_script
== NULL
) {
2341 if (aice_write_ctrl(AICE_WRITE_CTRL_JTAG_PIN_CONTROL
,
2342 AICE_JTAG_PIN_CONTROL_TRST
) != ERROR_OK
)
2345 /* custom trst operations */
2346 if (aice_execute_custom_script(custom_trst_script
) != ERROR_OK
)
2350 if (aice_usb_set_clock(jtag_clock
) != ERROR_OK
)
2356 static int aice_issue_srst(void)
2358 LOG_DEBUG("aice_issue_srst");
2360 /* After issuing srst, target will be running. So we need to restore EDM_CTL. */
2361 aice_restore_edm_registers();
2363 if (custom_srst_script
== NULL
) {
2364 if (aice_write_ctrl(AICE_WRITE_CTRL_JTAG_PIN_CONTROL
,
2365 AICE_JTAG_PIN_CONTROL_SRST
) != ERROR_OK
)
2368 /* custom srst operations */
2369 if (aice_execute_custom_script(custom_srst_script
) != ERROR_OK
)
2373 /* wait CRST infinitely */
2374 uint32_t dbger_value
;
2377 if (aice_read_misc(current_target_id
,
2378 NDS_EDM_MISC_DBGER
, &dbger_value
) != ERROR_OK
)
2381 if (dbger_value
& NDS_DBGER_CRST
)
2389 host_dtr_valid
= false;
2390 target_dtr_valid
= false;
2392 core_state
= AICE_TARGET_RUNNING
;
2396 static int aice_issue_reset_hold(void)
2398 LOG_DEBUG("aice_issue_reset_hold");
2400 /* set no_dbgi_pin to 0 */
2401 uint32_t pin_status
;
2402 aice_read_ctrl(AICE_READ_CTRL_GET_JTAG_PIN_STATUS
, &pin_status
);
2403 if (pin_status
| 0x4)
2404 aice_write_ctrl(AICE_WRITE_CTRL_JTAG_PIN_STATUS
, pin_status
& (~0x4));
2407 if (custom_restart_script
== NULL
) {
2408 if (aice_write_ctrl(AICE_WRITE_CTRL_JTAG_PIN_CONTROL
,
2409 AICE_JTAG_PIN_CONTROL_RESTART
) != ERROR_OK
)
2412 /* custom restart operations */
2413 if (aice_execute_custom_script(custom_restart_script
) != ERROR_OK
)
2417 if (aice_check_dbger(NDS_DBGER_CRST
| NDS_DBGER_DEX
) == ERROR_OK
) {
2418 aice_backup_tmp_registers();
2419 core_state
= AICE_TARGET_HALTED
;
2423 /* set no_dbgi_pin to 1 */
2424 aice_write_ctrl(AICE_WRITE_CTRL_JTAG_PIN_STATUS
, pin_status
| 0x4);
2426 /* issue restart again */
2427 if (custom_restart_script
== NULL
) {
2428 if (aice_write_ctrl(AICE_WRITE_CTRL_JTAG_PIN_CONTROL
,
2429 AICE_JTAG_PIN_CONTROL_RESTART
) != ERROR_OK
)
2432 /* custom restart operations */
2433 if (aice_execute_custom_script(custom_restart_script
) != ERROR_OK
)
2437 if (aice_check_dbger(NDS_DBGER_CRST
| NDS_DBGER_DEX
) == ERROR_OK
) {
2438 aice_backup_tmp_registers();
2439 core_state
= AICE_TARGET_HALTED
;
2444 /* do software reset-and-hold */
2449 aice_read_reg(IR3
, &value_ir3
);
2450 aice_write_reg(PC
, value_ir3
& 0xFFFF0000);
2456 static int aice_usb_assert_srst(enum aice_srst_type_s srst
)
2458 if ((AICE_SRST
!= srst
) && (AICE_RESET_HOLD
!= srst
))
2462 if (aice_write_misc(current_target_id
, NDS_EDM_MISC_DBGER
,
2463 NDS_DBGER_CLEAR_ALL
) != ERROR_OK
)
2466 int result
= ERROR_OK
;
2467 if (AICE_SRST
== srst
)
2468 result
= aice_issue_srst();
2470 result
= aice_issue_reset_hold();
2472 /* Clear DBGER.CRST after reset to avoid 'core-reset checking' errors.
2473 * assert_srst is user-intentional reset behavior, so we could
2474 * clear DBGER.CRST safely.
2476 if (aice_write_misc(current_target_id
,
2477 NDS_EDM_MISC_DBGER
, NDS_DBGER_CRST
) != ERROR_OK
)
2483 static int aice_usb_run(void)
2485 LOG_DEBUG("aice_usb_run");
2487 uint32_t dbger_value
;
2488 if (aice_read_misc(current_target_id
,
2489 NDS_EDM_MISC_DBGER
, &dbger_value
) != ERROR_OK
)
2492 if ((dbger_value
& NDS_DBGER_DEX
) != NDS_DBGER_DEX
) {
2493 LOG_WARNING("<-- TARGET WARNING! The debug target exited "
2494 "the debug mode unexpectedly. -->");
2498 /* restore r0 & r1 before free run */
2499 aice_restore_tmp_registers();
2500 core_state
= AICE_TARGET_RUNNING
;
2503 aice_write_misc(current_target_id
, NDS_EDM_MISC_DBGER
,
2504 NDS_DBGER_CLEAR_ALL
);
2506 /** restore EDM registers */
2507 /** OpenOCD should restore EDM_CTL **before** to exit debug state.
2508 * Otherwise, following instruction will read wrong EDM_CTL value.
2510 * pc -> mfsr $p0, EDM_CTL (single step)
2514 aice_restore_edm_registers();
2516 /** execute instructions in DIM */
2517 uint32_t instructions
[4] = {
2523 int result
= aice_execute_dim(instructions
, 4);
2528 static int aice_usb_step(void)
2530 LOG_DEBUG("aice_usb_step");
2533 uint32_t ir0_reg_num
;
2535 if (is_v2_edm() == true)
2536 /* V2 EDM will push interrupt stack as debug exception */
2542 aice_read_reg(ir0_reg_num
, &ir0_value
);
2543 if ((ir0_value
& 0x800) == 0) {
2545 ir0_value
|= (0x01 << 11);
2546 aice_write_reg(ir0_reg_num
, ir0_value
);
2549 if (ERROR_FAIL
== aice_usb_run())
2553 enum aice_target_state_s state
;
2556 if (aice_usb_state(&state
) != ERROR_OK
)
2559 if (AICE_TARGET_HALTED
== state
)
2564 then
= timeval_ms();
2567 if ((timeval_ms() - then
) > 1000)
2568 LOG_WARNING("Timeout (1000ms) waiting for halt to complete");
2576 aice_read_reg(ir0_reg_num
, &ir0_value
);
2577 ir0_value
&= ~(0x01 << 11);
2578 aice_write_reg(ir0_reg_num
, ir0_value
);
2583 static int aice_usb_read_mem_b_bus(uint32_t address
, uint32_t *data
)
2585 return aice_read_mem_b(current_target_id
, address
, data
);
2588 static int aice_usb_read_mem_h_bus(uint32_t address
, uint32_t *data
)
2590 return aice_read_mem_h(current_target_id
, address
, data
);
2593 static int aice_usb_read_mem_w_bus(uint32_t address
, uint32_t *data
)
2595 return aice_read_mem(current_target_id
, address
, data
);
2598 static int aice_usb_read_mem_b_dim(uint32_t address
, uint32_t *data
)
2601 uint32_t instructions
[4] = {
2608 aice_execute_dim(instructions
, 4);
2610 aice_read_dtr(current_target_id
, &value
);
2611 *data
= value
& 0xFF;
2616 static int aice_usb_read_mem_h_dim(uint32_t address
, uint32_t *data
)
2619 uint32_t instructions
[4] = {
2626 aice_execute_dim(instructions
, 4);
2628 aice_read_dtr(current_target_id
, &value
);
2629 *data
= value
& 0xFFFF;
2634 static int aice_usb_read_mem_w_dim(uint32_t address
, uint32_t *data
)
2636 uint32_t instructions
[4] = {
2643 aice_execute_dim(instructions
, 4);
2645 aice_read_dtr(current_target_id
, data
);
2650 static int aice_usb_set_address_dim(uint32_t address
)
2652 uint32_t instructions
[4] = {
2653 SETHI(R0
, address
>> 12),
2654 ORI(R0
, R0
, address
& 0x00000FFF),
2659 return aice_execute_dim(instructions
, 4);
2662 static int aice_usb_read_memory_unit(uint32_t addr
, uint32_t size
,
2663 uint32_t count
, uint8_t *buffer
)
2665 LOG_DEBUG("aice_usb_read_memory_unit, addr: 0x%08x, size: %d, count: %d",
2668 if (NDS_MEMORY_ACC_CPU
== access_channel
)
2669 aice_usb_set_address_dim(addr
);
2673 read_mem_func_t read_mem_func
;
2677 if (NDS_MEMORY_ACC_BUS
== access_channel
)
2678 read_mem_func
= aice_usb_read_mem_b_bus
;
2680 read_mem_func
= aice_usb_read_mem_b_dim
;
2682 for (i
= 0; i
< count
; i
++) {
2683 read_mem_func(addr
, &value
);
2684 *buffer
++ = (uint8_t)value
;
2689 if (NDS_MEMORY_ACC_BUS
== access_channel
)
2690 read_mem_func
= aice_usb_read_mem_h_bus
;
2692 read_mem_func
= aice_usb_read_mem_h_dim
;
2694 for (i
= 0; i
< count
; i
++) {
2695 read_mem_func(addr
, &value
);
2696 uint16_t svalue
= value
;
2697 memcpy(buffer
, &svalue
, sizeof(uint16_t));
2703 if (NDS_MEMORY_ACC_BUS
== access_channel
)
2704 read_mem_func
= aice_usb_read_mem_w_bus
;
2706 read_mem_func
= aice_usb_read_mem_w_dim
;
2708 for (i
= 0; i
< count
; i
++) {
2709 read_mem_func(addr
, &value
);
2710 memcpy(buffer
, &value
, sizeof(uint32_t));
2720 static int aice_usb_write_mem_b_bus(uint32_t address
, uint32_t data
)
2722 return aice_write_mem_b(current_target_id
, address
, data
);
2725 static int aice_usb_write_mem_h_bus(uint32_t address
, uint32_t data
)
2727 return aice_write_mem_h(current_target_id
, address
, data
);
2730 static int aice_usb_write_mem_w_bus(uint32_t address
, uint32_t data
)
2732 return aice_write_mem(current_target_id
, address
, data
);
2735 static int aice_usb_write_mem_b_dim(uint32_t address
, uint32_t data
)
2737 uint32_t instructions
[4] = {
2744 aice_write_dtr(current_target_id
, data
& 0xFF);
2745 aice_execute_dim(instructions
, 4);
2750 static int aice_usb_write_mem_h_dim(uint32_t address
, uint32_t data
)
2752 uint32_t instructions
[4] = {
2759 aice_write_dtr(current_target_id
, data
& 0xFFFF);
2760 aice_execute_dim(instructions
, 4);
2765 static int aice_usb_write_mem_w_dim(uint32_t address
, uint32_t data
)
2767 uint32_t instructions
[4] = {
2774 aice_write_dtr(current_target_id
, data
);
2775 aice_execute_dim(instructions
, 4);
2780 static int aice_usb_write_memory_unit(uint32_t addr
, uint32_t size
,
2781 uint32_t count
, const uint8_t *buffer
)
2783 LOG_DEBUG("aice_usb_write_memory_unit, addr: 0x%08x, size: %d, count: %d",
2786 if (NDS_MEMORY_ACC_CPU
== access_channel
)
2787 aice_usb_set_address_dim(addr
);
2790 write_mem_func_t write_mem_func
;
2794 if (NDS_MEMORY_ACC_BUS
== access_channel
)
2795 write_mem_func
= aice_usb_write_mem_b_bus
;
2797 write_mem_func
= aice_usb_write_mem_b_dim
;
2799 for (i
= 0; i
< count
; i
++) {
2800 write_mem_func(addr
, *buffer
);
2806 if (NDS_MEMORY_ACC_BUS
== access_channel
)
2807 write_mem_func
= aice_usb_write_mem_h_bus
;
2809 write_mem_func
= aice_usb_write_mem_h_dim
;
2811 for (i
= 0; i
< count
; i
++) {
2813 memcpy(&value
, buffer
, sizeof(uint16_t));
2815 write_mem_func(addr
, value
);
2821 if (NDS_MEMORY_ACC_BUS
== access_channel
)
2822 write_mem_func
= aice_usb_write_mem_w_bus
;
2824 write_mem_func
= aice_usb_write_mem_w_dim
;
2826 for (i
= 0; i
< count
; i
++) {
2828 memcpy(&value
, buffer
, sizeof(uint32_t));
2830 write_mem_func(addr
, value
);
2840 static int aice_bulk_read_mem(uint32_t addr
, uint32_t count
, uint8_t *buffer
)
2842 uint32_t packet_size
;
2845 packet_size
= (count
>= 0x100) ? 0x100 : count
;
2849 if (aice_write_misc(current_target_id
, NDS_EDM_MISC_SBAR
, addr
) != ERROR_OK
)
2852 if (aice_fastread_mem(current_target_id
, (uint32_t *)buffer
,
2853 packet_size
) != ERROR_OK
)
2856 buffer
+= (packet_size
* 4);
2857 addr
+= (packet_size
* 4);
2858 count
-= packet_size
;
2864 static int aice_bulk_write_mem(uint32_t addr
, uint32_t count
, const uint8_t *buffer
)
2866 uint32_t packet_size
;
2869 packet_size
= (count
>= 0x100) ? 0x100 : count
;
2873 if (aice_write_misc(current_target_id
, NDS_EDM_MISC_SBAR
, addr
| 1) != ERROR_OK
)
2876 if (aice_fastwrite_mem(current_target_id
, (const uint32_t *)buffer
,
2877 packet_size
) != ERROR_OK
)
2880 buffer
+= (packet_size
* 4);
2881 addr
+= (packet_size
* 4);
2882 count
-= packet_size
;
2888 static int aice_usb_bulk_read_mem(uint32_t addr
, uint32_t length
, uint8_t *buffer
)
2890 LOG_DEBUG("aice_usb_bulk_read_mem, addr: 0x%08x, length: 0x%08x", addr
, length
);
2894 if (NDS_MEMORY_ACC_CPU
== access_channel
)
2895 aice_usb_set_address_dim(addr
);
2897 if (NDS_MEMORY_ACC_CPU
== access_channel
)
2898 retval
= aice_usb_read_memory_unit(addr
, 4, length
/ 4, buffer
);
2900 retval
= aice_bulk_read_mem(addr
, length
/ 4, buffer
);
2905 static int aice_usb_bulk_write_mem(uint32_t addr
, uint32_t length
, const uint8_t *buffer
)
2907 LOG_DEBUG("aice_usb_bulk_write_mem, addr: 0x%08x, length: 0x%08x", addr
, length
);
2911 if (NDS_MEMORY_ACC_CPU
== access_channel
)
2912 aice_usb_set_address_dim(addr
);
2914 if (NDS_MEMORY_ACC_CPU
== access_channel
)
2915 retval
= aice_usb_write_memory_unit(addr
, 4, length
/ 4, buffer
);
2917 retval
= aice_bulk_write_mem(addr
, length
/ 4, buffer
);
2922 static int aice_usb_read_debug_reg(uint32_t addr
, uint32_t *val
)
2924 if (AICE_TARGET_HALTED
== core_state
) {
2925 if (NDS_EDM_SR_EDMSW
== addr
) {
2926 *val
= edmsw_backup
;
2927 } else if (NDS_EDM_SR_EDM_DTR
== addr
) {
2928 if (target_dtr_valid
) {
2929 /* if EDM_DTR has read out, clear it. */
2930 *val
= target_dtr_backup
;
2931 edmsw_backup
&= (~0x1);
2932 target_dtr_valid
= false;
2939 return aice_read_edmsr(current_target_id
, addr
, val
);
2942 static int aice_usb_write_debug_reg(uint32_t addr
, const uint32_t val
)
2944 if (AICE_TARGET_HALTED
== core_state
) {
2945 if (NDS_EDM_SR_EDM_DTR
== addr
) {
2946 host_dtr_backup
= val
;
2947 edmsw_backup
|= 0x2;
2948 host_dtr_valid
= true;
2952 return aice_write_edmsr(current_target_id
, addr
, val
);
2955 static int aice_usb_select_target(uint32_t target_id
)
2957 current_target_id
= target_id
;
2962 static int aice_usb_memory_access(enum nds_memory_access channel
)
2964 LOG_DEBUG("aice_usb_memory_access, access channel: %d", channel
);
2966 access_channel
= channel
;
2971 static int aice_usb_memory_mode(enum nds_memory_select mem_select
)
2973 if (memory_select
== mem_select
)
2976 LOG_DEBUG("aice_usb_memory_mode, memory select: %d", mem_select
);
2978 memory_select
= mem_select
;
2980 if (NDS_MEMORY_SELECT_AUTO
!= memory_select
)
2981 aice_write_misc(current_target_id
, NDS_EDM_MISC_ACC_CTL
,
2984 aice_write_misc(current_target_id
, NDS_EDM_MISC_ACC_CTL
,
2985 NDS_MEMORY_SELECT_MEM
- 1);
2990 static int aice_usb_read_tlb(uint32_t virtual_address
, uint32_t *physical_address
)
2992 LOG_DEBUG("aice_usb_read_tlb, virtual address: 0x%08x", virtual_address
);
2994 uint32_t instructions
[4];
2995 uint32_t probe_result
;
2998 uint32_t access_page_size
;
2999 uint32_t virtual_offset
;
3000 uint32_t physical_page_number
;
3002 aice_write_dtr(current_target_id
, virtual_address
);
3004 /* probe TLB first */
3005 instructions
[0] = MFSR_DTR(R0
);
3006 instructions
[1] = TLBOP_TARGET_PROBE(R1
, R0
);
3007 instructions
[2] = DSB
;
3008 instructions
[3] = BEQ_MINUS_12
;
3009 aice_execute_dim(instructions
, 4);
3011 aice_read_reg(R1
, &probe_result
);
3013 if (probe_result
& 0x80000000)
3016 /* read TLB entry */
3017 aice_write_dtr(current_target_id
, probe_result
& 0x7FF);
3019 /* probe TLB first */
3020 instructions
[0] = MFSR_DTR(R0
);
3021 instructions
[1] = TLBOP_TARGET_READ(R0
);
3022 instructions
[2] = DSB
;
3023 instructions
[3] = BEQ_MINUS_12
;
3024 aice_execute_dim(instructions
, 4);
3026 /* TODO: it should backup mr3, mr4 */
3027 aice_read_reg(MR3
, &value_mr3
);
3028 aice_read_reg(MR4
, &value_mr4
);
3030 access_page_size
= value_mr4
& 0xF;
3031 if (0 == access_page_size
) { /* 4K page */
3032 virtual_offset
= virtual_address
& 0x00000FFF;
3033 physical_page_number
= value_mr3
& 0xFFFFF000;
3034 } else if (1 == access_page_size
) { /* 8K page */
3035 virtual_offset
= virtual_address
& 0x00001FFF;
3036 physical_page_number
= value_mr3
& 0xFFFFE000;
3037 } else if (5 == access_page_size
) { /* 1M page */
3038 virtual_offset
= virtual_address
& 0x000FFFFF;
3039 physical_page_number
= value_mr3
& 0xFFF00000;
3044 *physical_address
= physical_page_number
| virtual_offset
;
3049 static int aice_usb_init_cache(void)
3051 LOG_DEBUG("aice_usb_init_cache");
3056 aice_read_reg(CR1
, &value_cr1
);
3057 aice_read_reg(CR2
, &value_cr2
);
3059 icache
.set
= value_cr1
& 0x7;
3060 icache
.log2_set
= icache
.set
+ 6;
3061 icache
.set
= 64 << icache
.set
;
3062 icache
.way
= ((value_cr1
>> 3) & 0x7) + 1;
3063 icache
.line_size
= (value_cr1
>> 6) & 0x7;
3064 if (icache
.line_size
!= 0) {
3065 icache
.log2_line_size
= icache
.line_size
+ 2;
3066 icache
.line_size
= 8 << (icache
.line_size
- 1);
3068 icache
.log2_line_size
= 0;
3071 LOG_DEBUG("\ticache set: %d, way: %d, line size: %d, "
3072 "log2(set): %d, log2(line_size): %d",
3073 icache
.set
, icache
.way
, icache
.line_size
,
3074 icache
.log2_set
, icache
.log2_line_size
);
3076 dcache
.set
= value_cr2
& 0x7;
3077 dcache
.log2_set
= dcache
.set
+ 6;
3078 dcache
.set
= 64 << dcache
.set
;
3079 dcache
.way
= ((value_cr2
>> 3) & 0x7) + 1;
3080 dcache
.line_size
= (value_cr2
>> 6) & 0x7;
3081 if (dcache
.line_size
!= 0) {
3082 dcache
.log2_line_size
= dcache
.line_size
+ 2;
3083 dcache
.line_size
= 8 << (dcache
.line_size
- 1);
3085 dcache
.log2_line_size
= 0;
3088 LOG_DEBUG("\tdcache set: %d, way: %d, line size: %d, "
3089 "log2(set): %d, log2(line_size): %d",
3090 dcache
.set
, dcache
.way
, dcache
.line_size
,
3091 dcache
.log2_set
, dcache
.log2_line_size
);
3098 static int aice_usb_dcache_inval_all(void)
3100 LOG_DEBUG("aice_usb_dcache_inval_all");
3104 uint32_t cache_index
;
3105 uint32_t instructions
[4];
3107 instructions
[0] = MFSR_DTR(R0
);
3108 instructions
[1] = L1D_IX_INVAL(R0
);
3109 instructions
[2] = DSB
;
3110 instructions
[3] = BEQ_MINUS_12
;
3112 for (set_index
= 0; set_index
< dcache
.set
; set_index
++) {
3113 for (way_index
= 0; way_index
< dcache
.way
; way_index
++) {
3114 cache_index
= (way_index
<< (dcache
.log2_set
+ dcache
.log2_line_size
)) |
3115 (set_index
<< dcache
.log2_line_size
);
3117 if (ERROR_OK
!= aice_write_dtr(current_target_id
, cache_index
))
3120 if (ERROR_OK
!= aice_execute_dim(instructions
, 4))
3128 static int aice_usb_dcache_va_inval(uint32_t address
)
3130 LOG_DEBUG("aice_usb_dcache_va_inval");
3132 uint32_t instructions
[4];
3134 aice_write_dtr(current_target_id
, address
);
3136 instructions
[0] = MFSR_DTR(R0
);
3137 instructions
[1] = L1D_VA_INVAL(R0
);
3138 instructions
[2] = DSB
;
3139 instructions
[3] = BEQ_MINUS_12
;
3141 return aice_execute_dim(instructions
, 4);
3144 static int aice_usb_dcache_wb_all(void)
3146 LOG_DEBUG("aice_usb_dcache_wb_all");
3150 uint32_t cache_index
;
3151 uint32_t instructions
[4];
3153 instructions
[0] = MFSR_DTR(R0
);
3154 instructions
[1] = L1D_IX_WB(R0
);
3155 instructions
[2] = DSB
;
3156 instructions
[3] = BEQ_MINUS_12
;
3158 for (set_index
= 0; set_index
< dcache
.set
; set_index
++) {
3159 for (way_index
= 0; way_index
< dcache
.way
; way_index
++) {
3160 cache_index
= (way_index
<< (dcache
.log2_set
+ dcache
.log2_line_size
)) |
3161 (set_index
<< dcache
.log2_line_size
);
3163 if (ERROR_OK
!= aice_write_dtr(current_target_id
, cache_index
))
3166 if (ERROR_OK
!= aice_execute_dim(instructions
, 4))
3174 static int aice_usb_dcache_va_wb(uint32_t address
)
3176 LOG_DEBUG("aice_usb_dcache_va_wb");
3178 uint32_t instructions
[4];
3180 aice_write_dtr(current_target_id
, address
);
3182 instructions
[0] = MFSR_DTR(R0
);
3183 instructions
[1] = L1D_VA_WB(R0
);
3184 instructions
[2] = DSB
;
3185 instructions
[3] = BEQ_MINUS_12
;
3187 return aice_execute_dim(instructions
, 4);
3190 static int aice_usb_icache_inval_all(void)
3192 LOG_DEBUG("aice_usb_icache_inval_all");
3196 uint32_t cache_index
;
3197 uint32_t instructions
[4];
3199 instructions
[0] = MFSR_DTR(R0
);
3200 instructions
[1] = L1I_IX_INVAL(R0
);
3201 instructions
[2] = ISB
;
3202 instructions
[3] = BEQ_MINUS_12
;
3204 for (set_index
= 0; set_index
< icache
.set
; set_index
++) {
3205 for (way_index
= 0; way_index
< icache
.way
; way_index
++) {
3206 cache_index
= (way_index
<< (icache
.log2_set
+ icache
.log2_line_size
)) |
3207 (set_index
<< icache
.log2_line_size
);
3209 if (ERROR_OK
!= aice_write_dtr(current_target_id
, cache_index
))
3212 if (ERROR_OK
!= aice_execute_dim(instructions
, 4))
3220 static int aice_usb_icache_va_inval(uint32_t address
)
3222 LOG_DEBUG("aice_usb_icache_va_inval");
3224 uint32_t instructions
[4];
3226 aice_write_dtr(current_target_id
, address
);
3228 instructions
[0] = MFSR_DTR(R0
);
3229 instructions
[1] = L1I_VA_INVAL(R0
);
3230 instructions
[2] = ISB
;
3231 instructions
[3] = BEQ_MINUS_12
;
3233 return aice_execute_dim(instructions
, 4);
3236 static int aice_usb_cache_ctl(uint32_t subtype
, uint32_t address
)
3238 LOG_DEBUG("aice_usb_cache_ctl");
3242 if (cache_init
== false)
3243 aice_usb_init_cache();
3246 case AICE_CACHE_CTL_L1D_INVALALL
:
3247 result
= aice_usb_dcache_inval_all();
3249 case AICE_CACHE_CTL_L1D_VA_INVAL
:
3250 result
= aice_usb_dcache_va_inval(address
);
3252 case AICE_CACHE_CTL_L1D_WBALL
:
3253 result
= aice_usb_dcache_wb_all();
3255 case AICE_CACHE_CTL_L1D_VA_WB
:
3256 result
= aice_usb_dcache_va_wb(address
);
3258 case AICE_CACHE_CTL_L1I_INVALALL
:
3259 result
= aice_usb_icache_inval_all();
3261 case AICE_CACHE_CTL_L1I_VA_INVAL
:
3262 result
= aice_usb_icache_va_inval(address
);
3265 result
= ERROR_FAIL
;
3272 static int aice_usb_set_retry_times(uint32_t a_retry_times
)
3274 aice_max_retry_times
= a_retry_times
;
3278 static int aice_usb_program_edm(char *command_sequence
)
3283 uint32_t data_value
;
3287 command_str
= strtok(command_sequence
, ";");
3288 if (command_str
== NULL
)
3293 /* process one command */
3294 while (command_str
[i
] == ' ' ||
3295 command_str
[i
] == '\n' ||
3296 command_str
[i
] == '\r' ||
3297 command_str
[i
] == '\t')
3300 /* skip ' ', '\r', '\n', '\t' */
3301 command_str
= command_str
+ i
;
3303 if (strncmp(command_str
, "write_misc", 10) == 0) {
3304 reg_name_0
= strstr(command_str
, "gen_port0");
3305 reg_name_1
= strstr(command_str
, "gen_port1");
3307 if (reg_name_0
!= NULL
) {
3308 data_value
= strtoul(reg_name_0
+ 9, NULL
, 0);
3310 if (aice_write_misc(current_target_id
,
3311 NDS_EDM_MISC_GEN_PORT0
, data_value
) != ERROR_OK
)
3314 } else if (reg_name_1
!= NULL
) {
3315 data_value
= strtoul(reg_name_1
+ 9, NULL
, 0);
3317 if (aice_write_misc(current_target_id
,
3318 NDS_EDM_MISC_GEN_PORT1
, data_value
) != ERROR_OK
)
3321 LOG_ERROR("program EDM, unsupported misc register: %s", command_str
);
3324 LOG_ERROR("program EDM, unsupported command: %s", command_str
);
3327 /* update command_str */
3328 command_str
= strtok(NULL
, ";");
3330 } while (command_str
!= NULL
);
3335 static int aice_usb_pack_command(bool enable_pack_command
)
3337 if (enable_pack_command
== false) {
3338 /* turn off usb_pack_command, flush usb_packets_buffer */
3339 aice_usb_packet_flush();
3342 usb_pack_command
= enable_pack_command
;
3347 static int aice_usb_execute(uint32_t *instructions
, uint32_t instruction_num
)
3350 uint8_t current_instruction_num
;
3351 uint32_t dim_instructions
[4] = {NOP
, NOP
, NOP
, BEQ_MINUS_12
};
3353 /* To execute 4 instructions as a special case */
3354 if (instruction_num
== 4)
3355 return aice_execute_dim(instructions
, 4);
3357 for (i
= 0 ; i
< instruction_num
; i
+= 3) {
3358 if (instruction_num
- i
< 3) {
3359 current_instruction_num
= instruction_num
- i
;
3360 for (j
= current_instruction_num
; j
< 3 ; j
++)
3361 dim_instructions
[j
] = NOP
;
3363 current_instruction_num
= 3;
3366 memcpy(dim_instructions
, instructions
+ i
,
3367 current_instruction_num
* sizeof(uint32_t));
3370 if (aice_write_dim(current_target_id
,
3375 /** clear DBGER.DPED */
3376 if (aice_write_misc(current_target_id
,
3377 NDS_EDM_MISC_DBGER
, NDS_DBGER_DPED
) != ERROR_OK
)
3381 if (aice_do_execute(current_target_id
) != ERROR_OK
)
3384 /** check DBGER.DPED */
3385 if (aice_check_dbger(NDS_DBGER_DPED
) != ERROR_OK
) {
3387 LOG_ERROR("<-- TARGET ERROR! Debug operations do not finish properly:"
3388 "0x%08x 0x%08x 0x%08x 0x%08x. -->",
3389 dim_instructions
[0],
3390 dim_instructions
[1],
3391 dim_instructions
[2],
3392 dim_instructions
[3]);
3400 static int aice_usb_set_custom_srst_script(const char *script
)
3402 custom_srst_script
= strdup(script
);
3407 static int aice_usb_set_custom_trst_script(const char *script
)
3409 custom_trst_script
= strdup(script
);
3414 static int aice_usb_set_custom_restart_script(const char *script
)
3416 custom_restart_script
= strdup(script
);
3421 static int aice_usb_set_count_to_check_dbger(uint32_t count_to_check
)
3423 aice_count_to_check_dbger
= count_to_check
;
3428 static int aice_usb_set_data_endian(enum aice_target_endian target_data_endian
)
3430 data_endian
= target_data_endian
;
3436 struct aice_port_api_s aice_usb_api
= {
3438 .open
= aice_open_device
,
3440 .close
= aice_usb_close
,
3442 .idcode
= aice_usb_idcode
,
3444 .state
= aice_usb_state
,
3446 .reset
= aice_usb_reset
,
3448 .assert_srst
= aice_usb_assert_srst
,
3450 .run
= aice_usb_run
,
3452 .halt
= aice_usb_halt
,
3454 .step
= aice_usb_step
,
3456 .read_reg
= aice_usb_read_reg
,
3458 .write_reg
= aice_usb_write_reg
,
3460 .read_reg_64
= aice_usb_read_reg_64
,
3462 .write_reg_64
= aice_usb_write_reg_64
,
3464 .read_mem_unit
= aice_usb_read_memory_unit
,
3466 .write_mem_unit
= aice_usb_write_memory_unit
,
3468 .read_mem_bulk
= aice_usb_bulk_read_mem
,
3470 .write_mem_bulk
= aice_usb_bulk_write_mem
,
3472 .read_debug_reg
= aice_usb_read_debug_reg
,
3474 .write_debug_reg
= aice_usb_write_debug_reg
,
3476 .set_jtag_clock
= aice_usb_set_jtag_clock
,
3478 .select_target
= aice_usb_select_target
,
3480 .memory_access
= aice_usb_memory_access
,
3482 .memory_mode
= aice_usb_memory_mode
,
3484 .read_tlb
= aice_usb_read_tlb
,
3486 .cache_ctl
= aice_usb_cache_ctl
,
3488 .set_retry_times
= aice_usb_set_retry_times
,
3490 .program_edm
= aice_usb_program_edm
,
3492 .pack_command
= aice_usb_pack_command
,
3494 .execute
= aice_usb_execute
,
3496 .set_custom_srst_script
= aice_usb_set_custom_srst_script
,
3498 .set_custom_trst_script
= aice_usb_set_custom_trst_script
,
3500 .set_custom_restart_script
= aice_usb_set_custom_restart_script
,
3502 .set_count_to_check_dbger
= aice_usb_set_count_to_check_dbger
,
3504 .set_data_endian
= aice_usb_set_data_endian
,