1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include "replacements.h"
31 #include "algorithm.h"
32 #include "binarybuffer.h"
38 str9x_mem_layout_t mem_layout_str9
[] = {
39 {0x00000000, 0x10000, 0x01},
40 {0x00010000, 0x10000, 0x02},
41 {0x00020000, 0x10000, 0x04},
42 {0x00030000, 0x10000, 0x08},
43 {0x00040000, 0x10000, 0x10},
44 {0x00050000, 0x10000, 0x20},
45 {0x00060000, 0x10000, 0x40},
46 {0x00070000, 0x10000, 0x80},
47 {0x00080000, 0x02000, 0x100},
48 {0x00082000, 0x02000, 0x200},
49 {0x00084000, 0x02000, 0x400},
50 {0x00086000, 0x02000, 0x800}
53 int str9x_register_commands(struct command_context_s
*cmd_ctx
);
54 int str9x_flash_bank_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct flash_bank_s
*bank
);
55 int str9x_erase(struct flash_bank_s
*bank
, int first
, int last
);
56 int str9x_protect(struct flash_bank_s
*bank
, int set
, int first
, int last
);
57 int str9x_write(struct flash_bank_s
*bank
, u8
*buffer
, u32 offset
, u32 count
);
58 int str9x_probe(struct flash_bank_s
*bank
);
59 int str9x_handle_part_id_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
60 int str9x_protect_check(struct flash_bank_s
*bank
);
61 int str9x_erase_check(struct flash_bank_s
*bank
);
62 int str9x_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
);
64 int str9x_handle_flash_config_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
66 flash_driver_t str9x_flash
=
69 .register_commands
= str9x_register_commands
,
70 .flash_bank_command
= str9x_flash_bank_command
,
72 .protect
= str9x_protect
,
75 .erase_check
= str9x_erase_check
,
76 .protect_check
= str9x_protect_check
,
80 int str9x_register_commands(struct command_context_s
*cmd_ctx
)
82 command_t
*str9x_cmd
= register_command(cmd_ctx
, NULL
, "str9x", NULL
, COMMAND_ANY
, NULL
);
84 register_command(cmd_ctx
, str9x_cmd
, "flash_config", str9x_handle_flash_config_command
, COMMAND_EXEC
,
85 "configure str9 flash controller");
90 int str9x_build_block_list(struct flash_bank_s
*bank
)
92 str9x_flash_bank_t
*str9x_info
= bank
->driver_priv
;
95 int num_sectors
= 0, b0_sectors
= 0;
106 ERROR("BUG: unknown bank->size encountered");
110 num_sectors
= b0_sectors
+ 4;
112 bank
->num_sectors
= num_sectors
;
113 bank
->sectors
= malloc(sizeof(flash_sector_t
) * num_sectors
);
114 str9x_info
->sector_bits
= malloc(sizeof(u32
) * num_sectors
);
118 for (i
= 0; i
< b0_sectors
; i
++)
120 bank
->sectors
[num_sectors
].offset
= mem_layout_str9
[i
].sector_start
;
121 bank
->sectors
[num_sectors
].size
= mem_layout_str9
[i
].sector_size
;
122 bank
->sectors
[num_sectors
].is_erased
= -1;
123 bank
->sectors
[num_sectors
].is_protected
= 1;
124 str9x_info
->sector_bits
[num_sectors
++] = mem_layout_str9
[i
].sector_bit
;
127 for (i
= 8; i
< 12; i
++)
129 bank
->sectors
[num_sectors
].offset
= mem_layout_str9
[i
].sector_start
;
130 bank
->sectors
[num_sectors
].size
= mem_layout_str9
[i
].sector_size
;
131 bank
->sectors
[num_sectors
].is_erased
= -1;
132 bank
->sectors
[num_sectors
].is_protected
= 1;
133 str9x_info
->sector_bits
[num_sectors
++] = mem_layout_str9
[i
].sector_bit
;
139 /* flash bank str9x <base> <size> 0 0 <target#>
141 int str9x_flash_bank_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct flash_bank_s
*bank
)
143 str9x_flash_bank_t
*str9x_info
;
147 WARNING("incomplete flash_bank str9x configuration");
148 return ERROR_FLASH_BANK_INVALID
;
151 str9x_info
= malloc(sizeof(str9x_flash_bank_t
));
152 bank
->driver_priv
= str9x_info
;
154 if (bank
->base
!= 0x00000000)
156 WARNING("overriding flash base address for STR91x device with 0x00000000");
157 bank
->base
= 0x00000000;
160 str9x_build_block_list(bank
);
162 str9x_info
->write_algorithm
= NULL
;
167 int str9x_blank_check(struct flash_bank_s
*bank
, int first
, int last
)
169 target_t
*target
= bank
->target
;
174 if ((first
< 0) || (last
> bank
->num_sectors
))
175 return ERROR_FLASH_SECTOR_INVALID
;
177 if (bank
->target
->state
!= TARGET_HALTED
)
179 return ERROR_TARGET_NOT_HALTED
;
182 buffer
= malloc(256);
184 for (i
= first
; i
<= last
; i
++)
186 bank
->sectors
[i
].is_erased
= 1;
188 target
->type
->read_memory(target
, bank
->base
+ bank
->sectors
[i
].offset
, 4, 256/4, buffer
);
190 for (nBytes
= 0; nBytes
< 256; nBytes
++)
192 if (buffer
[nBytes
] != 0xFF)
194 bank
->sectors
[i
].is_erased
= 0;
205 int str9x_protect_check(struct flash_bank_s
*bank
)
207 str9x_flash_bank_t
*str9x_info
= bank
->driver_priv
;
208 target_t
*target
= bank
->target
;
214 if (bank
->target
->state
!= TARGET_HALTED
)
216 return ERROR_TARGET_NOT_HALTED
;
219 /* read level one protection */
221 adr
= mem_layout_str9
[10].sector_start
+ 4;
223 target_write_u32(target
, adr
, 0x90);
224 target_read_u16(target
, adr
, &status
);
225 target_write_u32(target
, adr
, 0xFF);
227 for (i
= 0; i
< bank
->num_sectors
; i
++)
229 if (status
& str9x_info
->sector_bits
[i
])
230 bank
->sectors
[i
].is_protected
= 1;
232 bank
->sectors
[i
].is_protected
= 0;
238 int str9x_erase(struct flash_bank_s
*bank
, int first
, int last
)
240 target_t
*target
= bank
->target
;
245 if (bank
->target
->state
!= TARGET_HALTED
)
247 return ERROR_TARGET_NOT_HALTED
;
250 for (i
= first
; i
<= last
; i
++)
252 adr
= bank
->sectors
[i
].offset
;
255 target_write_u16(target
, adr
, 0x20);
256 target_write_u16(target
, adr
, 0xD0);
259 target_write_u16(target
, adr
, 0x70);
262 target_read_u8(target
, adr
, &status
);
268 /* clear status, also clear read array */
269 target_write_u16(target
, adr
, 0x50);
271 /* read array command */
272 target_write_u16(target
, adr
, 0xFF);
276 ERROR("error erasing flash bank, status: 0x%x", status
);
277 return ERROR_FLASH_OPERATION_FAILED
;
281 for (i
= first
; i
<= last
; i
++)
282 bank
->sectors
[i
].is_erased
= 1;
287 int str9x_protect(struct flash_bank_s
*bank
, int set
, int first
, int last
)
289 target_t
*target
= bank
->target
;
294 if (bank
->target
->state
!= TARGET_HALTED
)
296 return ERROR_TARGET_NOT_HALTED
;
299 for (i
= first
; i
<= last
; i
++)
301 /* Level One Protection */
303 adr
= bank
->sectors
[i
].offset
;
305 target_write_u16(target
, adr
, 0x60);
307 target_write_u16(target
, adr
, 0x01);
309 target_write_u16(target
, adr
, 0xD0);
312 target_read_u8(target
, adr
, &status
);
318 int str9x_write_block(struct flash_bank_s
*bank
, u8
*buffer
, u32 offset
, u32 count
)
320 str9x_flash_bank_t
*str9x_info
= bank
->driver_priv
;
321 target_t
*target
= bank
->target
;
322 u32 buffer_size
= 8192;
323 working_area_t
*source
;
324 u32 address
= bank
->base
+ offset
;
325 reg_param_t reg_params
[4];
326 armv4_5_algorithm_t armv4_5_info
;
329 u32 str9x_flash_write_code
[] = {
331 0xe3c14003, /* bic r4, r1, #3 */
332 0xe3a03040, /* mov r3, #0x40 */
333 0xe1c430b0, /* strh r3, [r4, #0] */
334 0xe0d030b2, /* ldrh r3, [r0], #2 */
335 0xe0c130b2, /* strh r3, [r1], #2 */
336 0xe3a03070, /* mov r3, #0x70 */
337 0xe1c430b0, /* strh r3, [r4, #0] */
339 0xe5d43000, /* ldrb r3, [r4, #0] */
340 0xe3130080, /* tst r3, #0x80 */
341 0x0afffffc, /* beq busy */
342 0xe3a05050, /* mov r5, #0x50 */
343 0xe1c450b0, /* strh r5, [r4, #0] */
344 0xe3a050ff, /* mov r5, #0xFF */
345 0xe1c450b0, /* strh r5, [r4, #0] */
346 0xe3130012, /* tst r3, #0x12 */
347 0x1a000001, /* bne exit */
348 0xe2522001, /* subs r2, r2, #1 */
349 0x1affffed, /* bne write */
351 0xeafffffe, /* b exit */
354 u8 str9x_flash_write_code_buf
[76];
357 /* flash write code */
358 if (!str9x_info
->write_algorithm
)
360 if (target_alloc_working_area(target
, 4 * 19, &str9x_info
->write_algorithm
) != ERROR_OK
)
362 WARNING("no working area available, can't do block memory writes");
363 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
366 /* convert flash writing code into a buffer in target endianness */
367 for (i
= 0; i
< 19; i
++)
368 target_buffer_set_u32(target
, str9x_flash_write_code_buf
+ i
*4, str9x_flash_write_code
[i
]);
370 target_write_buffer(target
, str9x_info
->write_algorithm
->address
, 19 * 4, str9x_flash_write_code_buf
);
374 while (target_alloc_working_area(target
, buffer_size
, &source
) != ERROR_OK
)
377 if (buffer_size
<= 256)
379 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
380 if (str9x_info
->write_algorithm
)
381 target_free_working_area(target
, str9x_info
->write_algorithm
);
383 WARNING("no large enough working area available, can't do block memory writes");
384 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
388 armv4_5_info
.common_magic
= ARMV4_5_COMMON_MAGIC
;
389 armv4_5_info
.core_mode
= ARMV4_5_MODE_SVC
;
390 armv4_5_info
.core_state
= ARMV4_5_STATE_ARM
;
392 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
393 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
394 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
395 init_reg_param(®_params
[3], "r3", 32, PARAM_IN
);
399 u32 thisrun_count
= (count
> (buffer_size
/ 2)) ? (buffer_size
/ 2) : count
;
401 target_write_buffer(target
, source
->address
, thisrun_count
* 2, buffer
);
403 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
404 buf_set_u32(reg_params
[1].value
, 0, 32, address
);
405 buf_set_u32(reg_params
[2].value
, 0, 32, thisrun_count
);
407 if ((retval
= target
->type
->run_algorithm(target
, 0, NULL
, 4, reg_params
, str9x_info
->write_algorithm
->address
, str9x_info
->write_algorithm
->address
+ (18 * 4), 10000, &armv4_5_info
)) != ERROR_OK
)
409 ERROR("error executing str9x flash write algorithm");
410 return ERROR_FLASH_OPERATION_FAILED
;
413 if (buf_get_u32(reg_params
[3].value
, 0, 32) != 0x80)
415 return ERROR_FLASH_OPERATION_FAILED
;
418 buffer
+= thisrun_count
* 2;
419 address
+= thisrun_count
* 2;
420 count
-= thisrun_count
;
423 destroy_reg_param(®_params
[0]);
424 destroy_reg_param(®_params
[1]);
425 destroy_reg_param(®_params
[2]);
426 destroy_reg_param(®_params
[3]);
431 int str9x_write(struct flash_bank_s
*bank
, u8
*buffer
, u32 offset
, u32 count
)
433 target_t
*target
= bank
->target
;
434 u32 words_remaining
= (count
/ 2);
435 u32 bytes_remaining
= (count
& 0x00000001);
436 u32 address
= bank
->base
+ offset
;
437 u32 bytes_written
= 0;
440 u32 check_address
= offset
;
444 if (bank
->target
->state
!= TARGET_HALTED
)
446 return ERROR_TARGET_NOT_HALTED
;
451 WARNING("offset 0x%x breaks required 2-byte alignment", offset
);
452 return ERROR_FLASH_DST_BREAKS_ALIGNMENT
;
455 for (i
= 0; i
< bank
->num_sectors
; i
++)
457 u32 sec_start
= bank
->sectors
[i
].offset
;
458 u32 sec_end
= sec_start
+ bank
->sectors
[i
].size
;
460 /* check if destination falls within the current sector */
461 if ((check_address
>= sec_start
) && (check_address
< sec_end
))
463 /* check if destination ends in the current sector */
464 if (offset
+ count
< sec_end
)
465 check_address
= offset
+ count
;
467 check_address
= sec_end
;
471 if (check_address
!= offset
+ count
)
472 return ERROR_FLASH_DST_OUT_OF_BANK
;
474 /* multiple half words (2-byte) to be programmed? */
475 if (words_remaining
> 0)
477 /* try using a block write */
478 if ((retval
= str9x_write_block(bank
, buffer
, offset
, words_remaining
)) != ERROR_OK
)
480 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
)
482 /* if block write failed (no sufficient working area),
483 * we use normal (slow) single dword accesses */
484 WARNING("couldn't use block writes, falling back to single memory accesses");
486 else if (retval
== ERROR_FLASH_OPERATION_FAILED
)
488 ERROR("flash writing failed with error code: 0x%x", retval
);
489 return ERROR_FLASH_OPERATION_FAILED
;
494 buffer
+= words_remaining
* 2;
495 address
+= words_remaining
* 2;
500 while (words_remaining
> 0)
502 bank_adr
= address
& ~0x03;
504 /* write data command */
505 target_write_u16(target
, bank_adr
, 0x40);
506 target
->type
->write_memory(target
, address
, 2, 1, buffer
+ bytes_written
);
508 /* get status command */
509 target_write_u16(target
, bank_adr
, 0x70);
512 target_read_u8(target
, bank_adr
, &status
);
518 /* clear status reg and read array */
519 target_write_u16(target
, bank_adr
, 0x50);
520 target_write_u16(target
, bank_adr
, 0xFF);
523 return ERROR_FLASH_OPERATION_FAILED
;
524 else if (status
& 0x02)
525 return ERROR_FLASH_OPERATION_FAILED
;
534 u8 last_halfword
[2] = {0xff, 0xff};
537 while(bytes_remaining
> 0)
539 last_halfword
[i
++] = *(buffer
+ bytes_written
);
544 bank_adr
= address
& ~0x03;
546 /* write data comamnd */
547 target_write_u16(target
, bank_adr
, 0x40);
548 target
->type
->write_memory(target
, address
, 2, 1, last_halfword
);
550 /* query status command */
551 target_write_u16(target
, bank_adr
, 0x70);
554 target_read_u8(target
, bank_adr
, &status
);
560 /* clear status reg and read array */
561 target_write_u16(target
, bank_adr
, 0x50);
562 target_write_u16(target
, bank_adr
, 0xFF);
565 return ERROR_FLASH_OPERATION_FAILED
;
566 else if (status
& 0x02)
567 return ERROR_FLASH_OPERATION_FAILED
;
573 int str9x_probe(struct flash_bank_s
*bank
)
578 int str9x_handle_part_id_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
583 int str9x_erase_check(struct flash_bank_s
*bank
)
585 return str9x_blank_check(bank
, 0, bank
->num_sectors
- 1);
588 int str9x_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
)
590 snprintf(buf
, buf_size
, "str9x flash driver info" );
594 int str9x_handle_flash_config_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
596 str9x_flash_bank_t
*str9x_info
;
598 target_t
*target
= NULL
;
602 command_print(cmd_ctx
, "usage: str9x flash_config <b0size> <b1size> <b0start> <b1start>");
606 bank
= get_flash_bank_by_num(0);
607 str9x_info
= bank
->driver_priv
;
608 target
= bank
->target
;
610 if (bank
->target
->state
!= TARGET_HALTED
)
612 return ERROR_TARGET_NOT_HALTED
;
615 /* config flash controller */
616 target_write_u32(target
, FLASH_BBSR
, strtoul(args
[0], NULL
, 0));
617 target_write_u32(target
, FLASH_NBBSR
, strtoul(args
[1], NULL
, 0));
618 target_write_u32(target
, FLASH_BBADR
, (strtoul(args
[2], NULL
, 0) >> 2));
619 target_write_u32(target
, FLASH_NBBADR
, (strtoul(args
[3], NULL
, 0) >> 2));
621 /* enable flash bank 1 */
622 target_write_u32(target
, FLASH_CR
, 0x18);
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