1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include "replacements.h"
31 #include "algorithm.h"
32 #include "binarybuffer.h"
37 int stm32x_register_commands(struct command_context_s
*cmd_ctx
);
38 int stm32x_flash_bank_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct flash_bank_s
*bank
);
39 int stm32x_erase(struct flash_bank_s
*bank
, int first
, int last
);
40 int stm32x_protect(struct flash_bank_s
*bank
, int set
, int first
, int last
);
41 int stm32x_write(struct flash_bank_s
*bank
, u8
*buffer
, u32 offset
, u32 count
);
42 int stm32x_probe(struct flash_bank_s
*bank
);
43 int stm32x_auto_probe(struct flash_bank_s
*bank
);
44 int stm32x_handle_part_id_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
45 int stm32x_protect_check(struct flash_bank_s
*bank
);
46 int stm32x_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
);
48 int stm32x_handle_lock_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
49 int stm32x_handle_unlock_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
50 int stm32x_handle_options_read_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
51 int stm32x_handle_options_write_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
52 int stm32x_handle_mass_erase_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
53 int stm32x_mass_erase(struct flash_bank_s
*bank
);
55 flash_driver_t stm32x_flash
=
58 .register_commands
= stm32x_register_commands
,
59 .flash_bank_command
= stm32x_flash_bank_command
,
60 .erase
= stm32x_erase
,
61 .protect
= stm32x_protect
,
62 .write
= stm32x_write
,
63 .probe
= stm32x_probe
,
64 .auto_probe
= stm32x_auto_probe
,
65 .erase_check
= default_flash_mem_blank_check
,
66 .protect_check
= stm32x_protect_check
,
70 int stm32x_register_commands(struct command_context_s
*cmd_ctx
)
72 command_t
*stm32x_cmd
= register_command(cmd_ctx
, NULL
, "stm32x", NULL
, COMMAND_ANY
, "stm32x flash specific commands");
74 register_command(cmd_ctx
, stm32x_cmd
, "lock", stm32x_handle_lock_command
, COMMAND_EXEC
,
76 register_command(cmd_ctx
, stm32x_cmd
, "unlock", stm32x_handle_unlock_command
, COMMAND_EXEC
,
77 "unlock protected device");
78 register_command(cmd_ctx
, stm32x_cmd
, "mass_erase", stm32x_handle_mass_erase_command
, COMMAND_EXEC
,
80 register_command(cmd_ctx
, stm32x_cmd
, "options_read", stm32x_handle_options_read_command
, COMMAND_EXEC
,
81 "read device option bytes");
82 register_command(cmd_ctx
, stm32x_cmd
, "options_write", stm32x_handle_options_write_command
, COMMAND_EXEC
,
83 "write device option bytes");
87 /* flash bank stm32x <base> <size> 0 0 <target#>
89 int stm32x_flash_bank_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct flash_bank_s
*bank
)
91 stm32x_flash_bank_t
*stm32x_info
;
95 LOG_WARNING("incomplete flash_bank stm32x configuration");
96 return ERROR_FLASH_BANK_INVALID
;
99 stm32x_info
= malloc(sizeof(stm32x_flash_bank_t
));
100 bank
->driver_priv
= stm32x_info
;
102 stm32x_info
->write_algorithm
= NULL
;
103 stm32x_info
->probed
= 0;
108 u32
stm32x_get_flash_status(flash_bank_t
*bank
)
110 target_t
*target
= bank
->target
;
113 target_read_u32(target
, STM32_FLASH_SR
, &status
);
118 u32
stm32x_wait_status_busy(flash_bank_t
*bank
, int timeout
)
122 /* wait for busy to clear */
123 while (((status
= stm32x_get_flash_status(bank
)) & FLASH_BSY
) && (timeout
-- > 0))
125 LOG_DEBUG("status: 0x%x", status
);
132 int stm32x_read_options(struct flash_bank_s
*bank
)
135 stm32x_flash_bank_t
*stm32x_info
= NULL
;
136 target_t
*target
= bank
->target
;
138 stm32x_info
= bank
->driver_priv
;
140 /* read current option bytes */
141 target_read_u32(target
, STM32_FLASH_OBR
, &optiondata
);
143 stm32x_info
->option_bytes
.user_options
= (u16
)0xFFF8|((optiondata
>> 2) & 0x07);
144 stm32x_info
->option_bytes
.RDP
= (optiondata
& (1 << OPT_READOUT
)) ? 0xFFFF : 0x5AA5;
146 if (optiondata
& (1 << OPT_READOUT
))
147 LOG_INFO("Device Security Bit Set");
149 /* each bit refers to a 4bank protection */
150 target_read_u32(target
, STM32_FLASH_WRPR
, &optiondata
);
152 stm32x_info
->option_bytes
.protection
[0] = (u16
)optiondata
;
153 stm32x_info
->option_bytes
.protection
[1] = (u16
)(optiondata
>> 8);
154 stm32x_info
->option_bytes
.protection
[2] = (u16
)(optiondata
>> 16);
155 stm32x_info
->option_bytes
.protection
[3] = (u16
)(optiondata
>> 24);
160 int stm32x_erase_options(struct flash_bank_s
*bank
)
162 stm32x_flash_bank_t
*stm32x_info
= NULL
;
163 target_t
*target
= bank
->target
;
166 stm32x_info
= bank
->driver_priv
;
168 /* read current options */
169 stm32x_read_options(bank
);
171 /* unlock flash registers */
172 target_write_u32(target
, STM32_FLASH_KEYR
, KEY1
);
173 target_write_u32(target
, STM32_FLASH_KEYR
, KEY2
);
175 /* unlock option flash registers */
176 target_write_u32(target
, STM32_FLASH_OPTKEYR
, KEY1
);
177 target_write_u32(target
, STM32_FLASH_OPTKEYR
, KEY2
);
179 /* erase option bytes */
180 target_write_u32(target
, STM32_FLASH_CR
, FLASH_OPTER
|FLASH_OPTWRE
);
181 target_write_u32(target
, STM32_FLASH_CR
, FLASH_OPTER
|FLASH_STRT
|FLASH_OPTWRE
);
183 status
= stm32x_wait_status_busy(bank
, 10);
185 if( status
& FLASH_WRPRTERR
)
186 return ERROR_FLASH_OPERATION_FAILED
;
187 if( status
& FLASH_PGERR
)
188 return ERROR_FLASH_OPERATION_FAILED
;
190 /* clear readout protection and complementary option bytes
191 * this will also force a device unlock if set */
192 stm32x_info
->option_bytes
.RDP
= 0x5AA5;
197 int stm32x_write_options(struct flash_bank_s
*bank
)
199 stm32x_flash_bank_t
*stm32x_info
= NULL
;
200 target_t
*target
= bank
->target
;
203 stm32x_info
= bank
->driver_priv
;
205 /* unlock flash registers */
206 target_write_u32(target
, STM32_FLASH_KEYR
, KEY1
);
207 target_write_u32(target
, STM32_FLASH_KEYR
, KEY2
);
209 /* unlock option flash registers */
210 target_write_u32(target
, STM32_FLASH_OPTKEYR
, KEY1
);
211 target_write_u32(target
, STM32_FLASH_OPTKEYR
, KEY2
);
213 /* program option bytes */
214 target_write_u32(target
, STM32_FLASH_CR
, FLASH_OPTPG
|FLASH_OPTWRE
);
216 /* write user option byte */
217 target_write_u16(target
, STM32_OB_USER
, stm32x_info
->option_bytes
.user_options
);
219 status
= stm32x_wait_status_busy(bank
, 10);
221 if( status
& FLASH_WRPRTERR
)
222 return ERROR_FLASH_OPERATION_FAILED
;
223 if( status
& FLASH_PGERR
)
224 return ERROR_FLASH_OPERATION_FAILED
;
226 /* write protection byte 1 */
227 target_write_u16(target
, STM32_OB_WRP0
, stm32x_info
->option_bytes
.protection
[0]);
229 status
= stm32x_wait_status_busy(bank
, 10);
231 if( status
& FLASH_WRPRTERR
)
232 return ERROR_FLASH_OPERATION_FAILED
;
233 if( status
& FLASH_PGERR
)
234 return ERROR_FLASH_OPERATION_FAILED
;
236 /* write protection byte 2 */
237 target_write_u16(target
, STM32_OB_WRP1
, stm32x_info
->option_bytes
.protection
[1]);
239 status
= stm32x_wait_status_busy(bank
, 10);
241 if( status
& FLASH_WRPRTERR
)
242 return ERROR_FLASH_OPERATION_FAILED
;
243 if( status
& FLASH_PGERR
)
244 return ERROR_FLASH_OPERATION_FAILED
;
246 /* write protection byte 3 */
247 target_write_u16(target
, STM32_OB_WRP2
, stm32x_info
->option_bytes
.protection
[2]);
249 status
= stm32x_wait_status_busy(bank
, 10);
251 if( status
& FLASH_WRPRTERR
)
252 return ERROR_FLASH_OPERATION_FAILED
;
253 if( status
& FLASH_PGERR
)
254 return ERROR_FLASH_OPERATION_FAILED
;
256 /* write protection byte 4 */
257 target_write_u16(target
, STM32_OB_WRP3
, stm32x_info
->option_bytes
.protection
[3]);
259 status
= stm32x_wait_status_busy(bank
, 10);
261 if( status
& FLASH_WRPRTERR
)
262 return ERROR_FLASH_OPERATION_FAILED
;
263 if( status
& FLASH_PGERR
)
264 return ERROR_FLASH_OPERATION_FAILED
;
266 /* write readout protection bit */
267 target_write_u16(target
, STM32_OB_RDP
, stm32x_info
->option_bytes
.RDP
);
269 status
= stm32x_wait_status_busy(bank
, 10);
271 if( status
& FLASH_WRPRTERR
)
272 return ERROR_FLASH_OPERATION_FAILED
;
273 if( status
& FLASH_PGERR
)
274 return ERROR_FLASH_OPERATION_FAILED
;
276 target_write_u32(target
, STM32_FLASH_CR
, FLASH_LOCK
);
281 int stm32x_protect_check(struct flash_bank_s
*bank
)
283 target_t
*target
= bank
->target
;
284 stm32x_flash_bank_t
*stm32x_info
= bank
->driver_priv
;
290 if (target
->state
!= TARGET_HALTED
)
292 return ERROR_TARGET_NOT_HALTED
;
295 /* medium density - each bit refers to a 4bank protection
296 * high density - each bit refers to a 2bank protection */
297 target_read_u32(target
, STM32_FLASH_WRPR
, &protection
);
299 /* medium density - each protection bit is for 4 * 1K pages
300 * high density - each protection bit is for 2 * 2K pages */
301 num_bits
= (bank
->num_sectors
/ stm32x_info
->ppage_size
);
303 for (i
= 0; i
< num_bits
; i
++)
307 if( protection
& (1 << i
))
310 for (s
= 0; s
< stm32x_info
->ppage_size
; s
++)
311 bank
->sectors
[(i
* stm32x_info
->ppage_size
) + s
].is_protected
= set
;
317 int stm32x_erase(struct flash_bank_s
*bank
, int first
, int last
)
319 target_t
*target
= bank
->target
;
323 if (bank
->target
->state
!= TARGET_HALTED
)
325 return ERROR_TARGET_NOT_HALTED
;
328 if ((first
== 0) && (last
== (bank
->num_sectors
- 1)))
330 return stm32x_mass_erase(bank
);
333 /* unlock flash registers */
334 target_write_u32(target
, STM32_FLASH_KEYR
, KEY1
);
335 target_write_u32(target
, STM32_FLASH_KEYR
, KEY2
);
337 for (i
= first
; i
<= last
; i
++)
339 target_write_u32(target
, STM32_FLASH_CR
, FLASH_PER
);
340 target_write_u32(target
, STM32_FLASH_AR
, bank
->base
+ bank
->sectors
[i
].offset
);
341 target_write_u32(target
, STM32_FLASH_CR
, FLASH_PER
|FLASH_STRT
);
343 status
= stm32x_wait_status_busy(bank
, 10);
345 if( status
& FLASH_WRPRTERR
)
346 return ERROR_FLASH_OPERATION_FAILED
;
347 if( status
& FLASH_PGERR
)
348 return ERROR_FLASH_OPERATION_FAILED
;
349 bank
->sectors
[i
].is_erased
= 1;
352 target_write_u32(target
, STM32_FLASH_CR
, FLASH_LOCK
);
357 int stm32x_protect(struct flash_bank_s
*bank
, int set
, int first
, int last
)
359 stm32x_flash_bank_t
*stm32x_info
= NULL
;
360 target_t
*target
= bank
->target
;
361 u16 prot_reg
[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
366 stm32x_info
= bank
->driver_priv
;
368 if (target
->state
!= TARGET_HALTED
)
370 return ERROR_TARGET_NOT_HALTED
;
373 if ((first
&& (first
% stm32x_info
->ppage_size
)) || ((last
+ 1) && (last
+ 1) % stm32x_info
->ppage_size
))
375 LOG_WARNING("sector start/end incorrect - stm32 has %dK sector protection", stm32x_info
->ppage_size
);
376 return ERROR_FLASH_SECTOR_INVALID
;
379 /* medium density - each bit refers to a 4bank protection
380 * high density - each bit refers to a 2bank protection */
381 target_read_u32(target
, STM32_FLASH_WRPR
, &protection
);
383 prot_reg
[0] = (u16
)protection
;
384 prot_reg
[1] = (u16
)(protection
>> 8);
385 prot_reg
[2] = (u16
)(protection
>> 16);
386 prot_reg
[3] = (u16
)(protection
>> 24);
388 for (i
= first
; i
<= last
; i
++)
390 reg
= (i
/ stm32x_info
->ppage_size
) / 8;
391 bit
= (i
/ stm32x_info
->ppage_size
) - (reg
* 8);
394 prot_reg
[reg
] &= ~(1 << bit
);
396 prot_reg
[reg
] |= (1 << bit
);
399 if ((status
= stm32x_erase_options(bank
)) != ERROR_OK
)
402 stm32x_info
->option_bytes
.protection
[0] = prot_reg
[0];
403 stm32x_info
->option_bytes
.protection
[1] = prot_reg
[1];
404 stm32x_info
->option_bytes
.protection
[2] = prot_reg
[2];
405 stm32x_info
->option_bytes
.protection
[3] = prot_reg
[3];
407 return stm32x_write_options(bank
);
410 int stm32x_write_block(struct flash_bank_s
*bank
, u8
*buffer
, u32 offset
, u32 count
)
412 stm32x_flash_bank_t
*stm32x_info
= bank
->driver_priv
;
413 target_t
*target
= bank
->target
;
414 u32 buffer_size
= 8192;
415 working_area_t
*source
;
416 u32 address
= bank
->base
+ offset
;
417 reg_param_t reg_params
[4];
418 armv7m_algorithm_t armv7m_info
;
419 int retval
= ERROR_OK
;
421 u8 stm32x_flash_write_code
[] = {
423 0xDF, 0xF8, 0x24, 0x40, /* ldr r4, STM32_FLASH_CR */
424 0x09, 0x4D, /* ldr r5, STM32_FLASH_SR */
425 0x4F, 0xF0, 0x01, 0x03, /* mov r3, #1 */
426 0x23, 0x60, /* str r3, [r4, #0] */
427 0x30, 0xF8, 0x02, 0x3B, /* ldrh r3, [r0], #2 */
428 0x21, 0xF8, 0x02, 0x3B, /* strh r3, [r1], #2 */
430 0x2B, 0x68, /* ldr r3, [r5, #0] */
431 0x13, 0xF0, 0x01, 0x0F, /* tst r3, #0x01 */
432 0xFB, 0xD0, /* beq busy */
433 0x13, 0xF0, 0x14, 0x0F, /* tst r3, #0x14 */
434 0x01, 0xD1, /* bne exit */
435 0x01, 0x3A, /* subs r2, r2, #1 */
436 0xED, 0xD1, /* bne write */
438 0xFE, 0xE7, /* b exit */
439 0x10, 0x20, 0x02, 0x40, /* STM32_FLASH_CR: .word 0x40022010 */
440 0x0C, 0x20, 0x02, 0x40 /* STM32_FLASH_SR: .word 0x4002200C */
443 /* flash write code */
444 if (target_alloc_working_area(target
, sizeof(stm32x_flash_write_code
), &stm32x_info
->write_algorithm
) != ERROR_OK
)
446 LOG_WARNING("no working area available, can't do block memory writes");
447 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
450 if ((retval
=target_write_buffer(target
, stm32x_info
->write_algorithm
->address
, sizeof(stm32x_flash_write_code
), stm32x_flash_write_code
))!=ERROR_OK
)
454 while (target_alloc_working_area(target
, buffer_size
, &source
) != ERROR_OK
)
457 if (buffer_size
<= 256)
459 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
460 if (stm32x_info
->write_algorithm
)
461 target_free_working_area(target
, stm32x_info
->write_algorithm
);
463 LOG_WARNING("no large enough working area available, can't do block memory writes");
464 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
468 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
469 armv7m_info
.core_mode
= ARMV7M_MODE_ANY
;
471 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
472 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
473 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
474 init_reg_param(®_params
[3], "r3", 32, PARAM_IN
);
478 u32 thisrun_count
= (count
> (buffer_size
/ 2)) ? (buffer_size
/ 2) : count
;
480 if ((retval
= target_write_buffer(target
, source
->address
, thisrun_count
* 2, buffer
))!=ERROR_OK
)
483 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
484 buf_set_u32(reg_params
[1].value
, 0, 32, address
);
485 buf_set_u32(reg_params
[2].value
, 0, 32, thisrun_count
);
487 if ((retval
= target
->type
->run_algorithm(target
, 0, NULL
, 4, reg_params
, stm32x_info
->write_algorithm
->address
, \
488 stm32x_info
->write_algorithm
->address
+ (sizeof(stm32x_flash_write_code
) - 10), 10000, &armv7m_info
)) != ERROR_OK
)
490 LOG_ERROR("error executing stm32x flash write algorithm");
491 retval
= ERROR_FLASH_OPERATION_FAILED
;
495 if (buf_get_u32(reg_params
[3].value
, 0, 32) & 0x14)
497 retval
= ERROR_FLASH_OPERATION_FAILED
;
501 buffer
+= thisrun_count
* 2;
502 address
+= thisrun_count
* 2;
503 count
-= thisrun_count
;
506 target_free_working_area(target
, source
);
507 target_free_working_area(target
, stm32x_info
->write_algorithm
);
509 destroy_reg_param(®_params
[0]);
510 destroy_reg_param(®_params
[1]);
511 destroy_reg_param(®_params
[2]);
512 destroy_reg_param(®_params
[3]);
517 int stm32x_write(struct flash_bank_s
*bank
, u8
*buffer
, u32 offset
, u32 count
)
519 target_t
*target
= bank
->target
;
520 u32 words_remaining
= (count
/ 2);
521 u32 bytes_remaining
= (count
& 0x00000001);
522 u32 address
= bank
->base
+ offset
;
523 u32 bytes_written
= 0;
527 if (bank
->target
->state
!= TARGET_HALTED
)
529 return ERROR_TARGET_NOT_HALTED
;
534 LOG_WARNING("offset 0x%x breaks required 2-byte alignment", offset
);
535 return ERROR_FLASH_DST_BREAKS_ALIGNMENT
;
538 /* unlock flash registers */
539 target_write_u32(target
, STM32_FLASH_KEYR
, KEY1
);
540 target_write_u32(target
, STM32_FLASH_KEYR
, KEY2
);
542 /* multiple half words (2-byte) to be programmed? */
543 if (words_remaining
> 0)
545 /* try using a block write */
546 if ((retval
= stm32x_write_block(bank
, buffer
, offset
, words_remaining
)) != ERROR_OK
)
548 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
)
550 /* if block write failed (no sufficient working area),
551 * we use normal (slow) single dword accesses */
552 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
554 else if (retval
== ERROR_FLASH_OPERATION_FAILED
)
556 LOG_ERROR("flash writing failed with error code: 0x%x", retval
);
557 return ERROR_FLASH_OPERATION_FAILED
;
562 buffer
+= words_remaining
* 2;
563 address
+= words_remaining
* 2;
568 while (words_remaining
> 0)
570 target_write_u32(target
, STM32_FLASH_CR
, FLASH_PG
);
571 target_write_u16(target
, address
, *(u16
*)(buffer
+ bytes_written
));
573 status
= stm32x_wait_status_busy(bank
, 5);
575 if( status
& FLASH_WRPRTERR
)
576 return ERROR_FLASH_OPERATION_FAILED
;
577 if( status
& FLASH_PGERR
)
578 return ERROR_FLASH_OPERATION_FAILED
;
587 u8 last_halfword
[2] = {0xff, 0xff};
590 while(bytes_remaining
> 0)
592 last_halfword
[i
++] = *(buffer
+ bytes_written
);
597 target_write_u32(target
, STM32_FLASH_CR
, FLASH_PG
);
598 target_write_u16(target
, address
, *(u16
*)last_halfword
);
600 status
= stm32x_wait_status_busy(bank
, 5);
602 if( status
& FLASH_WRPRTERR
)
603 return ERROR_FLASH_OPERATION_FAILED
;
604 if( status
& FLASH_PGERR
)
605 return ERROR_FLASH_OPERATION_FAILED
;
608 target_write_u32(target
, STM32_FLASH_CR
, FLASH_LOCK
);
613 int stm32x_probe(struct flash_bank_s
*bank
)
615 target_t
*target
= bank
->target
;
616 stm32x_flash_bank_t
*stm32x_info
= bank
->driver_priv
;
622 if (bank
->target
->state
!= TARGET_HALTED
)
624 return ERROR_TARGET_NOT_HALTED
;
627 stm32x_info
->probed
= 0;
629 /* read stm32 device id register */
630 target_read_u32(target
, 0xE0042000, &device_id
);
631 LOG_INFO( "device id = 0x%08x", device_id
);
633 switch (device_id
& 0x7ff)
636 /* medium density - we have 1k pages
637 * 4 pages for a protection area */
639 stm32x_info
->ppage_size
= 4;
643 /* high density - we have 2k pages
644 * 2 pages for a protection area */
646 stm32x_info
->ppage_size
= 2;
650 LOG_WARNING( "Cannot identify target as a STM32 family." );
651 return ERROR_FLASH_OPERATION_FAILED
;
654 /* get flash size from target */
655 if (target_read_u16(target
, 0x1FFFF7E0, &num_pages
) != ERROR_OK
)
657 /* failed reading flash size, default to 128k */
658 LOG_WARNING( "STM32 flash size failed, probe inaccurate - assuming 128k flash" );
662 /* check for early silicon rev A */
663 if ((device_id
>> 16) == 0 )
665 /* number of sectors incorrect on revA */
666 LOG_WARNING( "STM32 Rev A Silicon detected, probe inaccurate - assuming 128k flash" );
670 LOG_INFO( "flash size = %dkbytes", num_pages
);
672 /* calculate numbers of pages */
673 num_pages
/= (page_size
/ 1024);
675 bank
->base
= 0x08000000;
676 bank
->size
= (num_pages
* page_size
);
677 bank
->num_sectors
= num_pages
;
678 bank
->sectors
= malloc(sizeof(flash_sector_t
) * num_pages
);
680 for (i
= 0; i
< num_pages
; i
++)
682 bank
->sectors
[i
].offset
= i
* page_size
;
683 bank
->sectors
[i
].size
= page_size
;
684 bank
->sectors
[i
].is_erased
= -1;
685 bank
->sectors
[i
].is_protected
= 1;
688 stm32x_info
->probed
= 1;
693 int stm32x_auto_probe(struct flash_bank_s
*bank
)
695 stm32x_flash_bank_t
*stm32x_info
= bank
->driver_priv
;
696 if (stm32x_info
->probed
)
698 return stm32x_probe(bank
);
701 int stm32x_handle_part_id_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
706 int stm32x_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
)
708 snprintf(buf
, buf_size
, "stm32x flash driver info" );
712 int stm32x_handle_lock_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
715 target_t
*target
= NULL
;
716 stm32x_flash_bank_t
*stm32x_info
= NULL
;
720 command_print(cmd_ctx
, "stm32x lock <bank>");
724 bank
= get_flash_bank_by_num(strtoul(args
[0], NULL
, 0));
727 command_print(cmd_ctx
, "flash bank '#%s' is out of bounds", args
[0]);
731 stm32x_info
= bank
->driver_priv
;
733 target
= bank
->target
;
735 if (target
->state
!= TARGET_HALTED
)
737 return ERROR_TARGET_NOT_HALTED
;
740 if (stm32x_erase_options(bank
) != ERROR_OK
)
742 command_print(cmd_ctx
, "stm32x failed to erase options");
746 /* set readout protection */
747 stm32x_info
->option_bytes
.RDP
= 0;
749 if (stm32x_write_options(bank
) != ERROR_OK
)
751 command_print(cmd_ctx
, "stm32x failed to lock device");
755 command_print(cmd_ctx
, "stm32x locked");
760 int stm32x_handle_unlock_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
763 target_t
*target
= NULL
;
764 stm32x_flash_bank_t
*stm32x_info
= NULL
;
768 command_print(cmd_ctx
, "stm32x unlock <bank>");
772 bank
= get_flash_bank_by_num(strtoul(args
[0], NULL
, 0));
775 command_print(cmd_ctx
, "flash bank '#%s' is out of bounds", args
[0]);
779 stm32x_info
= bank
->driver_priv
;
781 target
= bank
->target
;
783 if (target
->state
!= TARGET_HALTED
)
785 return ERROR_TARGET_NOT_HALTED
;
788 if (stm32x_erase_options(bank
) != ERROR_OK
)
790 command_print(cmd_ctx
, "stm32x failed to unlock device");
794 if (stm32x_write_options(bank
) != ERROR_OK
)
796 command_print(cmd_ctx
, "stm32x failed to lock device");
800 command_print(cmd_ctx
, "stm32x unlocked");
805 int stm32x_handle_options_read_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
809 target_t
*target
= NULL
;
810 stm32x_flash_bank_t
*stm32x_info
= NULL
;
814 command_print(cmd_ctx
, "stm32x options_read <bank>");
818 bank
= get_flash_bank_by_num(strtoul(args
[0], NULL
, 0));
821 command_print(cmd_ctx
, "flash bank '#%s' is out of bounds", args
[0]);
825 stm32x_info
= bank
->driver_priv
;
827 target
= bank
->target
;
829 if (target
->state
!= TARGET_HALTED
)
831 return ERROR_TARGET_NOT_HALTED
;
834 target_read_u32(target
, STM32_FLASH_OBR
, &optionbyte
);
835 command_print(cmd_ctx
, "Option Byte: 0x%x", optionbyte
);
837 if (buf_get_u32((u8
*)&optionbyte
, OPT_ERROR
, 1))
838 command_print(cmd_ctx
, "Option Byte Complement Error");
840 if (buf_get_u32((u8
*)&optionbyte
, OPT_READOUT
, 1))
841 command_print(cmd_ctx
, "Readout Protection On");
843 command_print(cmd_ctx
, "Readout Protection Off");
845 if (buf_get_u32((u8
*)&optionbyte
, OPT_RDWDGSW
, 1))
846 command_print(cmd_ctx
, "Software Watchdog");
848 command_print(cmd_ctx
, "Hardware Watchdog");
850 if (buf_get_u32((u8
*)&optionbyte
, OPT_RDRSTSTOP
, 1))
851 command_print(cmd_ctx
, "Stop: No reset generated");
853 command_print(cmd_ctx
, "Stop: Reset generated");
855 if (buf_get_u32((u8
*)&optionbyte
, OPT_RDRSTSTDBY
, 1))
856 command_print(cmd_ctx
, "Standby: No reset generated");
858 command_print(cmd_ctx
, "Standby: Reset generated");
863 int stm32x_handle_options_write_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
866 target_t
*target
= NULL
;
867 stm32x_flash_bank_t
*stm32x_info
= NULL
;
868 u16 optionbyte
= 0xF8;
872 command_print(cmd_ctx
, "stm32x options_write <bank> <SWWDG|HWWDG> <RSTSTNDBY|NORSTSTNDBY> <RSTSTOP|NORSTSTOP>");
876 bank
= get_flash_bank_by_num(strtoul(args
[0], NULL
, 0));
879 command_print(cmd_ctx
, "flash bank '#%s' is out of bounds", args
[0]);
883 stm32x_info
= bank
->driver_priv
;
885 target
= bank
->target
;
887 if (target
->state
!= TARGET_HALTED
)
889 return ERROR_TARGET_NOT_HALTED
;
892 if (strcmp(args
[1], "SWWDG") == 0)
894 optionbyte
|= (1<<0);
898 optionbyte
&= ~(1<<0);
901 if (strcmp(args
[2], "NORSTSTNDBY") == 0)
903 optionbyte
|= (1<<1);
907 optionbyte
&= ~(1<<1);
910 if (strcmp(args
[3], "NORSTSTOP") == 0)
912 optionbyte
|= (1<<2);
916 optionbyte
&= ~(1<<2);
919 if (stm32x_erase_options(bank
) != ERROR_OK
)
921 command_print(cmd_ctx
, "stm32x failed to erase options");
925 stm32x_info
->option_bytes
.user_options
= optionbyte
;
927 if (stm32x_write_options(bank
) != ERROR_OK
)
929 command_print(cmd_ctx
, "stm32x failed to write options");
933 command_print(cmd_ctx
, "stm32x write options complete");
938 int stm32x_mass_erase(struct flash_bank_s
*bank
)
940 target_t
*target
= bank
->target
;
943 if (target
->state
!= TARGET_HALTED
)
945 return ERROR_TARGET_NOT_HALTED
;
948 /* unlock option flash registers */
949 target_write_u32(target
, STM32_FLASH_KEYR
, KEY1
);
950 target_write_u32(target
, STM32_FLASH_KEYR
, KEY2
);
952 /* mass erase flash memory */
953 target_write_u32(target
, STM32_FLASH_CR
, FLASH_MER
);
954 target_write_u32(target
, STM32_FLASH_CR
, FLASH_MER
|FLASH_STRT
);
956 status
= stm32x_wait_status_busy(bank
, 10);
958 target_write_u32(target
, STM32_FLASH_CR
, FLASH_LOCK
);
960 if( status
& FLASH_WRPRTERR
)
962 LOG_ERROR("stm32x device protected");
966 if( status
& FLASH_PGERR
)
968 LOG_ERROR("stm32x device programming failed");
975 int stm32x_handle_mass_erase_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
982 command_print(cmd_ctx
, "stm32x mass_erase <bank>");
986 bank
= get_flash_bank_by_num(strtoul(args
[0], NULL
, 0));
989 command_print(cmd_ctx
, "flash bank '#%s' is out of bounds", args
[0]);
993 if (stm32x_mass_erase(bank
) == ERROR_OK
)
995 /* set all sectors as erased */
996 for (i
= 0; i
< bank
->num_sectors
; i
++)
998 bank
->sectors
[i
].is_erased
= 1;
1001 command_print(cmd_ctx
, "stm32x mass erase complete");
1005 command_print(cmd_ctx
, "stm32x mass erase failed");
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