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stm32: add stm32 xl family flash support
[openocd.git] / src / flash / nor / stm32x.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
23 #ifdef HAVE_CONFIG_H
24 #include "config.h"
25 #endif
26
27 #include "imp.h"
28 #include <helper/binarybuffer.h>
29 #include <target/algorithm.h>
30 #include <target/armv7m.h>
31
32 /* stm32x register locations */
33
34 #define STM32_FLASH_ACR 0x40022000
35 #define STM32_FLASH_KEYR 0x40022004
36 #define STM32_FLASH_OPTKEYR 0x40022008
37 #define STM32_FLASH_SR 0x4002200C
38 #define STM32_FLASH_CR 0x40022010
39 #define STM32_FLASH_AR 0x40022014
40 #define STM32_FLASH_OBR 0x4002201C
41 #define STM32_FLASH_WRPR 0x40022020
42
43 /* option byte location */
44
45 #define STM32_OB_RDP 0x1FFFF800
46 #define STM32_OB_USER 0x1FFFF802
47 #define STM32_OB_DATA0 0x1FFFF804
48 #define STM32_OB_DATA1 0x1FFFF806
49 #define STM32_OB_WRP0 0x1FFFF808
50 #define STM32_OB_WRP1 0x1FFFF80A
51 #define STM32_OB_WRP2 0x1FFFF80C
52 #define STM32_OB_WRP3 0x1FFFF80E
53
54 /* FLASH_CR register bits */
55
56 #define FLASH_PG (1 << 0)
57 #define FLASH_PER (1 << 1)
58 #define FLASH_MER (1 << 2)
59 #define FLASH_OPTPG (1 << 4)
60 #define FLASH_OPTER (1 << 5)
61 #define FLASH_STRT (1 << 6)
62 #define FLASH_LOCK (1 << 7)
63 #define FLASH_OPTWRE (1 << 9)
64
65 /* FLASH_SR register bits */
66
67 #define FLASH_BSY (1 << 0)
68 #define FLASH_PGERR (1 << 2)
69 #define FLASH_WRPRTERR (1 << 4)
70 #define FLASH_EOP (1 << 5)
71
72 /* STM32_FLASH_OBR bit definitions (reading) */
73
74 #define OPT_ERROR 0
75 #define OPT_READOUT 1
76 #define OPT_RDWDGSW 2
77 #define OPT_RDRSTSTOP 3
78 #define OPT_RDRSTSTDBY 4
79
80 /* register unlock keys */
81
82 #define KEY1 0x45670123
83 #define KEY2 0xCDEF89AB
84
85 struct stm32x_options
86 {
87 uint16_t RDP;
88 uint16_t user_options;
89 uint16_t protection[4];
90 };
91
92 struct stm32x_flash_bank
93 {
94 struct stm32x_options option_bytes;
95 struct working_area *write_algorithm;
96 int ppage_size;
97 int probed;
98
99 /* used to access dual flash bank stm32xl
100 * 0x00 will address sector 0 flash
101 * 0x40 will address sector 1 flash */
102 int register_offset;
103 };
104
105 static int stm32x_mass_erase(struct flash_bank *bank);
106
107 /* flash bank stm32x <base> <size> 0 0 <target#>
108 */
109 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
110 {
111 struct stm32x_flash_bank *stm32x_info;
112
113 if (CMD_ARGC < 6)
114 {
115 LOG_WARNING("incomplete flash_bank stm32x configuration");
116 return ERROR_FLASH_BANK_INVALID;
117 }
118
119 stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
120 bank->driver_priv = stm32x_info;
121
122 stm32x_info->write_algorithm = NULL;
123 stm32x_info->probed = 0;
124 stm32x_info->register_offset = 0x00;
125
126 return ERROR_OK;
127 }
128
129 static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
130 {
131 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
132 return reg + stm32x_info->register_offset;
133 }
134
135 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
136 {
137 struct target *target = bank->target;
138 return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
139 }
140
141 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
142 {
143 struct target *target = bank->target;
144 uint32_t status;
145 int retval = ERROR_OK;
146
147 /* wait for busy to clear */
148 for (;;)
149 {
150 retval = stm32x_get_flash_status(bank, &status);
151 if (retval != ERROR_OK)
152 return retval;
153 LOG_DEBUG("status: 0x%" PRIx32 "", status);
154 if ((status & FLASH_BSY) == 0)
155 break;
156 if (timeout-- <= 0)
157 {
158 LOG_ERROR("timed out waiting for flash");
159 return ERROR_FAIL;
160 }
161 alive_sleep(1);
162 }
163
164 if (status & FLASH_WRPRTERR)
165 {
166 LOG_ERROR("stm32x device protected");
167 retval = ERROR_FAIL;
168 }
169
170 if (status & FLASH_PGERR)
171 {
172 LOG_ERROR("stm32x device programming failed");
173 retval = ERROR_FAIL;
174 }
175
176 /* Clear but report errors */
177 if (status & (FLASH_WRPRTERR | FLASH_PGERR))
178 {
179 /* If this operation fails, we ignore it and report the original
180 * retval
181 */
182 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
183 FLASH_WRPRTERR | FLASH_PGERR);
184 }
185 return retval;
186 }
187
188 static int stm32x_read_options(struct flash_bank *bank)
189 {
190 uint32_t optiondata;
191 struct stm32x_flash_bank *stm32x_info = NULL;
192 struct target *target = bank->target;
193
194 stm32x_info = bank->driver_priv;
195
196 /* read current option bytes */
197 int retval = target_read_u32(target, STM32_FLASH_OBR, &optiondata);
198 if (retval != ERROR_OK)
199 return retval;
200
201 stm32x_info->option_bytes.user_options = (uint16_t)0xFFF8 | ((optiondata >> 2) & 0x07);
202 stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
203
204 if (optiondata & (1 << OPT_READOUT))
205 LOG_INFO("Device Security Bit Set");
206
207 /* each bit refers to a 4bank protection */
208 retval = target_read_u32(target, STM32_FLASH_WRPR, &optiondata);
209 if (retval != ERROR_OK)
210 return retval;
211
212 stm32x_info->option_bytes.protection[0] = (uint16_t)optiondata;
213 stm32x_info->option_bytes.protection[1] = (uint16_t)(optiondata >> 8);
214 stm32x_info->option_bytes.protection[2] = (uint16_t)(optiondata >> 16);
215 stm32x_info->option_bytes.protection[3] = (uint16_t)(optiondata >> 24);
216
217 return ERROR_OK;
218 }
219
220 static int stm32x_erase_options(struct flash_bank *bank)
221 {
222 struct stm32x_flash_bank *stm32x_info = NULL;
223 struct target *target = bank->target;
224
225 stm32x_info = bank->driver_priv;
226
227 /* read current options */
228 stm32x_read_options(bank);
229
230 /* unlock flash registers */
231 int retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
232 if (retval != ERROR_OK)
233 return retval;
234
235 retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
236 if (retval != ERROR_OK)
237 return retval;
238
239 /* unlock option flash registers */
240 retval = target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
241 if (retval != ERROR_OK)
242 return retval;
243 retval = target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
244 if (retval != ERROR_OK)
245 return retval;
246
247 /* erase option bytes */
248 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER | FLASH_OPTWRE);
249 if (retval != ERROR_OK)
250 return retval;
251 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
252 if (retval != ERROR_OK)
253 return retval;
254
255 retval = stm32x_wait_status_busy(bank, 10);
256 if (retval != ERROR_OK)
257 return retval;
258
259 /* clear readout protection and complementary option bytes
260 * this will also force a device unlock if set */
261 stm32x_info->option_bytes.RDP = 0x5AA5;
262
263 return ERROR_OK;
264 }
265
266 static int stm32x_write_options(struct flash_bank *bank)
267 {
268 struct stm32x_flash_bank *stm32x_info = NULL;
269 struct target *target = bank->target;
270
271 stm32x_info = bank->driver_priv;
272
273 /* unlock flash registers */
274 int retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
275 if (retval != ERROR_OK)
276 return retval;
277 retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
278 if (retval != ERROR_OK)
279 return retval;
280
281 /* unlock option flash registers */
282 retval = target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
283 if (retval != ERROR_OK)
284 return retval;
285 retval = target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
286 if (retval != ERROR_OK)
287 return retval;
288
289 /* program option bytes */
290 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_OPTPG | FLASH_OPTWRE);
291 if (retval != ERROR_OK)
292 return retval;
293
294 /* write user option byte */
295 retval = target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options);
296 if (retval != ERROR_OK)
297 return retval;
298
299 retval = stm32x_wait_status_busy(bank, 10);
300 if (retval != ERROR_OK)
301 return retval;
302
303 /* write protection byte 1 */
304 retval = target_write_u16(target, STM32_OB_WRP0, stm32x_info->option_bytes.protection[0]);
305 if (retval != ERROR_OK)
306 return retval;
307
308 retval = stm32x_wait_status_busy(bank, 10);
309 if (retval != ERROR_OK)
310 return retval;
311
312 /* write protection byte 2 */
313 retval = target_write_u16(target, STM32_OB_WRP1, stm32x_info->option_bytes.protection[1]);
314 if (retval != ERROR_OK)
315 return retval;
316
317 retval = stm32x_wait_status_busy(bank, 10);
318 if (retval != ERROR_OK)
319 return retval;
320
321 /* write protection byte 3 */
322 retval = target_write_u16(target, STM32_OB_WRP2, stm32x_info->option_bytes.protection[2]);
323 if (retval != ERROR_OK)
324 return retval;
325
326 retval = stm32x_wait_status_busy(bank, 10);
327 if (retval != ERROR_OK)
328 return retval;
329
330 /* write protection byte 4 */
331 retval = target_write_u16(target, STM32_OB_WRP3, stm32x_info->option_bytes.protection[3]);
332 if (retval != ERROR_OK)
333 return retval;
334
335 retval = stm32x_wait_status_busy(bank, 10);
336 if (retval != ERROR_OK)
337 return retval;
338
339 /* write readout protection bit */
340 retval = target_write_u16(target, STM32_OB_RDP, stm32x_info->option_bytes.RDP);
341 if (retval != ERROR_OK)
342 return retval;
343
344 retval = stm32x_wait_status_busy(bank, 10);
345 if (retval != ERROR_OK)
346 return retval;
347
348 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
349 if (retval != ERROR_OK)
350 return retval;
351
352 return ERROR_OK;
353 }
354
355 static int stm32x_protect_check(struct flash_bank *bank)
356 {
357 struct target *target = bank->target;
358 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
359
360 uint32_t protection;
361 int i, s;
362 int num_bits;
363 int set;
364
365 if (target->state != TARGET_HALTED)
366 {
367 LOG_ERROR("Target not halted");
368 return ERROR_TARGET_NOT_HALTED;
369 }
370
371 /* medium density - each bit refers to a 4bank protection
372 * high density - each bit refers to a 2bank protection */
373 int retval = target_read_u32(target, STM32_FLASH_WRPR, &protection);
374 if (retval != ERROR_OK)
375 return retval;
376
377 /* medium density - each protection bit is for 4 * 1K pages
378 * high density - each protection bit is for 2 * 2K pages */
379 num_bits = (bank->num_sectors / stm32x_info->ppage_size);
380
381 if (stm32x_info->ppage_size == 2)
382 {
383 /* high density flash/connectivity line protection */
384
385 set = 1;
386
387 if (protection & (1 << 31))
388 set = 0;
389
390 /* bit 31 controls sector 62 - 255 protection for high density
391 * bit 31 controls sector 62 - 127 protection for connectivity line */
392 for (s = 62; s < bank->num_sectors; s++)
393 {
394 bank->sectors[s].is_protected = set;
395 }
396
397 if (bank->num_sectors > 61)
398 num_bits = 31;
399
400 for (i = 0; i < num_bits; i++)
401 {
402 set = 1;
403
404 if (protection & (1 << i))
405 set = 0;
406
407 for (s = 0; s < stm32x_info->ppage_size; s++)
408 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
409 }
410 }
411 else
412 {
413 /* low/medium density flash protection */
414 for (i = 0; i < num_bits; i++)
415 {
416 set = 1;
417
418 if (protection & (1 << i))
419 set = 0;
420
421 for (s = 0; s < stm32x_info->ppage_size; s++)
422 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
423 }
424 }
425
426 return ERROR_OK;
427 }
428
429 static int stm32x_erase(struct flash_bank *bank, int first, int last)
430 {
431 struct target *target = bank->target;
432 int i;
433
434 if (bank->target->state != TARGET_HALTED)
435 {
436 LOG_ERROR("Target not halted");
437 return ERROR_TARGET_NOT_HALTED;
438 }
439
440 if ((first == 0) && (last == (bank->num_sectors - 1)))
441 {
442 return stm32x_mass_erase(bank);
443 }
444
445 /* unlock flash registers */
446 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
447 if (retval != ERROR_OK)
448 return retval;
449 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
450 if (retval != ERROR_OK)
451 return retval;
452
453 for (i = first; i <= last; i++)
454 {
455 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER);
456 if (retval != ERROR_OK)
457 return retval;
458 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_AR),
459 bank->base + bank->sectors[i].offset);
460 if (retval != ERROR_OK)
461 return retval;
462 retval = target_write_u32(target,
463 stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER | FLASH_STRT);
464 if (retval != ERROR_OK)
465 return retval;
466
467 retval = stm32x_wait_status_busy(bank, 100);
468 if (retval != ERROR_OK)
469 return retval;
470
471 bank->sectors[i].is_erased = 1;
472 }
473
474 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
475 if (retval != ERROR_OK)
476 return retval;
477
478 return ERROR_OK;
479 }
480
481 static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
482 {
483 struct stm32x_flash_bank *stm32x_info = NULL;
484 struct target *target = bank->target;
485 uint16_t prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
486 int i, reg, bit;
487 int status;
488 uint32_t protection;
489
490 stm32x_info = bank->driver_priv;
491
492 if (target->state != TARGET_HALTED)
493 {
494 LOG_ERROR("Target not halted");
495 return ERROR_TARGET_NOT_HALTED;
496 }
497
498 if ((first % stm32x_info->ppage_size) != 0)
499 {
500 LOG_WARNING("aligned start protect sector to a %d sector boundary",
501 stm32x_info->ppage_size);
502 first = first - (first % stm32x_info->ppage_size);
503 }
504 if (((last + 1) % stm32x_info->ppage_size) != 0)
505 {
506 LOG_WARNING("aligned end protect sector to a %d sector boundary",
507 stm32x_info->ppage_size);
508 last++;
509 last = last - (last % stm32x_info->ppage_size);
510 last--;
511 }
512
513 /* medium density - each bit refers to a 4bank protection
514 * high density - each bit refers to a 2bank protection */
515 int retval = target_read_u32(target, STM32_FLASH_WRPR, &protection);
516 if (retval != ERROR_OK)
517 return retval;
518
519 prot_reg[0] = (uint16_t)protection;
520 prot_reg[1] = (uint16_t)(protection >> 8);
521 prot_reg[2] = (uint16_t)(protection >> 16);
522 prot_reg[3] = (uint16_t)(protection >> 24);
523
524 if (stm32x_info->ppage_size == 2)
525 {
526 /* high density flash */
527
528 /* bit 7 controls sector 62 - 255 protection */
529 if (last > 61)
530 {
531 if (set)
532 prot_reg[3] &= ~(1 << 7);
533 else
534 prot_reg[3] |= (1 << 7);
535 }
536
537 if (first > 61)
538 first = 62;
539 if (last > 61)
540 last = 61;
541
542 for (i = first; i <= last; i++)
543 {
544 reg = (i / stm32x_info->ppage_size) / 8;
545 bit = (i / stm32x_info->ppage_size) - (reg * 8);
546
547 if (set)
548 prot_reg[reg] &= ~(1 << bit);
549 else
550 prot_reg[reg] |= (1 << bit);
551 }
552 }
553 else
554 {
555 /* medium density flash */
556 for (i = first; i <= last; i++)
557 {
558 reg = (i / stm32x_info->ppage_size) / 8;
559 bit = (i / stm32x_info->ppage_size) - (reg * 8);
560
561 if (set)
562 prot_reg[reg] &= ~(1 << bit);
563 else
564 prot_reg[reg] |= (1 << bit);
565 }
566 }
567
568 if ((status = stm32x_erase_options(bank)) != ERROR_OK)
569 return status;
570
571 stm32x_info->option_bytes.protection[0] = prot_reg[0];
572 stm32x_info->option_bytes.protection[1] = prot_reg[1];
573 stm32x_info->option_bytes.protection[2] = prot_reg[2];
574 stm32x_info->option_bytes.protection[3] = prot_reg[3];
575
576 return stm32x_write_options(bank);
577 }
578
579 static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
580 uint32_t offset, uint32_t count)
581 {
582 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
583 struct target *target = bank->target;
584 uint32_t buffer_size = 16384;
585 struct working_area *source;
586 uint32_t address = bank->base + offset;
587 struct reg_param reg_params[4];
588 struct armv7m_algorithm armv7m_info;
589 int retval = ERROR_OK;
590
591 /* see contib/loaders/flash/stm32x.s for src */
592
593 static const uint8_t stm32x_flash_write_code[] = {
594 /* #define STM32_FLASH_CR_OFFSET 0x10 */
595 /* #define STM32_FLASH_SR_OFFSET 0x0C */
596 /* write: */
597 0x08, 0x4c, /* ldr r4, STM32_FLASH_BASE */
598 0x1c, 0x44, /* add r4, r3 */
599 /* write_half_word: */
600 0x01, 0x23, /* movs r3, #0x01 */
601 0x23, 0x61, /* str r3, [r4, #STM32_FLASH_CR_OFFSET] */
602 0x30, 0xf8, 0x02, 0x3b, /* ldrh r3, [r0], #0x02 */
603 0x21, 0xf8, 0x02, 0x3b, /* strh r3, [r1], #0x02 */
604 /* busy: */
605 0xe3, 0x68, /* ldr r3, [r4, #STM32_FLASH_SR_OFFSET] */
606 0x13, 0xf0, 0x01, 0x0f, /* tst r3, #0x01 */
607 0xfb, 0xd0, /* beq busy */
608 0x13, 0xf0, 0x14, 0x0f, /* tst r3, #0x14 */
609 0x01, 0xd1, /* bne exit */
610 0x01, 0x3a, /* subs r2, r2, #0x01 */
611 0xf0, 0xd1, /* bne write_half_word */
612 /* exit: */
613 0x00, 0xbe, /* bkpt #0x00 */
614 0x00, 0x20, 0x02, 0x40, /* STM32_FLASH_BASE: .word 0x40022000 */
615 };
616
617 /* flash write code */
618 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
619 &stm32x_info->write_algorithm) != ERROR_OK)
620 {
621 LOG_WARNING("no working area available, can't do block memory writes");
622 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
623 };
624
625 if ((retval = target_write_buffer(target, stm32x_info->write_algorithm->address,
626 sizeof(stm32x_flash_write_code),
627 (uint8_t*)stm32x_flash_write_code)) != ERROR_OK)
628 return retval;
629
630 /* memory buffer */
631 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
632 {
633 buffer_size /= 2;
634 if (buffer_size <= 256)
635 {
636 /* if we already allocated the writing code, but failed to get a
637 * buffer, free the algorithm */
638 if (stm32x_info->write_algorithm)
639 target_free_working_area(target, stm32x_info->write_algorithm);
640
641 LOG_WARNING("no large enough working area available, can't do block memory writes");
642 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
643 }
644 };
645
646 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
647 armv7m_info.core_mode = ARMV7M_MODE_ANY;
648
649 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
650 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
651 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
652 init_reg_param(&reg_params[3], "r3", 32, PARAM_IN_OUT);
653
654 while (count > 0)
655 {
656 uint32_t thisrun_count = (count > (buffer_size / 2)) ?
657 (buffer_size / 2) : count;
658
659 if ((retval = target_write_buffer(target, source->address,
660 thisrun_count * 2, buffer)) != ERROR_OK)
661 break;
662
663 buf_set_u32(reg_params[0].value, 0, 32, source->address);
664 buf_set_u32(reg_params[1].value, 0, 32, address);
665 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
666 buf_set_u32(reg_params[3].value, 0, 32, stm32x_info->register_offset);
667
668 if ((retval = target_run_algorithm(target, 0, NULL, 4, reg_params,
669 stm32x_info->write_algorithm->address,
670 0,
671 10000, &armv7m_info)) != ERROR_OK)
672 {
673 LOG_ERROR("error executing stm32x flash write algorithm");
674 break;
675 }
676
677 if (buf_get_u32(reg_params[3].value, 0, 32) & FLASH_PGERR)
678 {
679 LOG_ERROR("flash memory not erased before writing");
680 /* Clear but report errors */
681 target_write_u32(target, STM32_FLASH_SR, FLASH_PGERR);
682 retval = ERROR_FAIL;
683 break;
684 }
685
686 if (buf_get_u32(reg_params[3].value, 0, 32) & FLASH_WRPRTERR)
687 {
688 LOG_ERROR("flash memory write protected");
689 /* Clear but report errors */
690 target_write_u32(target, STM32_FLASH_SR, FLASH_WRPRTERR);
691 retval = ERROR_FAIL;
692 break;
693 }
694
695 buffer += thisrun_count * 2;
696 address += thisrun_count * 2;
697 count -= thisrun_count;
698 }
699
700 target_free_working_area(target, source);
701 target_free_working_area(target, stm32x_info->write_algorithm);
702
703 destroy_reg_param(&reg_params[0]);
704 destroy_reg_param(&reg_params[1]);
705 destroy_reg_param(&reg_params[2]);
706 destroy_reg_param(&reg_params[3]);
707
708 return retval;
709 }
710
711 static int stm32x_write(struct flash_bank *bank, uint8_t *buffer,
712 uint32_t offset, uint32_t count)
713 {
714 struct target *target = bank->target;
715 uint32_t words_remaining = (count / 2);
716 uint32_t bytes_remaining = (count & 0x00000001);
717 uint32_t address = bank->base + offset;
718 uint32_t bytes_written = 0;
719 int retval;
720
721 if (bank->target->state != TARGET_HALTED)
722 {
723 LOG_ERROR("Target not halted");
724 return ERROR_TARGET_NOT_HALTED;
725 }
726
727 if (offset & 0x1)
728 {
729 LOG_WARNING("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
730 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
731 }
732
733 /* unlock flash registers */
734 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
735 if (retval != ERROR_OK)
736 return retval;
737 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
738 if (retval != ERROR_OK)
739 return retval;
740
741 /* multiple half words (2-byte) to be programmed? */
742 if (words_remaining > 0)
743 {
744 /* try using a block write */
745 if ((retval = stm32x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
746 {
747 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
748 {
749 /* if block write failed (no sufficient working area),
750 * we use normal (slow) single dword accesses */
751 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
752 }
753 }
754 else
755 {
756 buffer += words_remaining * 2;
757 address += words_remaining * 2;
758 words_remaining = 0;
759 }
760 }
761
762 if ((retval != ERROR_OK) && (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE))
763 return retval;
764
765 while (words_remaining > 0)
766 {
767 uint16_t value;
768 memcpy(&value, buffer + bytes_written, sizeof(uint16_t));
769
770 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
771 if (retval != ERROR_OK)
772 return retval;
773 retval = target_write_u16(target, address, value);
774 if (retval != ERROR_OK)
775 return retval;
776
777 retval = stm32x_wait_status_busy(bank, 5);
778 if (retval != ERROR_OK)
779 return retval;
780
781 bytes_written += 2;
782 words_remaining--;
783 address += 2;
784 }
785
786 if (bytes_remaining)
787 {
788 uint16_t value = 0xffff;
789 memcpy(&value, buffer + bytes_written, bytes_remaining);
790
791 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
792 if (retval != ERROR_OK)
793 return retval;
794 retval = target_write_u16(target, address, value);
795 if (retval != ERROR_OK)
796 return retval;
797
798 retval = stm32x_wait_status_busy(bank, 5);
799 if (retval != ERROR_OK)
800 return retval;
801 }
802
803 return target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
804 }
805
806 static int stm32x_probe(struct flash_bank *bank)
807 {
808 struct target *target = bank->target;
809 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
810 int i;
811 uint16_t num_pages;
812 uint32_t device_id;
813 int page_size;
814
815 stm32x_info->probed = 0;
816 stm32x_info->register_offset = 0x00;
817
818 /* read stm32 device id register */
819 int retval = target_read_u32(target, 0xE0042000, &device_id);
820 if (retval != ERROR_OK)
821 return retval;
822 LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
823
824 /* get flash size from target. */
825 retval = target_read_u16(target, 0x1FFFF7E0, &num_pages);
826 if (retval != ERROR_OK)
827 {
828 LOG_WARNING("failed reading flash size, default to max target family");
829 /* failed reading flash size, default to max target family */
830 num_pages = 0xffff;
831 }
832
833 if ((device_id & 0x7ff) == 0x410)
834 {
835 /* medium density - we have 1k pages
836 * 4 pages for a protection area */
837 page_size = 1024;
838 stm32x_info->ppage_size = 4;
839
840 /* check for early silicon */
841 if (num_pages == 0xffff)
842 {
843 /* number of sectors incorrect on revA */
844 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
845 num_pages = 128;
846 }
847 }
848 else if ((device_id & 0x7ff) == 0x412)
849 {
850 /* low density - we have 1k pages
851 * 4 pages for a protection area */
852 page_size = 1024;
853 stm32x_info->ppage_size = 4;
854
855 /* check for early silicon */
856 if (num_pages == 0xffff)
857 {
858 /* number of sectors incorrect on revA */
859 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 32k flash");
860 num_pages = 32;
861 }
862 }
863 else if ((device_id & 0x7ff) == 0x414)
864 {
865 /* high density - we have 2k pages
866 * 2 pages for a protection area */
867 page_size = 2048;
868 stm32x_info->ppage_size = 2;
869
870 /* check for early silicon */
871 if (num_pages == 0xffff)
872 {
873 /* number of sectors incorrect on revZ */
874 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 512k flash");
875 num_pages = 512;
876 }
877 }
878 else if ((device_id & 0x7ff) == 0x418)
879 {
880 /* connectivity line density - we have 2k pages
881 * 2 pages for a protection area */
882 page_size = 2048;
883 stm32x_info->ppage_size = 2;
884
885 /* check for early silicon */
886 if (num_pages == 0xffff)
887 {
888 /* number of sectors incorrect on revZ */
889 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 256k flash");
890 num_pages = 256;
891 }
892 }
893 else if ((device_id & 0x7ff) == 0x420)
894 {
895 /* value line density - we have 1k pages
896 * 4 pages for a protection area */
897 page_size = 1024;
898 stm32x_info->ppage_size = 4;
899
900 /* check for early silicon */
901 if (num_pages == 0xffff)
902 {
903 /* number of sectors may be incorrrect on early silicon */
904 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
905 num_pages = 128;
906 }
907 }
908 else if ((device_id & 0x7ff) == 0x430)
909 {
910 /* xl line density - we have 2k pages
911 * 2 pages for a protection area */
912 page_size = 2048;
913 stm32x_info->ppage_size = 2;
914
915 /* check for early silicon */
916 if (num_pages == 0xffff)
917 {
918 /* number of sectors may be incorrrect on early silicon */
919 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 1024k flash");
920 num_pages = 1024;
921 }
922
923 /* split reported size into matching bank */
924 if (bank->base != 0x08080000)
925 {
926 /* bank 0 will be fixed 512k */
927 num_pages = 512;
928 }
929 else
930 {
931 num_pages -= 512;
932 /* bank1 also uses a register offset */
933 stm32x_info->register_offset = 0x40;
934 }
935 }
936 else
937 {
938 LOG_WARNING("Cannot identify target as a STM32 family.");
939 return ERROR_FAIL;
940 }
941
942 LOG_INFO("flash size = %dkbytes", num_pages);
943
944 /* calculate numbers of pages */
945 num_pages /= (page_size / 1024);
946
947 if (bank->sectors)
948 {
949 free(bank->sectors);
950 bank->sectors = NULL;
951 }
952
953 bank->size = (num_pages * page_size);
954 bank->num_sectors = num_pages;
955 bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
956
957 for (i = 0; i < num_pages; i++)
958 {
959 bank->sectors[i].offset = i * page_size;
960 bank->sectors[i].size = page_size;
961 bank->sectors[i].is_erased = -1;
962 bank->sectors[i].is_protected = 1;
963 }
964
965 stm32x_info->probed = 1;
966
967 return ERROR_OK;
968 }
969
970 static int stm32x_auto_probe(struct flash_bank *bank)
971 {
972 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
973 if (stm32x_info->probed)
974 return ERROR_OK;
975 return stm32x_probe(bank);
976 }
977
978 #if 0
979 COMMAND_HANDLER(stm32x_handle_part_id_command)
980 {
981 return ERROR_OK;
982 }
983 #endif
984
985 static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
986 {
987 struct target *target = bank->target;
988 uint32_t device_id;
989 int printed;
990
991 /* read stm32 device id register */
992 int retval = target_read_u32(target, 0xE0042000, &device_id);
993 if (retval != ERROR_OK)
994 return retval;
995
996 if ((device_id & 0x7ff) == 0x410)
997 {
998 printed = snprintf(buf, buf_size, "stm32x (Medium Density) - Rev: ");
999 buf += printed;
1000 buf_size -= printed;
1001
1002 switch (device_id >> 16)
1003 {
1004 case 0x0000:
1005 snprintf(buf, buf_size, "A");
1006 break;
1007
1008 case 0x2000:
1009 snprintf(buf, buf_size, "B");
1010 break;
1011
1012 case 0x2001:
1013 snprintf(buf, buf_size, "Z");
1014 break;
1015
1016 case 0x2003:
1017 snprintf(buf, buf_size, "Y");
1018 break;
1019
1020 default:
1021 snprintf(buf, buf_size, "unknown");
1022 break;
1023 }
1024 }
1025 else if ((device_id & 0x7ff) == 0x412)
1026 {
1027 printed = snprintf(buf, buf_size, "stm32x (Low Density) - Rev: ");
1028 buf += printed;
1029 buf_size -= printed;
1030
1031 switch (device_id >> 16)
1032 {
1033 case 0x1000:
1034 snprintf(buf, buf_size, "A");
1035 break;
1036
1037 default:
1038 snprintf(buf, buf_size, "unknown");
1039 break;
1040 }
1041 }
1042 else if ((device_id & 0x7ff) == 0x414)
1043 {
1044 printed = snprintf(buf, buf_size, "stm32x (High Density) - Rev: ");
1045 buf += printed;
1046 buf_size -= printed;
1047
1048 switch (device_id >> 16)
1049 {
1050 case 0x1000:
1051 snprintf(buf, buf_size, "A");
1052 break;
1053
1054 case 0x1001:
1055 snprintf(buf, buf_size, "Z");
1056 break;
1057
1058 default:
1059 snprintf(buf, buf_size, "unknown");
1060 break;
1061 }
1062 }
1063 else if ((device_id & 0x7ff) == 0x418)
1064 {
1065 printed = snprintf(buf, buf_size, "stm32x (Connectivity) - Rev: ");
1066 buf += printed;
1067 buf_size -= printed;
1068
1069 switch (device_id >> 16)
1070 {
1071 case 0x1000:
1072 snprintf(buf, buf_size, "A");
1073 break;
1074
1075 case 0x1001:
1076 snprintf(buf, buf_size, "Z");
1077 break;
1078
1079 default:
1080 snprintf(buf, buf_size, "unknown");
1081 break;
1082 }
1083 }
1084 else if ((device_id & 0x7ff) == 0x420)
1085 {
1086 printed = snprintf(buf, buf_size, "stm32x (Value) - Rev: ");
1087 buf += printed;
1088 buf_size -= printed;
1089
1090 switch (device_id >> 16)
1091 {
1092 case 0x1000:
1093 snprintf(buf, buf_size, "A");
1094 break;
1095
1096 case 0x1001:
1097 snprintf(buf, buf_size, "Z");
1098 break;
1099
1100 default:
1101 snprintf(buf, buf_size, "unknown");
1102 break;
1103 }
1104 }
1105 else if ((device_id & 0x7ff) == 0x430)
1106 {
1107 printed = snprintf(buf, buf_size, "stm32x (XL) - Rev: ");
1108 buf += printed;
1109 buf_size -= printed;
1110
1111 switch (device_id >> 16)
1112 {
1113 case 0x1000:
1114 snprintf(buf, buf_size, "A");
1115 break;
1116
1117 default:
1118 snprintf(buf, buf_size, "unknown");
1119 break;
1120 }
1121 }
1122 else
1123 {
1124 snprintf(buf, buf_size, "Cannot identify target as a stm32x\n");
1125 return ERROR_FAIL;
1126 }
1127
1128 return ERROR_OK;
1129 }
1130
1131 COMMAND_HANDLER(stm32x_handle_lock_command)
1132 {
1133 struct target *target = NULL;
1134 struct stm32x_flash_bank *stm32x_info = NULL;
1135
1136 if (CMD_ARGC < 1)
1137 {
1138 command_print(CMD_CTX, "stm32x lock <bank>");
1139 return ERROR_OK;
1140 }
1141
1142 struct flash_bank *bank;
1143 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1144 if (ERROR_OK != retval)
1145 return retval;
1146
1147 stm32x_info = bank->driver_priv;
1148
1149 target = bank->target;
1150
1151 if (target->state != TARGET_HALTED)
1152 {
1153 LOG_ERROR("Target not halted");
1154 return ERROR_TARGET_NOT_HALTED;
1155 }
1156
1157 if (stm32x_erase_options(bank) != ERROR_OK)
1158 {
1159 command_print(CMD_CTX, "stm32x failed to erase options");
1160 return ERROR_OK;
1161 }
1162
1163 /* set readout protection */
1164 stm32x_info->option_bytes.RDP = 0;
1165
1166 if (stm32x_write_options(bank) != ERROR_OK)
1167 {
1168 command_print(CMD_CTX, "stm32x failed to lock device");
1169 return ERROR_OK;
1170 }
1171
1172 command_print(CMD_CTX, "stm32x locked");
1173
1174 return ERROR_OK;
1175 }
1176
1177 COMMAND_HANDLER(stm32x_handle_unlock_command)
1178 {
1179 struct target *target = NULL;
1180 struct stm32x_flash_bank *stm32x_info = NULL;
1181
1182 if (CMD_ARGC < 1)
1183 {
1184 command_print(CMD_CTX, "stm32x unlock <bank>");
1185 return ERROR_OK;
1186 }
1187
1188 struct flash_bank *bank;
1189 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1190 if (ERROR_OK != retval)
1191 return retval;
1192
1193 stm32x_info = bank->driver_priv;
1194
1195 target = bank->target;
1196
1197 if (target->state != TARGET_HALTED)
1198 {
1199 LOG_ERROR("Target not halted");
1200 return ERROR_TARGET_NOT_HALTED;
1201 }
1202
1203 if (stm32x_erase_options(bank) != ERROR_OK)
1204 {
1205 command_print(CMD_CTX, "stm32x failed to unlock device");
1206 return ERROR_OK;
1207 }
1208
1209 if (stm32x_write_options(bank) != ERROR_OK)
1210 {
1211 command_print(CMD_CTX, "stm32x failed to lock device");
1212 return ERROR_OK;
1213 }
1214
1215 command_print(CMD_CTX, "stm32x unlocked.\n"
1216 "INFO: a reset or power cycle is required "
1217 "for the new settings to take effect.");
1218
1219 return ERROR_OK;
1220 }
1221
1222 COMMAND_HANDLER(stm32x_handle_options_read_command)
1223 {
1224 uint32_t optionbyte;
1225 struct target *target = NULL;
1226 struct stm32x_flash_bank *stm32x_info = NULL;
1227
1228 if (CMD_ARGC < 1)
1229 {
1230 command_print(CMD_CTX, "stm32x options_read <bank>");
1231 return ERROR_OK;
1232 }
1233
1234 struct flash_bank *bank;
1235 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1236 if (ERROR_OK != retval)
1237 return retval;
1238
1239 stm32x_info = bank->driver_priv;
1240
1241 target = bank->target;
1242
1243 if (target->state != TARGET_HALTED)
1244 {
1245 LOG_ERROR("Target not halted");
1246 return ERROR_TARGET_NOT_HALTED;
1247 }
1248
1249 retval = target_read_u32(target, STM32_FLASH_OBR, &optionbyte);
1250 if (retval != ERROR_OK)
1251 return retval;
1252 command_print(CMD_CTX, "Option Byte: 0x%" PRIx32 "", optionbyte);
1253
1254 if (buf_get_u32((uint8_t*)&optionbyte, OPT_ERROR, 1))
1255 command_print(CMD_CTX, "Option Byte Complement Error");
1256
1257 if (buf_get_u32((uint8_t*)&optionbyte, OPT_READOUT, 1))
1258 command_print(CMD_CTX, "Readout Protection On");
1259 else
1260 command_print(CMD_CTX, "Readout Protection Off");
1261
1262 if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDWDGSW, 1))
1263 command_print(CMD_CTX, "Software Watchdog");
1264 else
1265 command_print(CMD_CTX, "Hardware Watchdog");
1266
1267 if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDRSTSTOP, 1))
1268 command_print(CMD_CTX, "Stop: No reset generated");
1269 else
1270 command_print(CMD_CTX, "Stop: Reset generated");
1271
1272 if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDRSTSTDBY, 1))
1273 command_print(CMD_CTX, "Standby: No reset generated");
1274 else
1275 command_print(CMD_CTX, "Standby: Reset generated");
1276
1277 return ERROR_OK;
1278 }
1279
1280 COMMAND_HANDLER(stm32x_handle_options_write_command)
1281 {
1282 struct target *target = NULL;
1283 struct stm32x_flash_bank *stm32x_info = NULL;
1284 uint16_t optionbyte = 0xF8;
1285
1286 if (CMD_ARGC < 4)
1287 {
1288 command_print(CMD_CTX, "stm32x options_write <bank> <SWWDG | HWWDG> <RSTSTNDBY | NORSTSTNDBY> <RSTSTOP | NORSTSTOP>");
1289 return ERROR_OK;
1290 }
1291
1292 struct flash_bank *bank;
1293 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1294 if (ERROR_OK != retval)
1295 return retval;
1296
1297 stm32x_info = bank->driver_priv;
1298
1299 target = bank->target;
1300
1301 if (target->state != TARGET_HALTED)
1302 {
1303 LOG_ERROR("Target not halted");
1304 return ERROR_TARGET_NOT_HALTED;
1305 }
1306
1307 /* REVISIT: ignores some options which we will display...
1308 * and doesn't insist on the specified syntax.
1309 */
1310
1311 /* OPT_RDWDGSW */
1312 if (strcmp(CMD_ARGV[1], "SWWDG") == 0)
1313 {
1314 optionbyte |= (1 << 0);
1315 }
1316 else /* REVISIT must be "HWWDG" then ... */
1317 {
1318 optionbyte &= ~(1 << 0);
1319 }
1320
1321 /* OPT_RDRSTSTDBY */
1322 if (strcmp(CMD_ARGV[2], "NORSTSTNDBY") == 0)
1323 {
1324 optionbyte |= (1 << 1);
1325 }
1326 else /* REVISIT must be "RSTSTNDBY" then ... */
1327 {
1328 optionbyte &= ~(1 << 1);
1329 }
1330
1331 /* OPT_RDRSTSTOP */
1332 if (strcmp(CMD_ARGV[3], "NORSTSTOP") == 0)
1333 {
1334 optionbyte |= (1 << 2);
1335 }
1336 else /* REVISIT must be "RSTSTOP" then ... */
1337 {
1338 optionbyte &= ~(1 << 2);
1339 }
1340
1341 if (stm32x_erase_options(bank) != ERROR_OK)
1342 {
1343 command_print(CMD_CTX, "stm32x failed to erase options");
1344 return ERROR_OK;
1345 }
1346
1347 stm32x_info->option_bytes.user_options = optionbyte;
1348
1349 if (stm32x_write_options(bank) != ERROR_OK)
1350 {
1351 command_print(CMD_CTX, "stm32x failed to write options");
1352 return ERROR_OK;
1353 }
1354
1355 command_print(CMD_CTX, "stm32x write options complete.\n"
1356 "INFO: a reset or power cycle is required "
1357 "for the new settings to take effect.");
1358
1359 return ERROR_OK;
1360 }
1361
1362 static int stm32x_mass_erase(struct flash_bank *bank)
1363 {
1364 struct target *target = bank->target;
1365
1366 if (target->state != TARGET_HALTED)
1367 {
1368 LOG_ERROR("Target not halted");
1369 return ERROR_TARGET_NOT_HALTED;
1370 }
1371
1372 /* unlock option flash registers */
1373 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1374 if (retval != ERROR_OK)
1375 return retval;
1376 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1377 if (retval != ERROR_OK)
1378 return retval;
1379
1380 /* mass erase flash memory */
1381 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
1382 if (retval != ERROR_OK)
1383 return retval;
1384 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER | FLASH_STRT);
1385 if (retval != ERROR_OK)
1386 return retval;
1387
1388 retval = stm32x_wait_status_busy(bank, 100);
1389 if (retval != ERROR_OK)
1390 return retval;
1391
1392 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
1393 if (retval != ERROR_OK)
1394 return retval;
1395
1396 return ERROR_OK;
1397 }
1398
1399 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1400 {
1401 int i;
1402
1403 if (CMD_ARGC < 1)
1404 {
1405 command_print(CMD_CTX, "stm32x mass_erase <bank>");
1406 return ERROR_OK;
1407 }
1408
1409 struct flash_bank *bank;
1410 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1411 if (ERROR_OK != retval)
1412 return retval;
1413
1414 retval = stm32x_mass_erase(bank);
1415 if (retval == ERROR_OK)
1416 {
1417 /* set all sectors as erased */
1418 for (i = 0; i < bank->num_sectors; i++)
1419 {
1420 bank->sectors[i].is_erased = 1;
1421 }
1422
1423 command_print(CMD_CTX, "stm32x mass erase complete");
1424 }
1425 else
1426 {
1427 command_print(CMD_CTX, "stm32x mass erase failed");
1428 }
1429
1430 return retval;
1431 }
1432
1433 static const struct command_registration stm32x_exec_command_handlers[] = {
1434 {
1435 .name = "lock",
1436 .handler = stm32x_handle_lock_command,
1437 .mode = COMMAND_EXEC,
1438 .usage = "bank_id",
1439 .help = "Lock entire flash device.",
1440 },
1441 {
1442 .name = "unlock",
1443 .handler = stm32x_handle_unlock_command,
1444 .mode = COMMAND_EXEC,
1445 .usage = "bank_id",
1446 .help = "Unlock entire protected flash device.",
1447 },
1448 {
1449 .name = "mass_erase",
1450 .handler = stm32x_handle_mass_erase_command,
1451 .mode = COMMAND_EXEC,
1452 .usage = "bank_id",
1453 .help = "Erase entire flash device.",
1454 },
1455 {
1456 .name = "options_read",
1457 .handler = stm32x_handle_options_read_command,
1458 .mode = COMMAND_EXEC,
1459 .usage = "bank_id",
1460 .help = "Read and display device option byte.",
1461 },
1462 {
1463 .name = "options_write",
1464 .handler = stm32x_handle_options_write_command,
1465 .mode = COMMAND_EXEC,
1466 .usage = "bank_id ('SWWDG'|'HWWDG') "
1467 "('RSTSTNDBY'|'NORSTSTNDBY') "
1468 "('RSTSTOP'|'NORSTSTOP')",
1469 .help = "Replace bits in device option byte.",
1470 },
1471 COMMAND_REGISTRATION_DONE
1472 };
1473
1474 static const struct command_registration stm32x_command_handlers[] = {
1475 {
1476 .name = "stm32x",
1477 .mode = COMMAND_ANY,
1478 .help = "stm32x flash command group",
1479 .chain = stm32x_exec_command_handlers,
1480 },
1481 COMMAND_REGISTRATION_DONE
1482 };
1483
1484 struct flash_driver stm32x_flash = {
1485 .name = "stm32x",
1486 .commands = stm32x_command_handlers,
1487 .flash_bank_command = stm32x_flash_bank_command,
1488 .erase = stm32x_erase,
1489 .protect = stm32x_protect,
1490 .write = stm32x_write,
1491 .read = default_flash_read,
1492 .probe = stm32x_probe,
1493 .auto_probe = stm32x_auto_probe,
1494 .erase_check = default_flash_mem_blank_check,
1495 .protect_check = stm32x_protect_check,
1496 .info = get_stm32x_info,
1497 };
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