1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2011 by Clement Burin des Roziers *
9 * clement.burin-des-roziers@hikob.com *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
32 #include <helper/binarybuffer.h>
33 #include <target/algorithm.h>
34 #include <target/armv7m.h>
36 /* stm32lx flash register locations */
38 #define FLASH_BASE 0x40023C00
39 #define FLASH_ACR 0x40023C00
40 #define FLASH_PECR 0x40023C04
41 #define FLASH_PDKEYR 0x40023C08
42 #define FLASH_PEKEYR 0x40023C0C
43 #define FLASH_PRGKEYR 0x40023C10
44 #define FLASH_OPTKEYR 0x40023C14
45 #define FLASH_SR 0x40023C18
46 #define FLASH_OBR 0x40023C1C
47 #define FLASH_WRPR 0x40023C20
50 #define FLASH_ACR__LATENCY (1<<0)
51 #define FLASH_ACR__PRFTEN (1<<1)
52 #define FLASH_ACR__ACC64 (1<<2)
53 #define FLASH_ACR__SLEEP_PD (1<<3)
54 #define FLASH_ACR__RUN_PD (1<<4)
57 #define FLASH_PECR__PELOCK (1<<0)
58 #define FLASH_PECR__PRGLOCK (1<<1)
59 #define FLASH_PECR__OPTLOCK (1<<2)
60 #define FLASH_PECR__PROG (1<<3)
61 #define FLASH_PECR__DATA (1<<4)
62 #define FLASH_PECR__FTDW (1<<8)
63 #define FLASH_PECR__ERASE (1<<9)
64 #define FLASH_PECR__FPRG (1<<10)
65 #define FLASH_PECR__EOPIE (1<<16)
66 #define FLASH_PECR__ERRIE (1<<17)
67 #define FLASH_PECR__OBL_LAUNCH (1<<18)
70 #define FLASH_SR__BSY (1<<0)
71 #define FLASH_SR__EOP (1<<1)
72 #define FLASH_SR__ENDHV (1<<2)
73 #define FLASH_SR__READY (1<<3)
74 #define FLASH_SR__WRPERR (1<<8)
75 #define FLASH_SR__PGAERR (1<<9)
76 #define FLASH_SR__SIZERR (1<<10)
77 #define FLASH_SR__OPTVERR (1<<11)
80 #define PEKEY1 0x89ABCDEF
81 #define PEKEY2 0x02030405
82 #define PRGKEY1 0x8C9DAEBF
83 #define PRGKEY2 0x13141516
84 #define OPTKEY1 0xFBEAD9C8
85 #define OPTKEY2 0x24252627
88 #define DBGMCU_IDCODE 0xE0042000
89 #define F_SIZE 0x1FF8004C
92 #define FLASH_PAGE_SIZE 256
93 #define FLASH_SECTOR_SIZE 4096
94 #define FLASH_PAGES_PER_SECTOR 16
95 #define FLASH_BANK0_ADDRESS 0x08000000
97 /* stm32lx option byte register location */
98 #define OB_RDP 0x1FF80000
99 #define OB_USER 0x1FF80004
100 #define OB_WRP0_1 0x1FF80008
101 #define OB_WRP2_3 0x1FF8000C
104 #define OB_RDP__LEVEL0 0xFF5500AA
105 #define OB_RDP__LEVEL1 0xFFFF0000
107 /* stm32lx RCC register locations */
108 #define RCC_CR 0x40023800
109 #define RCC_ICSCR 0x40023804
110 #define RCC_CFGR 0x40023808
113 #define RCC_ICSCR__MSIRANGE_MASK (7<<13)
115 static int stm32lx_unlock_program_memory(struct flash_bank
*bank
);
116 static int stm32lx_lock_program_memory(struct flash_bank
*bank
);
117 static int stm32lx_enable_write_half_page(struct flash_bank
*bank
);
118 static int stm32lx_erase_sector(struct flash_bank
*bank
, int sector
);
119 static int stm32lx_wait_until_bsy_clear(struct flash_bank
*bank
);
121 struct stm32lx_flash_bank
{
125 /* flash bank stm32lx <base> <size> 0 0 <target#>
127 FLASH_BANK_COMMAND_HANDLER(stm32lx_flash_bank_command
)
129 struct stm32lx_flash_bank
*stm32lx_info
;
131 return ERROR_COMMAND_SYNTAX_ERROR
;
133 /* Create the bank structure */
134 stm32lx_info
= malloc(sizeof(struct stm32lx_flash_bank
));
136 /* Check allocation */
137 if (stm32lx_info
== NULL
) {
138 LOG_ERROR("failed to allocate bank structure");
142 bank
->driver_priv
= stm32lx_info
;
144 stm32lx_info
->probed
= 0;
149 static int stm32lx_protect_check(struct flash_bank
*bank
)
152 struct target
*target
= bank
->target
;
156 if (target
->state
!= TARGET_HALTED
) {
157 LOG_ERROR("Target not halted");
158 return ERROR_TARGET_NOT_HALTED
;
162 * Read the WRPR word, and check each bit (corresponding to each
165 retval
= target_read_u32(target
, FLASH_WRPR
, &wrpr
);
166 if (retval
!= ERROR_OK
)
169 for (int i
= 0; i
< 32; i
++) {
171 bank
->sectors
[i
].is_protected
= 1;
173 bank
->sectors
[i
].is_protected
= 0;
178 static int stm32lx_erase(struct flash_bank
*bank
, int first
, int last
)
183 * It could be possible to do a mass erase if all sectors must be
184 * erased, but it is not implemented yet.
187 if (bank
->target
->state
!= TARGET_HALTED
) {
188 LOG_ERROR("Target not halted");
189 return ERROR_TARGET_NOT_HALTED
;
193 * Loop over the selected sectors and erase them
195 for (int i
= first
; i
<= last
; i
++) {
196 retval
= stm32lx_erase_sector(bank
, i
);
197 if (retval
!= ERROR_OK
)
199 bank
->sectors
[i
].is_erased
= 1;
204 static int stm32lx_protect(struct flash_bank
*bank
, int set
, int first
,
207 LOG_WARNING("protection of the STM32L flash is not implemented");
211 static int stm32lx_write_half_pages(struct flash_bank
*bank
, uint8_t *buffer
,
212 uint32_t offset
, uint32_t count
)
214 struct target
*target
= bank
->target
;
215 uint32_t buffer_size
= 4096 * 4;
216 struct working_area
*write_algorithm
;
217 struct working_area
*source
;
218 uint32_t address
= bank
->base
+ offset
;
220 struct reg_param reg_params
[5];
221 struct armv7m_algorithm armv7m_info
;
223 int retval
= ERROR_OK
;
226 /* see contib/loaders/flash/stm32lx.s for src */
228 static const uint16_t stm32lx_flash_write_code_16
[] = {
229 /* 00000000 <write_word-0x4>: */
230 0x2300, /* 0: 2300 movs r3, #0 */
231 0xe004, /* 2: e004 b.n e <test_done> */
233 /* 00000004 <write_word>: */
234 0xf851, 0xcb04, /* 4: f851 cb04 ldr.w ip, [r1], #4 */
235 0xf840, 0xcb04, /* 8: f840 cb04 str.w ip, [r0], #4 */
236 0x3301, /* c: 3301 adds r3, #1 */
238 /* 0000000e <test_done>: */
239 0x4293, /* e: 4293 cmp r3, r2 */
240 0xd3f8, /* 10: d3f8 bcc.n 4 <write_word> */
241 0xbe00, /* 12: be00 bkpt 0x0000 */
246 uint8_t stm32lx_flash_write_code
[sizeof(stm32lx_flash_write_code_16
)];
247 for (unsigned int i
= 0; i
< sizeof(stm32lx_flash_write_code_16
) / 2; i
++) {
248 stm32lx_flash_write_code
[i
* 2 + 0] = stm32lx_flash_write_code_16
[i
]
250 stm32lx_flash_write_code
[i
* 2 + 1] = (stm32lx_flash_write_code_16
[i
]
253 /* Check if there is an even number of half pages (128bytes) */
255 LOG_ERROR("there should be an even number "
256 "of half pages = 128 bytes (count = %" PRIi32
" bytes)", count
);
260 /* Allocate working area */
261 reg32
= sizeof(stm32lx_flash_write_code
);
262 /* Add bytes to make 4byte aligned */
263 reg32
+= (4 - (reg32
% 4)) % 4;
264 retval
= target_alloc_working_area(target
, reg32
,
266 if (retval
!= ERROR_OK
)
269 /* Write the flashing code */
270 retval
= target_write_buffer(target
,
271 write_algorithm
->address
,
272 sizeof(stm32lx_flash_write_code
),
273 (uint8_t *)stm32lx_flash_write_code
);
274 if (retval
!= ERROR_OK
) {
275 target_free_working_area(target
, write_algorithm
);
279 /* Allocate half pages memory */
280 while (target_alloc_working_area_try(target
, buffer_size
, &source
)
282 if (buffer_size
> 1024)
287 if (buffer_size
<= 256) {
288 /* we already allocated the writing code, but failed to get a
289 * buffer, free the algorithm */
290 target_free_working_area(target
, write_algorithm
);
292 LOG_WARNING("no large enough working area available, can't do block memory writes");
293 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
296 LOG_DEBUG("allocated working area for data (%" PRIx32
" bytes)", buffer_size
);
298 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
299 armv7m_info
.core_mode
= ARMV7M_MODE_ANY
;
300 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
301 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
302 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
303 init_reg_param(®_params
[3], "r3", 32, PARAM_IN_OUT
);
304 init_reg_param(®_params
[4], "r4", 32, PARAM_OUT
);
306 /* Enable half-page write */
307 retval
= stm32lx_enable_write_half_page(bank
);
308 if (retval
!= ERROR_OK
) {
309 target_free_working_area(target
, source
);
310 target_free_working_area(target
, write_algorithm
);
312 destroy_reg_param(®_params
[0]);
313 destroy_reg_param(®_params
[1]);
314 destroy_reg_param(®_params
[2]);
315 destroy_reg_param(®_params
[3]);
319 /* Loop while there are bytes to write */
322 this_count
= (count
> buffer_size
) ? buffer_size
: count
;
324 /* Write the next half pages */
325 retval
= target_write_buffer(target
, source
->address
, this_count
,
327 if (retval
!= ERROR_OK
)
330 /* 4: Store useful information in the registers */
331 /* the destination address of the copy (R0) */
332 buf_set_u32(reg_params
[0].value
, 0, 32, address
);
333 /* The source address of the copy (R1) */
334 buf_set_u32(reg_params
[1].value
, 0, 32, source
->address
);
335 /* The length of the copy (R2) */
336 buf_set_u32(reg_params
[2].value
, 0, 32, this_count
/ 4);
338 /* 5: Execute the bunch of code */
339 retval
= target_run_algorithm(target
, 0, NULL
, sizeof(reg_params
)
340 / sizeof(*reg_params
), reg_params
,
341 write_algorithm
->address
, 0, 20000, &armv7m_info
);
342 if (retval
!= ERROR_OK
)
345 /* 6: Wait while busy */
346 retval
= stm32lx_wait_until_bsy_clear(bank
);
347 if (retval
!= ERROR_OK
)
350 buffer
+= this_count
;
351 address
+= this_count
;
355 if (retval
== ERROR_OK
)
356 retval
= stm32lx_lock_program_memory(bank
);
358 target_free_working_area(target
, source
);
359 target_free_working_area(target
, write_algorithm
);
361 destroy_reg_param(®_params
[0]);
362 destroy_reg_param(®_params
[1]);
363 destroy_reg_param(®_params
[2]);
364 destroy_reg_param(®_params
[3]);
368 static int stm32lx_write(struct flash_bank
*bank
, uint8_t *buffer
,
369 uint32_t offset
, uint32_t count
)
371 struct target
*target
= bank
->target
;
373 uint32_t halfpages_number
;
374 uint32_t words_remaining
;
375 uint32_t bytes_remaining
;
376 uint32_t address
= bank
->base
+ offset
;
377 uint32_t bytes_written
= 0;
380 if (bank
->target
->state
!= TARGET_HALTED
) {
381 LOG_ERROR("Target not halted");
382 return ERROR_TARGET_NOT_HALTED
;
386 LOG_ERROR("offset 0x%" PRIx32
" breaks required 2-byte alignment", offset
);
387 return ERROR_FLASH_DST_BREAKS_ALIGNMENT
;
390 /* Check if there are some full half pages */
391 if (((offset
% 128) == 0) && (count
>= 128)) {
392 halfpages_number
= count
/ 128;
393 words_remaining
= (count
- 128 * halfpages_number
) / 4;
394 bytes_remaining
= (count
& 0x3);
396 halfpages_number
= 0;
397 words_remaining
= (count
/ 4);
398 bytes_remaining
= (count
& 0x3);
401 if (halfpages_number
) {
402 retval
= stm32lx_write_half_pages(bank
, buffer
, offset
, 128
404 if (retval
!= ERROR_OK
)
408 bytes_written
= 128 * halfpages_number
;
409 address
+= bytes_written
;
411 retval
= stm32lx_unlock_program_memory(bank
);
412 if (retval
!= ERROR_OK
)
415 while (words_remaining
> 0) {
417 uint8_t *p
= buffer
+ bytes_written
;
419 /* Prepare the word, Little endian conversion */
420 value
= p
[0] + (p
[1] << 8) + (p
[2] << 16) + (p
[3] << 24);
422 retval
= target_write_u32(target
, address
, value
);
423 if (retval
!= ERROR_OK
)
430 retval
= stm32lx_wait_until_bsy_clear(bank
);
431 if (retval
!= ERROR_OK
)
435 if (bytes_remaining
) {
436 uint8_t last_word
[4] = {0xff, 0xff, 0xff, 0xff};
438 /* copy the last remaining bytes into the write buffer */
439 memcpy(last_word
, buffer
+bytes_written
, bytes_remaining
);
441 retval
= target_write_buffer(target
, address
, 4, last_word
);
442 if (retval
!= ERROR_OK
)
445 retval
= stm32lx_wait_until_bsy_clear(bank
);
446 if (retval
!= ERROR_OK
)
450 retval
= stm32lx_lock_program_memory(bank
);
451 if (retval
!= ERROR_OK
)
457 static int stm32lx_probe(struct flash_bank
*bank
)
459 struct target
*target
= bank
->target
;
460 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
462 uint16_t flash_size_in_kb
;
463 uint16_t max_flash_size_in_kb
;
466 stm32lx_info
->probed
= 0;
468 /* read stm32 device id register */
469 int retval
= target_read_u32(target
, DBGMCU_IDCODE
, &device_id
);
470 if (retval
!= ERROR_OK
)
473 LOG_DEBUG("device id = 0x%08" PRIx32
"", device_id
);
475 /* set max flash size depending on family */
476 switch (device_id
& 0xfff) {
478 max_flash_size_in_kb
= 128;
481 max_flash_size_in_kb
= 384;
484 LOG_WARNING("Cannot identify target as a STM32L family.");
488 /* get flash size from target. */
489 retval
= target_read_u16(target
, F_SIZE
, &flash_size_in_kb
);
491 /* failed reading flash size or flash size invalid (early silicon),
492 * default to max target family */
493 if (retval
!= ERROR_OK
|| flash_size_in_kb
== 0xffff || flash_size_in_kb
== 0) {
494 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
495 max_flash_size_in_kb
);
496 flash_size_in_kb
= max_flash_size_in_kb
;
499 /* STM32L - we have 32 sectors, 16 pages per sector -> 512 pages
500 * 16 pages for a protection area */
502 /* calculate numbers of sectors (4kB per sector) */
503 int num_sectors
= (flash_size_in_kb
* 1024) / FLASH_SECTOR_SIZE
;
504 LOG_INFO("flash size = %dkbytes", flash_size_in_kb
);
508 bank
->sectors
= NULL
;
511 bank
->base
= FLASH_BANK0_ADDRESS
;
512 bank
->size
= flash_size_in_kb
* 1024;
513 bank
->num_sectors
= num_sectors
;
514 bank
->sectors
= malloc(sizeof(struct flash_sector
) * num_sectors
);
515 if (bank
->sectors
== NULL
) {
516 LOG_ERROR("failed to allocate bank sectors");
520 for (i
= 0; i
< num_sectors
; i
++) {
521 bank
->sectors
[i
].offset
= i
* FLASH_SECTOR_SIZE
;
522 bank
->sectors
[i
].size
= FLASH_SECTOR_SIZE
;
523 bank
->sectors
[i
].is_erased
= -1;
524 bank
->sectors
[i
].is_protected
= 1;
527 stm32lx_info
->probed
= 1;
532 static int stm32lx_auto_probe(struct flash_bank
*bank
)
534 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
536 if (stm32lx_info
->probed
)
539 return stm32lx_probe(bank
);
542 static int stm32lx_erase_check(struct flash_bank
*bank
)
544 struct target
*target
= bank
->target
;
545 const int buffer_size
= 4096;
548 int retval
= ERROR_OK
;
550 if (bank
->target
->state
!= TARGET_HALTED
) {
551 LOG_ERROR("Target not halted");
552 return ERROR_TARGET_NOT_HALTED
;
555 uint8_t *buffer
= malloc(buffer_size
);
556 if (buffer
== NULL
) {
557 LOG_ERROR("failed to allocate read buffer");
561 for (i
= 0; i
< bank
->num_sectors
; i
++) {
563 bank
->sectors
[i
].is_erased
= 1;
565 /* Loop chunk by chunk over the sector */
566 for (j
= 0; j
< bank
->sectors
[i
].size
; j
+= buffer_size
) {
569 if (chunk
> (j
- bank
->sectors
[i
].size
))
570 chunk
= (j
- bank
->sectors
[i
].size
);
572 retval
= target_read_memory(target
, bank
->base
573 + bank
->sectors
[i
].offset
+ j
, 4, chunk
/ 4, buffer
);
574 if (retval
!= ERROR_OK
)
577 for (nBytes
= 0; nBytes
< chunk
; nBytes
++) {
578 if (buffer
[nBytes
] != 0x00) {
579 bank
->sectors
[i
].is_erased
= 0;
584 if (retval
!= ERROR_OK
)
592 static int stm32lx_get_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
594 /* This method must return a string displaying information about the bank */
596 struct target
*target
= bank
->target
;
600 /* read stm32 device id register */
601 int retval
= target_read_u32(target
, DBGMCU_IDCODE
, &device_id
);
602 if (retval
!= ERROR_OK
)
605 if ((device_id
& 0xfff) == 0x416) {
606 printed
= snprintf(buf
, buf_size
, "stm32lx - Rev: ");
610 switch (device_id
>> 16) {
612 snprintf(buf
, buf_size
, "A");
616 snprintf(buf
, buf_size
, "Y");
620 snprintf(buf
, buf_size
, "X");
624 snprintf(buf
, buf_size
, "W");
628 snprintf(buf
, buf_size
, "V");
632 snprintf(buf
, buf_size
, "unknown");
635 } else if ((device_id
& 0xfff) == 0x436) {
636 printed
= snprintf(buf
, buf_size
, "stm32lx (HD) - Rev: ");
640 switch (device_id
>> 16) {
642 snprintf(buf
, buf_size
, "A");
646 snprintf(buf
, buf_size
, "Z");
650 snprintf(buf
, buf_size
, "Y");
654 snprintf(buf
, buf_size
, "unknown");
658 snprintf(buf
, buf_size
, "Cannot identify target as a stm32lx");
665 static const struct command_registration stm32lx_exec_command_handlers
[] = {
666 COMMAND_REGISTRATION_DONE
669 static const struct command_registration stm32lx_command_handlers
[] = {
673 .help
= "stm32lx flash command group",
675 .chain
= stm32lx_exec_command_handlers
,
677 COMMAND_REGISTRATION_DONE
680 struct flash_driver stm32lx_flash
= {
682 .commands
= stm32lx_command_handlers
,
683 .flash_bank_command
= stm32lx_flash_bank_command
,
684 .erase
= stm32lx_erase
,
685 .protect
= stm32lx_protect
,
686 .write
= stm32lx_write
,
687 .read
= default_flash_read
,
688 .probe
= stm32lx_probe
,
689 .auto_probe
= stm32lx_auto_probe
,
690 .erase_check
= stm32lx_erase_check
,
691 .protect_check
= stm32lx_protect_check
,
692 .info
= stm32lx_get_info
,
695 /* Static methods implementation */
696 static int stm32lx_unlock_program_memory(struct flash_bank
*bank
)
698 struct target
*target
= bank
->target
;
703 * Unlocking the program memory is done by unlocking the PECR,
704 * then by writing the 2 PRGKEY to the PRGKEYR register
707 /* To unlock the PECR write the 2 PEKEY to the PEKEYR register */
708 retval
= target_write_u32(target
, FLASH_PEKEYR
, PEKEY1
);
709 if (retval
!= ERROR_OK
)
712 retval
= target_write_u32(target
, FLASH_PEKEYR
, PEKEY2
);
713 if (retval
!= ERROR_OK
)
716 /* Make sure it worked */
717 retval
= target_read_u32(target
, FLASH_PECR
, ®32
);
718 if (retval
!= ERROR_OK
)
721 if (reg32
& FLASH_PECR__PELOCK
) {
722 LOG_ERROR("PELOCK is not cleared :(");
723 return ERROR_FLASH_OPERATION_FAILED
;
726 retval
= target_write_u32(target
, FLASH_PRGKEYR
, PRGKEY1
);
727 if (retval
!= ERROR_OK
)
729 retval
= target_write_u32(target
, FLASH_PRGKEYR
, PRGKEY2
);
730 if (retval
!= ERROR_OK
)
733 /* Make sure it worked */
734 retval
= target_read_u32(target
, FLASH_PECR
, ®32
);
735 if (retval
!= ERROR_OK
)
738 if (reg32
& FLASH_PECR__PRGLOCK
) {
739 LOG_ERROR("PRGLOCK is not cleared :(");
740 return ERROR_FLASH_OPERATION_FAILED
;
745 static int stm32lx_enable_write_half_page(struct flash_bank
*bank
)
747 struct target
*target
= bank
->target
;
752 * Unlock the program memory, then set the FPRG bit in the PECR register.
754 retval
= stm32lx_unlock_program_memory(bank
);
755 if (retval
!= ERROR_OK
)
758 retval
= target_read_u32(target
, FLASH_PECR
, ®32
);
759 if (retval
!= ERROR_OK
)
762 reg32
|= FLASH_PECR__FPRG
;
763 retval
= target_write_u32(target
, FLASH_PECR
, reg32
);
764 if (retval
!= ERROR_OK
)
767 retval
= target_read_u32(target
, FLASH_PECR
, ®32
);
768 if (retval
!= ERROR_OK
)
771 reg32
|= FLASH_PECR__PROG
;
772 retval
= target_write_u32(target
, FLASH_PECR
, reg32
);
777 static int stm32lx_lock_program_memory(struct flash_bank
*bank
)
779 struct target
*target
= bank
->target
;
783 /* To lock the program memory, simply set the lock bit and lock PECR */
785 retval
= target_read_u32(target
, FLASH_PECR
, ®32
);
786 if (retval
!= ERROR_OK
)
789 reg32
|= FLASH_PECR__PRGLOCK
;
790 retval
= target_write_u32(target
, FLASH_PECR
, reg32
);
791 if (retval
!= ERROR_OK
)
794 retval
= target_read_u32(target
, FLASH_PECR
, ®32
);
795 if (retval
!= ERROR_OK
)
798 reg32
|= FLASH_PECR__PELOCK
;
799 retval
= target_write_u32(target
, FLASH_PECR
, reg32
);
800 if (retval
!= ERROR_OK
)
806 static int stm32lx_erase_sector(struct flash_bank
*bank
, int sector
)
808 struct target
*target
= bank
->target
;
813 * To erase a sector (i.e. FLASH_PAGES_PER_SECTOR pages),
814 * first unlock the memory, loop over the pages of this sector
815 * and write 0x0 to its first word.
818 retval
= stm32lx_unlock_program_memory(bank
);
819 if (retval
!= ERROR_OK
)
822 for (int page
= 0; page
< FLASH_PAGES_PER_SECTOR
; page
++) {
823 reg32
= FLASH_PECR__PROG
| FLASH_PECR__ERASE
;
824 retval
= target_write_u32(target
, FLASH_PECR
, reg32
);
825 if (retval
!= ERROR_OK
)
828 retval
= stm32lx_wait_until_bsy_clear(bank
);
829 if (retval
!= ERROR_OK
)
832 uint32_t addr
= bank
->base
+ bank
->sectors
[sector
].offset
+ (page
834 retval
= target_write_u32(target
, addr
, 0x0);
835 if (retval
!= ERROR_OK
)
838 retval
= stm32lx_wait_until_bsy_clear(bank
);
839 if (retval
!= ERROR_OK
)
843 retval
= stm32lx_lock_program_memory(bank
);
844 if (retval
!= ERROR_OK
)
850 static int stm32lx_wait_until_bsy_clear(struct flash_bank
*bank
)
852 struct target
*target
= bank
->target
;
854 int retval
= ERROR_OK
;
857 /* wait for busy to clear */
859 retval
= target_read_u32(target
, FLASH_SR
, &status
);
860 if (retval
!= ERROR_OK
)
863 if ((status
& FLASH_SR__BSY
) == 0)
865 if (timeout
-- <= 0) {
866 LOG_ERROR("timed out waiting for flash");
872 if (status
& FLASH_SR__WRPERR
) {
873 LOG_ERROR("access denied / write protected");
877 if (status
& FLASH_SR__PGAERR
) {
878 LOG_ERROR("invalid program address");
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