1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2011 Øyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
30 #include <helper/binarybuffer.h>
31 #include <target/algorithm.h>
32 #include <target/armv7m.h>
34 /* Regarding performance:
36 * Short story - it might be best to leave the performance at
39 * You may see a jump in speed if you change to using
40 * 32bit words for the block programming.
42 * Its a shame you cannot use the double word as its
43 * even faster - but you require external VPP for that mode.
45 * Having said all that 16bit writes give us the widest vdd
46 * operating range, so may be worth adding a note to that effect.
50 /* Danger!!!! The STM32F1x and STM32F2x series actually have
51 * quite different flash controllers.
53 * What's more scary is that the names of the registers and their
54 * addresses are the same, but the actual bits and what they do are
55 * can be very different.
57 * To reduce testing complexity and dangers of regressions,
58 * a seperate file is used for stm32fx2x.
60 * Sector sizes in kiBytes:
61 * 1 MiByte part with 4 x 16, 1 x 64, 7 x 128.
62 * 1.5 MiByte part with 4 x 16, 1 x 64, 11 x 128.
63 * 2 MiByte part with 4 x 16, 1 x 64, 7 x 128, 4 x 16, 1 x 64, 7 x 128.
64 * 1 MiByte STM32F42x/43x part with DB1M Option set:
65 * 4 x 16, 1 x 64, 3 x 128, 4 x 16, 1 x 64, 3 x 128.
68 * 512 kiByte part with 4 x 16, 1 x 64, 3 x 128.
71 * 1 MiByte part with 4 x 32, 1 x 128, 3 x 256.
74 * 1 MiByte part in single bank mode with 4 x 32, 1 x 128, 3 x 256.
75 * 1 MiByte part in dual-bank mode two banks with 4 x 16, 1 x 64, 3 x 128 each.
76 * 2 MiByte part in single-bank mode with 4 x 32, 1 x 128, 7 x 256.
77 * 2 MiByte part in dual-bank mode two banks with 4 x 16, 1 x 64, 7 x 128 each.
79 * Protection size is sector size.
81 * Tested with STM3220F-EVAL board.
83 * STM32F4xx series for reference.
86 * http://www.st.com/web/en/resource/technical/document/reference_manual/DM00031020.pdf
89 * www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/
90 * PROGRAMMING_MANUAL/CD00233952.pdf
92 * STM32F7xx series for reference.
95 * http://www.st.com/web/en/resource/technical/document/reference_manual/DM00124865.pdf
98 * http://www.st.com/resource/en/reference_manual/dm00224583.pdf
101 * http://www.st.com/resource/en/reference_manual/dm00305666.pdf
104 * http://www.st.com/resource/en/reference_manual/dm00305990.pdf
106 * STM32F1x series - notice that this code was copy, pasted and knocked
107 * into a stm32f2x driver, so in case something has been converted or
108 * bugs haven't been fixed, here are the original manuals:
110 * RM0008 - Reference manual
112 * RM0042, the Flash programming manual for low-, medium- high-density and
113 * connectivity line STM32F10x devices
115 * PM0068, the Flash programming manual for XL-density STM32F10x devices.
119 /* Erase time can be as high as 1000ms, 10x this and it's toast... */
120 #define FLASH_ERASE_TIMEOUT 10000
121 #define FLASH_WRITE_TIMEOUT 5
123 /* Mass erase time can be as high as 32 s in x8 mode. */
124 #define FLASH_MASS_ERASE_TIMEOUT 33000
126 #define STM32_FLASH_BASE 0x40023c00
127 #define STM32_FLASH_ACR 0x40023c00
128 #define STM32_FLASH_KEYR 0x40023c04
129 #define STM32_FLASH_OPTKEYR 0x40023c08
130 #define STM32_FLASH_SR 0x40023c0C
131 #define STM32_FLASH_CR 0x40023c10
132 #define STM32_FLASH_OPTCR 0x40023c14
133 #define STM32_FLASH_OPTCR1 0x40023c18
134 #define STM32_FLASH_OPTCR2 0x40023c1c
136 /* FLASH_CR register bits */
137 #define FLASH_PG (1 << 0)
138 #define FLASH_SER (1 << 1)
139 #define FLASH_MER (1 << 2) /* MER/MER1 for f76x/77x */
140 #define FLASH_MER1 (1 << 15) /* MER2 for f76x/77x, confusing ... */
141 #define FLASH_STRT (1 << 16)
142 #define FLASH_PSIZE_8 (0 << 8)
143 #define FLASH_PSIZE_16 (1 << 8)
144 #define FLASH_PSIZE_32 (2 << 8)
145 #define FLASH_PSIZE_64 (3 << 8)
146 /* The sector number encoding is not straight binary for dual bank flash. */
147 #define FLASH_SNB(a) ((a) << 3)
148 #define FLASH_LOCK (1 << 31)
150 /* FLASH_SR register bits */
151 #define FLASH_BSY (1 << 16)
152 #define FLASH_PGSERR (1 << 7) /* Programming sequence error */
153 #define FLASH_PGPERR (1 << 6) /* Programming parallelism error */
154 #define FLASH_PGAERR (1 << 5) /* Programming alignment error */
155 #define FLASH_WRPERR (1 << 4) /* Write protection error */
156 #define FLASH_OPERR (1 << 1) /* Operation error */
158 #define FLASH_ERROR (FLASH_PGSERR | FLASH_PGPERR | FLASH_PGAERR | FLASH_WRPERR | FLASH_OPERR)
160 /* STM32_FLASH_OPTCR register bits */
161 #define OPTCR_LOCK (1 << 0)
162 #define OPTCR_START (1 << 1)
163 #define OPTCR_NDBANK (1 << 29) /* not dual bank mode */
164 #define OPTCR_DB1M (1 << 30) /* 1 MiB devices dual flash bank option */
165 #define OPTCR_SPRMOD (1 << 31) /* switches PCROPi/nWPRi interpretation */
167 /* STM32_FLASH_OPTCR2 register bits */
168 #define OPTCR2_PCROP_RDP (1 << 31) /* erase PCROP zone when decreasing RDP */
170 /* register unlock keys */
171 #define KEY1 0x45670123
172 #define KEY2 0xCDEF89AB
174 /* option register unlock key */
175 #define OPTKEY1 0x08192A3B
176 #define OPTKEY2 0x4C5D6E7F
178 struct stm32x_options
{
180 uint16_t user_options
; /* bit 0-7 usual options, bit 8-11 extra options */
183 uint32_t optcr2_pcrop
;
186 struct stm32x_flash_bank
{
187 struct stm32x_options option_bytes
;
189 bool has_large_mem
; /* F42x/43x/469/479/7xx in dual bank mode */
190 bool has_extra_options
; /* F42x/43x/469/479/7xx */
191 bool has_boot_addr
; /* F7xx */
192 bool has_optcr2_pcrop
; /* F72x/73x */
193 int protection_bits
; /* F413/423 */
194 uint32_t user_bank_size
;
197 /* flash bank stm32x <base> <size> 0 0 <target#>
199 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command
)
201 struct stm32x_flash_bank
*stm32x_info
;
204 return ERROR_COMMAND_SYNTAX_ERROR
;
206 stm32x_info
= malloc(sizeof(struct stm32x_flash_bank
));
207 bank
->driver_priv
= stm32x_info
;
209 stm32x_info
->probed
= 0;
210 stm32x_info
->user_bank_size
= bank
->size
;
215 static inline int stm32x_get_flash_reg(struct flash_bank
*bank
, uint32_t reg
)
220 static inline int stm32x_get_flash_status(struct flash_bank
*bank
, uint32_t *status
)
222 struct target
*target
= bank
->target
;
223 return target_read_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_SR
), status
);
226 static int stm32x_wait_status_busy(struct flash_bank
*bank
, int timeout
)
228 struct target
*target
= bank
->target
;
230 int retval
= ERROR_OK
;
232 /* wait for busy to clear */
234 retval
= stm32x_get_flash_status(bank
, &status
);
235 if (retval
!= ERROR_OK
)
237 LOG_DEBUG("status: 0x%" PRIx32
"", status
);
238 if ((status
& FLASH_BSY
) == 0)
240 if (timeout
-- <= 0) {
241 LOG_ERROR("timed out waiting for flash");
248 if (status
& FLASH_WRPERR
) {
249 LOG_ERROR("stm32x device protected");
253 /* Clear but report errors */
254 if (status
& FLASH_ERROR
) {
255 if (retval
== ERROR_OK
)
257 /* If this operation fails, we ignore it and report the original
260 target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_SR
),
261 status
& FLASH_ERROR
);
266 static int stm32x_unlock_reg(struct target
*target
)
270 /* first check if not already unlocked
271 * otherwise writing on STM32_FLASH_KEYR will fail
273 int retval
= target_read_u32(target
, STM32_FLASH_CR
, &ctrl
);
274 if (retval
!= ERROR_OK
)
277 if ((ctrl
& FLASH_LOCK
) == 0)
280 /* unlock flash registers */
281 retval
= target_write_u32(target
, STM32_FLASH_KEYR
, KEY1
);
282 if (retval
!= ERROR_OK
)
285 retval
= target_write_u32(target
, STM32_FLASH_KEYR
, KEY2
);
286 if (retval
!= ERROR_OK
)
289 retval
= target_read_u32(target
, STM32_FLASH_CR
, &ctrl
);
290 if (retval
!= ERROR_OK
)
293 if (ctrl
& FLASH_LOCK
) {
294 LOG_ERROR("flash not unlocked STM32_FLASH_CR: %" PRIx32
, ctrl
);
295 return ERROR_TARGET_FAILURE
;
301 static int stm32x_unlock_option_reg(struct target
*target
)
305 int retval
= target_read_u32(target
, STM32_FLASH_OPTCR
, &ctrl
);
306 if (retval
!= ERROR_OK
)
309 if ((ctrl
& OPTCR_LOCK
) == 0)
312 /* unlock option registers */
313 retval
= target_write_u32(target
, STM32_FLASH_OPTKEYR
, OPTKEY1
);
314 if (retval
!= ERROR_OK
)
317 retval
= target_write_u32(target
, STM32_FLASH_OPTKEYR
, OPTKEY2
);
318 if (retval
!= ERROR_OK
)
321 retval
= target_read_u32(target
, STM32_FLASH_OPTCR
, &ctrl
);
322 if (retval
!= ERROR_OK
)
325 if (ctrl
& OPTCR_LOCK
) {
326 LOG_ERROR("options not unlocked STM32_FLASH_OPTCR: %" PRIx32
, ctrl
);
327 return ERROR_TARGET_FAILURE
;
333 static int stm32x_read_options(struct flash_bank
*bank
)
336 struct stm32x_flash_bank
*stm32x_info
= NULL
;
337 struct target
*target
= bank
->target
;
339 stm32x_info
= bank
->driver_priv
;
341 /* read current option bytes */
342 int retval
= target_read_u32(target
, STM32_FLASH_OPTCR
, &optiondata
);
343 if (retval
!= ERROR_OK
)
346 /* caution: F2 implements 5 bits (WDG_SW only)
347 * whereas F7 6 bits (IWDG_SW and WWDG_SW) in user_options */
348 stm32x_info
->option_bytes
.user_options
= optiondata
& 0xfc;
349 stm32x_info
->option_bytes
.RDP
= (optiondata
>> 8) & 0xff;
350 stm32x_info
->option_bytes
.protection
=
351 (optiondata
>> 16) & (~(0xffff << stm32x_info
->protection_bits
) & 0xffff);
353 if (stm32x_info
->has_extra_options
) {
354 /* F42x/43x/469/479 and 7xx have up to 4 bits of extra options */
355 stm32x_info
->option_bytes
.user_options
|= (optiondata
>> 20) &
356 ((0xf00 << (stm32x_info
->protection_bits
- 12)) & 0xf00);
359 if (stm32x_info
->has_large_mem
|| stm32x_info
->has_boot_addr
) {
360 retval
= target_read_u32(target
, STM32_FLASH_OPTCR1
, &optiondata
);
361 if (retval
!= ERROR_OK
)
364 /* FLASH_OPTCR1 has quite diffent meanings ... */
365 if (stm32x_info
->has_boot_addr
) {
366 /* for F7xx it contains boot0 and boot1 */
367 stm32x_info
->option_bytes
.boot_addr
= optiondata
;
369 /* for F42x/43x/469/479 it contains 12 additional protection bits */
370 stm32x_info
->option_bytes
.protection
|= (optiondata
>> 4) & 0x00fff000;
374 if (stm32x_info
->has_optcr2_pcrop
) {
375 retval
= target_read_u32(target
, STM32_FLASH_OPTCR2
, &optiondata
);
376 if (retval
!= ERROR_OK
)
379 stm32x_info
->option_bytes
.optcr2_pcrop
= optiondata
;
380 if (stm32x_info
->has_optcr2_pcrop
&&
381 (stm32x_info
->option_bytes
.optcr2_pcrop
& ~OPTCR2_PCROP_RDP
)) {
382 LOG_INFO("PCROP Engaged");
385 stm32x_info
->option_bytes
.optcr2_pcrop
= 0x0;
388 if (stm32x_info
->option_bytes
.RDP
!= 0xAA)
389 LOG_INFO("Device Security Bit Set");
394 static int stm32x_write_options(struct flash_bank
*bank
)
396 struct stm32x_flash_bank
*stm32x_info
= NULL
;
397 struct target
*target
= bank
->target
;
398 uint32_t optiondata
, optiondata2
;
400 stm32x_info
= bank
->driver_priv
;
402 int retval
= stm32x_unlock_option_reg(target
);
403 if (retval
!= ERROR_OK
)
406 /* rebuild option data */
407 optiondata
= stm32x_info
->option_bytes
.user_options
& 0xfc;
408 optiondata
|= stm32x_info
->option_bytes
.RDP
<< 8;
409 optiondata
|= (stm32x_info
->option_bytes
.protection
&
410 (~(0xffff << stm32x_info
->protection_bits
))) << 16;
412 if (stm32x_info
->has_extra_options
) {
413 /* F42x/43x/469/479 and 7xx have up to 4 bits of extra options */
414 optiondata
|= (stm32x_info
->option_bytes
.user_options
&
415 ((0xf00 << (stm32x_info
->protection_bits
- 12)) & 0xf00)) << 20;
418 if (stm32x_info
->has_large_mem
|| stm32x_info
->has_boot_addr
) {
419 if (stm32x_info
->has_boot_addr
) {
420 /* F7xx uses FLASH_OPTCR1 for boot0 and boot1 ... */
421 optiondata2
= stm32x_info
->option_bytes
.boot_addr
;
423 /* F42x/43x/469/479 uses FLASH_OPTCR1 for additional protection bits */
424 optiondata2
= (stm32x_info
->option_bytes
.protection
& 0x00fff000) << 4;
427 retval
= target_write_u32(target
, STM32_FLASH_OPTCR1
, optiondata2
);
428 if (retval
!= ERROR_OK
)
432 /* program extra pcrop register */
433 if (stm32x_info
->has_optcr2_pcrop
) {
434 retval
= target_write_u32(target
, STM32_FLASH_OPTCR2
,
435 stm32x_info
->option_bytes
.optcr2_pcrop
);
436 if (retval
!= ERROR_OK
)
440 /* program options */
441 retval
= target_write_u32(target
, STM32_FLASH_OPTCR
, optiondata
);
442 if (retval
!= ERROR_OK
)
445 /* start programming cycle */
446 retval
= target_write_u32(target
, STM32_FLASH_OPTCR
, optiondata
| OPTCR_START
);
447 if (retval
!= ERROR_OK
)
450 /* wait for completion, this might trigger a security erase and take a while */
451 retval
= stm32x_wait_status_busy(bank
, FLASH_MASS_ERASE_TIMEOUT
);
452 if (retval
!= ERROR_OK
)
455 /* relock registers */
456 retval
= target_write_u32(target
, STM32_FLASH_OPTCR
, optiondata
| OPTCR_LOCK
);
457 if (retval
!= ERROR_OK
)
463 static int stm32x_protect_check(struct flash_bank
*bank
)
465 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
466 struct flash_sector
*prot_blocks
;
469 /* read write protection settings */
470 int retval
= stm32x_read_options(bank
);
471 if (retval
!= ERROR_OK
) {
472 LOG_DEBUG("unable to read option bytes");
476 if (bank
->prot_blocks
) {
477 num_prot_blocks
= bank
->num_prot_blocks
;
478 prot_blocks
= bank
->prot_blocks
;
480 num_prot_blocks
= bank
->num_sectors
;
481 prot_blocks
= bank
->sectors
;
484 for (int i
= 0; i
< num_prot_blocks
; i
++)
485 prot_blocks
[i
].is_protected
=
486 ~(stm32x_info
->option_bytes
.protection
>> i
) & 1;
491 static int stm32x_erase(struct flash_bank
*bank
, int first
, int last
)
493 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
494 struct target
*target
= bank
->target
;
497 assert((0 <= first
) && (first
<= last
) && (last
< bank
->num_sectors
));
499 if (bank
->target
->state
!= TARGET_HALTED
) {
500 LOG_ERROR("Target not halted");
501 return ERROR_TARGET_NOT_HALTED
;
505 retval
= stm32x_unlock_reg(target
);
506 if (retval
!= ERROR_OK
)
511 To erase a sector, follow the procedure below:
512 1. Check that no Flash memory operation is ongoing by checking the BSY bit in the
514 2. Set the SER bit and select the sector
515 you wish to erase (SNB) in the FLASH_CR register
516 3. Set the STRT bit in the FLASH_CR register
517 4. Wait for the BSY bit to be cleared
520 for (i
= first
; i
<= last
; i
++) {
522 if (stm32x_info
->has_large_mem
&& i
>= 12)
523 snb
= (i
- 12) | 0x10;
527 retval
= target_write_u32(target
,
528 stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_SER
| FLASH_SNB(snb
) | FLASH_STRT
);
529 if (retval
!= ERROR_OK
)
532 retval
= stm32x_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
);
533 if (retval
!= ERROR_OK
)
536 bank
->sectors
[i
].is_erased
= 1;
539 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_LOCK
);
540 if (retval
!= ERROR_OK
)
546 static int stm32x_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
548 struct target
*target
= bank
->target
;
549 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
551 if (target
->state
!= TARGET_HALTED
) {
552 LOG_ERROR("Target not halted");
553 return ERROR_TARGET_NOT_HALTED
;
556 /* read protection settings */
557 int retval
= stm32x_read_options(bank
);
558 if (retval
!= ERROR_OK
) {
559 LOG_DEBUG("unable to read option bytes");
563 for (int i
= first
; i
<= last
; i
++) {
565 stm32x_info
->option_bytes
.protection
&= ~(1 << i
);
567 stm32x_info
->option_bytes
.protection
|= (1 << i
);
570 retval
= stm32x_write_options(bank
);
571 if (retval
!= ERROR_OK
)
577 static int stm32x_write_block(struct flash_bank
*bank
, const uint8_t *buffer
,
578 uint32_t offset
, uint32_t count
)
580 struct target
*target
= bank
->target
;
581 uint32_t buffer_size
= 16384;
582 struct working_area
*write_algorithm
;
583 struct working_area
*source
;
584 uint32_t address
= bank
->base
+ offset
;
585 struct reg_param reg_params
[5];
586 struct armv7m_algorithm armv7m_info
;
587 int retval
= ERROR_OK
;
589 static const uint8_t stm32x_flash_write_code
[] = {
590 #include "../../../contrib/loaders/flash/stm32/stm32f2x.inc"
593 if (target_alloc_working_area(target
, sizeof(stm32x_flash_write_code
),
594 &write_algorithm
) != ERROR_OK
) {
595 LOG_WARNING("no working area available, can't do block memory writes");
596 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
599 retval
= target_write_buffer(target
, write_algorithm
->address
,
600 sizeof(stm32x_flash_write_code
),
601 stm32x_flash_write_code
);
602 if (retval
!= ERROR_OK
)
606 while (target_alloc_working_area_try(target
, buffer_size
, &source
) != ERROR_OK
) {
608 if (buffer_size
<= 256) {
609 /* we already allocated the writing code, but failed to get a
610 * buffer, free the algorithm */
611 target_free_working_area(target
, write_algorithm
);
613 LOG_WARNING("no large enough working area available, can't do block memory writes");
614 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
618 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
619 armv7m_info
.core_mode
= ARM_MODE_THREAD
;
621 init_reg_param(®_params
[0], "r0", 32, PARAM_IN_OUT
); /* buffer start, status (out) */
622 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
); /* buffer end */
623 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
); /* target address */
624 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
); /* count (halfword-16bit) */
625 init_reg_param(®_params
[4], "r4", 32, PARAM_OUT
); /* flash base */
627 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
628 buf_set_u32(reg_params
[1].value
, 0, 32, source
->address
+ source
->size
);
629 buf_set_u32(reg_params
[2].value
, 0, 32, address
);
630 buf_set_u32(reg_params
[3].value
, 0, 32, count
);
631 buf_set_u32(reg_params
[4].value
, 0, 32, STM32_FLASH_BASE
);
633 retval
= target_run_flash_async_algorithm(target
, buffer
, count
, 2,
636 source
->address
, source
->size
,
637 write_algorithm
->address
, 0,
640 if (retval
== ERROR_FLASH_OPERATION_FAILED
) {
641 LOG_ERROR("error executing stm32x flash write algorithm");
643 uint32_t error
= buf_get_u32(reg_params
[0].value
, 0, 32) & FLASH_ERROR
;
645 if (error
& FLASH_WRPERR
)
646 LOG_ERROR("flash memory write protected");
649 LOG_ERROR("flash write failed = %08" PRIx32
, error
);
650 /* Clear but report errors */
651 target_write_u32(target
, STM32_FLASH_SR
, error
);
656 target_free_working_area(target
, source
);
657 target_free_working_area(target
, write_algorithm
);
659 destroy_reg_param(®_params
[0]);
660 destroy_reg_param(®_params
[1]);
661 destroy_reg_param(®_params
[2]);
662 destroy_reg_param(®_params
[3]);
663 destroy_reg_param(®_params
[4]);
668 static int stm32x_write(struct flash_bank
*bank
, const uint8_t *buffer
,
669 uint32_t offset
, uint32_t count
)
671 struct target
*target
= bank
->target
;
672 uint32_t words_remaining
= (count
/ 2);
673 uint32_t bytes_remaining
= (count
& 0x00000001);
674 uint32_t address
= bank
->base
+ offset
;
675 uint32_t bytes_written
= 0;
678 if (bank
->target
->state
!= TARGET_HALTED
) {
679 LOG_ERROR("Target not halted");
680 return ERROR_TARGET_NOT_HALTED
;
684 LOG_WARNING("offset 0x%" PRIx32
" breaks required 2-byte alignment", offset
);
685 return ERROR_FLASH_DST_BREAKS_ALIGNMENT
;
688 retval
= stm32x_unlock_reg(target
);
689 if (retval
!= ERROR_OK
)
692 /* multiple half words (2-byte) to be programmed? */
693 if (words_remaining
> 0) {
694 /* try using a block write */
695 retval
= stm32x_write_block(bank
, buffer
, offset
, words_remaining
);
696 if (retval
!= ERROR_OK
) {
697 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
) {
698 /* if block write failed (no sufficient working area),
699 * we use normal (slow) single dword accesses */
700 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
703 buffer
+= words_remaining
* 2;
704 address
+= words_remaining
* 2;
709 if ((retval
!= ERROR_OK
) && (retval
!= ERROR_TARGET_RESOURCE_NOT_AVAILABLE
))
714 The Flash memory programming sequence is as follows:
715 1. Check that no main Flash memory operation is ongoing by checking the BSY bit in the
717 2. Set the PG bit in the FLASH_CR register
718 3. Perform the data write operation(s) to the desired memory address (inside main
719 memory block or OTP area):
720 – – Half-word access in case of x16 parallelism
721 – Word access in case of x32 parallelism
724 Byte access in case of x8 parallelism
725 Double word access in case of x64 parallelism
726 Wait for the BSY bit to be cleared
728 while (words_remaining
> 0) {
730 memcpy(&value
, buffer
+ bytes_written
, sizeof(uint16_t));
732 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
),
733 FLASH_PG
| FLASH_PSIZE_16
);
734 if (retval
!= ERROR_OK
)
737 retval
= target_write_u16(target
, address
, value
);
738 if (retval
!= ERROR_OK
)
741 retval
= stm32x_wait_status_busy(bank
, FLASH_WRITE_TIMEOUT
);
742 if (retval
!= ERROR_OK
)
750 if (bytes_remaining
) {
751 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
),
752 FLASH_PG
| FLASH_PSIZE_8
);
753 if (retval
!= ERROR_OK
)
755 retval
= target_write_u8(target
, address
, buffer
[bytes_written
]);
756 if (retval
!= ERROR_OK
)
759 retval
= stm32x_wait_status_busy(bank
, FLASH_WRITE_TIMEOUT
);
760 if (retval
!= ERROR_OK
)
764 return target_write_u32(target
, STM32_FLASH_CR
, FLASH_LOCK
);
767 static int setup_sector(struct flash_bank
*bank
, int start
, int num
, int size
)
770 for (int i
= start
; i
< (start
+ num
) ; i
++) {
771 assert(i
< bank
->num_sectors
);
772 bank
->sectors
[i
].offset
= bank
->size
;
773 bank
->sectors
[i
].size
= size
;
774 bank
->size
+= bank
->sectors
[i
].size
;
775 LOG_DEBUG("sector %d: %dkBytes", i
, size
>> 10);
781 static void setup_bank(struct flash_bank
*bank
, int start
,
782 uint16_t flash_size_in_kb
, uint16_t max_sector_size_in_kb
)
786 start
= setup_sector(bank
, start
, 4, (max_sector_size_in_kb
/ 8) * 1024);
787 start
= setup_sector(bank
, start
, 1, (max_sector_size_in_kb
/ 2) * 1024);
789 /* remaining sectors all of size max_sector_size_in_kb */
790 remain
= (flash_size_in_kb
/ max_sector_size_in_kb
) - 1;
791 start
= setup_sector(bank
, start
, remain
, max_sector_size_in_kb
* 1024);
794 static int stm32x_get_device_id(struct flash_bank
*bank
, uint32_t *device_id
)
796 /* this checks for a stm32f4x errata issue where a
797 * stm32f2x DBGMCU_IDCODE is incorrectly returned.
798 * If the issue is detected target is forced to stm32f4x Rev A.
799 * Only effects Rev A silicon */
801 struct target
*target
= bank
->target
;
804 /* read stm32 device id register */
805 int retval
= target_read_u32(target
, 0xE0042000, device_id
);
806 if (retval
!= ERROR_OK
)
809 if ((*device_id
& 0xfff) == 0x411) {
810 /* read CPUID reg to check core type */
811 retval
= target_read_u32(target
, 0xE000ED00, &cpuid
);
812 if (retval
!= ERROR_OK
)
815 /* check for cortex_m4 */
816 if (((cpuid
>> 4) & 0xFFF) == 0xC24) {
817 *device_id
&= ~((0xFFFF << 16) | 0xfff);
818 *device_id
|= (0x1000 << 16) | 0x413;
819 LOG_INFO("stm32f4x errata detected - fixing incorrect MCU_IDCODE");
825 static int stm32x_probe(struct flash_bank
*bank
)
827 struct target
*target
= bank
->target
;
828 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
829 int i
, num_prot_blocks
;
830 uint16_t flash_size_in_kb
;
831 uint32_t flash_size_reg
= 0x1FFF7A22;
832 uint16_t max_sector_size_in_kb
= 128;
833 uint16_t max_flash_size_in_kb
;
835 uint32_t base_address
= 0x08000000;
837 stm32x_info
->probed
= 0;
838 stm32x_info
->has_large_mem
= false;
839 stm32x_info
->has_boot_addr
= false;
840 stm32x_info
->has_extra_options
= false;
841 stm32x_info
->has_optcr2_pcrop
= false;
842 stm32x_info
->protection_bits
= 12; /* max. number of nWRPi bits (in FLASH_OPTCR !!!) */
847 bank
->num_sectors
= 0;
848 bank
->sectors
= NULL
;
851 if (bank
->prot_blocks
) {
852 free(bank
->prot_blocks
);
853 bank
->num_prot_blocks
= 0;
854 bank
->prot_blocks
= NULL
;
857 /* read stm32 device id register */
858 int retval
= stm32x_get_device_id(bank
, &device_id
);
859 if (retval
!= ERROR_OK
)
861 LOG_INFO("device id = 0x%08" PRIx32
"", device_id
);
862 device_id
&= 0xfff; /* only bits 0-11 are used further on */
864 /* set max flash size depending on family, id taken from AN2606 */
866 case 0x411: /* F20x/21x */
867 case 0x413: /* F40x/41x */
868 max_flash_size_in_kb
= 1024;
871 case 0x419: /* F42x/43x */
872 case 0x434: /* F469/479 */
873 stm32x_info
->has_extra_options
= true;
874 max_flash_size_in_kb
= 2048;
877 case 0x423: /* F401xB/C */
878 max_flash_size_in_kb
= 256;
881 case 0x421: /* F446 */
882 case 0x431: /* F411 */
883 case 0x433: /* F401xD/E */
884 case 0x441: /* F412 */
885 max_flash_size_in_kb
= 512;
888 case 0x458: /* F410 */
889 max_flash_size_in_kb
= 128;
892 case 0x449: /* F74x/75x */
893 max_flash_size_in_kb
= 1024;
894 max_sector_size_in_kb
= 256;
895 flash_size_reg
= 0x1FF0F442;
896 stm32x_info
->has_extra_options
= true;
897 stm32x_info
->has_boot_addr
= true;
900 case 0x451: /* F76x/77x */
901 max_flash_size_in_kb
= 2048;
902 max_sector_size_in_kb
= 256;
903 flash_size_reg
= 0x1FF0F442;
904 stm32x_info
->has_extra_options
= true;
905 stm32x_info
->has_boot_addr
= true;
908 case 0x452: /* F72x/73x */
909 max_flash_size_in_kb
= 512;
910 flash_size_reg
= 0x1FF07A22; /* yes, 0x1FF*0*7A22, not 0x1FF*F*7A22 */
911 stm32x_info
->has_extra_options
= true;
912 stm32x_info
->has_boot_addr
= true;
913 stm32x_info
->has_optcr2_pcrop
= true;
916 case 0x463: /* F413x/423x */
917 max_flash_size_in_kb
= 1536;
918 stm32x_info
->has_extra_options
= true;
919 stm32x_info
->protection_bits
= 15;
920 num_prot_blocks
= 15;
924 LOG_WARNING("Cannot identify target as a STM32 family.");
928 /* get flash size from target. */
929 retval
= target_read_u16(target
, flash_size_reg
, &flash_size_in_kb
);
931 /* failed reading flash size or flash size invalid (early silicon),
932 * default to max target family */
933 if (retval
!= ERROR_OK
|| flash_size_in_kb
== 0xffff || flash_size_in_kb
== 0) {
934 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
935 max_flash_size_in_kb
);
936 flash_size_in_kb
= max_flash_size_in_kb
;
939 /* if the user sets the size manually then ignore the probed value
940 * this allows us to work around devices that have a invalid flash size register value */
941 if (stm32x_info
->user_bank_size
) {
942 LOG_INFO("ignoring flash probed value, using configured bank size");
943 flash_size_in_kb
= stm32x_info
->user_bank_size
/ 1024;
946 LOG_INFO("flash size = %dkbytes", flash_size_in_kb
);
948 /* did we assign flash size? */
949 assert(flash_size_in_kb
!= 0xffff);
951 /* F42x/43x/469/479 1024 kiByte devices have a dual bank option */
952 if ((device_id
== 0x419) || (device_id
== 0x434)) {
954 retval
= target_read_u32(target
, STM32_FLASH_OPTCR
, &optiondata
);
955 if (retval
!= ERROR_OK
) {
956 LOG_DEBUG("unable to read option bytes");
959 if ((flash_size_in_kb
> 1024) || (optiondata
& OPTCR_DB1M
)) {
960 stm32x_info
->has_large_mem
= true;
961 LOG_INFO("Dual Bank %d kiB STM32F42x/43x/469/479 found", flash_size_in_kb
);
963 stm32x_info
->has_large_mem
= false;
964 LOG_INFO("Single Bank %d kiB STM32F42x/43x/469/479 found", flash_size_in_kb
);
968 /* F76x/77x devices have a dual bank option */
969 if (device_id
== 0x451) {
971 retval
= target_read_u32(target
, STM32_FLASH_OPTCR
, &optiondata
);
972 if (retval
!= ERROR_OK
) {
973 LOG_DEBUG("unable to read option bytes");
976 if (optiondata
& OPTCR_NDBANK
) {
977 stm32x_info
->has_large_mem
= false;
978 LOG_INFO("Single Bank %d kiB STM32F76x/77x found", flash_size_in_kb
);
980 stm32x_info
->has_large_mem
= true;
981 max_sector_size_in_kb
>>= 1; /* sector size divided by 2 in dual-bank mode */
982 LOG_INFO("Dual Bank %d kiB STM32F76x/77x found", flash_size_in_kb
);
986 /* calculate numbers of pages */
987 int num_pages
= flash_size_in_kb
/ max_sector_size_in_kb
988 + (stm32x_info
->has_large_mem
? 8 : 4);
990 bank
->base
= base_address
;
991 bank
->num_sectors
= num_pages
;
992 bank
->sectors
= malloc(sizeof(struct flash_sector
) * num_pages
);
993 for (i
= 0; i
< num_pages
; i
++) {
994 bank
->sectors
[i
].is_erased
= -1;
995 bank
->sectors
[i
].is_protected
= 0;
998 LOG_DEBUG("allocated %d sectors", num_pages
);
1000 /* F76x/77x in dual bank mode */
1001 if ((device_id
== 0x451) && stm32x_info
->has_large_mem
)
1002 num_prot_blocks
= num_pages
>> 1;
1004 if (num_prot_blocks
) {
1005 bank
->prot_blocks
= malloc(sizeof(struct flash_sector
) * num_prot_blocks
);
1006 for (i
= 0; i
< num_prot_blocks
; i
++)
1007 bank
->prot_blocks
[i
].is_protected
= 0;
1008 LOG_DEBUG("allocated %d prot blocks", num_prot_blocks
);
1011 if (stm32x_info
->has_large_mem
) {
1013 setup_bank(bank
, 0, flash_size_in_kb
>> 1, max_sector_size_in_kb
);
1014 setup_bank(bank
, num_pages
>> 1, flash_size_in_kb
>> 1,
1015 max_sector_size_in_kb
);
1017 /* F767x/F77x in dual mode, one protection bit refers to two adjacent sectors */
1018 if (device_id
== 0x451) {
1019 for (i
= 0; i
< num_prot_blocks
; i
++) {
1020 bank
->prot_blocks
[i
].offset
= bank
->sectors
[i
<< 1].offset
;
1021 bank
->prot_blocks
[i
].size
= bank
->sectors
[i
<< 1].size
1022 + bank
->sectors
[(i
<< 1) + 1].size
;
1027 setup_bank(bank
, 0, flash_size_in_kb
, max_sector_size_in_kb
);
1029 /* F413/F423, sectors 14 and 15 share one common protection bit */
1030 if (device_id
== 0x463) {
1031 for (i
= 0; i
< num_prot_blocks
; i
++) {
1032 bank
->prot_blocks
[i
].offset
= bank
->sectors
[i
].offset
;
1033 bank
->prot_blocks
[i
].size
= bank
->sectors
[i
].size
;
1035 bank
->prot_blocks
[num_prot_blocks
- 1].size
<<= 1;
1038 bank
->num_prot_blocks
= num_prot_blocks
;
1039 assert((bank
->size
>> 10) == flash_size_in_kb
);
1041 stm32x_info
->probed
= 1;
1045 static int stm32x_auto_probe(struct flash_bank
*bank
)
1047 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
1048 if (stm32x_info
->probed
)
1050 return stm32x_probe(bank
);
1053 static int get_stm32x_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
1055 uint32_t dbgmcu_idcode
;
1057 /* read stm32 device id register */
1058 int retval
= stm32x_get_device_id(bank
, &dbgmcu_idcode
);
1059 if (retval
!= ERROR_OK
)
1062 uint16_t device_id
= dbgmcu_idcode
& 0xfff;
1063 uint16_t rev_id
= dbgmcu_idcode
>> 16;
1064 const char *device_str
;
1065 const char *rev_str
= NULL
;
1067 switch (device_id
) {
1069 device_str
= "STM32F2xx";
1109 device_str
= "STM32F4xx";
1135 device_str
= "STM32F446";
1149 device_str
= "STM32F4xx (Low Power)";
1171 device_str
= "STM32F7[4|5]x";
1185 device_str
= "STM32F7[6|7]x";
1195 device_str
= "STM32F7[2|3]x";
1205 device_str
= "STM32F4[1|2]3";
1215 snprintf(buf
, buf_size
, "Cannot identify target as a STM32F2/4/7\n");
1219 if (rev_str
!= NULL
)
1220 snprintf(buf
, buf_size
, "%s - Rev: %s", device_str
, rev_str
);
1222 snprintf(buf
, buf_size
, "%s - Rev: unknown (0x%04x)", device_str
, rev_id
);
1227 COMMAND_HANDLER(stm32x_handle_lock_command
)
1229 struct target
*target
= NULL
;
1230 struct stm32x_flash_bank
*stm32x_info
= NULL
;
1233 return ERROR_COMMAND_SYNTAX_ERROR
;
1235 struct flash_bank
*bank
;
1236 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1237 if (ERROR_OK
!= retval
)
1240 stm32x_info
= bank
->driver_priv
;
1241 target
= bank
->target
;
1243 if (target
->state
!= TARGET_HALTED
) {
1244 LOG_INFO("Target not halted");
1245 /* return ERROR_TARGET_NOT_HALTED; */
1248 if (stm32x_read_options(bank
) != ERROR_OK
) {
1249 command_print(CMD_CTX
, "%s failed to read options", bank
->driver
->name
);
1253 /* set readout protection */
1254 stm32x_info
->option_bytes
.RDP
= 0;
1256 if (stm32x_write_options(bank
) != ERROR_OK
) {
1257 command_print(CMD_CTX
, "%s failed to lock device", bank
->driver
->name
);
1261 command_print(CMD_CTX
, "%s locked", bank
->driver
->name
);
1266 COMMAND_HANDLER(stm32x_handle_unlock_command
)
1268 struct target
*target
= NULL
;
1269 struct stm32x_flash_bank
*stm32x_info
= NULL
;
1272 return ERROR_COMMAND_SYNTAX_ERROR
;
1274 struct flash_bank
*bank
;
1275 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1276 if (ERROR_OK
!= retval
)
1279 stm32x_info
= bank
->driver_priv
;
1280 target
= bank
->target
;
1282 if (target
->state
!= TARGET_HALTED
) {
1283 LOG_INFO("Target not halted");
1284 /* return ERROR_TARGET_NOT_HALTED; */
1287 if (stm32x_read_options(bank
) != ERROR_OK
) {
1288 command_print(CMD_CTX
, "%s failed to read options", bank
->driver
->name
);
1292 /* clear readout protection and complementary option bytes
1293 * this will also force a device unlock if set */
1294 stm32x_info
->option_bytes
.RDP
= 0xAA;
1295 if (stm32x_info
->has_optcr2_pcrop
) {
1296 stm32x_info
->option_bytes
.optcr2_pcrop
= OPTCR2_PCROP_RDP
| (~1U << bank
->num_sectors
);
1299 if (stm32x_write_options(bank
) != ERROR_OK
) {
1300 command_print(CMD_CTX
, "%s failed to unlock device", bank
->driver
->name
);
1304 command_print(CMD_CTX
, "%s unlocked.\n"
1305 "INFO: a reset or power cycle is required "
1306 "for the new settings to take effect.", bank
->driver
->name
);
1311 static int stm32x_mass_erase(struct flash_bank
*bank
)
1315 struct target
*target
= bank
->target
;
1316 struct stm32x_flash_bank
*stm32x_info
= NULL
;
1318 if (target
->state
!= TARGET_HALTED
) {
1319 LOG_ERROR("Target not halted");
1320 return ERROR_TARGET_NOT_HALTED
;
1323 stm32x_info
= bank
->driver_priv
;
1325 retval
= stm32x_unlock_reg(target
);
1326 if (retval
!= ERROR_OK
)
1329 /* mass erase flash memory */
1330 if (stm32x_info
->has_large_mem
)
1331 flash_mer
= FLASH_MER
| FLASH_MER1
;
1333 flash_mer
= FLASH_MER
;
1335 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), flash_mer
);
1336 if (retval
!= ERROR_OK
)
1338 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
),
1339 flash_mer
| FLASH_STRT
);
1340 if (retval
!= ERROR_OK
)
1343 retval
= stm32x_wait_status_busy(bank
, FLASH_MASS_ERASE_TIMEOUT
);
1344 if (retval
!= ERROR_OK
)
1347 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_LOCK
);
1348 if (retval
!= ERROR_OK
)
1354 COMMAND_HANDLER(stm32x_handle_mass_erase_command
)
1359 command_print(CMD_CTX
, "stm32x mass_erase <bank>");
1360 return ERROR_COMMAND_SYNTAX_ERROR
;
1363 struct flash_bank
*bank
;
1364 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1365 if (ERROR_OK
!= retval
)
1368 retval
= stm32x_mass_erase(bank
);
1369 if (retval
== ERROR_OK
) {
1370 /* set all sectors as erased */
1371 for (i
= 0; i
< bank
->num_sectors
; i
++)
1372 bank
->sectors
[i
].is_erased
= 1;
1374 command_print(CMD_CTX
, "stm32x mass erase complete");
1376 command_print(CMD_CTX
, "stm32x mass erase failed");
1382 COMMAND_HANDLER(stm32f2x_handle_options_read_command
)
1385 struct flash_bank
*bank
;
1386 struct stm32x_flash_bank
*stm32x_info
= NULL
;
1388 if (CMD_ARGC
!= 1) {
1389 command_print(CMD_CTX
, "stm32f2x options_read <bank>");
1390 return ERROR_COMMAND_SYNTAX_ERROR
;
1393 retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1394 if (ERROR_OK
!= retval
)
1397 retval
= stm32x_read_options(bank
);
1398 if (ERROR_OK
!= retval
)
1401 stm32x_info
= bank
->driver_priv
;
1402 if (stm32x_info
->has_extra_options
) {
1403 if (stm32x_info
->has_boot_addr
) {
1404 uint32_t boot_addr
= stm32x_info
->option_bytes
.boot_addr
;
1406 command_print(CMD_CTX
, "stm32f2x user_options 0x%03X,"
1407 " boot_add0 0x%04X, boot_add1 0x%04X",
1408 stm32x_info
->option_bytes
.user_options
,
1409 boot_addr
& 0xffff, (boot_addr
& 0xffff0000) >> 16);
1410 if (stm32x_info
->has_optcr2_pcrop
) {
1411 command_print(CMD_CTX
, "stm32f2x optcr2_pcrop 0x%08X",
1412 stm32x_info
->option_bytes
.optcr2_pcrop
);
1415 command_print(CMD_CTX
, "stm32f2x user_options 0x%03X",
1416 stm32x_info
->option_bytes
.user_options
);
1419 command_print(CMD_CTX
, "stm32f2x user_options 0x%02X",
1420 stm32x_info
->option_bytes
.user_options
);
1427 COMMAND_HANDLER(stm32f2x_handle_options_write_command
)
1430 struct flash_bank
*bank
;
1431 struct stm32x_flash_bank
*stm32x_info
= NULL
;
1432 uint16_t user_options
, boot_addr0
, boot_addr1
, options_mask
;
1435 command_print(CMD_CTX
, "stm32f2x options_write <bank> ...");
1436 return ERROR_COMMAND_SYNTAX_ERROR
;
1439 retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1440 if (ERROR_OK
!= retval
)
1443 retval
= stm32x_read_options(bank
);
1444 if (ERROR_OK
!= retval
)
1447 stm32x_info
= bank
->driver_priv
;
1448 if (stm32x_info
->has_boot_addr
) {
1449 if (CMD_ARGC
!= 4) {
1450 command_print(CMD_CTX
, "stm32f2x options_write <bank> <user_options>"
1451 " <boot_addr0> <boot_addr1>");
1452 return ERROR_COMMAND_SYNTAX_ERROR
;
1454 COMMAND_PARSE_NUMBER(u16
, CMD_ARGV
[2], boot_addr0
);
1455 COMMAND_PARSE_NUMBER(u16
, CMD_ARGV
[3], boot_addr1
);
1456 stm32x_info
->option_bytes
.boot_addr
= boot_addr0
| (((uint32_t) boot_addr1
) << 16);
1458 if (CMD_ARGC
!= 2) {
1459 command_print(CMD_CTX
, "stm32f2x options_write <bank> <user_options>");
1460 return ERROR_COMMAND_SYNTAX_ERROR
;
1464 COMMAND_PARSE_NUMBER(u16
, CMD_ARGV
[1], user_options
);
1465 options_mask
= !stm32x_info
->has_extra_options
? ~0xfc :
1466 ~(((0xf00 << (stm32x_info
->protection_bits
- 12)) | 0xff) & 0xffc);
1467 if (user_options
& options_mask
) {
1468 command_print(CMD_CTX
, "stm32f2x invalid user_options");
1469 return ERROR_COMMAND_ARGUMENT_INVALID
;
1472 stm32x_info
->option_bytes
.user_options
= user_options
;
1474 if (stm32x_write_options(bank
) != ERROR_OK
) {
1475 command_print(CMD_CTX
, "stm32f2x failed to write options");
1479 /* switching between single- and dual-bank modes requires re-probe */
1480 /* ... and reprogramming of whole flash */
1481 stm32x_info
->probed
= 0;
1483 command_print(CMD_CTX
, "stm32f2x write options complete.\n"
1484 "INFO: a reset or power cycle is required "
1485 "for the new settings to take effect.");
1489 COMMAND_HANDLER(stm32f2x_handle_optcr2_write_command
)
1492 struct flash_bank
*bank
;
1493 struct stm32x_flash_bank
*stm32x_info
= NULL
;
1494 uint32_t optcr2_pcrop
;
1496 if (CMD_ARGC
!= 2) {
1497 command_print(CMD_CTX
, "stm32f2x optcr2_write <bank> <optcr2_value>");
1498 return ERROR_COMMAND_SYNTAX_ERROR
;
1501 retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1502 if (ERROR_OK
!= retval
)
1505 stm32x_info
= bank
->driver_priv
;
1506 if (!stm32x_info
->has_optcr2_pcrop
) {
1507 command_print(CMD_CTX
, "no optcr2 register");
1508 return ERROR_COMMAND_ARGUMENT_INVALID
;
1511 command_print(CMD_CTX
, "INFO: To disable PCROP, set PCROP_RDP"
1512 " with PCROPi bits STILL SET, then\nlock device and"
1513 " finally unlock it. Clears PCROP and mass erases flash.");
1515 retval
= stm32x_read_options(bank
);
1516 if (ERROR_OK
!= retval
)
1519 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], optcr2_pcrop
);
1520 stm32x_info
->option_bytes
.optcr2_pcrop
= optcr2_pcrop
;
1522 if (stm32x_write_options(bank
) != ERROR_OK
) {
1523 command_print(CMD_CTX
, "stm32f2x failed to write options");
1527 command_print(CMD_CTX
, "stm32f2x optcr2_write complete.");
1531 static const struct command_registration stm32x_exec_command_handlers
[] = {
1534 .handler
= stm32x_handle_lock_command
,
1535 .mode
= COMMAND_EXEC
,
1537 .help
= "Lock entire flash device.",
1541 .handler
= stm32x_handle_unlock_command
,
1542 .mode
= COMMAND_EXEC
,
1544 .help
= "Unlock entire protected flash device.",
1547 .name
= "mass_erase",
1548 .handler
= stm32x_handle_mass_erase_command
,
1549 .mode
= COMMAND_EXEC
,
1551 .help
= "Erase entire flash device.",
1554 .name
= "options_read",
1555 .handler
= stm32f2x_handle_options_read_command
,
1556 .mode
= COMMAND_EXEC
,
1558 .help
= "Read and display device option bytes.",
1561 .name
= "options_write",
1562 .handler
= stm32f2x_handle_options_write_command
,
1563 .mode
= COMMAND_EXEC
,
1564 .usage
= "bank_id user_options [ boot_add0 boot_add1 ]",
1565 .help
= "Write option bytes",
1568 .name
= "optcr2_write",
1569 .handler
= stm32f2x_handle_optcr2_write_command
,
1570 .mode
= COMMAND_EXEC
,
1571 .usage
= "bank_id optcr2",
1572 .help
= "Write optcr2 word",
1575 COMMAND_REGISTRATION_DONE
1578 static const struct command_registration stm32x_command_handlers
[] = {
1581 .mode
= COMMAND_ANY
,
1582 .help
= "stm32f2x flash command group",
1584 .chain
= stm32x_exec_command_handlers
,
1586 COMMAND_REGISTRATION_DONE
1589 struct flash_driver stm32f2x_flash
= {
1591 .commands
= stm32x_command_handlers
,
1592 .flash_bank_command
= stm32x_flash_bank_command
,
1593 .erase
= stm32x_erase
,
1594 .protect
= stm32x_protect
,
1595 .write
= stm32x_write
,
1596 .read
= default_flash_read
,
1597 .probe
= stm32x_probe
,
1598 .auto_probe
= stm32x_auto_probe
,
1599 .erase_check
= default_flash_blank_check
,
1600 .protect_check
= stm32x_protect_check
,
1601 .info
= get_stm32x_info
,
1602 .free_driver_priv
= default_flash_free_driver_priv
,
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