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flash/nor/stm32f1x: lock flash in case of error
[openocd.git] / src / flash / nor / stm32f1x.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2011 by Andreas Fritiofson *
9 * andreas.fritiofson@gmail.com *
10 *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
24
25 #ifdef HAVE_CONFIG_H
26 #include "config.h"
27 #endif
28
29 #include "imp.h"
30 #include <helper/binarybuffer.h>
31 #include <target/algorithm.h>
32 #include <target/cortex_m.h>
33
34 /* stm32x register locations */
35
36 #define FLASH_REG_BASE_B0 0x40022000
37 #define FLASH_REG_BASE_B1 0x40022040
38
39 #define STM32_FLASH_ACR 0x00
40 #define STM32_FLASH_KEYR 0x04
41 #define STM32_FLASH_OPTKEYR 0x08
42 #define STM32_FLASH_SR 0x0C
43 #define STM32_FLASH_CR 0x10
44 #define STM32_FLASH_AR 0x14
45 #define STM32_FLASH_OBR 0x1C
46 #define STM32_FLASH_WRPR 0x20
47
48 /* TODO: Check if code using these really should be hard coded to bank 0.
49 * There are valid cases, on dual flash devices the protection of the
50 * second bank is done on the bank0 reg's. */
51 #define STM32_FLASH_ACR_B0 0x40022000
52 #define STM32_FLASH_KEYR_B0 0x40022004
53 #define STM32_FLASH_OPTKEYR_B0 0x40022008
54 #define STM32_FLASH_SR_B0 0x4002200C
55 #define STM32_FLASH_CR_B0 0x40022010
56 #define STM32_FLASH_AR_B0 0x40022014
57 #define STM32_FLASH_OBR_B0 0x4002201C
58 #define STM32_FLASH_WRPR_B0 0x40022020
59
60 /* option byte location */
61
62 #define STM32_OB_RDP 0x1FFFF800
63 #define STM32_OB_USER 0x1FFFF802
64 #define STM32_OB_DATA0 0x1FFFF804
65 #define STM32_OB_DATA1 0x1FFFF806
66 #define STM32_OB_WRP0 0x1FFFF808
67 #define STM32_OB_WRP1 0x1FFFF80A
68 #define STM32_OB_WRP2 0x1FFFF80C
69 #define STM32_OB_WRP3 0x1FFFF80E
70
71 /* FLASH_CR register bits */
72
73 #define FLASH_PG (1 << 0)
74 #define FLASH_PER (1 << 1)
75 #define FLASH_MER (1 << 2)
76 #define FLASH_OPTPG (1 << 4)
77 #define FLASH_OPTER (1 << 5)
78 #define FLASH_STRT (1 << 6)
79 #define FLASH_LOCK (1 << 7)
80 #define FLASH_OPTWRE (1 << 9)
81 #define FLASH_OBL_LAUNCH (1 << 13) /* except stm32f1x series */
82
83 /* FLASH_SR register bits */
84
85 #define FLASH_BSY (1 << 0)
86 #define FLASH_PGERR (1 << 2)
87 #define FLASH_WRPRTERR (1 << 4)
88 #define FLASH_EOP (1 << 5)
89
90 /* STM32_FLASH_OBR bit definitions (reading) */
91
92 #define OPT_ERROR 0
93 #define OPT_READOUT 1
94 #define OPT_RDWDGSW 2
95 #define OPT_RDRSTSTOP 3
96 #define OPT_RDRSTSTDBY 4
97 #define OPT_BFB2 5 /* dual flash bank only */
98
99 /* register unlock keys */
100
101 #define KEY1 0x45670123
102 #define KEY2 0xCDEF89AB
103
104 /* timeout values */
105
106 #define FLASH_WRITE_TIMEOUT 10
107 #define FLASH_ERASE_TIMEOUT 100
108
109 struct stm32x_options {
110 uint8_t rdp;
111 uint8_t user;
112 uint16_t data;
113 uint32_t protection;
114 };
115
116 struct stm32x_flash_bank {
117 struct stm32x_options option_bytes;
118 int ppage_size;
119 bool probed;
120
121 bool has_dual_banks;
122 /* used to access dual flash bank stm32xl */
123 bool can_load_options;
124 uint32_t register_base;
125 uint8_t default_rdp;
126 int user_data_offset;
127 int option_offset;
128 uint32_t user_bank_size;
129 };
130
131 static int stm32x_mass_erase(struct flash_bank *bank);
132 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id);
133 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
134 uint32_t address, uint32_t hwords_count);
135
136 /* flash bank stm32x <base> <size> 0 0 <target#>
137 */
138 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
139 {
140 struct stm32x_flash_bank *stm32x_info;
141
142 if (CMD_ARGC < 6)
143 return ERROR_COMMAND_SYNTAX_ERROR;
144
145 stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
146
147 bank->driver_priv = stm32x_info;
148 stm32x_info->probed = false;
149 stm32x_info->has_dual_banks = false;
150 stm32x_info->can_load_options = false;
151 stm32x_info->register_base = FLASH_REG_BASE_B0;
152 stm32x_info->user_bank_size = bank->size;
153
154 /* The flash write must be aligned to a halfword boundary */
155 bank->write_start_alignment = bank->write_end_alignment = 2;
156
157 return ERROR_OK;
158 }
159
160 static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
161 {
162 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
163 return reg + stm32x_info->register_base;
164 }
165
166 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
167 {
168 struct target *target = bank->target;
169 return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
170 }
171
172 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
173 {
174 struct target *target = bank->target;
175 uint32_t status;
176 int retval = ERROR_OK;
177
178 /* wait for busy to clear */
179 for (;;) {
180 retval = stm32x_get_flash_status(bank, &status);
181 if (retval != ERROR_OK)
182 return retval;
183 LOG_DEBUG("status: 0x%" PRIx32 "", status);
184 if ((status & FLASH_BSY) == 0)
185 break;
186 if (timeout-- <= 0) {
187 LOG_ERROR("timed out waiting for flash");
188 return ERROR_FLASH_BUSY;
189 }
190 alive_sleep(1);
191 }
192
193 if (status & FLASH_WRPRTERR) {
194 LOG_ERROR("stm32x device protected");
195 retval = ERROR_FLASH_PROTECTED;
196 }
197
198 if (status & FLASH_PGERR) {
199 LOG_ERROR("stm32x device programming failed / flash not erased");
200 retval = ERROR_FLASH_OPERATION_FAILED;
201 }
202
203 /* Clear but report errors */
204 if (status & (FLASH_WRPRTERR | FLASH_PGERR)) {
205 /* If this operation fails, we ignore it and report the original
206 * retval
207 */
208 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
209 FLASH_WRPRTERR | FLASH_PGERR);
210 }
211 return retval;
212 }
213
214 static int stm32x_check_operation_supported(struct flash_bank *bank)
215 {
216 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
217
218 /* if we have a dual flash bank device then
219 * we need to perform option byte stuff on bank0 only */
220 if (stm32x_info->register_base != FLASH_REG_BASE_B0) {
221 LOG_ERROR("Option byte operations must use bank 0");
222 return ERROR_FLASH_OPERATION_FAILED;
223 }
224
225 return ERROR_OK;
226 }
227
228 static int stm32x_read_options(struct flash_bank *bank)
229 {
230 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
231 struct target *target = bank->target;
232 uint32_t option_bytes;
233 int retval;
234
235 /* read user and read protection option bytes, user data option bytes */
236 retval = target_read_u32(target, STM32_FLASH_OBR_B0, &option_bytes);
237 if (retval != ERROR_OK)
238 return retval;
239
240 stm32x_info->option_bytes.rdp = (option_bytes & (1 << OPT_READOUT)) ? 0 : stm32x_info->default_rdp;
241 stm32x_info->option_bytes.user = (option_bytes >> stm32x_info->option_offset >> 2) & 0xff;
242 stm32x_info->option_bytes.data = (option_bytes >> stm32x_info->user_data_offset) & 0xffff;
243
244 /* read write protection option bytes */
245 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &stm32x_info->option_bytes.protection);
246 if (retval != ERROR_OK)
247 return retval;
248
249 return ERROR_OK;
250 }
251
252 static int stm32x_erase_options(struct flash_bank *bank)
253 {
254 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
255 struct target *target = bank->target;
256
257 /* read current options */
258 stm32x_read_options(bank);
259
260 /* unlock flash registers */
261 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
262 if (retval != ERROR_OK)
263 return retval;
264 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
265 if (retval != ERROR_OK)
266 goto flash_lock;
267
268 /* unlock option flash registers */
269 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
270 if (retval != ERROR_OK)
271 goto flash_lock;
272 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
273 if (retval != ERROR_OK)
274 goto flash_lock;
275
276 /* erase option bytes */
277 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_OPTWRE);
278 if (retval != ERROR_OK)
279 goto flash_lock;
280 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
281 if (retval != ERROR_OK)
282 goto flash_lock;
283
284 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
285 if (retval != ERROR_OK)
286 goto flash_lock;
287
288 /* clear read protection option byte
289 * this will also force a device unlock if set */
290 stm32x_info->option_bytes.rdp = stm32x_info->default_rdp;
291
292 return ERROR_OK;
293
294 flash_lock:
295 target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
296 return retval;
297 }
298
299 static int stm32x_write_options(struct flash_bank *bank)
300 {
301 struct stm32x_flash_bank *stm32x_info = NULL;
302 struct target *target = bank->target;
303
304 stm32x_info = bank->driver_priv;
305
306 /* unlock flash registers */
307 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
308 if (retval != ERROR_OK)
309 return retval;
310 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
311 if (retval != ERROR_OK)
312 goto flash_lock;
313
314 /* unlock option flash registers */
315 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
316 if (retval != ERROR_OK)
317 goto flash_lock;
318 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
319 if (retval != ERROR_OK)
320 goto flash_lock;
321
322 /* program option bytes */
323 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTPG | FLASH_OPTWRE);
324 if (retval != ERROR_OK)
325 goto flash_lock;
326
327 uint8_t opt_bytes[16];
328
329 target_buffer_set_u16(target, opt_bytes, stm32x_info->option_bytes.rdp);
330 target_buffer_set_u16(target, opt_bytes + 2, stm32x_info->option_bytes.user);
331 target_buffer_set_u16(target, opt_bytes + 4, stm32x_info->option_bytes.data & 0xff);
332 target_buffer_set_u16(target, opt_bytes + 6, (stm32x_info->option_bytes.data >> 8) & 0xff);
333 target_buffer_set_u16(target, opt_bytes + 8, stm32x_info->option_bytes.protection & 0xff);
334 target_buffer_set_u16(target, opt_bytes + 10, (stm32x_info->option_bytes.protection >> 8) & 0xff);
335 target_buffer_set_u16(target, opt_bytes + 12, (stm32x_info->option_bytes.protection >> 16) & 0xff);
336 target_buffer_set_u16(target, opt_bytes + 14, (stm32x_info->option_bytes.protection >> 24) & 0xff);
337
338 /* Block write is preferred in favour of operation with ancient ST-Link
339 * firmwares without 16-bit memory access. See
340 * 480: flash: stm32f1x: write option bytes using the loader
341 * https://review.openocd.org/c/openocd/+/480
342 */
343 retval = stm32x_write_block(bank, opt_bytes, STM32_OB_RDP, sizeof(opt_bytes) / 2);
344
345 flash_lock:
346 {
347 int retval2 = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
348 if (retval == ERROR_OK)
349 retval = retval2;
350 }
351 return retval;
352 }
353
354 static int stm32x_protect_check(struct flash_bank *bank)
355 {
356 struct target *target = bank->target;
357 uint32_t protection;
358
359 int retval = stm32x_check_operation_supported(bank);
360 if (retval != ERROR_OK)
361 return retval;
362
363 /* medium density - each bit refers to a 4 sector protection block
364 * high density - each bit refers to a 2 sector protection block
365 * bit 31 refers to all remaining sectors in a bank */
366 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
367 if (retval != ERROR_OK)
368 return retval;
369
370 for (unsigned int i = 0; i < bank->num_prot_blocks; i++)
371 bank->prot_blocks[i].is_protected = (protection & (1 << i)) ? 0 : 1;
372
373 return ERROR_OK;
374 }
375
376 static int stm32x_erase(struct flash_bank *bank, unsigned int first,
377 unsigned int last)
378 {
379 struct target *target = bank->target;
380
381 if (bank->target->state != TARGET_HALTED) {
382 LOG_ERROR("Target not halted");
383 return ERROR_TARGET_NOT_HALTED;
384 }
385
386 if ((first == 0) && (last == (bank->num_sectors - 1)))
387 return stm32x_mass_erase(bank);
388
389 /* unlock flash registers */
390 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
391 if (retval != ERROR_OK)
392 return retval;
393 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
394 if (retval != ERROR_OK)
395 goto flash_lock;
396
397 for (unsigned int i = first; i <= last; i++) {
398 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER);
399 if (retval != ERROR_OK)
400 goto flash_lock;
401 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_AR),
402 bank->base + bank->sectors[i].offset);
403 if (retval != ERROR_OK)
404 goto flash_lock;
405 retval = target_write_u32(target,
406 stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER | FLASH_STRT);
407 if (retval != ERROR_OK)
408 goto flash_lock;
409
410 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
411 if (retval != ERROR_OK)
412 goto flash_lock;
413 }
414
415 flash_lock:
416 {
417 int retval2 = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
418 if (retval == ERROR_OK)
419 retval = retval2;
420 }
421 return retval;
422 }
423
424 static int stm32x_protect(struct flash_bank *bank, int set, unsigned int first,
425 unsigned int last)
426 {
427 struct target *target = bank->target;
428 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
429
430 if (target->state != TARGET_HALTED) {
431 LOG_ERROR("Target not halted");
432 return ERROR_TARGET_NOT_HALTED;
433 }
434
435 int retval = stm32x_check_operation_supported(bank);
436 if (retval != ERROR_OK)
437 return retval;
438
439 retval = stm32x_erase_options(bank);
440 if (retval != ERROR_OK) {
441 LOG_ERROR("stm32x failed to erase options");
442 return retval;
443 }
444
445 for (unsigned int i = first; i <= last; i++) {
446 if (set)
447 stm32x_info->option_bytes.protection &= ~(1 << i);
448 else
449 stm32x_info->option_bytes.protection |= (1 << i);
450 }
451
452 return stm32x_write_options(bank);
453 }
454
455 static int stm32x_write_block_async(struct flash_bank *bank, const uint8_t *buffer,
456 uint32_t address, uint32_t hwords_count)
457 {
458 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
459 struct target *target = bank->target;
460 uint32_t buffer_size;
461 struct working_area *write_algorithm;
462 struct working_area *source;
463 struct armv7m_algorithm armv7m_info;
464 int retval;
465
466 static const uint8_t stm32x_flash_write_code[] = {
467 #include "../../../contrib/loaders/flash/stm32/stm32f1x.inc"
468 };
469
470 /* flash write code */
471 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
472 &write_algorithm) != ERROR_OK) {
473 LOG_WARNING("no working area available, can't do block memory writes");
474 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
475 }
476
477 retval = target_write_buffer(target, write_algorithm->address,
478 sizeof(stm32x_flash_write_code), stm32x_flash_write_code);
479 if (retval != ERROR_OK) {
480 target_free_working_area(target, write_algorithm);
481 return retval;
482 }
483
484 /* memory buffer */
485 buffer_size = target_get_working_area_avail(target);
486 buffer_size = MIN(hwords_count * 2, MAX(buffer_size, 256));
487 /* Normally we allocate all available working area.
488 * MIN shrinks buffer_size if the size of the written block is smaller.
489 * MAX prevents using async algo if the available working area is smaller
490 * than 256, the following allocation fails with
491 * ERROR_TARGET_RESOURCE_NOT_AVAILABLE and slow flashing takes place.
492 */
493
494 retval = target_alloc_working_area(target, buffer_size, &source);
495 /* Allocated size is always 32-bit word aligned */
496 if (retval != ERROR_OK) {
497 target_free_working_area(target, write_algorithm);
498 LOG_WARNING("no large enough working area available, can't do block memory writes");
499 /* target_alloc_working_area() may return ERROR_FAIL if area backup fails:
500 * convert any error to ERROR_TARGET_RESOURCE_NOT_AVAILABLE
501 */
502 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
503 }
504
505 struct reg_param reg_params[5];
506
507 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
508 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* count (halfword-16bit) */
509 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* buffer start */
510 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* buffer end */
511 init_reg_param(&reg_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
512
513 buf_set_u32(reg_params[0].value, 0, 32, stm32x_info->register_base);
514 buf_set_u32(reg_params[1].value, 0, 32, hwords_count);
515 buf_set_u32(reg_params[2].value, 0, 32, source->address);
516 buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
517 buf_set_u32(reg_params[4].value, 0, 32, address);
518
519 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
520 armv7m_info.core_mode = ARM_MODE_THREAD;
521
522 retval = target_run_flash_async_algorithm(target, buffer, hwords_count, 2,
523 0, NULL,
524 ARRAY_SIZE(reg_params), reg_params,
525 source->address, source->size,
526 write_algorithm->address, 0,
527 &armv7m_info);
528
529 if (retval == ERROR_FLASH_OPERATION_FAILED) {
530 /* Actually we just need to check for programming errors
531 * stm32x_wait_status_busy also reports error and clears status bits.
532 *
533 * Target algo returns flash status in r0 only if properly finished.
534 * It is safer to re-read status register.
535 */
536 int retval2 = stm32x_wait_status_busy(bank, 5);
537 if (retval2 != ERROR_OK)
538 retval = retval2;
539
540 LOG_ERROR("flash write failed just before address 0x%"PRIx32,
541 buf_get_u32(reg_params[4].value, 0, 32));
542 }
543
544 for (unsigned int i = 0; i < ARRAY_SIZE(reg_params); i++)
545 destroy_reg_param(&reg_params[i]);
546
547 target_free_working_area(target, source);
548 target_free_working_area(target, write_algorithm);
549
550 return retval;
551 }
552
553 /** Writes a block to flash either using target algorithm
554 * or use fallback, host controlled halfword-by-halfword access.
555 * Flash controller must be unlocked before this call.
556 */
557 static int stm32x_write_block(struct flash_bank *bank,
558 const uint8_t *buffer, uint32_t address, uint32_t hwords_count)
559 {
560 struct target *target = bank->target;
561
562 /* The flash write must be aligned to a halfword boundary.
563 * The flash infrastructure ensures it, do just a security check
564 */
565 assert(address % 2 == 0);
566
567 /* try using a block write - on ARM architecture or... */
568 int retval = stm32x_write_block_async(bank, buffer, address, hwords_count);
569
570 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
571 /* if block write failed (no sufficient working area),
572 * we use normal (slow) single halfword accesses */
573 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
574
575 while (hwords_count > 0) {
576 retval = target_write_memory(target, address, 2, 1, buffer);
577 if (retval != ERROR_OK)
578 return retval;
579
580 retval = stm32x_wait_status_busy(bank, 5);
581 if (retval != ERROR_OK)
582 return retval;
583
584 hwords_count--;
585 buffer += 2;
586 address += 2;
587 }
588 }
589 return retval;
590 }
591
592 static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
593 uint32_t offset, uint32_t count)
594 {
595 struct target *target = bank->target;
596
597 if (bank->target->state != TARGET_HALTED) {
598 LOG_ERROR("Target not halted");
599 return ERROR_TARGET_NOT_HALTED;
600 }
601
602 /* The flash write must be aligned to a halfword boundary.
603 * The flash infrastructure ensures it, do just a security check
604 */
605 assert(offset % 2 == 0);
606 assert(count % 2 == 0);
607
608 int retval, retval2;
609
610 /* unlock flash registers */
611 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
612 if (retval != ERROR_OK)
613 return retval;
614 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
615 if (retval != ERROR_OK)
616 goto reset_pg_and_lock;
617
618 /* enable flash programming */
619 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
620 if (retval != ERROR_OK)
621 goto reset_pg_and_lock;
622
623 /* write to flash */
624 retval = stm32x_write_block(bank, buffer, bank->base + offset, count / 2);
625
626 reset_pg_and_lock:
627 retval2 = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
628 if (retval == ERROR_OK)
629 retval = retval2;
630
631 return retval;
632 }
633
634 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
635 {
636 struct target *target = bank->target;
637 uint32_t device_id_register = 0;
638
639 if (!target_was_examined(target)) {
640 LOG_ERROR("Target not examined yet");
641 return ERROR_TARGET_NOT_EXAMINED;
642 }
643
644 switch (cortex_m_get_partno_safe(target)) {
645 case CORTEX_M0_PARTNO: /* STM32F0x devices */
646 device_id_register = 0x40015800;
647 break;
648 case CORTEX_M3_PARTNO: /* STM32F1x devices */
649 device_id_register = 0xE0042000;
650 break;
651 case CORTEX_M4_PARTNO: /* STM32F3x devices */
652 device_id_register = 0xE0042000;
653 break;
654 case CORTEX_M23_PARTNO: /* GD32E23x devices */
655 device_id_register = 0x40015800;
656 break;
657 default:
658 LOG_ERROR("Cannot identify target as a stm32x");
659 return ERROR_FAIL;
660 }
661
662 /* read stm32 device id register */
663 int retval = target_read_u32(target, device_id_register, device_id);
664 if (retval != ERROR_OK)
665 return retval;
666
667 return retval;
668 }
669
670 static int stm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_in_kb)
671 {
672 struct target *target = bank->target;
673 uint32_t flash_size_reg;
674
675 if (!target_was_examined(target)) {
676 LOG_ERROR("Target not examined yet");
677 return ERROR_TARGET_NOT_EXAMINED;
678 }
679
680 switch (cortex_m_get_partno_safe(target)) {
681 case CORTEX_M0_PARTNO: /* STM32F0x devices */
682 flash_size_reg = 0x1FFFF7CC;
683 break;
684 case CORTEX_M3_PARTNO: /* STM32F1x devices */
685 flash_size_reg = 0x1FFFF7E0;
686 break;
687 case CORTEX_M4_PARTNO: /* STM32F3x devices */
688 flash_size_reg = 0x1FFFF7CC;
689 break;
690 case CORTEX_M23_PARTNO: /* GD32E23x devices */
691 flash_size_reg = 0x1FFFF7E0;
692 break;
693 default:
694 LOG_ERROR("Cannot identify target as a stm32x");
695 return ERROR_FAIL;
696 }
697
698 int retval = target_read_u16(target, flash_size_reg, flash_size_in_kb);
699 if (retval != ERROR_OK)
700 return retval;
701
702 return retval;
703 }
704
705 static int stm32x_probe(struct flash_bank *bank)
706 {
707 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
708 uint16_t flash_size_in_kb;
709 uint16_t max_flash_size_in_kb;
710 uint32_t dbgmcu_idcode;
711 int page_size;
712 uint32_t base_address = 0x08000000;
713
714 stm32x_info->probed = false;
715 stm32x_info->register_base = FLASH_REG_BASE_B0;
716 stm32x_info->user_data_offset = 10;
717 stm32x_info->option_offset = 0;
718
719 /* default factory read protection level 0 */
720 stm32x_info->default_rdp = 0xA5;
721
722 /* read stm32 device id register */
723 int retval = stm32x_get_device_id(bank, &dbgmcu_idcode);
724 if (retval != ERROR_OK)
725 return retval;
726
727 LOG_INFO("device id = 0x%08" PRIx32 "", dbgmcu_idcode);
728
729 uint16_t device_id = dbgmcu_idcode & 0xfff;
730 uint16_t rev_id = dbgmcu_idcode >> 16;
731
732 /* set page size, protection granularity and max flash size depending on family */
733 switch (device_id) {
734 case 0x440: /* stm32f05x */
735 page_size = 1024;
736 stm32x_info->ppage_size = 4;
737 max_flash_size_in_kb = 64;
738 stm32x_info->user_data_offset = 16;
739 stm32x_info->option_offset = 6;
740 stm32x_info->default_rdp = 0xAA;
741 stm32x_info->can_load_options = true;
742 break;
743 case 0x444: /* stm32f03x */
744 case 0x445: /* stm32f04x */
745 page_size = 1024;
746 stm32x_info->ppage_size = 4;
747 max_flash_size_in_kb = 32;
748 stm32x_info->user_data_offset = 16;
749 stm32x_info->option_offset = 6;
750 stm32x_info->default_rdp = 0xAA;
751 stm32x_info->can_load_options = true;
752 break;
753 case 0x448: /* stm32f07x */
754 page_size = 2048;
755 stm32x_info->ppage_size = 4;
756 max_flash_size_in_kb = 128;
757 stm32x_info->user_data_offset = 16;
758 stm32x_info->option_offset = 6;
759 stm32x_info->default_rdp = 0xAA;
760 stm32x_info->can_load_options = true;
761 break;
762 case 0x442: /* stm32f09x */
763 page_size = 2048;
764 stm32x_info->ppage_size = 4;
765 max_flash_size_in_kb = 256;
766 stm32x_info->user_data_offset = 16;
767 stm32x_info->option_offset = 6;
768 stm32x_info->default_rdp = 0xAA;
769 stm32x_info->can_load_options = true;
770 break;
771 case 0x410: /* stm32f1x medium-density */
772 page_size = 1024;
773 stm32x_info->ppage_size = 4;
774 max_flash_size_in_kb = 128;
775 /* GigaDevice GD32F1x0 & GD32F3x0 & GD32E23x series devices
776 share DEV_ID with STM32F101/2/3 medium-density line,
777 however they use a REV_ID different from any STM32 device.
778 The main difference is another offset of user option bits
779 (like WDG_SW, nRST_STOP, nRST_STDBY) in option byte register
780 (FLASH_OBR/FMC_OBSTAT 0x4002201C).
781 This caused problems e.g. during flash block programming
782 because of unexpected active hardware watchog. */
783 switch (rev_id) {
784 case 0x1303: /* gd32f1x0 */
785 stm32x_info->user_data_offset = 16;
786 stm32x_info->option_offset = 6;
787 max_flash_size_in_kb = 64;
788 break;
789 case 0x1704: /* gd32f3x0 */
790 stm32x_info->user_data_offset = 16;
791 stm32x_info->option_offset = 6;
792 break;
793 case 0x1909: /* gd32e23x */
794 stm32x_info->user_data_offset = 16;
795 stm32x_info->option_offset = 6;
796 max_flash_size_in_kb = 64;
797 break;
798 }
799 break;
800 case 0x412: /* stm32f1x low-density */
801 page_size = 1024;
802 stm32x_info->ppage_size = 4;
803 max_flash_size_in_kb = 32;
804 break;
805 case 0x414: /* stm32f1x high-density */
806 page_size = 2048;
807 stm32x_info->ppage_size = 2;
808 max_flash_size_in_kb = 512;
809 break;
810 case 0x418: /* stm32f1x connectivity */
811 page_size = 2048;
812 stm32x_info->ppage_size = 2;
813 max_flash_size_in_kb = 256;
814 break;
815 case 0x430: /* stm32f1 XL-density (dual flash banks) */
816 page_size = 2048;
817 stm32x_info->ppage_size = 2;
818 max_flash_size_in_kb = 1024;
819 stm32x_info->has_dual_banks = true;
820 break;
821 case 0x420: /* stm32f100xx low- and medium-density value line */
822 page_size = 1024;
823 stm32x_info->ppage_size = 4;
824 max_flash_size_in_kb = 128;
825 break;
826 case 0x428: /* stm32f100xx high-density value line */
827 page_size = 2048;
828 stm32x_info->ppage_size = 4;
829 max_flash_size_in_kb = 512;
830 break;
831 case 0x422: /* stm32f302/3xb/c */
832 page_size = 2048;
833 stm32x_info->ppage_size = 2;
834 max_flash_size_in_kb = 256;
835 stm32x_info->user_data_offset = 16;
836 stm32x_info->option_offset = 6;
837 stm32x_info->default_rdp = 0xAA;
838 stm32x_info->can_load_options = true;
839 break;
840 case 0x446: /* stm32f303xD/E */
841 page_size = 2048;
842 stm32x_info->ppage_size = 2;
843 max_flash_size_in_kb = 512;
844 stm32x_info->user_data_offset = 16;
845 stm32x_info->option_offset = 6;
846 stm32x_info->default_rdp = 0xAA;
847 stm32x_info->can_load_options = true;
848 break;
849 case 0x432: /* stm32f37x */
850 page_size = 2048;
851 stm32x_info->ppage_size = 2;
852 max_flash_size_in_kb = 256;
853 stm32x_info->user_data_offset = 16;
854 stm32x_info->option_offset = 6;
855 stm32x_info->default_rdp = 0xAA;
856 stm32x_info->can_load_options = true;
857 break;
858 case 0x438: /* stm32f33x */
859 case 0x439: /* stm32f302x6/8 */
860 page_size = 2048;
861 stm32x_info->ppage_size = 2;
862 max_flash_size_in_kb = 64;
863 stm32x_info->user_data_offset = 16;
864 stm32x_info->option_offset = 6;
865 stm32x_info->default_rdp = 0xAA;
866 stm32x_info->can_load_options = true;
867 break;
868 default:
869 LOG_WARNING("Cannot identify target as a STM32 family.");
870 return ERROR_FAIL;
871 }
872
873 /* get flash size from target. */
874 retval = stm32x_get_flash_size(bank, &flash_size_in_kb);
875
876 /* failed reading flash size or flash size invalid (early silicon),
877 * default to max target family */
878 if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
879 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
880 max_flash_size_in_kb);
881 flash_size_in_kb = max_flash_size_in_kb;
882 }
883
884 if (stm32x_info->has_dual_banks) {
885 /* split reported size into matching bank */
886 if (bank->base != 0x08080000) {
887 /* bank 0 will be fixed 512k */
888 flash_size_in_kb = 512;
889 } else {
890 flash_size_in_kb -= 512;
891 /* bank1 also uses a register offset */
892 stm32x_info->register_base = FLASH_REG_BASE_B1;
893 base_address = 0x08080000;
894 }
895 }
896
897 /* if the user sets the size manually then ignore the probed value
898 * this allows us to work around devices that have a invalid flash size register value */
899 if (stm32x_info->user_bank_size) {
900 LOG_INFO("ignoring flash probed value, using configured bank size");
901 flash_size_in_kb = stm32x_info->user_bank_size / 1024;
902 }
903
904 LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
905
906 /* did we assign flash size? */
907 assert(flash_size_in_kb != 0xffff);
908
909 /* calculate numbers of pages */
910 int num_pages = flash_size_in_kb * 1024 / page_size;
911
912 /* check that calculation result makes sense */
913 assert(num_pages > 0);
914
915 free(bank->sectors);
916 bank->sectors = NULL;
917
918 free(bank->prot_blocks);
919 bank->prot_blocks = NULL;
920
921 bank->base = base_address;
922 bank->size = (num_pages * page_size);
923
924 bank->num_sectors = num_pages;
925 bank->sectors = alloc_block_array(0, page_size, num_pages);
926 if (!bank->sectors)
927 return ERROR_FAIL;
928
929 /* calculate number of write protection blocks */
930 int num_prot_blocks = num_pages / stm32x_info->ppage_size;
931 if (num_prot_blocks > 32)
932 num_prot_blocks = 32;
933
934 bank->num_prot_blocks = num_prot_blocks;
935 bank->prot_blocks = alloc_block_array(0, stm32x_info->ppage_size * page_size, num_prot_blocks);
936 if (!bank->prot_blocks)
937 return ERROR_FAIL;
938
939 if (num_prot_blocks == 32)
940 bank->prot_blocks[31].size = (num_pages - (31 * stm32x_info->ppage_size)) * page_size;
941
942 stm32x_info->probed = true;
943
944 return ERROR_OK;
945 }
946
947 static int stm32x_auto_probe(struct flash_bank *bank)
948 {
949 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
950 if (stm32x_info->probed)
951 return ERROR_OK;
952 return stm32x_probe(bank);
953 }
954
955 #if 0
956 COMMAND_HANDLER(stm32x_handle_part_id_command)
957 {
958 return ERROR_OK;
959 }
960 #endif
961
962 static const char *get_stm32f0_revision(uint16_t rev_id)
963 {
964 const char *rev_str = NULL;
965
966 switch (rev_id) {
967 case 0x1000:
968 rev_str = "1.0";
969 break;
970 case 0x2000:
971 rev_str = "2.0";
972 break;
973 }
974 return rev_str;
975 }
976
977 static int get_stm32x_info(struct flash_bank *bank, struct command_invocation *cmd)
978 {
979 uint32_t dbgmcu_idcode;
980
981 /* read stm32 device id register */
982 int retval = stm32x_get_device_id(bank, &dbgmcu_idcode);
983 if (retval != ERROR_OK)
984 return retval;
985
986 uint16_t device_id = dbgmcu_idcode & 0xfff;
987 uint16_t rev_id = dbgmcu_idcode >> 16;
988 const char *device_str;
989 const char *rev_str = NULL;
990
991 switch (device_id) {
992 case 0x410:
993 device_str = "STM32F10x (Medium Density)";
994
995 switch (rev_id) {
996 case 0x0000:
997 rev_str = "A";
998 break;
999
1000 case 0x1303: /* gd32f1x0 */
1001 device_str = "GD32F1x0";
1002 break;
1003
1004 case 0x1704: /* gd32f3x0 */
1005 device_str = "GD32F3x0";
1006 break;
1007
1008 case 0x1909: /* gd32e23x */
1009 device_str = "GD32E23x";
1010 break;
1011
1012 case 0x2000:
1013 rev_str = "B";
1014 break;
1015
1016 case 0x2001:
1017 rev_str = "Z";
1018 break;
1019
1020 case 0x2003:
1021 rev_str = "Y";
1022 break;
1023 }
1024 break;
1025
1026 case 0x412:
1027 device_str = "STM32F10x (Low Density)";
1028
1029 switch (rev_id) {
1030 case 0x1000:
1031 rev_str = "A";
1032 break;
1033 }
1034 break;
1035
1036 case 0x414:
1037 device_str = "STM32F10x (High Density)";
1038
1039 switch (rev_id) {
1040 case 0x1000:
1041 rev_str = "A";
1042 break;
1043
1044 case 0x1001:
1045 rev_str = "Z";
1046 break;
1047
1048 case 0x1003:
1049 rev_str = "Y";
1050 break;
1051 }
1052 break;
1053
1054 case 0x418:
1055 device_str = "STM32F10x (Connectivity)";
1056
1057 switch (rev_id) {
1058 case 0x1000:
1059 rev_str = "A";
1060 break;
1061
1062 case 0x1001:
1063 rev_str = "Z";
1064 break;
1065 }
1066 break;
1067
1068 case 0x420:
1069 device_str = "STM32F100 (Low/Medium Density)";
1070
1071 switch (rev_id) {
1072 case 0x1000:
1073 rev_str = "A";
1074 break;
1075
1076 case 0x1001:
1077 rev_str = "Z";
1078 break;
1079 }
1080 break;
1081
1082 case 0x422:
1083 device_str = "STM32F302xB/C";
1084
1085 switch (rev_id) {
1086 case 0x1000:
1087 rev_str = "A";
1088 break;
1089
1090 case 0x1001:
1091 rev_str = "Z";
1092 break;
1093
1094 case 0x1003:
1095 rev_str = "Y";
1096 break;
1097
1098 case 0x2000:
1099 rev_str = "B";
1100 break;
1101 }
1102 break;
1103
1104 case 0x428:
1105 device_str = "STM32F100 (High Density)";
1106
1107 switch (rev_id) {
1108 case 0x1000:
1109 rev_str = "A";
1110 break;
1111
1112 case 0x1001:
1113 rev_str = "Z";
1114 break;
1115 }
1116 break;
1117
1118 case 0x430:
1119 device_str = "STM32F10x (XL Density)";
1120
1121 switch (rev_id) {
1122 case 0x1000:
1123 rev_str = "A";
1124 break;
1125 }
1126 break;
1127
1128 case 0x432:
1129 device_str = "STM32F37x";
1130
1131 switch (rev_id) {
1132 case 0x1000:
1133 rev_str = "A";
1134 break;
1135
1136 case 0x2000:
1137 rev_str = "B";
1138 break;
1139 }
1140 break;
1141
1142 case 0x438:
1143 device_str = "STM32F33x";
1144
1145 switch (rev_id) {
1146 case 0x1000:
1147 rev_str = "A";
1148 break;
1149 }
1150 break;
1151
1152 case 0x439:
1153 device_str = "STM32F302x6/8";
1154
1155 switch (rev_id) {
1156 case 0x1000:
1157 rev_str = "A";
1158 break;
1159
1160 case 0x1001:
1161 rev_str = "Z";
1162 break;
1163 }
1164 break;
1165
1166 case 0x444:
1167 device_str = "STM32F03x";
1168 rev_str = get_stm32f0_revision(rev_id);
1169 break;
1170
1171 case 0x440:
1172 device_str = "STM32F05x";
1173 rev_str = get_stm32f0_revision(rev_id);
1174 break;
1175
1176 case 0x445:
1177 device_str = "STM32F04x";
1178 rev_str = get_stm32f0_revision(rev_id);
1179 break;
1180
1181 case 0x446:
1182 device_str = "STM32F303xD/E";
1183 switch (rev_id) {
1184 case 0x1000:
1185 rev_str = "A";
1186 break;
1187 }
1188 break;
1189
1190 case 0x448:
1191 device_str = "STM32F07x";
1192 rev_str = get_stm32f0_revision(rev_id);
1193 break;
1194
1195 case 0x442:
1196 device_str = "STM32F09x";
1197 rev_str = get_stm32f0_revision(rev_id);
1198 break;
1199
1200 default:
1201 command_print_sameline(cmd, "Cannot identify target as a STM32F0/1/3\n");
1202 return ERROR_FAIL;
1203 }
1204
1205 if (rev_str)
1206 command_print_sameline(cmd, "%s - Rev: %s", device_str, rev_str);
1207 else
1208 command_print_sameline(cmd, "%s - Rev: unknown (0x%04x)", device_str, rev_id);
1209
1210 return ERROR_OK;
1211 }
1212
1213 COMMAND_HANDLER(stm32x_handle_lock_command)
1214 {
1215 struct target *target = NULL;
1216 struct stm32x_flash_bank *stm32x_info = NULL;
1217
1218 if (CMD_ARGC < 1)
1219 return ERROR_COMMAND_SYNTAX_ERROR;
1220
1221 struct flash_bank *bank;
1222 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1223 if (retval != ERROR_OK)
1224 return retval;
1225
1226 stm32x_info = bank->driver_priv;
1227
1228 target = bank->target;
1229
1230 if (target->state != TARGET_HALTED) {
1231 LOG_ERROR("Target not halted");
1232 return ERROR_TARGET_NOT_HALTED;
1233 }
1234
1235 retval = stm32x_check_operation_supported(bank);
1236 if (retval != ERROR_OK)
1237 return retval;
1238
1239 if (stm32x_erase_options(bank) != ERROR_OK) {
1240 command_print(CMD, "stm32x failed to erase options");
1241 return ERROR_OK;
1242 }
1243
1244 /* set readout protection */
1245 stm32x_info->option_bytes.rdp = 0;
1246
1247 if (stm32x_write_options(bank) != ERROR_OK) {
1248 command_print(CMD, "stm32x failed to lock device");
1249 return ERROR_OK;
1250 }
1251
1252 command_print(CMD, "stm32x locked");
1253
1254 return ERROR_OK;
1255 }
1256
1257 COMMAND_HANDLER(stm32x_handle_unlock_command)
1258 {
1259 struct target *target = NULL;
1260
1261 if (CMD_ARGC < 1)
1262 return ERROR_COMMAND_SYNTAX_ERROR;
1263
1264 struct flash_bank *bank;
1265 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1266 if (retval != ERROR_OK)
1267 return retval;
1268
1269 target = bank->target;
1270
1271 if (target->state != TARGET_HALTED) {
1272 LOG_ERROR("Target not halted");
1273 return ERROR_TARGET_NOT_HALTED;
1274 }
1275
1276 retval = stm32x_check_operation_supported(bank);
1277 if (retval != ERROR_OK)
1278 return retval;
1279
1280 if (stm32x_erase_options(bank) != ERROR_OK) {
1281 command_print(CMD, "stm32x failed to erase options");
1282 return ERROR_OK;
1283 }
1284
1285 if (stm32x_write_options(bank) != ERROR_OK) {
1286 command_print(CMD, "stm32x failed to unlock device");
1287 return ERROR_OK;
1288 }
1289
1290 command_print(CMD, "stm32x unlocked.\n"
1291 "INFO: a reset or power cycle is required "
1292 "for the new settings to take effect.");
1293
1294 return ERROR_OK;
1295 }
1296
1297 COMMAND_HANDLER(stm32x_handle_options_read_command)
1298 {
1299 uint32_t optionbyte, protection;
1300 struct target *target = NULL;
1301 struct stm32x_flash_bank *stm32x_info = NULL;
1302
1303 if (CMD_ARGC < 1)
1304 return ERROR_COMMAND_SYNTAX_ERROR;
1305
1306 struct flash_bank *bank;
1307 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1308 if (retval != ERROR_OK)
1309 return retval;
1310
1311 stm32x_info = bank->driver_priv;
1312
1313 target = bank->target;
1314
1315 if (target->state != TARGET_HALTED) {
1316 LOG_ERROR("Target not halted");
1317 return ERROR_TARGET_NOT_HALTED;
1318 }
1319
1320 retval = stm32x_check_operation_supported(bank);
1321 if (retval != ERROR_OK)
1322 return retval;
1323
1324 retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optionbyte);
1325 if (retval != ERROR_OK)
1326 return retval;
1327
1328 uint16_t user_data = optionbyte >> stm32x_info->user_data_offset;
1329
1330 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
1331 if (retval != ERROR_OK)
1332 return retval;
1333
1334 if (optionbyte & (1 << OPT_ERROR))
1335 command_print(CMD, "option byte complement error");
1336
1337 command_print(CMD, "option byte register = 0x%" PRIx32 "", optionbyte);
1338 command_print(CMD, "write protection register = 0x%" PRIx32 "", protection);
1339
1340 command_print(CMD, "read protection: %s",
1341 (optionbyte & (1 << OPT_READOUT)) ? "on" : "off");
1342
1343 /* user option bytes are offset depending on variant */
1344 optionbyte >>= stm32x_info->option_offset;
1345
1346 command_print(CMD, "watchdog: %sware",
1347 (optionbyte & (1 << OPT_RDWDGSW)) ? "soft" : "hard");
1348
1349 command_print(CMD, "stop mode: %sreset generated upon entry",
1350 (optionbyte & (1 << OPT_RDRSTSTOP)) ? "no " : "");
1351
1352 command_print(CMD, "standby mode: %sreset generated upon entry",
1353 (optionbyte & (1 << OPT_RDRSTSTDBY)) ? "no " : "");
1354
1355 if (stm32x_info->has_dual_banks)
1356 command_print(CMD, "boot: bank %d", (optionbyte & (1 << OPT_BFB2)) ? 0 : 1);
1357
1358 command_print(CMD, "user data = 0x%02" PRIx16 "", user_data);
1359
1360 return ERROR_OK;
1361 }
1362
1363 COMMAND_HANDLER(stm32x_handle_options_write_command)
1364 {
1365 struct target *target = NULL;
1366 struct stm32x_flash_bank *stm32x_info = NULL;
1367 uint8_t optionbyte;
1368 uint16_t useropt;
1369
1370 if (CMD_ARGC < 2)
1371 return ERROR_COMMAND_SYNTAX_ERROR;
1372
1373 struct flash_bank *bank;
1374 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1375 if (retval != ERROR_OK)
1376 return retval;
1377
1378 stm32x_info = bank->driver_priv;
1379
1380 target = bank->target;
1381
1382 if (target->state != TARGET_HALTED) {
1383 LOG_ERROR("Target not halted");
1384 return ERROR_TARGET_NOT_HALTED;
1385 }
1386
1387 retval = stm32x_check_operation_supported(bank);
1388 if (retval != ERROR_OK)
1389 return retval;
1390
1391 retval = stm32x_read_options(bank);
1392 if (retval != ERROR_OK)
1393 return retval;
1394
1395 /* start with current options */
1396 optionbyte = stm32x_info->option_bytes.user;
1397 useropt = stm32x_info->option_bytes.data;
1398
1399 /* skip over flash bank */
1400 CMD_ARGC--;
1401 CMD_ARGV++;
1402
1403 while (CMD_ARGC) {
1404 if (strcmp("SWWDG", CMD_ARGV[0]) == 0)
1405 optionbyte |= (1 << 0);
1406 else if (strcmp("HWWDG", CMD_ARGV[0]) == 0)
1407 optionbyte &= ~(1 << 0);
1408 else if (strcmp("NORSTSTOP", CMD_ARGV[0]) == 0)
1409 optionbyte |= (1 << 1);
1410 else if (strcmp("RSTSTOP", CMD_ARGV[0]) == 0)
1411 optionbyte &= ~(1 << 1);
1412 else if (strcmp("NORSTSTNDBY", CMD_ARGV[0]) == 0)
1413 optionbyte |= (1 << 2);
1414 else if (strcmp("RSTSTNDBY", CMD_ARGV[0]) == 0)
1415 optionbyte &= ~(1 << 2);
1416 else if (strcmp("USEROPT", CMD_ARGV[0]) == 0) {
1417 if (CMD_ARGC < 2)
1418 return ERROR_COMMAND_SYNTAX_ERROR;
1419 COMMAND_PARSE_NUMBER(u16, CMD_ARGV[1], useropt);
1420 CMD_ARGC--;
1421 CMD_ARGV++;
1422 } else if (stm32x_info->has_dual_banks) {
1423 if (strcmp("BOOT0", CMD_ARGV[0]) == 0)
1424 optionbyte |= (1 << 3);
1425 else if (strcmp("BOOT1", CMD_ARGV[0]) == 0)
1426 optionbyte &= ~(1 << 3);
1427 else
1428 return ERROR_COMMAND_SYNTAX_ERROR;
1429 } else
1430 return ERROR_COMMAND_SYNTAX_ERROR;
1431 CMD_ARGC--;
1432 CMD_ARGV++;
1433 }
1434
1435 if (stm32x_erase_options(bank) != ERROR_OK) {
1436 command_print(CMD, "stm32x failed to erase options");
1437 return ERROR_OK;
1438 }
1439
1440 stm32x_info->option_bytes.user = optionbyte;
1441 stm32x_info->option_bytes.data = useropt;
1442
1443 if (stm32x_write_options(bank) != ERROR_OK) {
1444 command_print(CMD, "stm32x failed to write options");
1445 return ERROR_OK;
1446 }
1447
1448 command_print(CMD, "stm32x write options complete.\n"
1449 "INFO: %spower cycle is required "
1450 "for the new settings to take effect.",
1451 stm32x_info->can_load_options
1452 ? "'stm32f1x options_load' command or " : "");
1453
1454 return ERROR_OK;
1455 }
1456
1457 COMMAND_HANDLER(stm32x_handle_options_load_command)
1458 {
1459 if (CMD_ARGC < 1)
1460 return ERROR_COMMAND_SYNTAX_ERROR;
1461
1462 struct flash_bank *bank;
1463 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1464 if (retval != ERROR_OK)
1465 return retval;
1466
1467 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
1468
1469 if (!stm32x_info->can_load_options) {
1470 LOG_ERROR("Command not applicable to stm32f1x devices - power cycle is "
1471 "required instead.");
1472 return ERROR_FAIL;
1473 }
1474
1475 struct target *target = bank->target;
1476
1477 if (target->state != TARGET_HALTED) {
1478 LOG_ERROR("Target not halted");
1479 return ERROR_TARGET_NOT_HALTED;
1480 }
1481
1482 retval = stm32x_check_operation_supported(bank);
1483 if (retval != ERROR_OK)
1484 return retval;
1485
1486 /* unlock option flash registers */
1487 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1488 if (retval != ERROR_OK)
1489 return retval;
1490 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1491 if (retval != ERROR_OK) {
1492 (void)target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
1493 return retval;
1494 }
1495
1496 /* force re-load of option bytes - generates software reset */
1497 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_OBL_LAUNCH);
1498 if (retval != ERROR_OK)
1499 return retval;
1500
1501 return ERROR_OK;
1502 }
1503
1504 static int stm32x_mass_erase(struct flash_bank *bank)
1505 {
1506 struct target *target = bank->target;
1507
1508 if (target->state != TARGET_HALTED) {
1509 LOG_ERROR("Target not halted");
1510 return ERROR_TARGET_NOT_HALTED;
1511 }
1512
1513 /* unlock option flash registers */
1514 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1515 if (retval != ERROR_OK)
1516 return retval;
1517 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1518 if (retval != ERROR_OK)
1519 goto flash_lock;
1520
1521 /* mass erase flash memory */
1522 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
1523 if (retval != ERROR_OK)
1524 goto flash_lock;
1525 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
1526 FLASH_MER | FLASH_STRT);
1527 if (retval != ERROR_OK)
1528 goto flash_lock;
1529
1530 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
1531
1532 flash_lock:
1533 {
1534 int retval2 = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
1535 if (retval == ERROR_OK)
1536 retval = retval2;
1537 }
1538 return retval;
1539 }
1540
1541 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1542 {
1543 if (CMD_ARGC < 1)
1544 return ERROR_COMMAND_SYNTAX_ERROR;
1545
1546 struct flash_bank *bank;
1547 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1548 if (retval != ERROR_OK)
1549 return retval;
1550
1551 retval = stm32x_mass_erase(bank);
1552 if (retval == ERROR_OK)
1553 command_print(CMD, "stm32x mass erase complete");
1554 else
1555 command_print(CMD, "stm32x mass erase failed");
1556
1557 return retval;
1558 }
1559
1560 static const struct command_registration stm32f1x_exec_command_handlers[] = {
1561 {
1562 .name = "lock",
1563 .handler = stm32x_handle_lock_command,
1564 .mode = COMMAND_EXEC,
1565 .usage = "bank_id",
1566 .help = "Lock entire flash device.",
1567 },
1568 {
1569 .name = "unlock",
1570 .handler = stm32x_handle_unlock_command,
1571 .mode = COMMAND_EXEC,
1572 .usage = "bank_id",
1573 .help = "Unlock entire protected flash device.",
1574 },
1575 {
1576 .name = "mass_erase",
1577 .handler = stm32x_handle_mass_erase_command,
1578 .mode = COMMAND_EXEC,
1579 .usage = "bank_id",
1580 .help = "Erase entire flash device.",
1581 },
1582 {
1583 .name = "options_read",
1584 .handler = stm32x_handle_options_read_command,
1585 .mode = COMMAND_EXEC,
1586 .usage = "bank_id",
1587 .help = "Read and display device option bytes.",
1588 },
1589 {
1590 .name = "options_write",
1591 .handler = stm32x_handle_options_write_command,
1592 .mode = COMMAND_EXEC,
1593 .usage = "bank_id ('SWWDG'|'HWWDG') "
1594 "('RSTSTNDBY'|'NORSTSTNDBY') "
1595 "('RSTSTOP'|'NORSTSTOP') ('USEROPT' user_data)",
1596 .help = "Replace bits in device option bytes.",
1597 },
1598 {
1599 .name = "options_load",
1600 .handler = stm32x_handle_options_load_command,
1601 .mode = COMMAND_EXEC,
1602 .usage = "bank_id",
1603 .help = "Force re-load of device option bytes.",
1604 },
1605 COMMAND_REGISTRATION_DONE
1606 };
1607
1608 static const struct command_registration stm32f1x_command_handlers[] = {
1609 {
1610 .name = "stm32f1x",
1611 .mode = COMMAND_ANY,
1612 .help = "stm32f1x flash command group",
1613 .usage = "",
1614 .chain = stm32f1x_exec_command_handlers,
1615 },
1616 COMMAND_REGISTRATION_DONE
1617 };
1618
1619 const struct flash_driver stm32f1x_flash = {
1620 .name = "stm32f1x",
1621 .commands = stm32f1x_command_handlers,
1622 .flash_bank_command = stm32x_flash_bank_command,
1623 .erase = stm32x_erase,
1624 .protect = stm32x_protect,
1625 .write = stm32x_write,
1626 .read = default_flash_read,
1627 .probe = stm32x_probe,
1628 .auto_probe = stm32x_auto_probe,
1629 .erase_check = default_flash_blank_check,
1630 .protect_check = stm32x_protect_check,
1631 .info = get_stm32x_info,
1632 .free_driver_priv = default_flash_free_driver_priv,
1633 };
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