1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2011 by Andreas Fritiofson *
9 * andreas.fritiofson@gmail.com *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
30 #include <helper/binarybuffer.h>
31 #include <target/algorithm.h>
32 #include <target/cortex_m.h>
34 /* stm32x register locations */
36 #define FLASH_REG_BASE_B0 0x40022000
37 #define FLASH_REG_BASE_B1 0x40022040
39 #define STM32_FLASH_ACR 0x00
40 #define STM32_FLASH_KEYR 0x04
41 #define STM32_FLASH_OPTKEYR 0x08
42 #define STM32_FLASH_SR 0x0C
43 #define STM32_FLASH_CR 0x10
44 #define STM32_FLASH_AR 0x14
45 #define STM32_FLASH_OBR 0x1C
46 #define STM32_FLASH_WRPR 0x20
48 /* TODO: Check if code using these really should be hard coded to bank 0.
49 * There are valid cases, on dual flash devices the protection of the
50 * second bank is done on the bank0 reg's. */
51 #define STM32_FLASH_ACR_B0 0x40022000
52 #define STM32_FLASH_KEYR_B0 0x40022004
53 #define STM32_FLASH_OPTKEYR_B0 0x40022008
54 #define STM32_FLASH_SR_B0 0x4002200C
55 #define STM32_FLASH_CR_B0 0x40022010
56 #define STM32_FLASH_AR_B0 0x40022014
57 #define STM32_FLASH_OBR_B0 0x4002201C
58 #define STM32_FLASH_WRPR_B0 0x40022020
60 /* option byte location */
62 #define STM32_OB_RDP 0x1FFFF800
63 #define STM32_OB_USER 0x1FFFF802
64 #define STM32_OB_DATA0 0x1FFFF804
65 #define STM32_OB_DATA1 0x1FFFF806
66 #define STM32_OB_WRP0 0x1FFFF808
67 #define STM32_OB_WRP1 0x1FFFF80A
68 #define STM32_OB_WRP2 0x1FFFF80C
69 #define STM32_OB_WRP3 0x1FFFF80E
71 /* FLASH_CR register bits */
73 #define FLASH_PG (1 << 0)
74 #define FLASH_PER (1 << 1)
75 #define FLASH_MER (1 << 2)
76 #define FLASH_OPTPG (1 << 4)
77 #define FLASH_OPTER (1 << 5)
78 #define FLASH_STRT (1 << 6)
79 #define FLASH_LOCK (1 << 7)
80 #define FLASH_OPTWRE (1 << 9)
81 #define FLASH_OBL_LAUNCH (1 << 13) /* except stm32f1x series */
83 /* FLASH_SR register bits */
85 #define FLASH_BSY (1 << 0)
86 #define FLASH_PGERR (1 << 2)
87 #define FLASH_WRPRTERR (1 << 4)
88 #define FLASH_EOP (1 << 5)
90 /* STM32_FLASH_OBR bit definitions (reading) */
95 #define OPT_RDRSTSTOP 3
96 #define OPT_RDRSTSTDBY 4
97 #define OPT_BFB2 5 /* dual flash bank only */
99 /* register unlock keys */
101 #define KEY1 0x45670123
102 #define KEY2 0xCDEF89AB
106 #define FLASH_WRITE_TIMEOUT 10
107 #define FLASH_ERASE_TIMEOUT 100
109 struct stm32x_options
{
116 struct stm32x_flash_bank
{
117 struct stm32x_options option_bytes
;
122 /* used to access dual flash bank stm32xl */
123 bool can_load_options
;
124 uint32_t register_base
;
126 int user_data_offset
;
128 uint32_t user_bank_size
;
131 static int stm32x_mass_erase(struct flash_bank
*bank
);
132 static int stm32x_get_device_id(struct flash_bank
*bank
, uint32_t *device_id
);
133 static int stm32x_write_block(struct flash_bank
*bank
, const uint8_t *buffer
,
134 uint32_t address
, uint32_t hwords_count
);
136 /* flash bank stm32x <base> <size> 0 0 <target#>
138 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command
)
140 struct stm32x_flash_bank
*stm32x_info
;
143 return ERROR_COMMAND_SYNTAX_ERROR
;
145 stm32x_info
= malloc(sizeof(struct stm32x_flash_bank
));
147 bank
->driver_priv
= stm32x_info
;
148 stm32x_info
->probed
= false;
149 stm32x_info
->has_dual_banks
= false;
150 stm32x_info
->can_load_options
= false;
151 stm32x_info
->register_base
= FLASH_REG_BASE_B0
;
152 stm32x_info
->user_bank_size
= bank
->size
;
154 /* The flash write must be aligned to a halfword boundary */
155 bank
->write_start_alignment
= bank
->write_end_alignment
= 2;
160 static inline int stm32x_get_flash_reg(struct flash_bank
*bank
, uint32_t reg
)
162 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
163 return reg
+ stm32x_info
->register_base
;
166 static inline int stm32x_get_flash_status(struct flash_bank
*bank
, uint32_t *status
)
168 struct target
*target
= bank
->target
;
169 return target_read_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_SR
), status
);
172 static int stm32x_wait_status_busy(struct flash_bank
*bank
, int timeout
)
174 struct target
*target
= bank
->target
;
176 int retval
= ERROR_OK
;
178 /* wait for busy to clear */
180 retval
= stm32x_get_flash_status(bank
, &status
);
181 if (retval
!= ERROR_OK
)
183 LOG_DEBUG("status: 0x%" PRIx32
"", status
);
184 if ((status
& FLASH_BSY
) == 0)
186 if (timeout
-- <= 0) {
187 LOG_ERROR("timed out waiting for flash");
193 if (status
& FLASH_WRPRTERR
) {
194 LOG_ERROR("stm32x device protected");
198 if (status
& FLASH_PGERR
) {
199 LOG_ERROR("stm32x device programming failed");
203 /* Clear but report errors */
204 if (status
& (FLASH_WRPRTERR
| FLASH_PGERR
)) {
205 /* If this operation fails, we ignore it and report the original
208 target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_SR
),
209 FLASH_WRPRTERR
| FLASH_PGERR
);
214 static int stm32x_check_operation_supported(struct flash_bank
*bank
)
216 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
218 /* if we have a dual flash bank device then
219 * we need to perform option byte stuff on bank0 only */
220 if (stm32x_info
->register_base
!= FLASH_REG_BASE_B0
) {
221 LOG_ERROR("Option byte operations must use bank 0");
222 return ERROR_FLASH_OPERATION_FAILED
;
228 static int stm32x_read_options(struct flash_bank
*bank
)
230 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
231 struct target
*target
= bank
->target
;
232 uint32_t option_bytes
;
235 /* read user and read protection option bytes, user data option bytes */
236 retval
= target_read_u32(target
, STM32_FLASH_OBR_B0
, &option_bytes
);
237 if (retval
!= ERROR_OK
)
240 stm32x_info
->option_bytes
.rdp
= (option_bytes
& (1 << OPT_READOUT
)) ? 0 : stm32x_info
->default_rdp
;
241 stm32x_info
->option_bytes
.user
= (option_bytes
>> stm32x_info
->option_offset
>> 2) & 0xff;
242 stm32x_info
->option_bytes
.data
= (option_bytes
>> stm32x_info
->user_data_offset
) & 0xffff;
244 /* read write protection option bytes */
245 retval
= target_read_u32(target
, STM32_FLASH_WRPR_B0
, &stm32x_info
->option_bytes
.protection
);
246 if (retval
!= ERROR_OK
)
252 static int stm32x_erase_options(struct flash_bank
*bank
)
254 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
255 struct target
*target
= bank
->target
;
257 /* read current options */
258 stm32x_read_options(bank
);
260 /* unlock flash registers */
261 int retval
= target_write_u32(target
, STM32_FLASH_KEYR_B0
, KEY1
);
262 if (retval
!= ERROR_OK
)
265 retval
= target_write_u32(target
, STM32_FLASH_KEYR_B0
, KEY2
);
266 if (retval
!= ERROR_OK
)
269 /* unlock option flash registers */
270 retval
= target_write_u32(target
, STM32_FLASH_OPTKEYR_B0
, KEY1
);
271 if (retval
!= ERROR_OK
)
273 retval
= target_write_u32(target
, STM32_FLASH_OPTKEYR_B0
, KEY2
);
274 if (retval
!= ERROR_OK
)
277 /* erase option bytes */
278 retval
= target_write_u32(target
, STM32_FLASH_CR_B0
, FLASH_OPTER
| FLASH_OPTWRE
);
279 if (retval
!= ERROR_OK
)
281 retval
= target_write_u32(target
, STM32_FLASH_CR_B0
, FLASH_OPTER
| FLASH_STRT
| FLASH_OPTWRE
);
282 if (retval
!= ERROR_OK
)
285 retval
= stm32x_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
);
286 if (retval
!= ERROR_OK
)
289 /* clear read protection option byte
290 * this will also force a device unlock if set */
291 stm32x_info
->option_bytes
.rdp
= stm32x_info
->default_rdp
;
296 static int stm32x_write_options(struct flash_bank
*bank
)
298 struct stm32x_flash_bank
*stm32x_info
= NULL
;
299 struct target
*target
= bank
->target
;
301 stm32x_info
= bank
->driver_priv
;
303 /* unlock flash registers */
304 int retval
= target_write_u32(target
, STM32_FLASH_KEYR_B0
, KEY1
);
305 if (retval
!= ERROR_OK
)
307 retval
= target_write_u32(target
, STM32_FLASH_KEYR_B0
, KEY2
);
308 if (retval
!= ERROR_OK
)
311 /* unlock option flash registers */
312 retval
= target_write_u32(target
, STM32_FLASH_OPTKEYR_B0
, KEY1
);
313 if (retval
!= ERROR_OK
)
315 retval
= target_write_u32(target
, STM32_FLASH_OPTKEYR_B0
, KEY2
);
316 if (retval
!= ERROR_OK
)
319 /* program option bytes */
320 retval
= target_write_u32(target
, STM32_FLASH_CR_B0
, FLASH_OPTPG
| FLASH_OPTWRE
);
321 if (retval
!= ERROR_OK
)
324 uint8_t opt_bytes
[16];
326 target_buffer_set_u16(target
, opt_bytes
, stm32x_info
->option_bytes
.rdp
);
327 target_buffer_set_u16(target
, opt_bytes
+ 2, stm32x_info
->option_bytes
.user
);
328 target_buffer_set_u16(target
, opt_bytes
+ 4, stm32x_info
->option_bytes
.data
& 0xff);
329 target_buffer_set_u16(target
, opt_bytes
+ 6, (stm32x_info
->option_bytes
.data
>> 8) & 0xff);
330 target_buffer_set_u16(target
, opt_bytes
+ 8, stm32x_info
->option_bytes
.protection
& 0xff);
331 target_buffer_set_u16(target
, opt_bytes
+ 10, (stm32x_info
->option_bytes
.protection
>> 8) & 0xff);
332 target_buffer_set_u16(target
, opt_bytes
+ 12, (stm32x_info
->option_bytes
.protection
>> 16) & 0xff);
333 target_buffer_set_u16(target
, opt_bytes
+ 14, (stm32x_info
->option_bytes
.protection
>> 24) & 0xff);
335 /* Block write is preferred in favour of operation with ancient ST-Link
336 * firmwares without 16-bit memory access. See
337 * 480: flash: stm32f1x: write option bytes using the loader
338 * https://review.openocd.org/c/openocd/+/480
340 retval
= stm32x_write_block(bank
, opt_bytes
, STM32_OB_RDP
, sizeof(opt_bytes
) / 2);
341 if (retval
!= ERROR_OK
)
344 retval
= target_write_u32(target
, STM32_FLASH_CR_B0
, FLASH_LOCK
);
345 if (retval
!= ERROR_OK
)
351 static int stm32x_protect_check(struct flash_bank
*bank
)
353 struct target
*target
= bank
->target
;
356 int retval
= stm32x_check_operation_supported(bank
);
357 if (retval
!= ERROR_OK
)
360 /* medium density - each bit refers to a 4 sector protection block
361 * high density - each bit refers to a 2 sector protection block
362 * bit 31 refers to all remaining sectors in a bank */
363 retval
= target_read_u32(target
, STM32_FLASH_WRPR_B0
, &protection
);
364 if (retval
!= ERROR_OK
)
367 for (unsigned int i
= 0; i
< bank
->num_prot_blocks
; i
++)
368 bank
->prot_blocks
[i
].is_protected
= (protection
& (1 << i
)) ? 0 : 1;
373 static int stm32x_erase(struct flash_bank
*bank
, unsigned int first
,
376 struct target
*target
= bank
->target
;
378 if (bank
->target
->state
!= TARGET_HALTED
) {
379 LOG_ERROR("Target not halted");
380 return ERROR_TARGET_NOT_HALTED
;
383 if ((first
== 0) && (last
== (bank
->num_sectors
- 1)))
384 return stm32x_mass_erase(bank
);
386 /* unlock flash registers */
387 int retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY1
);
388 if (retval
!= ERROR_OK
)
390 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY2
);
391 if (retval
!= ERROR_OK
)
394 for (unsigned int i
= first
; i
<= last
; i
++) {
395 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_PER
);
396 if (retval
!= ERROR_OK
)
398 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_AR
),
399 bank
->base
+ bank
->sectors
[i
].offset
);
400 if (retval
!= ERROR_OK
)
402 retval
= target_write_u32(target
,
403 stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_PER
| FLASH_STRT
);
404 if (retval
!= ERROR_OK
)
407 retval
= stm32x_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
);
408 if (retval
!= ERROR_OK
)
412 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_LOCK
);
413 if (retval
!= ERROR_OK
)
419 static int stm32x_protect(struct flash_bank
*bank
, int set
, unsigned int first
,
422 struct target
*target
= bank
->target
;
423 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
425 if (target
->state
!= TARGET_HALTED
) {
426 LOG_ERROR("Target not halted");
427 return ERROR_TARGET_NOT_HALTED
;
430 int retval
= stm32x_check_operation_supported(bank
);
431 if (retval
!= ERROR_OK
)
434 retval
= stm32x_erase_options(bank
);
435 if (retval
!= ERROR_OK
) {
436 LOG_ERROR("stm32x failed to erase options");
440 for (unsigned int i
= first
; i
<= last
; i
++) {
442 stm32x_info
->option_bytes
.protection
&= ~(1 << i
);
444 stm32x_info
->option_bytes
.protection
|= (1 << i
);
447 return stm32x_write_options(bank
);
450 static int stm32x_write_block_async(struct flash_bank
*bank
, const uint8_t *buffer
,
451 uint32_t address
, uint32_t hwords_count
)
453 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
454 struct target
*target
= bank
->target
;
455 uint32_t buffer_size
;
456 struct working_area
*write_algorithm
;
457 struct working_area
*source
;
458 struct armv7m_algorithm armv7m_info
;
461 static const uint8_t stm32x_flash_write_code
[] = {
462 #include "../../../contrib/loaders/flash/stm32/stm32f1x.inc"
465 /* flash write code */
466 if (target_alloc_working_area(target
, sizeof(stm32x_flash_write_code
),
467 &write_algorithm
) != ERROR_OK
) {
468 LOG_WARNING("no working area available, can't do block memory writes");
469 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
472 retval
= target_write_buffer(target
, write_algorithm
->address
,
473 sizeof(stm32x_flash_write_code
), stm32x_flash_write_code
);
474 if (retval
!= ERROR_OK
) {
475 target_free_working_area(target
, write_algorithm
);
480 buffer_size
= target_get_working_area_avail(target
);
481 buffer_size
= MIN(hwords_count
* 2, MAX(buffer_size
, 256));
482 /* Normally we allocate all available working area.
483 * MIN shrinks buffer_size if the size of the written block is smaller.
484 * MAX prevents using async algo if the available working area is smaller
485 * than 256, the following allocation fails with
486 * ERROR_TARGET_RESOURCE_NOT_AVAILABLE and slow flashing takes place.
489 retval
= target_alloc_working_area(target
, buffer_size
, &source
);
490 /* Allocated size is always 32-bit word aligned */
491 if (retval
!= ERROR_OK
) {
492 target_free_working_area(target
, write_algorithm
);
493 LOG_WARNING("no large enough working area available, can't do block memory writes");
494 /* target_alloc_working_area() may return ERROR_FAIL if area backup fails:
495 * convert any error to ERROR_TARGET_RESOURCE_NOT_AVAILABLE
497 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
500 struct reg_param reg_params
[5];
502 init_reg_param(®_params
[0], "r0", 32, PARAM_IN_OUT
); /* flash base (in), status (out) */
503 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
); /* count (halfword-16bit) */
504 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
); /* buffer start */
505 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
); /* buffer end */
506 init_reg_param(®_params
[4], "r4", 32, PARAM_IN_OUT
); /* target address */
508 buf_set_u32(reg_params
[0].value
, 0, 32, stm32x_info
->register_base
);
509 buf_set_u32(reg_params
[1].value
, 0, 32, hwords_count
);
510 buf_set_u32(reg_params
[2].value
, 0, 32, source
->address
);
511 buf_set_u32(reg_params
[3].value
, 0, 32, source
->address
+ source
->size
);
512 buf_set_u32(reg_params
[4].value
, 0, 32, address
);
514 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
515 armv7m_info
.core_mode
= ARM_MODE_THREAD
;
517 retval
= target_run_flash_async_algorithm(target
, buffer
, hwords_count
, 2,
519 ARRAY_SIZE(reg_params
), reg_params
,
520 source
->address
, source
->size
,
521 write_algorithm
->address
, 0,
524 if (retval
== ERROR_FLASH_OPERATION_FAILED
) {
525 LOG_ERROR("flash write failed at address 0x%"PRIx32
,
526 buf_get_u32(reg_params
[4].value
, 0, 32));
528 if (buf_get_u32(reg_params
[0].value
, 0, 32) & FLASH_PGERR
) {
529 LOG_ERROR("flash memory not erased before writing");
530 /* Clear but report errors */
531 target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_SR
), FLASH_PGERR
);
534 if (buf_get_u32(reg_params
[0].value
, 0, 32) & FLASH_WRPRTERR
) {
535 LOG_ERROR("flash memory write protected");
536 /* Clear but report errors */
537 target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_SR
), FLASH_WRPRTERR
);
541 for (unsigned int i
= 0; i
< ARRAY_SIZE(reg_params
); i
++)
542 destroy_reg_param(®_params
[i
]);
544 target_free_working_area(target
, source
);
545 target_free_working_area(target
, write_algorithm
);
550 /** Writes a block to flash either using target algorithm
551 * or use fallback, host controlled halfword-by-halfword access.
552 * Flash controller must be unlocked before this call.
554 static int stm32x_write_block(struct flash_bank
*bank
,
555 const uint8_t *buffer
, uint32_t address
, uint32_t hwords_count
)
557 struct target
*target
= bank
->target
;
559 /* The flash write must be aligned to a halfword boundary.
560 * The flash infrastructure ensures it, do just a security check
562 assert(address
% 2 == 0);
564 /* try using a block write - on ARM architecture or... */
565 int retval
= stm32x_write_block_async(bank
, buffer
, address
, hwords_count
);
567 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
) {
568 /* if block write failed (no sufficient working area),
569 * we use normal (slow) single halfword accesses */
570 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
572 while (hwords_count
> 0) {
573 retval
= target_write_memory(target
, address
, 2, 1, buffer
);
574 if (retval
!= ERROR_OK
)
577 retval
= stm32x_wait_status_busy(bank
, 5);
578 if (retval
!= ERROR_OK
)
589 static int stm32x_write(struct flash_bank
*bank
, const uint8_t *buffer
,
590 uint32_t offset
, uint32_t count
)
592 struct target
*target
= bank
->target
;
594 if (bank
->target
->state
!= TARGET_HALTED
) {
595 LOG_ERROR("Target not halted");
596 return ERROR_TARGET_NOT_HALTED
;
599 /* The flash write must be aligned to a halfword boundary.
600 * The flash infrastructure ensures it, do just a security check
602 assert(offset
% 2 == 0);
603 assert(count
% 2 == 0);
607 /* unlock flash registers */
608 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY1
);
609 if (retval
!= ERROR_OK
)
611 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY2
);
612 if (retval
!= ERROR_OK
)
613 goto reset_pg_and_lock
;
615 /* enable flash programming */
616 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_PG
);
617 if (retval
!= ERROR_OK
)
618 goto reset_pg_and_lock
;
621 retval
= stm32x_write_block(bank
, buffer
, bank
->base
+ offset
, count
/ 2);
624 retval2
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_LOCK
);
625 if (retval
== ERROR_OK
)
631 static int stm32x_get_device_id(struct flash_bank
*bank
, uint32_t *device_id
)
633 struct target
*target
= bank
->target
;
634 uint32_t device_id_register
= 0;
636 if (!target_was_examined(target
)) {
637 LOG_ERROR("Target not examined yet");
638 return ERROR_TARGET_NOT_EXAMINED
;
641 switch (cortex_m_get_partno_safe(target
)) {
642 case CORTEX_M0_PARTNO
: /* STM32F0x devices */
643 device_id_register
= 0x40015800;
645 case CORTEX_M3_PARTNO
: /* STM32F1x devices */
646 device_id_register
= 0xE0042000;
648 case CORTEX_M4_PARTNO
: /* STM32F3x devices */
649 device_id_register
= 0xE0042000;
651 case CORTEX_M23_PARTNO
: /* GD32E23x devices */
652 device_id_register
= 0x40015800;
655 LOG_ERROR("Cannot identify target as a stm32x");
659 /* read stm32 device id register */
660 int retval
= target_read_u32(target
, device_id_register
, device_id
);
661 if (retval
!= ERROR_OK
)
667 static int stm32x_get_flash_size(struct flash_bank
*bank
, uint16_t *flash_size_in_kb
)
669 struct target
*target
= bank
->target
;
670 uint32_t flash_size_reg
;
672 if (!target_was_examined(target
)) {
673 LOG_ERROR("Target not examined yet");
674 return ERROR_TARGET_NOT_EXAMINED
;
677 switch (cortex_m_get_partno_safe(target
)) {
678 case CORTEX_M0_PARTNO
: /* STM32F0x devices */
679 flash_size_reg
= 0x1FFFF7CC;
681 case CORTEX_M3_PARTNO
: /* STM32F1x devices */
682 flash_size_reg
= 0x1FFFF7E0;
684 case CORTEX_M4_PARTNO
: /* STM32F3x devices */
685 flash_size_reg
= 0x1FFFF7CC;
687 case CORTEX_M23_PARTNO
: /* GD32E23x devices */
688 flash_size_reg
= 0x1FFFF7E0;
691 LOG_ERROR("Cannot identify target as a stm32x");
695 int retval
= target_read_u16(target
, flash_size_reg
, flash_size_in_kb
);
696 if (retval
!= ERROR_OK
)
702 static int stm32x_probe(struct flash_bank
*bank
)
704 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
705 uint16_t flash_size_in_kb
;
706 uint16_t max_flash_size_in_kb
;
707 uint32_t dbgmcu_idcode
;
709 uint32_t base_address
= 0x08000000;
711 stm32x_info
->probed
= false;
712 stm32x_info
->register_base
= FLASH_REG_BASE_B0
;
713 stm32x_info
->user_data_offset
= 10;
714 stm32x_info
->option_offset
= 0;
716 /* default factory read protection level 0 */
717 stm32x_info
->default_rdp
= 0xA5;
719 /* read stm32 device id register */
720 int retval
= stm32x_get_device_id(bank
, &dbgmcu_idcode
);
721 if (retval
!= ERROR_OK
)
724 LOG_INFO("device id = 0x%08" PRIx32
"", dbgmcu_idcode
);
726 uint16_t device_id
= dbgmcu_idcode
& 0xfff;
727 uint16_t rev_id
= dbgmcu_idcode
>> 16;
729 /* set page size, protection granularity and max flash size depending on family */
731 case 0x440: /* stm32f05x */
733 stm32x_info
->ppage_size
= 4;
734 max_flash_size_in_kb
= 64;
735 stm32x_info
->user_data_offset
= 16;
736 stm32x_info
->option_offset
= 6;
737 stm32x_info
->default_rdp
= 0xAA;
738 stm32x_info
->can_load_options
= true;
740 case 0x444: /* stm32f03x */
741 case 0x445: /* stm32f04x */
743 stm32x_info
->ppage_size
= 4;
744 max_flash_size_in_kb
= 32;
745 stm32x_info
->user_data_offset
= 16;
746 stm32x_info
->option_offset
= 6;
747 stm32x_info
->default_rdp
= 0xAA;
748 stm32x_info
->can_load_options
= true;
750 case 0x448: /* stm32f07x */
752 stm32x_info
->ppage_size
= 4;
753 max_flash_size_in_kb
= 128;
754 stm32x_info
->user_data_offset
= 16;
755 stm32x_info
->option_offset
= 6;
756 stm32x_info
->default_rdp
= 0xAA;
757 stm32x_info
->can_load_options
= true;
759 case 0x442: /* stm32f09x */
761 stm32x_info
->ppage_size
= 4;
762 max_flash_size_in_kb
= 256;
763 stm32x_info
->user_data_offset
= 16;
764 stm32x_info
->option_offset
= 6;
765 stm32x_info
->default_rdp
= 0xAA;
766 stm32x_info
->can_load_options
= true;
768 case 0x410: /* stm32f1x medium-density */
770 stm32x_info
->ppage_size
= 4;
771 max_flash_size_in_kb
= 128;
772 /* GigaDevice GD32F1x0 & GD32F3x0 & GD32E23x series devices
773 share DEV_ID with STM32F101/2/3 medium-density line,
774 however they use a REV_ID different from any STM32 device.
775 The main difference is another offset of user option bits
776 (like WDG_SW, nRST_STOP, nRST_STDBY) in option byte register
777 (FLASH_OBR/FMC_OBSTAT 0x4002201C).
778 This caused problems e.g. during flash block programming
779 because of unexpected active hardware watchog. */
781 case 0x1303: /* gd32f1x0 */
782 stm32x_info
->user_data_offset
= 16;
783 stm32x_info
->option_offset
= 6;
784 max_flash_size_in_kb
= 64;
786 case 0x1704: /* gd32f3x0 */
787 stm32x_info
->user_data_offset
= 16;
788 stm32x_info
->option_offset
= 6;
790 case 0x1909: /* gd32e23x */
791 stm32x_info
->user_data_offset
= 16;
792 stm32x_info
->option_offset
= 6;
793 max_flash_size_in_kb
= 64;
797 case 0x412: /* stm32f1x low-density */
799 stm32x_info
->ppage_size
= 4;
800 max_flash_size_in_kb
= 32;
802 case 0x414: /* stm32f1x high-density */
804 stm32x_info
->ppage_size
= 2;
805 max_flash_size_in_kb
= 512;
807 case 0x418: /* stm32f1x connectivity */
809 stm32x_info
->ppage_size
= 2;
810 max_flash_size_in_kb
= 256;
812 case 0x430: /* stm32f1 XL-density (dual flash banks) */
814 stm32x_info
->ppage_size
= 2;
815 max_flash_size_in_kb
= 1024;
816 stm32x_info
->has_dual_banks
= true;
818 case 0x420: /* stm32f100xx low- and medium-density value line */
820 stm32x_info
->ppage_size
= 4;
821 max_flash_size_in_kb
= 128;
823 case 0x428: /* stm32f100xx high-density value line */
825 stm32x_info
->ppage_size
= 4;
826 max_flash_size_in_kb
= 512;
828 case 0x422: /* stm32f302/3xb/c */
830 stm32x_info
->ppage_size
= 2;
831 max_flash_size_in_kb
= 256;
832 stm32x_info
->user_data_offset
= 16;
833 stm32x_info
->option_offset
= 6;
834 stm32x_info
->default_rdp
= 0xAA;
835 stm32x_info
->can_load_options
= true;
837 case 0x446: /* stm32f303xD/E */
839 stm32x_info
->ppage_size
= 2;
840 max_flash_size_in_kb
= 512;
841 stm32x_info
->user_data_offset
= 16;
842 stm32x_info
->option_offset
= 6;
843 stm32x_info
->default_rdp
= 0xAA;
844 stm32x_info
->can_load_options
= true;
846 case 0x432: /* stm32f37x */
848 stm32x_info
->ppage_size
= 2;
849 max_flash_size_in_kb
= 256;
850 stm32x_info
->user_data_offset
= 16;
851 stm32x_info
->option_offset
= 6;
852 stm32x_info
->default_rdp
= 0xAA;
853 stm32x_info
->can_load_options
= true;
855 case 0x438: /* stm32f33x */
856 case 0x439: /* stm32f302x6/8 */
858 stm32x_info
->ppage_size
= 2;
859 max_flash_size_in_kb
= 64;
860 stm32x_info
->user_data_offset
= 16;
861 stm32x_info
->option_offset
= 6;
862 stm32x_info
->default_rdp
= 0xAA;
863 stm32x_info
->can_load_options
= true;
866 LOG_WARNING("Cannot identify target as a STM32 family.");
870 /* get flash size from target. */
871 retval
= stm32x_get_flash_size(bank
, &flash_size_in_kb
);
873 /* failed reading flash size or flash size invalid (early silicon),
874 * default to max target family */
875 if (retval
!= ERROR_OK
|| flash_size_in_kb
== 0xffff || flash_size_in_kb
== 0) {
876 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
877 max_flash_size_in_kb
);
878 flash_size_in_kb
= max_flash_size_in_kb
;
881 if (stm32x_info
->has_dual_banks
) {
882 /* split reported size into matching bank */
883 if (bank
->base
!= 0x08080000) {
884 /* bank 0 will be fixed 512k */
885 flash_size_in_kb
= 512;
887 flash_size_in_kb
-= 512;
888 /* bank1 also uses a register offset */
889 stm32x_info
->register_base
= FLASH_REG_BASE_B1
;
890 base_address
= 0x08080000;
894 /* if the user sets the size manually then ignore the probed value
895 * this allows us to work around devices that have a invalid flash size register value */
896 if (stm32x_info
->user_bank_size
) {
897 LOG_INFO("ignoring flash probed value, using configured bank size");
898 flash_size_in_kb
= stm32x_info
->user_bank_size
/ 1024;
901 LOG_INFO("flash size = %dkbytes", flash_size_in_kb
);
903 /* did we assign flash size? */
904 assert(flash_size_in_kb
!= 0xffff);
906 /* calculate numbers of pages */
907 int num_pages
= flash_size_in_kb
* 1024 / page_size
;
909 /* check that calculation result makes sense */
910 assert(num_pages
> 0);
913 bank
->sectors
= NULL
;
915 free(bank
->prot_blocks
);
916 bank
->prot_blocks
= NULL
;
918 bank
->base
= base_address
;
919 bank
->size
= (num_pages
* page_size
);
921 bank
->num_sectors
= num_pages
;
922 bank
->sectors
= alloc_block_array(0, page_size
, num_pages
);
926 /* calculate number of write protection blocks */
927 int num_prot_blocks
= num_pages
/ stm32x_info
->ppage_size
;
928 if (num_prot_blocks
> 32)
929 num_prot_blocks
= 32;
931 bank
->num_prot_blocks
= num_prot_blocks
;
932 bank
->prot_blocks
= alloc_block_array(0, stm32x_info
->ppage_size
* page_size
, num_prot_blocks
);
933 if (!bank
->prot_blocks
)
936 if (num_prot_blocks
== 32)
937 bank
->prot_blocks
[31].size
= (num_pages
- (31 * stm32x_info
->ppage_size
)) * page_size
;
939 stm32x_info
->probed
= true;
944 static int stm32x_auto_probe(struct flash_bank
*bank
)
946 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
947 if (stm32x_info
->probed
)
949 return stm32x_probe(bank
);
953 COMMAND_HANDLER(stm32x_handle_part_id_command
)
959 static const char *get_stm32f0_revision(uint16_t rev_id
)
961 const char *rev_str
= NULL
;
974 static int get_stm32x_info(struct flash_bank
*bank
, struct command_invocation
*cmd
)
976 uint32_t dbgmcu_idcode
;
978 /* read stm32 device id register */
979 int retval
= stm32x_get_device_id(bank
, &dbgmcu_idcode
);
980 if (retval
!= ERROR_OK
)
983 uint16_t device_id
= dbgmcu_idcode
& 0xfff;
984 uint16_t rev_id
= dbgmcu_idcode
>> 16;
985 const char *device_str
;
986 const char *rev_str
= NULL
;
990 device_str
= "STM32F10x (Medium Density)";
997 case 0x1303: /* gd32f1x0 */
998 device_str
= "GD32F1x0";
1001 case 0x1704: /* gd32f3x0 */
1002 device_str
= "GD32F3x0";
1005 case 0x1909: /* gd32e23x */
1006 device_str
= "GD32E23x";
1024 device_str
= "STM32F10x (Low Density)";
1034 device_str
= "STM32F10x (High Density)";
1052 device_str
= "STM32F10x (Connectivity)";
1066 device_str
= "STM32F100 (Low/Medium Density)";
1080 device_str
= "STM32F302xB/C";
1102 device_str
= "STM32F100 (High Density)";
1116 device_str
= "STM32F10x (XL Density)";
1126 device_str
= "STM32F37x";
1140 device_str
= "STM32F33x";
1150 device_str
= "STM32F302x6/8";
1164 device_str
= "STM32F03x";
1165 rev_str
= get_stm32f0_revision(rev_id
);
1169 device_str
= "STM32F05x";
1170 rev_str
= get_stm32f0_revision(rev_id
);
1174 device_str
= "STM32F04x";
1175 rev_str
= get_stm32f0_revision(rev_id
);
1179 device_str
= "STM32F303xD/E";
1188 device_str
= "STM32F07x";
1189 rev_str
= get_stm32f0_revision(rev_id
);
1193 device_str
= "STM32F09x";
1194 rev_str
= get_stm32f0_revision(rev_id
);
1198 command_print_sameline(cmd
, "Cannot identify target as a STM32F0/1/3\n");
1203 command_print_sameline(cmd
, "%s - Rev: %s", device_str
, rev_str
);
1205 command_print_sameline(cmd
, "%s - Rev: unknown (0x%04x)", device_str
, rev_id
);
1210 COMMAND_HANDLER(stm32x_handle_lock_command
)
1212 struct target
*target
= NULL
;
1213 struct stm32x_flash_bank
*stm32x_info
= NULL
;
1216 return ERROR_COMMAND_SYNTAX_ERROR
;
1218 struct flash_bank
*bank
;
1219 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1220 if (retval
!= ERROR_OK
)
1223 stm32x_info
= bank
->driver_priv
;
1225 target
= bank
->target
;
1227 if (target
->state
!= TARGET_HALTED
) {
1228 LOG_ERROR("Target not halted");
1229 return ERROR_TARGET_NOT_HALTED
;
1232 retval
= stm32x_check_operation_supported(bank
);
1233 if (retval
!= ERROR_OK
)
1236 if (stm32x_erase_options(bank
) != ERROR_OK
) {
1237 command_print(CMD
, "stm32x failed to erase options");
1241 /* set readout protection */
1242 stm32x_info
->option_bytes
.rdp
= 0;
1244 if (stm32x_write_options(bank
) != ERROR_OK
) {
1245 command_print(CMD
, "stm32x failed to lock device");
1249 command_print(CMD
, "stm32x locked");
1254 COMMAND_HANDLER(stm32x_handle_unlock_command
)
1256 struct target
*target
= NULL
;
1259 return ERROR_COMMAND_SYNTAX_ERROR
;
1261 struct flash_bank
*bank
;
1262 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1263 if (retval
!= ERROR_OK
)
1266 target
= bank
->target
;
1268 if (target
->state
!= TARGET_HALTED
) {
1269 LOG_ERROR("Target not halted");
1270 return ERROR_TARGET_NOT_HALTED
;
1273 retval
= stm32x_check_operation_supported(bank
);
1274 if (retval
!= ERROR_OK
)
1277 if (stm32x_erase_options(bank
) != ERROR_OK
) {
1278 command_print(CMD
, "stm32x failed to erase options");
1282 if (stm32x_write_options(bank
) != ERROR_OK
) {
1283 command_print(CMD
, "stm32x failed to unlock device");
1287 command_print(CMD
, "stm32x unlocked.\n"
1288 "INFO: a reset or power cycle is required "
1289 "for the new settings to take effect.");
1294 COMMAND_HANDLER(stm32x_handle_options_read_command
)
1296 uint32_t optionbyte
, protection
;
1297 struct target
*target
= NULL
;
1298 struct stm32x_flash_bank
*stm32x_info
= NULL
;
1301 return ERROR_COMMAND_SYNTAX_ERROR
;
1303 struct flash_bank
*bank
;
1304 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1305 if (retval
!= ERROR_OK
)
1308 stm32x_info
= bank
->driver_priv
;
1310 target
= bank
->target
;
1312 if (target
->state
!= TARGET_HALTED
) {
1313 LOG_ERROR("Target not halted");
1314 return ERROR_TARGET_NOT_HALTED
;
1317 retval
= stm32x_check_operation_supported(bank
);
1318 if (retval
!= ERROR_OK
)
1321 retval
= target_read_u32(target
, STM32_FLASH_OBR_B0
, &optionbyte
);
1322 if (retval
!= ERROR_OK
)
1325 uint16_t user_data
= optionbyte
>> stm32x_info
->user_data_offset
;
1327 retval
= target_read_u32(target
, STM32_FLASH_WRPR_B0
, &protection
);
1328 if (retval
!= ERROR_OK
)
1331 if (optionbyte
& (1 << OPT_ERROR
))
1332 command_print(CMD
, "option byte complement error");
1334 command_print(CMD
, "option byte register = 0x%" PRIx32
"", optionbyte
);
1335 command_print(CMD
, "write protection register = 0x%" PRIx32
"", protection
);
1337 command_print(CMD
, "read protection: %s",
1338 (optionbyte
& (1 << OPT_READOUT
)) ? "on" : "off");
1340 /* user option bytes are offset depending on variant */
1341 optionbyte
>>= stm32x_info
->option_offset
;
1343 command_print(CMD
, "watchdog: %sware",
1344 (optionbyte
& (1 << OPT_RDWDGSW
)) ? "soft" : "hard");
1346 command_print(CMD
, "stop mode: %sreset generated upon entry",
1347 (optionbyte
& (1 << OPT_RDRSTSTOP
)) ? "no " : "");
1349 command_print(CMD
, "standby mode: %sreset generated upon entry",
1350 (optionbyte
& (1 << OPT_RDRSTSTDBY
)) ? "no " : "");
1352 if (stm32x_info
->has_dual_banks
)
1353 command_print(CMD
, "boot: bank %d", (optionbyte
& (1 << OPT_BFB2
)) ? 0 : 1);
1355 command_print(CMD
, "user data = 0x%02" PRIx16
"", user_data
);
1360 COMMAND_HANDLER(stm32x_handle_options_write_command
)
1362 struct target
*target
= NULL
;
1363 struct stm32x_flash_bank
*stm32x_info
= NULL
;
1368 return ERROR_COMMAND_SYNTAX_ERROR
;
1370 struct flash_bank
*bank
;
1371 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1372 if (retval
!= ERROR_OK
)
1375 stm32x_info
= bank
->driver_priv
;
1377 target
= bank
->target
;
1379 if (target
->state
!= TARGET_HALTED
) {
1380 LOG_ERROR("Target not halted");
1381 return ERROR_TARGET_NOT_HALTED
;
1384 retval
= stm32x_check_operation_supported(bank
);
1385 if (retval
!= ERROR_OK
)
1388 retval
= stm32x_read_options(bank
);
1389 if (retval
!= ERROR_OK
)
1392 /* start with current options */
1393 optionbyte
= stm32x_info
->option_bytes
.user
;
1394 useropt
= stm32x_info
->option_bytes
.data
;
1396 /* skip over flash bank */
1401 if (strcmp("SWWDG", CMD_ARGV
[0]) == 0)
1402 optionbyte
|= (1 << 0);
1403 else if (strcmp("HWWDG", CMD_ARGV
[0]) == 0)
1404 optionbyte
&= ~(1 << 0);
1405 else if (strcmp("NORSTSTOP", CMD_ARGV
[0]) == 0)
1406 optionbyte
|= (1 << 1);
1407 else if (strcmp("RSTSTOP", CMD_ARGV
[0]) == 0)
1408 optionbyte
&= ~(1 << 1);
1409 else if (strcmp("NORSTSTNDBY", CMD_ARGV
[0]) == 0)
1410 optionbyte
|= (1 << 2);
1411 else if (strcmp("RSTSTNDBY", CMD_ARGV
[0]) == 0)
1412 optionbyte
&= ~(1 << 2);
1413 else if (strcmp("USEROPT", CMD_ARGV
[0]) == 0) {
1415 return ERROR_COMMAND_SYNTAX_ERROR
;
1416 COMMAND_PARSE_NUMBER(u16
, CMD_ARGV
[1], useropt
);
1419 } else if (stm32x_info
->has_dual_banks
) {
1420 if (strcmp("BOOT0", CMD_ARGV
[0]) == 0)
1421 optionbyte
|= (1 << 3);
1422 else if (strcmp("BOOT1", CMD_ARGV
[0]) == 0)
1423 optionbyte
&= ~(1 << 3);
1425 return ERROR_COMMAND_SYNTAX_ERROR
;
1427 return ERROR_COMMAND_SYNTAX_ERROR
;
1432 if (stm32x_erase_options(bank
) != ERROR_OK
) {
1433 command_print(CMD
, "stm32x failed to erase options");
1437 stm32x_info
->option_bytes
.user
= optionbyte
;
1438 stm32x_info
->option_bytes
.data
= useropt
;
1440 if (stm32x_write_options(bank
) != ERROR_OK
) {
1441 command_print(CMD
, "stm32x failed to write options");
1445 command_print(CMD
, "stm32x write options complete.\n"
1446 "INFO: %spower cycle is required "
1447 "for the new settings to take effect.",
1448 stm32x_info
->can_load_options
1449 ? "'stm32f1x options_load' command or " : "");
1454 COMMAND_HANDLER(stm32x_handle_options_load_command
)
1457 return ERROR_COMMAND_SYNTAX_ERROR
;
1459 struct flash_bank
*bank
;
1460 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1461 if (retval
!= ERROR_OK
)
1464 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
1466 if (!stm32x_info
->can_load_options
) {
1467 LOG_ERROR("Command not applicable to stm32f1x devices - power cycle is "
1468 "required instead.");
1472 struct target
*target
= bank
->target
;
1474 if (target
->state
!= TARGET_HALTED
) {
1475 LOG_ERROR("Target not halted");
1476 return ERROR_TARGET_NOT_HALTED
;
1479 retval
= stm32x_check_operation_supported(bank
);
1480 if (retval
!= ERROR_OK
)
1483 /* unlock option flash registers */
1484 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY1
);
1485 if (retval
!= ERROR_OK
)
1487 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY2
);
1488 if (retval
!= ERROR_OK
)
1491 /* force re-load of option bytes - generates software reset */
1492 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_OBL_LAUNCH
);
1493 if (retval
!= ERROR_OK
)
1499 static int stm32x_mass_erase(struct flash_bank
*bank
)
1501 struct target
*target
= bank
->target
;
1503 if (target
->state
!= TARGET_HALTED
) {
1504 LOG_ERROR("Target not halted");
1505 return ERROR_TARGET_NOT_HALTED
;
1508 /* unlock option flash registers */
1509 int retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY1
);
1510 if (retval
!= ERROR_OK
)
1512 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY2
);
1513 if (retval
!= ERROR_OK
)
1516 /* mass erase flash memory */
1517 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_MER
);
1518 if (retval
!= ERROR_OK
)
1520 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
),
1521 FLASH_MER
| FLASH_STRT
);
1522 if (retval
!= ERROR_OK
)
1525 retval
= stm32x_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
);
1526 if (retval
!= ERROR_OK
)
1529 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_LOCK
);
1530 if (retval
!= ERROR_OK
)
1536 COMMAND_HANDLER(stm32x_handle_mass_erase_command
)
1539 return ERROR_COMMAND_SYNTAX_ERROR
;
1541 struct flash_bank
*bank
;
1542 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1543 if (retval
!= ERROR_OK
)
1546 retval
= stm32x_mass_erase(bank
);
1547 if (retval
== ERROR_OK
)
1548 command_print(CMD
, "stm32x mass erase complete");
1550 command_print(CMD
, "stm32x mass erase failed");
1555 static const struct command_registration stm32f1x_exec_command_handlers
[] = {
1558 .handler
= stm32x_handle_lock_command
,
1559 .mode
= COMMAND_EXEC
,
1561 .help
= "Lock entire flash device.",
1565 .handler
= stm32x_handle_unlock_command
,
1566 .mode
= COMMAND_EXEC
,
1568 .help
= "Unlock entire protected flash device.",
1571 .name
= "mass_erase",
1572 .handler
= stm32x_handle_mass_erase_command
,
1573 .mode
= COMMAND_EXEC
,
1575 .help
= "Erase entire flash device.",
1578 .name
= "options_read",
1579 .handler
= stm32x_handle_options_read_command
,
1580 .mode
= COMMAND_EXEC
,
1582 .help
= "Read and display device option bytes.",
1585 .name
= "options_write",
1586 .handler
= stm32x_handle_options_write_command
,
1587 .mode
= COMMAND_EXEC
,
1588 .usage
= "bank_id ('SWWDG'|'HWWDG') "
1589 "('RSTSTNDBY'|'NORSTSTNDBY') "
1590 "('RSTSTOP'|'NORSTSTOP') ('USEROPT' user_data)",
1591 .help
= "Replace bits in device option bytes.",
1594 .name
= "options_load",
1595 .handler
= stm32x_handle_options_load_command
,
1596 .mode
= COMMAND_EXEC
,
1598 .help
= "Force re-load of device option bytes.",
1600 COMMAND_REGISTRATION_DONE
1603 static const struct command_registration stm32f1x_command_handlers
[] = {
1606 .mode
= COMMAND_ANY
,
1607 .help
= "stm32f1x flash command group",
1609 .chain
= stm32f1x_exec_command_handlers
,
1611 COMMAND_REGISTRATION_DONE
1614 const struct flash_driver stm32f1x_flash
= {
1616 .commands
= stm32f1x_command_handlers
,
1617 .flash_bank_command
= stm32x_flash_bank_command
,
1618 .erase
= stm32x_erase
,
1619 .protect
= stm32x_protect
,
1620 .write
= stm32x_write
,
1621 .read
= default_flash_read
,
1622 .probe
= stm32x_probe
,
1623 .auto_probe
= stm32x_auto_probe
,
1624 .erase_check
= default_flash_blank_check
,
1625 .protect_check
= stm32x_protect_check
,
1626 .info
= get_stm32x_info
,
1627 .free_driver_priv
= default_flash_free_driver_priv
,
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