1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2011 by Andreas Fritiofson *
9 * andreas.fritiofson@gmail.com *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
30 #include <helper/binarybuffer.h>
31 #include <target/algorithm.h>
32 #include <target/armv7m.h>
34 /* stm32x register locations */
36 #define FLASH_REG_BASE_B0 0x40022000
37 #define FLASH_REG_BASE_B1 0x40022040
39 #define STM32_FLASH_ACR 0x00
40 #define STM32_FLASH_KEYR 0x04
41 #define STM32_FLASH_OPTKEYR 0x08
42 #define STM32_FLASH_SR 0x0C
43 #define STM32_FLASH_CR 0x10
44 #define STM32_FLASH_AR 0x14
45 #define STM32_FLASH_OBR 0x1C
46 #define STM32_FLASH_WRPR 0x20
48 /* TODO: Check if code using these really should be hard coded to bank 0.
49 * There are valid cases, on dual flash devices the protection of the
50 * second bank is done on the bank0 reg's. */
51 #define STM32_FLASH_ACR_B0 0x40022000
52 #define STM32_FLASH_KEYR_B0 0x40022004
53 #define STM32_FLASH_OPTKEYR_B0 0x40022008
54 #define STM32_FLASH_SR_B0 0x4002200C
55 #define STM32_FLASH_CR_B0 0x40022010
56 #define STM32_FLASH_AR_B0 0x40022014
57 #define STM32_FLASH_OBR_B0 0x4002201C
58 #define STM32_FLASH_WRPR_B0 0x40022020
60 /* option byte location */
62 #define STM32_OB_RDP 0x1FFFF800
63 #define STM32_OB_USER 0x1FFFF802
64 #define STM32_OB_DATA0 0x1FFFF804
65 #define STM32_OB_DATA1 0x1FFFF806
66 #define STM32_OB_WRP0 0x1FFFF808
67 #define STM32_OB_WRP1 0x1FFFF80A
68 #define STM32_OB_WRP2 0x1FFFF80C
69 #define STM32_OB_WRP3 0x1FFFF80E
71 /* FLASH_CR register bits */
73 #define FLASH_PG (1 << 0)
74 #define FLASH_PER (1 << 1)
75 #define FLASH_MER (1 << 2)
76 #define FLASH_OPTPG (1 << 4)
77 #define FLASH_OPTER (1 << 5)
78 #define FLASH_STRT (1 << 6)
79 #define FLASH_LOCK (1 << 7)
80 #define FLASH_OPTWRE (1 << 9)
81 #define FLASH_OBL_LAUNCH (1 << 13) /* except stm32f1x series */
83 /* FLASH_SR register bits */
85 #define FLASH_BSY (1 << 0)
86 #define FLASH_PGERR (1 << 2)
87 #define FLASH_WRPRTERR (1 << 4)
88 #define FLASH_EOP (1 << 5)
90 /* STM32_FLASH_OBR bit definitions (reading) */
95 #define OPT_RDRSTSTOP 3
96 #define OPT_RDRSTSTDBY 4
97 #define OPT_BFB2 5 /* dual flash bank only */
99 /* register unlock keys */
101 #define KEY1 0x45670123
102 #define KEY2 0xCDEF89AB
106 #define FLASH_WRITE_TIMEOUT 10
107 #define FLASH_ERASE_TIMEOUT 100
109 struct stm32x_options
{
116 struct stm32x_flash_bank
{
117 struct stm32x_options option_bytes
;
122 /* used to access dual flash bank stm32xl */
123 bool can_load_options
;
124 uint32_t register_base
;
126 int user_data_offset
;
128 uint32_t user_bank_size
;
131 static int stm32x_mass_erase(struct flash_bank
*bank
);
132 static int stm32x_get_device_id(struct flash_bank
*bank
, uint32_t *device_id
);
133 static int stm32x_write_block(struct flash_bank
*bank
, const uint8_t *buffer
,
134 uint32_t address
, uint32_t count
);
136 /* flash bank stm32x <base> <size> 0 0 <target#>
138 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command
)
140 struct stm32x_flash_bank
*stm32x_info
;
143 return ERROR_COMMAND_SYNTAX_ERROR
;
145 stm32x_info
= malloc(sizeof(struct stm32x_flash_bank
));
147 bank
->driver_priv
= stm32x_info
;
148 stm32x_info
->probed
= false;
149 stm32x_info
->has_dual_banks
= false;
150 stm32x_info
->can_load_options
= false;
151 stm32x_info
->register_base
= FLASH_REG_BASE_B0
;
152 stm32x_info
->user_bank_size
= bank
->size
;
157 static inline int stm32x_get_flash_reg(struct flash_bank
*bank
, uint32_t reg
)
159 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
160 return reg
+ stm32x_info
->register_base
;
163 static inline int stm32x_get_flash_status(struct flash_bank
*bank
, uint32_t *status
)
165 struct target
*target
= bank
->target
;
166 return target_read_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_SR
), status
);
169 static int stm32x_wait_status_busy(struct flash_bank
*bank
, int timeout
)
171 struct target
*target
= bank
->target
;
173 int retval
= ERROR_OK
;
175 /* wait for busy to clear */
177 retval
= stm32x_get_flash_status(bank
, &status
);
178 if (retval
!= ERROR_OK
)
180 LOG_DEBUG("status: 0x%" PRIx32
"", status
);
181 if ((status
& FLASH_BSY
) == 0)
183 if (timeout
-- <= 0) {
184 LOG_ERROR("timed out waiting for flash");
190 if (status
& FLASH_WRPRTERR
) {
191 LOG_ERROR("stm32x device protected");
195 if (status
& FLASH_PGERR
) {
196 LOG_ERROR("stm32x device programming failed");
200 /* Clear but report errors */
201 if (status
& (FLASH_WRPRTERR
| FLASH_PGERR
)) {
202 /* If this operation fails, we ignore it and report the original
205 target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_SR
),
206 FLASH_WRPRTERR
| FLASH_PGERR
);
211 static int stm32x_check_operation_supported(struct flash_bank
*bank
)
213 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
215 /* if we have a dual flash bank device then
216 * we need to perform option byte stuff on bank0 only */
217 if (stm32x_info
->register_base
!= FLASH_REG_BASE_B0
) {
218 LOG_ERROR("Option Byte Operation's must use bank0");
219 return ERROR_FLASH_OPERATION_FAILED
;
225 static int stm32x_read_options(struct flash_bank
*bank
)
227 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
228 struct target
*target
= bank
->target
;
229 uint32_t option_bytes
;
232 /* read user and read protection option bytes, user data option bytes */
233 retval
= target_read_u32(target
, STM32_FLASH_OBR_B0
, &option_bytes
);
234 if (retval
!= ERROR_OK
)
237 stm32x_info
->option_bytes
.rdp
= (option_bytes
& (1 << OPT_READOUT
)) ? 0 : stm32x_info
->default_rdp
;
238 stm32x_info
->option_bytes
.user
= (option_bytes
>> stm32x_info
->option_offset
>> 2) & 0xff;
239 stm32x_info
->option_bytes
.data
= (option_bytes
>> stm32x_info
->user_data_offset
) & 0xffff;
241 /* read write protection option bytes */
242 retval
= target_read_u32(target
, STM32_FLASH_WRPR_B0
, &stm32x_info
->option_bytes
.protection
);
243 if (retval
!= ERROR_OK
)
249 static int stm32x_erase_options(struct flash_bank
*bank
)
251 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
252 struct target
*target
= bank
->target
;
254 /* read current options */
255 stm32x_read_options(bank
);
257 /* unlock flash registers */
258 int retval
= target_write_u32(target
, STM32_FLASH_KEYR_B0
, KEY1
);
259 if (retval
!= ERROR_OK
)
262 retval
= target_write_u32(target
, STM32_FLASH_KEYR_B0
, KEY2
);
263 if (retval
!= ERROR_OK
)
266 /* unlock option flash registers */
267 retval
= target_write_u32(target
, STM32_FLASH_OPTKEYR_B0
, KEY1
);
268 if (retval
!= ERROR_OK
)
270 retval
= target_write_u32(target
, STM32_FLASH_OPTKEYR_B0
, KEY2
);
271 if (retval
!= ERROR_OK
)
274 /* erase option bytes */
275 retval
= target_write_u32(target
, STM32_FLASH_CR_B0
, FLASH_OPTER
| FLASH_OPTWRE
);
276 if (retval
!= ERROR_OK
)
278 retval
= target_write_u32(target
, STM32_FLASH_CR_B0
, FLASH_OPTER
| FLASH_STRT
| FLASH_OPTWRE
);
279 if (retval
!= ERROR_OK
)
282 retval
= stm32x_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
);
283 if (retval
!= ERROR_OK
)
286 /* clear read protection option byte
287 * this will also force a device unlock if set */
288 stm32x_info
->option_bytes
.rdp
= stm32x_info
->default_rdp
;
293 static int stm32x_write_options(struct flash_bank
*bank
)
295 struct stm32x_flash_bank
*stm32x_info
= NULL
;
296 struct target
*target
= bank
->target
;
298 stm32x_info
= bank
->driver_priv
;
300 /* unlock flash registers */
301 int retval
= target_write_u32(target
, STM32_FLASH_KEYR_B0
, KEY1
);
302 if (retval
!= ERROR_OK
)
304 retval
= target_write_u32(target
, STM32_FLASH_KEYR_B0
, KEY2
);
305 if (retval
!= ERROR_OK
)
308 /* unlock option flash registers */
309 retval
= target_write_u32(target
, STM32_FLASH_OPTKEYR_B0
, KEY1
);
310 if (retval
!= ERROR_OK
)
312 retval
= target_write_u32(target
, STM32_FLASH_OPTKEYR_B0
, KEY2
);
313 if (retval
!= ERROR_OK
)
316 /* program option bytes */
317 retval
= target_write_u32(target
, STM32_FLASH_CR_B0
, FLASH_OPTPG
| FLASH_OPTWRE
);
318 if (retval
!= ERROR_OK
)
321 uint8_t opt_bytes
[16];
323 target_buffer_set_u16(target
, opt_bytes
, stm32x_info
->option_bytes
.rdp
);
324 target_buffer_set_u16(target
, opt_bytes
+ 2, stm32x_info
->option_bytes
.user
);
325 target_buffer_set_u16(target
, opt_bytes
+ 4, stm32x_info
->option_bytes
.data
& 0xff);
326 target_buffer_set_u16(target
, opt_bytes
+ 6, (stm32x_info
->option_bytes
.data
>> 8) & 0xff);
327 target_buffer_set_u16(target
, opt_bytes
+ 8, stm32x_info
->option_bytes
.protection
& 0xff);
328 target_buffer_set_u16(target
, opt_bytes
+ 10, (stm32x_info
->option_bytes
.protection
>> 8) & 0xff);
329 target_buffer_set_u16(target
, opt_bytes
+ 12, (stm32x_info
->option_bytes
.protection
>> 16) & 0xff);
330 target_buffer_set_u16(target
, opt_bytes
+ 14, (stm32x_info
->option_bytes
.protection
>> 24) & 0xff);
332 retval
= stm32x_write_block(bank
, opt_bytes
, STM32_OB_RDP
, sizeof(opt_bytes
) / 2);
333 if (retval
!= ERROR_OK
) {
334 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
)
335 LOG_ERROR("working area required to erase options bytes");
339 retval
= target_write_u32(target
, STM32_FLASH_CR_B0
, FLASH_LOCK
);
340 if (retval
!= ERROR_OK
)
346 static int stm32x_protect_check(struct flash_bank
*bank
)
348 struct target
*target
= bank
->target
;
351 int retval
= stm32x_check_operation_supported(bank
);
352 if (ERROR_OK
!= retval
)
355 /* medium density - each bit refers to a 4 sector protection block
356 * high density - each bit refers to a 2 sector protection block
357 * bit 31 refers to all remaining sectors in a bank */
358 retval
= target_read_u32(target
, STM32_FLASH_WRPR_B0
, &protection
);
359 if (retval
!= ERROR_OK
)
362 for (int i
= 0; i
< bank
->num_prot_blocks
; i
++)
363 bank
->prot_blocks
[i
].is_protected
= (protection
& (1 << i
)) ? 0 : 1;
368 static int stm32x_erase(struct flash_bank
*bank
, int first
, int last
)
370 struct target
*target
= bank
->target
;
372 if (bank
->target
->state
!= TARGET_HALTED
) {
373 LOG_ERROR("Target not halted");
374 return ERROR_TARGET_NOT_HALTED
;
377 if ((first
== 0) && (last
== (bank
->num_sectors
- 1)))
378 return stm32x_mass_erase(bank
);
380 /* unlock flash registers */
381 int retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY1
);
382 if (retval
!= ERROR_OK
)
384 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY2
);
385 if (retval
!= ERROR_OK
)
388 for (int i
= first
; i
<= last
; i
++) {
389 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_PER
);
390 if (retval
!= ERROR_OK
)
392 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_AR
),
393 bank
->base
+ bank
->sectors
[i
].offset
);
394 if (retval
!= ERROR_OK
)
396 retval
= target_write_u32(target
,
397 stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_PER
| FLASH_STRT
);
398 if (retval
!= ERROR_OK
)
401 retval
= stm32x_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
);
402 if (retval
!= ERROR_OK
)
405 bank
->sectors
[i
].is_erased
= 1;
408 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_LOCK
);
409 if (retval
!= ERROR_OK
)
415 static int stm32x_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
417 struct target
*target
= bank
->target
;
418 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
420 if (target
->state
!= TARGET_HALTED
) {
421 LOG_ERROR("Target not halted");
422 return ERROR_TARGET_NOT_HALTED
;
425 int retval
= stm32x_check_operation_supported(bank
);
426 if (retval
!= ERROR_OK
)
429 retval
= stm32x_erase_options(bank
);
430 if (retval
!= ERROR_OK
) {
431 LOG_ERROR("stm32x failed to erase options");
435 for (int i
= first
; i
<= last
; i
++) {
437 stm32x_info
->option_bytes
.protection
&= ~(1 << i
);
439 stm32x_info
->option_bytes
.protection
|= (1 << i
);
442 return stm32x_write_options(bank
);
445 static int stm32x_write_block(struct flash_bank
*bank
, const uint8_t *buffer
,
446 uint32_t address
, uint32_t count
)
448 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
449 struct target
*target
= bank
->target
;
450 uint32_t buffer_size
= 16384;
451 struct working_area
*write_algorithm
;
452 struct working_area
*source
;
453 struct reg_param reg_params
[5];
454 struct armv7m_algorithm armv7m_info
;
455 int retval
= ERROR_OK
;
457 static const uint8_t stm32x_flash_write_code
[] = {
458 #include "../../../contrib/loaders/flash/stm32/stm32f1x.inc"
461 /* flash write code */
462 if (target_alloc_working_area(target
, sizeof(stm32x_flash_write_code
),
463 &write_algorithm
) != ERROR_OK
) {
464 LOG_WARNING("no working area available, can't do block memory writes");
465 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
468 retval
= target_write_buffer(target
, write_algorithm
->address
,
469 sizeof(stm32x_flash_write_code
), stm32x_flash_write_code
);
470 if (retval
!= ERROR_OK
) {
471 target_free_working_area(target
, write_algorithm
);
476 while (target_alloc_working_area_try(target
, buffer_size
, &source
) != ERROR_OK
) {
478 buffer_size
&= ~3UL; /* Make sure it's 4 byte aligned */
479 if (buffer_size
<= 256) {
480 /* we already allocated the writing code, but failed to get a
481 * buffer, free the algorithm */
482 target_free_working_area(target
, write_algorithm
);
484 LOG_WARNING("no large enough working area available, can't do block memory writes");
485 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
489 init_reg_param(®_params
[0], "r0", 32, PARAM_IN_OUT
); /* flash base (in), status (out) */
490 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
); /* count (halfword-16bit) */
491 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
); /* buffer start */
492 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
); /* buffer end */
493 init_reg_param(®_params
[4], "r4", 32, PARAM_IN_OUT
); /* target address */
495 buf_set_u32(reg_params
[0].value
, 0, 32, stm32x_info
->register_base
);
496 buf_set_u32(reg_params
[1].value
, 0, 32, count
);
497 buf_set_u32(reg_params
[2].value
, 0, 32, source
->address
);
498 buf_set_u32(reg_params
[3].value
, 0, 32, source
->address
+ source
->size
);
499 buf_set_u32(reg_params
[4].value
, 0, 32, address
);
501 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
502 armv7m_info
.core_mode
= ARM_MODE_THREAD
;
504 retval
= target_run_flash_async_algorithm(target
, buffer
, count
, 2,
507 source
->address
, source
->size
,
508 write_algorithm
->address
, 0,
511 if (retval
== ERROR_FLASH_OPERATION_FAILED
) {
512 LOG_ERROR("flash write failed at address 0x%"PRIx32
,
513 buf_get_u32(reg_params
[4].value
, 0, 32));
515 if (buf_get_u32(reg_params
[0].value
, 0, 32) & FLASH_PGERR
) {
516 LOG_ERROR("flash memory not erased before writing");
517 /* Clear but report errors */
518 target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_SR
), FLASH_PGERR
);
521 if (buf_get_u32(reg_params
[0].value
, 0, 32) & FLASH_WRPRTERR
) {
522 LOG_ERROR("flash memory write protected");
523 /* Clear but report errors */
524 target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_SR
), FLASH_WRPRTERR
);
528 target_free_working_area(target
, source
);
529 target_free_working_area(target
, write_algorithm
);
531 destroy_reg_param(®_params
[0]);
532 destroy_reg_param(®_params
[1]);
533 destroy_reg_param(®_params
[2]);
534 destroy_reg_param(®_params
[3]);
535 destroy_reg_param(®_params
[4]);
540 static int stm32x_write(struct flash_bank
*bank
, const uint8_t *buffer
,
541 uint32_t offset
, uint32_t count
)
543 struct target
*target
= bank
->target
;
544 uint8_t *new_buffer
= NULL
;
546 if (bank
->target
->state
!= TARGET_HALTED
) {
547 LOG_ERROR("Target not halted");
548 return ERROR_TARGET_NOT_HALTED
;
552 LOG_ERROR("offset 0x%" PRIx32
" breaks required 2-byte alignment", offset
);
553 return ERROR_FLASH_DST_BREAKS_ALIGNMENT
;
556 /* If there's an odd number of bytes, the data has to be padded. Duplicate
557 * the buffer and use the normal code path with a single block write since
558 * it's probably cheaper than to special case the last odd write using
559 * discrete accesses. */
561 new_buffer
= malloc(count
+ 1);
562 if (new_buffer
== NULL
) {
563 LOG_ERROR("odd number of bytes to write and no memory for padding buffer");
566 LOG_INFO("odd number of bytes to write, padding with 0xff");
567 buffer
= memcpy(new_buffer
, buffer
, count
);
568 new_buffer
[count
++] = 0xff;
571 uint32_t words_remaining
= count
/ 2;
574 /* unlock flash registers */
575 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY1
);
576 if (retval
!= ERROR_OK
)
578 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY2
);
579 if (retval
!= ERROR_OK
)
582 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_PG
);
583 if (retval
!= ERROR_OK
)
586 /* try using a block write */
587 retval
= stm32x_write_block(bank
, buffer
, bank
->base
+ offset
, words_remaining
);
589 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
) {
590 /* if block write failed (no sufficient working area),
591 * we use normal (slow) single halfword accesses */
592 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
594 while (words_remaining
> 0) {
596 memcpy(&value
, buffer
, sizeof(uint16_t));
598 retval
= target_write_u16(target
, bank
->base
+ offset
, value
);
599 if (retval
!= ERROR_OK
)
600 goto reset_pg_and_lock
;
602 retval
= stm32x_wait_status_busy(bank
, 5);
603 if (retval
!= ERROR_OK
)
604 goto reset_pg_and_lock
;
613 retval2
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_LOCK
);
614 if (retval
== ERROR_OK
)
624 static int stm32x_get_device_id(struct flash_bank
*bank
, uint32_t *device_id
)
626 /* This check the device CPUID core register to detect
627 * the M0 from the M3 devices. */
629 struct target
*target
= bank
->target
;
630 uint32_t cpuid
, device_id_register
= 0;
632 /* Get the CPUID from the ARM Core
633 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0432c/DDI0432C_cortex_m0_r0p0_trm.pdf 4.2.1 */
634 int retval
= target_read_u32(target
, 0xE000ED00, &cpuid
);
635 if (retval
!= ERROR_OK
)
638 if (((cpuid
>> 4) & 0xFFF) == 0xC20) {
639 /* 0xC20 is M0 devices */
640 device_id_register
= 0x40015800;
641 } else if (((cpuid
>> 4) & 0xFFF) == 0xC23) {
642 /* 0xC23 is M3 devices */
643 device_id_register
= 0xE0042000;
644 } else if (((cpuid
>> 4) & 0xFFF) == 0xC24) {
645 /* 0xC24 is M4 devices */
646 device_id_register
= 0xE0042000;
648 LOG_ERROR("Cannot identify target as a stm32x");
652 /* read stm32 device id register */
653 retval
= target_read_u32(target
, device_id_register
, device_id
);
654 if (retval
!= ERROR_OK
)
660 static int stm32x_get_flash_size(struct flash_bank
*bank
, uint16_t *flash_size_in_kb
)
662 struct target
*target
= bank
->target
;
663 uint32_t cpuid
, flash_size_reg
;
665 int retval
= target_read_u32(target
, 0xE000ED00, &cpuid
);
666 if (retval
!= ERROR_OK
)
669 if (((cpuid
>> 4) & 0xFFF) == 0xC20) {
670 /* 0xC20 is M0 devices */
671 flash_size_reg
= 0x1FFFF7CC;
672 } else if (((cpuid
>> 4) & 0xFFF) == 0xC23) {
673 /* 0xC23 is M3 devices */
674 flash_size_reg
= 0x1FFFF7E0;
675 } else if (((cpuid
>> 4) & 0xFFF) == 0xC24) {
676 /* 0xC24 is M4 devices */
677 flash_size_reg
= 0x1FFFF7CC;
679 LOG_ERROR("Cannot identify target as a stm32x");
683 retval
= target_read_u16(target
, flash_size_reg
, flash_size_in_kb
);
684 if (retval
!= ERROR_OK
)
690 static int stm32x_probe(struct flash_bank
*bank
)
692 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
693 uint16_t flash_size_in_kb
;
694 uint16_t max_flash_size_in_kb
;
697 uint32_t base_address
= 0x08000000;
699 stm32x_info
->probed
= false;
700 stm32x_info
->register_base
= FLASH_REG_BASE_B0
;
701 stm32x_info
->user_data_offset
= 10;
702 stm32x_info
->option_offset
= 0;
704 /* default factory read protection level 0 */
705 stm32x_info
->default_rdp
= 0xA5;
707 /* read stm32 device id register */
708 int retval
= stm32x_get_device_id(bank
, &device_id
);
709 if (retval
!= ERROR_OK
)
712 LOG_INFO("device id = 0x%08" PRIx32
"", device_id
);
714 /* set page size, protection granularity and max flash size depending on family */
715 switch (device_id
& 0xfff) {
716 case 0x440: /* stm32f05x */
717 case 0x444: /* stm32f03x */
718 case 0x445: /* stm32f04x */
720 stm32x_info
->ppage_size
= 4;
721 max_flash_size_in_kb
= 64;
722 stm32x_info
->user_data_offset
= 16;
723 stm32x_info
->option_offset
= 6;
724 stm32x_info
->default_rdp
= 0xAA;
725 stm32x_info
->can_load_options
= true;
727 case 0x448: /* stm32f07x */
728 case 0x442: /* stm32f09x */
730 stm32x_info
->ppage_size
= 4;
731 max_flash_size_in_kb
= 256;
732 stm32x_info
->user_data_offset
= 16;
733 stm32x_info
->option_offset
= 6;
734 stm32x_info
->default_rdp
= 0xAA;
735 stm32x_info
->can_load_options
= true;
737 case 0x410: /* stm32f1x medium-density */
739 stm32x_info
->ppage_size
= 4;
740 max_flash_size_in_kb
= 128;
742 case 0x412: /* stm32f1x low-density */
744 stm32x_info
->ppage_size
= 4;
745 max_flash_size_in_kb
= 32;
747 case 0x414: /* stm32f1x high-density */
749 stm32x_info
->ppage_size
= 2;
750 max_flash_size_in_kb
= 512;
752 case 0x418: /* stm32f1x connectivity */
754 stm32x_info
->ppage_size
= 2;
755 max_flash_size_in_kb
= 256;
757 case 0x430: /* stm32f1 XL-density (dual flash banks) */
759 stm32x_info
->ppage_size
= 2;
760 max_flash_size_in_kb
= 1024;
761 stm32x_info
->has_dual_banks
= true;
763 case 0x420: /* stm32f100xx low- and medium-density value line */
765 stm32x_info
->ppage_size
= 4;
766 max_flash_size_in_kb
= 128;
768 case 0x428: /* stm32f100xx high-density value line */
770 stm32x_info
->ppage_size
= 4;
771 max_flash_size_in_kb
= 128;
773 case 0x422: /* stm32f302/3xb/c */
775 stm32x_info
->ppage_size
= 2;
776 max_flash_size_in_kb
= 256;
777 stm32x_info
->user_data_offset
= 16;
778 stm32x_info
->option_offset
= 6;
779 stm32x_info
->default_rdp
= 0xAA;
780 stm32x_info
->can_load_options
= true;
782 case 0x446: /* stm32f303xD/E */
784 stm32x_info
->ppage_size
= 2;
785 max_flash_size_in_kb
= 512;
786 stm32x_info
->user_data_offset
= 16;
787 stm32x_info
->option_offset
= 6;
788 stm32x_info
->default_rdp
= 0xAA;
789 stm32x_info
->can_load_options
= true;
791 case 0x432: /* stm32f37x */
793 stm32x_info
->ppage_size
= 2;
794 max_flash_size_in_kb
= 256;
795 stm32x_info
->user_data_offset
= 16;
796 stm32x_info
->option_offset
= 6;
797 stm32x_info
->default_rdp
= 0xAA;
798 stm32x_info
->can_load_options
= true;
800 case 0x438: /* stm32f33x */
801 case 0x439: /* stm32f302x6/8 */
803 stm32x_info
->ppage_size
= 2;
804 max_flash_size_in_kb
= 64;
805 stm32x_info
->user_data_offset
= 16;
806 stm32x_info
->option_offset
= 6;
807 stm32x_info
->default_rdp
= 0xAA;
808 stm32x_info
->can_load_options
= true;
811 LOG_WARNING("Cannot identify target as a STM32 family.");
815 /* get flash size from target. */
816 retval
= stm32x_get_flash_size(bank
, &flash_size_in_kb
);
818 /* failed reading flash size or flash size invalid (early silicon),
819 * default to max target family */
820 if (retval
!= ERROR_OK
|| flash_size_in_kb
== 0xffff || flash_size_in_kb
== 0) {
821 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
822 max_flash_size_in_kb
);
823 flash_size_in_kb
= max_flash_size_in_kb
;
826 if (stm32x_info
->has_dual_banks
) {
827 /* split reported size into matching bank */
828 if (bank
->base
!= 0x08080000) {
829 /* bank 0 will be fixed 512k */
830 flash_size_in_kb
= 512;
832 flash_size_in_kb
-= 512;
833 /* bank1 also uses a register offset */
834 stm32x_info
->register_base
= FLASH_REG_BASE_B1
;
835 base_address
= 0x08080000;
839 /* if the user sets the size manually then ignore the probed value
840 * this allows us to work around devices that have a invalid flash size register value */
841 if (stm32x_info
->user_bank_size
) {
842 LOG_INFO("ignoring flash probed value, using configured bank size");
843 flash_size_in_kb
= stm32x_info
->user_bank_size
/ 1024;
846 LOG_INFO("flash size = %dkbytes", flash_size_in_kb
);
848 /* did we assign flash size? */
849 assert(flash_size_in_kb
!= 0xffff);
851 /* calculate numbers of pages */
852 int num_pages
= flash_size_in_kb
* 1024 / page_size
;
854 /* check that calculation result makes sense */
855 assert(num_pages
> 0);
859 bank
->sectors
= NULL
;
862 if (bank
->prot_blocks
) {
863 free(bank
->prot_blocks
);
864 bank
->prot_blocks
= NULL
;
867 bank
->base
= base_address
;
868 bank
->size
= (num_pages
* page_size
);
870 bank
->num_sectors
= num_pages
;
871 bank
->sectors
= alloc_block_array(0, page_size
, num_pages
);
875 /* calculate number of write protection blocks */
876 int num_prot_blocks
= num_pages
/ stm32x_info
->ppage_size
;
877 if (num_prot_blocks
> 32)
878 num_prot_blocks
= 32;
880 bank
->num_prot_blocks
= num_prot_blocks
;
881 bank
->prot_blocks
= alloc_block_array(0, stm32x_info
->ppage_size
* page_size
, num_prot_blocks
);
882 if (!bank
->prot_blocks
)
885 if (num_prot_blocks
== 32)
886 bank
->prot_blocks
[31].size
= (num_pages
- (31 * stm32x_info
->ppage_size
)) * page_size
;
888 stm32x_info
->probed
= true;
893 static int stm32x_auto_probe(struct flash_bank
*bank
)
895 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
896 if (stm32x_info
->probed
)
898 return stm32x_probe(bank
);
902 COMMAND_HANDLER(stm32x_handle_part_id_command
)
908 static const char *get_stm32f0_revision(uint16_t rev_id
)
910 const char *rev_str
= NULL
;
923 static int get_stm32x_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
925 uint32_t dbgmcu_idcode
;
927 /* read stm32 device id register */
928 int retval
= stm32x_get_device_id(bank
, &dbgmcu_idcode
);
929 if (retval
!= ERROR_OK
)
932 uint16_t device_id
= dbgmcu_idcode
& 0xfff;
933 uint16_t rev_id
= dbgmcu_idcode
>> 16;
934 const char *device_str
;
935 const char *rev_str
= NULL
;
939 device_str
= "STM32F10x (Medium Density)";
961 device_str
= "STM32F10x (Low Density)";
971 device_str
= "STM32F10x (High Density)";
989 device_str
= "STM32F10x (Connectivity)";
1003 device_str
= "STM32F100 (Low/Medium Density)";
1017 device_str
= "STM32F302xB/C";
1039 device_str
= "STM32F100 (High Density)";
1053 device_str
= "STM32F10x (XL Density)";
1063 device_str
= "STM32F37x";
1077 device_str
= "STM32F33x";
1087 device_str
= "STM32F302x6/8";
1101 device_str
= "STM32F03x";
1102 rev_str
= get_stm32f0_revision(rev_id
);
1106 device_str
= "STM32F05x";
1107 rev_str
= get_stm32f0_revision(rev_id
);
1111 device_str
= "STM32F04x";
1112 rev_str
= get_stm32f0_revision(rev_id
);
1116 device_str
= "STM32F303xD/E";
1125 device_str
= "STM32F07x";
1126 rev_str
= get_stm32f0_revision(rev_id
);
1130 device_str
= "STM32F09x";
1131 rev_str
= get_stm32f0_revision(rev_id
);
1135 snprintf(buf
, buf_size
, "Cannot identify target as a STM32F0/1/3\n");
1139 if (rev_str
!= NULL
)
1140 snprintf(buf
, buf_size
, "%s - Rev: %s", device_str
, rev_str
);
1142 snprintf(buf
, buf_size
, "%s - Rev: unknown (0x%04x)", device_str
, rev_id
);
1147 COMMAND_HANDLER(stm32x_handle_lock_command
)
1149 struct target
*target
= NULL
;
1150 struct stm32x_flash_bank
*stm32x_info
= NULL
;
1153 return ERROR_COMMAND_SYNTAX_ERROR
;
1155 struct flash_bank
*bank
;
1156 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1157 if (ERROR_OK
!= retval
)
1160 stm32x_info
= bank
->driver_priv
;
1162 target
= bank
->target
;
1164 if (target
->state
!= TARGET_HALTED
) {
1165 LOG_ERROR("Target not halted");
1166 return ERROR_TARGET_NOT_HALTED
;
1169 retval
= stm32x_check_operation_supported(bank
);
1170 if (ERROR_OK
!= retval
)
1173 if (stm32x_erase_options(bank
) != ERROR_OK
) {
1174 command_print(CMD
, "stm32x failed to erase options");
1178 /* set readout protection */
1179 stm32x_info
->option_bytes
.rdp
= 0;
1181 if (stm32x_write_options(bank
) != ERROR_OK
) {
1182 command_print(CMD
, "stm32x failed to lock device");
1186 command_print(CMD
, "stm32x locked");
1191 COMMAND_HANDLER(stm32x_handle_unlock_command
)
1193 struct target
*target
= NULL
;
1196 return ERROR_COMMAND_SYNTAX_ERROR
;
1198 struct flash_bank
*bank
;
1199 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1200 if (ERROR_OK
!= retval
)
1203 target
= bank
->target
;
1205 if (target
->state
!= TARGET_HALTED
) {
1206 LOG_ERROR("Target not halted");
1207 return ERROR_TARGET_NOT_HALTED
;
1210 retval
= stm32x_check_operation_supported(bank
);
1211 if (ERROR_OK
!= retval
)
1214 if (stm32x_erase_options(bank
) != ERROR_OK
) {
1215 command_print(CMD
, "stm32x failed to erase options");
1219 if (stm32x_write_options(bank
) != ERROR_OK
) {
1220 command_print(CMD
, "stm32x failed to unlock device");
1224 command_print(CMD
, "stm32x unlocked.\n"
1225 "INFO: a reset or power cycle is required "
1226 "for the new settings to take effect.");
1231 COMMAND_HANDLER(stm32x_handle_options_read_command
)
1233 uint32_t optionbyte
, protection
;
1234 struct target
*target
= NULL
;
1235 struct stm32x_flash_bank
*stm32x_info
= NULL
;
1238 return ERROR_COMMAND_SYNTAX_ERROR
;
1240 struct flash_bank
*bank
;
1241 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1242 if (ERROR_OK
!= retval
)
1245 stm32x_info
= bank
->driver_priv
;
1247 target
= bank
->target
;
1249 if (target
->state
!= TARGET_HALTED
) {
1250 LOG_ERROR("Target not halted");
1251 return ERROR_TARGET_NOT_HALTED
;
1254 retval
= stm32x_check_operation_supported(bank
);
1255 if (ERROR_OK
!= retval
)
1258 retval
= target_read_u32(target
, STM32_FLASH_OBR_B0
, &optionbyte
);
1259 if (retval
!= ERROR_OK
)
1262 uint16_t user_data
= optionbyte
>> stm32x_info
->user_data_offset
;
1264 retval
= target_read_u32(target
, STM32_FLASH_WRPR_B0
, &protection
);
1265 if (retval
!= ERROR_OK
)
1268 if (optionbyte
& (1 << OPT_ERROR
))
1269 command_print(CMD
, "option byte complement error");
1271 command_print(CMD
, "option byte register = 0x%" PRIx32
"", optionbyte
);
1272 command_print(CMD
, "write protection register = 0x%" PRIx32
"", protection
);
1274 command_print(CMD
, "read protection: %s",
1275 (optionbyte
& (1 << OPT_READOUT
)) ? "on" : "off");
1277 /* user option bytes are offset depending on variant */
1278 optionbyte
>>= stm32x_info
->option_offset
;
1280 command_print(CMD
, "watchdog: %sware",
1281 (optionbyte
& (1 << OPT_RDWDGSW
)) ? "soft" : "hard");
1283 command_print(CMD
, "stop mode: %sreset generated upon entry",
1284 (optionbyte
& (1 << OPT_RDRSTSTOP
)) ? "no " : "");
1286 command_print(CMD
, "standby mode: %sreset generated upon entry",
1287 (optionbyte
& (1 << OPT_RDRSTSTDBY
)) ? "no " : "");
1289 if (stm32x_info
->has_dual_banks
)
1290 command_print(CMD
, "boot: bank %d", (optionbyte
& (1 << OPT_BFB2
)) ? 0 : 1);
1292 command_print(CMD
, "user data = 0x%02" PRIx16
"", user_data
);
1297 COMMAND_HANDLER(stm32x_handle_options_write_command
)
1299 struct target
*target
= NULL
;
1300 struct stm32x_flash_bank
*stm32x_info
= NULL
;
1305 return ERROR_COMMAND_SYNTAX_ERROR
;
1307 struct flash_bank
*bank
;
1308 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1309 if (ERROR_OK
!= retval
)
1312 stm32x_info
= bank
->driver_priv
;
1314 target
= bank
->target
;
1316 if (target
->state
!= TARGET_HALTED
) {
1317 LOG_ERROR("Target not halted");
1318 return ERROR_TARGET_NOT_HALTED
;
1321 retval
= stm32x_check_operation_supported(bank
);
1322 if (ERROR_OK
!= retval
)
1325 retval
= stm32x_read_options(bank
);
1326 if (ERROR_OK
!= retval
)
1329 /* start with current options */
1330 optionbyte
= stm32x_info
->option_bytes
.user
;
1331 useropt
= stm32x_info
->option_bytes
.data
;
1333 /* skip over flash bank */
1338 if (strcmp("SWWDG", CMD_ARGV
[0]) == 0)
1339 optionbyte
|= (1 << 0);
1340 else if (strcmp("HWWDG", CMD_ARGV
[0]) == 0)
1341 optionbyte
&= ~(1 << 0);
1342 else if (strcmp("NORSTSTOP", CMD_ARGV
[0]) == 0)
1343 optionbyte
|= (1 << 1);
1344 else if (strcmp("RSTSTOP", CMD_ARGV
[0]) == 0)
1345 optionbyte
&= ~(1 << 1);
1346 else if (strcmp("NORSTSTNDBY", CMD_ARGV
[0]) == 0)
1347 optionbyte
|= (1 << 2);
1348 else if (strcmp("RSTSTNDBY", CMD_ARGV
[0]) == 0)
1349 optionbyte
&= ~(1 << 2);
1350 else if (strcmp("USEROPT", CMD_ARGV
[0]) == 0) {
1352 return ERROR_COMMAND_SYNTAX_ERROR
;
1353 COMMAND_PARSE_NUMBER(u16
, CMD_ARGV
[1], useropt
);
1357 else if (stm32x_info
->has_dual_banks
) {
1358 if (strcmp("BOOT0", CMD_ARGV
[0]) == 0)
1359 optionbyte
|= (1 << 3);
1360 else if (strcmp("BOOT1", CMD_ARGV
[0]) == 0)
1361 optionbyte
&= ~(1 << 3);
1363 return ERROR_COMMAND_SYNTAX_ERROR
;
1365 return ERROR_COMMAND_SYNTAX_ERROR
;
1370 if (stm32x_erase_options(bank
) != ERROR_OK
) {
1371 command_print(CMD
, "stm32x failed to erase options");
1375 stm32x_info
->option_bytes
.user
= optionbyte
;
1376 stm32x_info
->option_bytes
.data
= useropt
;
1378 if (stm32x_write_options(bank
) != ERROR_OK
) {
1379 command_print(CMD
, "stm32x failed to write options");
1383 command_print(CMD
, "stm32x write options complete.\n"
1384 "INFO: %spower cycle is required "
1385 "for the new settings to take effect.",
1386 stm32x_info
->can_load_options
1387 ? "'stm32f1x options_load' command or " : "");
1392 COMMAND_HANDLER(stm32x_handle_options_load_command
)
1395 return ERROR_COMMAND_SYNTAX_ERROR
;
1397 struct flash_bank
*bank
;
1398 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1399 if (ERROR_OK
!= retval
)
1402 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
1404 if (!stm32x_info
->can_load_options
) {
1405 LOG_ERROR("Command not applicable to stm32f1x devices - power cycle is "
1406 "required instead.");
1410 struct target
*target
= bank
->target
;
1412 if (target
->state
!= TARGET_HALTED
) {
1413 LOG_ERROR("Target not halted");
1414 return ERROR_TARGET_NOT_HALTED
;
1417 retval
= stm32x_check_operation_supported(bank
);
1418 if (ERROR_OK
!= retval
)
1421 /* unlock option flash registers */
1422 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY1
);
1423 if (retval
!= ERROR_OK
)
1425 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY2
);
1426 if (retval
!= ERROR_OK
)
1429 /* force re-load of option bytes - generates software reset */
1430 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_OBL_LAUNCH
);
1431 if (retval
!= ERROR_OK
)
1437 static int stm32x_mass_erase(struct flash_bank
*bank
)
1439 struct target
*target
= bank
->target
;
1441 if (target
->state
!= TARGET_HALTED
) {
1442 LOG_ERROR("Target not halted");
1443 return ERROR_TARGET_NOT_HALTED
;
1446 /* unlock option flash registers */
1447 int retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY1
);
1448 if (retval
!= ERROR_OK
)
1450 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY2
);
1451 if (retval
!= ERROR_OK
)
1454 /* mass erase flash memory */
1455 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_MER
);
1456 if (retval
!= ERROR_OK
)
1458 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
),
1459 FLASH_MER
| FLASH_STRT
);
1460 if (retval
!= ERROR_OK
)
1463 retval
= stm32x_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
);
1464 if (retval
!= ERROR_OK
)
1467 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_LOCK
);
1468 if (retval
!= ERROR_OK
)
1474 COMMAND_HANDLER(stm32x_handle_mass_erase_command
)
1477 return ERROR_COMMAND_SYNTAX_ERROR
;
1479 struct flash_bank
*bank
;
1480 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1481 if (ERROR_OK
!= retval
)
1484 retval
= stm32x_mass_erase(bank
);
1485 if (retval
== ERROR_OK
) {
1486 /* set all sectors as erased */
1487 for (int i
= 0; i
< bank
->num_sectors
; i
++)
1488 bank
->sectors
[i
].is_erased
= 1;
1490 command_print(CMD
, "stm32x mass erase complete");
1492 command_print(CMD
, "stm32x mass erase failed");
1497 static const struct command_registration stm32x_exec_command_handlers
[] = {
1500 .handler
= stm32x_handle_lock_command
,
1501 .mode
= COMMAND_EXEC
,
1503 .help
= "Lock entire flash device.",
1507 .handler
= stm32x_handle_unlock_command
,
1508 .mode
= COMMAND_EXEC
,
1510 .help
= "Unlock entire protected flash device.",
1513 .name
= "mass_erase",
1514 .handler
= stm32x_handle_mass_erase_command
,
1515 .mode
= COMMAND_EXEC
,
1517 .help
= "Erase entire flash device.",
1520 .name
= "options_read",
1521 .handler
= stm32x_handle_options_read_command
,
1522 .mode
= COMMAND_EXEC
,
1524 .help
= "Read and display device option bytes.",
1527 .name
= "options_write",
1528 .handler
= stm32x_handle_options_write_command
,
1529 .mode
= COMMAND_EXEC
,
1530 .usage
= "bank_id ('SWWDG'|'HWWDG') "
1531 "('RSTSTNDBY'|'NORSTSTNDBY') "
1532 "('RSTSTOP'|'NORSTSTOP') ('USEROPT' user_data)",
1533 .help
= "Replace bits in device option bytes.",
1536 .name
= "options_load",
1537 .handler
= stm32x_handle_options_load_command
,
1538 .mode
= COMMAND_EXEC
,
1540 .help
= "Force re-load of device option bytes.",
1542 COMMAND_REGISTRATION_DONE
1545 static const struct command_registration stm32x_command_handlers
[] = {
1548 .mode
= COMMAND_ANY
,
1549 .help
= "stm32f1x flash command group",
1551 .chain
= stm32x_exec_command_handlers
,
1553 COMMAND_REGISTRATION_DONE
1556 const struct flash_driver stm32f1x_flash
= {
1558 .commands
= stm32x_command_handlers
,
1559 .flash_bank_command
= stm32x_flash_bank_command
,
1560 .erase
= stm32x_erase
,
1561 .protect
= stm32x_protect
,
1562 .write
= stm32x_write
,
1563 .read
= default_flash_read
,
1564 .probe
= stm32x_probe
,
1565 .auto_probe
= stm32x_auto_probe
,
1566 .erase_check
= default_flash_blank_check
,
1567 .protect_check
= stm32x_protect_check
,
1568 .info
= get_stm32x_info
,
1569 .free_driver_priv
= default_flash_free_driver_priv
,
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