1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2011 by Andreas Fritiofson *
9 * andreas.fritiofson@gmail.com *
11 * Copyright (C) 2014 by Tomas Vanek (PSoC 4 support derived from STM32) *
14 * This program is free software; you can redistribute it and/or modify *
15 * it under the terms of the GNU General Public License as published by *
16 * the Free Software Foundation; either version 2 of the License, or *
17 * (at your option) any later version. *
19 * This program is distributed in the hope that it will be useful, *
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
22 * GNU General Public License for more details. *
24 * You should have received a copy of the GNU General Public License *
25 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
26 ***************************************************************************/
33 #include <helper/binarybuffer.h>
34 #include <jtag/jtag.h>
35 #include <target/algorithm.h>
36 #include <target/armv7m.h>
40 PSoC(R) 4: PSoC 4200 Family Datasheet
41 Document Number: 001-87197 Rev. *B Revised August 29, 2013
43 PSoC 4100/4200 Family PSoC(R) 4 Architecture TRM
44 Document No. 001-85634 Rev. *E June 28, 2016
46 PSoC(R) 4 Registers TRM Spec.
47 Document No. 001-85847 Rev. *A June 25, 2013
49 PSoC 4000 Family PSoC(R) 4 Technical Reference Manual
50 Document No. 001-89309 Rev. *B May 9, 2016
52 PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM
53 Document No. 001-92738 Rev. *C February 12, 2016
55 PSoC 4200L Family PSoC 4 Architecture TRM
56 Document No. 001-97952 Rev. *A December 15, 2015
58 PSoC 4200L Family PSoC 4 Registers TRM
59 Document No. 001-98126 Rev. *A December 16, 2015
61 PSoC 4100M/4200M Family PSoC 4 Architecture TRM
62 Document No. 001-95223 Rev. *B July 29, 2015
64 PSoC 4100S Family PSoC 4 Architecture TRM
65 Document No. 002-10621 Rev. *A July 29, 2016
67 PSoC 4100S Family PSoC 4 Registers TRM
68 Document No. 002-10523 Rev. *A July 20, 2016
70 PSoC Analog Coprocessor Architecture TRM
71 Document No. 002-10404 Rev. ** December 18, 2015
73 CY8C4Axx PSoC Analog Coprocessor Registers TRM
74 Document No. 002-10405 Rev. ** December 18, 2015
76 CY8C41xx, CY8C42xx Programming Specifications
77 Document No. 001-81799 Rev. *C March 4, 2014
79 CYBL10x6x, CY8C4127_BL, CY8C4247_BL Programming Specifications
80 Document No. 001-91508 Rev. *B September 22, 2014
82 http://dmitry.gr/index.php?r=05.Projects&proj=24.%20PSoC4%20confidential
85 /* register locations */
86 #define PSOC4_SFLASH_MACRO0 0x0FFFF000
88 #define PSOC4_CPUSS_SYSREQ_LEGACY 0x40000004
89 #define PSOC4_CPUSS_SYSARG_LEGACY 0x40000008
90 #define PSOC4_SPCIF_GEOMETRY_LEGACY 0x400E0000
92 #define PSOC4_CPUSS_SYSREQ_NEW 0x40100004
93 #define PSOC4_CPUSS_SYSARG_NEW 0x40100008
94 #define PSOC4_SPCIF_GEOMETRY_NEW 0x40110000
96 #define PSOC4_TEST_MODE 0x40030014
98 #define PSOC4_ROMTABLE_PID0 0xF0000FE0
102 #define PSOC4_SFLASH_MACRO_SIZE 0x800
103 #define PSOC4_ROWS_PER_MACRO 512
105 #define PSOC4_SROM_KEY1 0xb6
106 #define PSOC4_SROM_KEY2 0xd3
107 #define PSOC4_SROM_SYSREQ_BIT (1<<31)
108 #define PSOC4_SROM_HMASTER_BIT (1<<30)
109 #define PSOC4_SROM_PRIVILEGED_BIT (1<<28)
110 #define PSOC4_SROM_STATUS_SUCCEEDED 0xa0000000
111 #define PSOC4_SROM_STATUS_FAILED 0xf0000000
112 #define PSOC4_SROM_STATUS_MASK 0xf0000000
114 /* not documented in any TRM */
115 #define PSOC4_SROM_ERR_IMO_NOT_IMPLEM 0xf0000013
117 #define PSOC4_CMD_GET_SILICON_ID 0
118 #define PSOC4_CMD_LOAD_LATCH 4
119 #define PSOC4_CMD_WRITE_ROW 5
120 #define PSOC4_CMD_PROGRAM_ROW 6
121 #define PSOC4_CMD_ERASE_ALL 0xa
122 #define PSOC4_CMD_CHECKSUM 0xb
123 #define PSOC4_CMD_WRITE_PROTECTION 0xd
124 #define PSOC4_CMD_SET_IMO48 0x15
125 #define PSOC4_CMD_WRITE_SFLASH_ROW 0x18
127 #define PSOC4_CHIP_PROT_VIRGIN 0x0
128 #define PSOC4_CHIP_PROT_OPEN 0x1
129 #define PSOC4_CHIP_PROT_PROTECTED 0x2
130 #define PSOC4_CHIP_PROT_KILL 0x4
132 #define PSOC4_ROMTABLE_DESIGNER_CHECK 0xb4
134 #define PSOC4_FAMILY_FLAG_LEGACY 1
136 struct psoc4_chip_family
{
142 static const struct psoc4_chip_family psoc4_families
[] = {
143 { 0x93, "PSoC4100/4200", .flags
= PSOC4_FAMILY_FLAG_LEGACY
},
144 { 0x9A, "PSoC4000", .flags
= 0 },
145 { 0x9E, "PSoC/PRoC BLE (119E)", .flags
= 0 },
146 { 0xA0, "PSoC4200L", .flags
= 0 },
147 { 0xA1, "PSoC4100M/4200M", .flags
= 0 },
148 { 0xA3, "PSoC/PRoC BLE (11A3)", .flags
= 0 },
149 { 0xA9, "PSoC4000S", .flags
= 0 },
150 { 0xAA, "PSoC/PRoC BLE (11AA)", .flags
= 0 },
151 { 0xAB, "PSoC4100S", .flags
= 0 },
152 { 0xAC, "PSoC Analog Coprocessor", .flags
= 0 },
153 { 0, "Unknown", .flags
= 0 }
157 struct psoc4_flash_bank
{
159 uint32_t user_bank_size
;
160 unsigned int num_macros
;
162 uint8_t cmd_program_row
;
165 uint32_t cpuss_sysreq_addr
;
166 uint32_t cpuss_sysarg_addr
;
167 uint32_t spcif_geometry_addr
;
171 static const struct psoc4_chip_family
*psoc4_family_by_id(uint16_t family_id
)
173 const struct psoc4_chip_family
*p
= psoc4_families
;
174 while (p
->id
&& p
->id
!= family_id
)
180 static const char *psoc4_decode_chip_protection(uint8_t protection
)
182 switch (protection
) {
183 case PSOC4_CHIP_PROT_VIRGIN
:
184 return "protection VIRGIN";
185 case PSOC4_CHIP_PROT_OPEN
:
186 return "protection open";
187 case PSOC4_CHIP_PROT_PROTECTED
:
189 case PSOC4_CHIP_PROT_KILL
:
190 return "protection KILL";
192 LOG_WARNING("Unknown protection state 0x%02" PRIx8
"", protection
);
198 /* flash bank <name> psoc <base> <size> 0 0 <target#>
200 FLASH_BANK_COMMAND_HANDLER(psoc4_flash_bank_command
)
202 struct psoc4_flash_bank
*psoc4_info
;
205 return ERROR_COMMAND_SYNTAX_ERROR
;
207 psoc4_info
= calloc(1, sizeof(struct psoc4_flash_bank
));
209 bank
->driver_priv
= psoc4_info
;
210 bank
->default_padded_value
= bank
->erased_value
= 0x00;
211 psoc4_info
->user_bank_size
= bank
->size
;
212 psoc4_info
->cmd_program_row
= PSOC4_CMD_WRITE_ROW
;
218 /* PSoC 4 system ROM request
219 * Setting SROM_SYSREQ_BIT in CPUSS_SYSREQ register runs NMI service
220 * in sysrem ROM. Algorithm just waits for NMI to finish.
221 * When sysreq_params_size == 0 only one parameter is passed in CPUSS_SYSARG register.
222 * Otherwise address of memory parameter block is set in CPUSS_SYSARG
223 * and the first parameter is written to the first word of parameter block
225 static int psoc4_sysreq(struct flash_bank
*bank
, uint8_t cmd
,
227 uint32_t *sysreq_params
, uint32_t sysreq_params_size
,
228 uint32_t *sysarg_out
)
230 struct target
*target
= bank
->target
;
231 struct psoc4_flash_bank
*psoc4_info
= bank
->driver_priv
;
233 struct working_area
*sysreq_wait_algorithm
;
234 struct working_area
*sysreq_mem
;
236 struct reg_param reg_params
[1];
237 struct armv7m_algorithm armv7m_info
;
239 int retval
= ERROR_OK
;
241 uint32_t param1
= PSOC4_SROM_KEY1
242 | ((PSOC4_SROM_KEY2
+ cmd
) << 8)
245 static uint8_t psoc4_sysreq_wait_code
[] = {
246 /* system request NMI is served immediately after algo run
247 now we are done: break */
248 0x00, 0xbe, /* bkpt 0 */
251 const int code_words
= (sizeof(psoc4_sysreq_wait_code
) + 3) / 4;
252 /* stack must be aligned */
253 const int stack_size
= 256;
254 /* tested stack sizes on PSoC4200:
260 /* allocate area for sysreq wait code and stack */
261 if (target_alloc_working_area(target
, code_words
* 4 + stack_size
,
262 &sysreq_wait_algorithm
) != ERROR_OK
) {
263 LOG_DEBUG("no working area for sysreq code");
264 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
268 retval
= target_write_buffer(target
,
269 sysreq_wait_algorithm
->address
,
270 sizeof(psoc4_sysreq_wait_code
),
271 psoc4_sysreq_wait_code
);
272 if (retval
!= ERROR_OK
) {
273 /* we already allocated the writing code, but failed to get a
274 * buffer, free the algorithm */
278 if (sysreq_params_size
) {
279 LOG_DEBUG("SYSREQ %02" PRIx8
" %04" PRIx16
" %08" PRIx32
" size %" PRIu32
,
280 cmd
, cmd_param
, param1
, sysreq_params_size
);
281 /* Allocate memory for sysreq_params */
282 retval
= target_alloc_working_area(target
, sysreq_params_size
, &sysreq_mem
);
283 if (retval
!= ERROR_OK
) {
284 LOG_WARNING("no working area for sysreq parameters");
286 /* we already allocated the writing code, but failed to get a
287 * buffer, free the algorithm */
288 retval
= ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
292 /* Write sysreq_params */
293 target_buffer_set_u32(target
, (uint8_t *)sysreq_params
, param1
);
294 retval
= target_write_buffer(target
, sysreq_mem
->address
,
295 sysreq_params_size
, (uint8_t *)sysreq_params
);
296 if (retval
!= ERROR_OK
)
299 /* Set address of sysreq parameters block */
300 retval
= target_write_u32(target
, psoc4_info
->cpuss_sysarg_addr
, sysreq_mem
->address
);
301 if (retval
!= ERROR_OK
)
305 /* Sysreq without memory block of parameters */
306 LOG_DEBUG("SYSREQ %02" PRIx8
" %04" PRIx16
" %08" PRIx32
,
307 cmd
, cmd_param
, param1
);
308 /* Set register parameter */
309 retval
= target_write_u32(target
, psoc4_info
->cpuss_sysarg_addr
, param1
);
310 if (retval
!= ERROR_OK
)
314 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
315 armv7m_info
.core_mode
= ARM_MODE_THREAD
;
318 init_reg_param(®_params
[0], "sp", 32, PARAM_OUT
);
319 buf_set_u32(reg_params
[0].value
, 0, 32,
320 sysreq_wait_algorithm
->address
+ sysreq_wait_algorithm
->size
);
322 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
324 /* something is very wrong if armv7m is NULL */
325 LOG_ERROR("unable to get armv7m target");
330 /* Set SROM request */
331 retval
= target_write_u32(target
, psoc4_info
->cpuss_sysreq_addr
,
332 PSOC4_SROM_SYSREQ_BIT
| PSOC4_SROM_HMASTER_BIT
| cmd
);
333 if (retval
!= ERROR_OK
)
336 /* Execute wait code */
337 retval
= target_run_algorithm(target
, 0, NULL
,
338 ARRAY_SIZE(reg_params
), reg_params
,
339 sysreq_wait_algorithm
->address
, 0, 1000, &armv7m_info
);
340 if (retval
!= ERROR_OK
) {
341 LOG_ERROR("sysreq wait code execution failed");
345 uint32_t sysarg_out_tmp
;
346 retval
= target_read_u32(target
, psoc4_info
->cpuss_sysarg_addr
, &sysarg_out_tmp
);
347 if (retval
!= ERROR_OK
)
351 *sysarg_out
= sysarg_out_tmp
;
352 /* If result is an error, do not show now, let caller to decide */
353 } else if ((sysarg_out_tmp
& PSOC4_SROM_STATUS_MASK
) != PSOC4_SROM_STATUS_SUCCEEDED
) {
354 LOG_ERROR("sysreq error 0x%" PRIx32
, sysarg_out_tmp
);
358 destroy_reg_param(®_params
[0]);
361 if (sysreq_params_size
)
362 target_free_working_area(target
, sysreq_mem
);
365 target_free_working_area(target
, sysreq_wait_algorithm
);
371 /* helper routine to get silicon ID from a PSoC 4 chip */
372 static int psoc4_get_silicon_id(struct flash_bank
*bank
, uint32_t *silicon_id
, uint16_t *family_id
, uint8_t *protection
)
374 struct target
*target
= bank
->target
;
375 struct psoc4_flash_bank
*psoc4_info
= bank
->driver_priv
;
377 uint32_t part0
, part1
;
379 int retval
= psoc4_sysreq(bank
, PSOC4_CMD_GET_SILICON_ID
, 0, NULL
, 0, &part0
);
380 if (retval
!= ERROR_OK
)
383 if ((part0
& PSOC4_SROM_STATUS_MASK
) != PSOC4_SROM_STATUS_SUCCEEDED
) {
384 LOG_ERROR("sysreq error 0x%" PRIx32
, part0
);
388 retval
= target_read_u32(target
, psoc4_info
->cpuss_sysreq_addr
, &part1
);
389 if (retval
!= ERROR_OK
)
392 /* build ID as Cypress sw does:
393 * bit 31..16 silicon ID
394 * bit 15..8 revision ID (so far 0x11 for all devices)
395 * bit 7..0 family ID (lowest 8 bits)
398 *silicon_id
= ((part0
& 0x0000ffff) << 16)
399 | ((part0
& 0x00ff0000) >> 8)
400 | (part1
& 0x000000ff);
403 *family_id
= part1
& 0x0fff;
406 *protection
= (part1
>> 12) & 0x0f;
412 static int psoc4_get_family(struct target
*target
, uint16_t *family_id
)
418 retval
= target_read_memory(target
, PSOC4_ROMTABLE_PID0
, 4, 3, (uint8_t *)pidbf
);
419 if (retval
!= ERROR_OK
)
422 for (i
= 0; i
< 3; i
++) {
423 uint32_t tmp
= target_buffer_get_u32(target
, (uint8_t *)(pidbf
+ i
));
424 if (tmp
& 0xffffff00) {
425 LOG_ERROR("Unexpected data in ROMTABLE");
431 uint16_t family
= pid
[0] | ((pid
[1] & 0xf) << 8);
432 uint32_t designer
= ((pid
[1] & 0xf0) >> 4) | ((pid
[2] & 0xf) << 4);
434 if (designer
!= PSOC4_ROMTABLE_DESIGNER_CHECK
) {
435 LOG_ERROR("ROMTABLE designer is not Cypress");
444 static int psoc4_flash_prepare(struct flash_bank
*bank
)
446 struct target
*target
= bank
->target
;
447 struct psoc4_flash_bank
*psoc4_info
= bank
->driver_priv
;
449 if (target
->state
!= TARGET_HALTED
) {
450 LOG_ERROR("Target not halted");
451 return ERROR_TARGET_NOT_HALTED
;
457 /* get family ID from SROM call */
458 retval
= psoc4_get_silicon_id(bank
, NULL
, &family_id
, NULL
);
459 if (retval
!= ERROR_OK
)
462 /* and check with family ID from ROMTABLE */
463 if (family_id
!= psoc4_info
->family_id
) {
464 LOG_ERROR("Family mismatch");
468 if (!psoc4_info
->legacy_family
) {
469 uint32_t sysreq_status
;
470 retval
= psoc4_sysreq(bank
, PSOC4_CMD_SET_IMO48
, 0, NULL
, 0, &sysreq_status
);
471 if (retval
!= ERROR_OK
)
474 if ((sysreq_status
& PSOC4_SROM_STATUS_MASK
) != PSOC4_SROM_STATUS_SUCCEEDED
) {
475 /* This undocumented error code is returned probably when
476 * PSOC4_CMD_SET_IMO48 command is not implemented.
477 * Can be safely ignored, programming works.
479 if (sysreq_status
== PSOC4_SROM_ERR_IMO_NOT_IMPLEM
)
480 LOG_INFO("PSOC4_CMD_SET_IMO48 is not implemented on this device.");
482 LOG_ERROR("sysreq error 0x%" PRIx32
, sysreq_status
);
492 static int psoc4_protect_check(struct flash_bank
*bank
)
494 struct target
*target
= bank
->target
;
495 struct psoc4_flash_bank
*psoc4_info
= bank
->driver_priv
;
497 uint32_t prot_addr
= PSOC4_SFLASH_MACRO0
;
499 uint8_t bf
[PSOC4_ROWS_PER_MACRO
/8];
502 for (unsigned int m
= 0; m
< psoc4_info
->num_macros
; m
++, prot_addr
+= PSOC4_SFLASH_MACRO_SIZE
) {
503 retval
= target_read_memory(target
, prot_addr
, 4, PSOC4_ROWS_PER_MACRO
/32, bf
);
504 if (retval
!= ERROR_OK
)
507 for (unsigned int i
= 0; i
< PSOC4_ROWS_PER_MACRO
&& s
< bank
->num_sectors
; i
++, s
++)
508 bank
->sectors
[s
].is_protected
= bf
[i
/8] & (1 << (i
%8)) ? 1 : 0;
515 static int psoc4_mass_erase(struct flash_bank
*bank
)
517 int retval
= psoc4_flash_prepare(bank
);
518 if (retval
!= ERROR_OK
)
521 /* Call "Erase All" system ROM API */
523 return psoc4_sysreq(bank
, PSOC4_CMD_ERASE_ALL
,
525 ¶m
, sizeof(param
), NULL
);
529 static int psoc4_erase(struct flash_bank
*bank
, unsigned int first
,
532 struct psoc4_flash_bank
*psoc4_info
= bank
->driver_priv
;
533 if (psoc4_info
->cmd_program_row
== PSOC4_CMD_WRITE_ROW
) {
534 LOG_INFO("Autoerase enabled, erase command ignored");
538 if ((first
== 0) && (last
== (bank
->num_sectors
- 1)))
539 return psoc4_mass_erase(bank
);
541 LOG_ERROR("Only mass erase available! Consider using 'psoc4 flash_autoerase 0 on'");
547 static int psoc4_protect(struct flash_bank
*bank
, int set
, unsigned int first
,
550 struct target
*target
= bank
->target
;
551 struct psoc4_flash_bank
*psoc4_info
= bank
->driver_priv
;
553 if (!psoc4_info
->probed
)
556 int retval
= psoc4_flash_prepare(bank
);
557 if (retval
!= ERROR_OK
)
560 uint32_t *sysrq_buffer
= NULL
;
561 const int param_sz
= 8;
562 int chip_prot
= PSOC4_CHIP_PROT_OPEN
;
564 unsigned int num_bits
= bank
->num_sectors
;
566 if (num_bits
> PSOC4_ROWS_PER_MACRO
)
567 num_bits
= PSOC4_ROWS_PER_MACRO
;
569 int prot_sz
= num_bits
/ 8;
571 sysrq_buffer
= malloc(param_sz
+ prot_sz
);
573 LOG_ERROR("no memory for row buffer");
577 for (i
= first
; i
<= last
&& i
< bank
->num_sectors
; i
++)
578 bank
->sectors
[i
].is_protected
= set
;
580 for (unsigned int m
= 0, sect
= 0; m
< psoc4_info
->num_macros
; m
++) {
581 uint8_t *p
= (uint8_t *)(sysrq_buffer
+ 2);
582 memset(p
, 0, prot_sz
);
583 for (i
= 0; i
< num_bits
&& sect
< bank
->num_sectors
; i
++, sect
++) {
584 if (bank
->sectors
[sect
].is_protected
)
585 p
[i
/8] |= 1 << (i
%8);
588 /* Call "Load Latch" system ROM API */
589 target_buffer_set_u32(target
, (uint8_t *)(sysrq_buffer
+ 1),
591 retval
= psoc4_sysreq(bank
, PSOC4_CMD_LOAD_LATCH
,
592 0 /* Byte number in latch from what to write */
593 | (m
<< 8), /* flash macro index */
594 sysrq_buffer
, param_sz
+ prot_sz
,
596 if (retval
!= ERROR_OK
)
599 /* Call "Write Protection" system ROM API */
600 retval
= psoc4_sysreq(bank
, PSOC4_CMD_WRITE_PROTECTION
,
601 chip_prot
| (m
<< 8), NULL
, 0, NULL
);
602 if (retval
!= ERROR_OK
)
608 psoc4_protect_check(bank
);
613 COMMAND_HANDLER(psoc4_handle_flash_autoerase_command
)
616 return ERROR_COMMAND_SYNTAX_ERROR
;
618 struct flash_bank
*bank
;
619 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
620 if (retval
!= ERROR_OK
)
623 struct psoc4_flash_bank
*psoc4_info
= bank
->driver_priv
;
624 bool enable
= psoc4_info
->cmd_program_row
== PSOC4_CMD_WRITE_ROW
;
627 COMMAND_PARSE_ON_OFF(CMD_ARGV
[1], enable
);
630 psoc4_info
->cmd_program_row
= PSOC4_CMD_WRITE_ROW
;
631 LOG_INFO("Flash auto-erase enabled, non mass erase commands will be ignored.");
633 psoc4_info
->cmd_program_row
= PSOC4_CMD_PROGRAM_ROW
;
634 LOG_INFO("Flash auto-erase disabled. Use psoc mass_erase before flash programming.");
641 static int psoc4_write(struct flash_bank
*bank
, const uint8_t *buffer
,
642 uint32_t offset
, uint32_t count
)
644 struct target
*target
= bank
->target
;
645 struct psoc4_flash_bank
*psoc4_info
= bank
->driver_priv
;
646 uint32_t *sysrq_buffer
= NULL
;
647 const int param_sz
= 8;
649 int retval
= psoc4_flash_prepare(bank
);
650 if (retval
!= ERROR_OK
)
653 sysrq_buffer
= malloc(param_sz
+ psoc4_info
->row_size
);
655 LOG_ERROR("no memory for row buffer");
659 uint8_t *row_buffer
= (uint8_t *)sysrq_buffer
+ param_sz
;
660 uint32_t row_num
= offset
/ psoc4_info
->row_size
;
661 uint32_t row_offset
= offset
- row_num
* psoc4_info
->row_size
;
663 memset(row_buffer
, bank
->default_padded_value
, row_offset
);
665 bool save_poll
= jtag_poll_get_enabled();
666 jtag_poll_set_enabled(false);
669 uint32_t chunk_size
= psoc4_info
->row_size
- row_offset
;
670 if (chunk_size
> count
) {
672 memset(row_buffer
+ chunk_size
, bank
->default_padded_value
, psoc4_info
->row_size
- chunk_size
);
674 memcpy(row_buffer
+ row_offset
, buffer
, chunk_size
);
675 LOG_DEBUG("offset / row: 0x%08" PRIx32
" / %" PRIu32
", size %" PRIu32
"",
676 offset
, row_offset
, chunk_size
);
678 uint32_t macro_idx
= row_num
/ PSOC4_ROWS_PER_MACRO
;
680 /* Call "Load Latch" system ROM API */
681 target_buffer_set_u32(target
, (uint8_t *)(sysrq_buffer
+ 1),
682 psoc4_info
->row_size
- 1);
683 retval
= psoc4_sysreq(bank
, PSOC4_CMD_LOAD_LATCH
,
684 0 /* Byte number in latch from what to write */
686 sysrq_buffer
, param_sz
+ psoc4_info
->row_size
,
688 if (retval
!= ERROR_OK
)
691 /* Call "Program Row" or "Write Row" system ROM API */
692 uint32_t sysrq_param
;
693 retval
= psoc4_sysreq(bank
, psoc4_info
->cmd_program_row
,
695 &sysrq_param
, sizeof(sysrq_param
),
697 if (retval
!= ERROR_OK
)
700 buffer
+= chunk_size
;
707 jtag_poll_set_enabled(save_poll
);
714 /* Due to Cypress's method of market segmentation some devices
715 * have accessible only 1/2, 1/4 or 1/8 of SPCIF described flash */
716 static int psoc4_test_flash_wounding(struct target
*target
, uint32_t flash_size
)
719 for (i
= 3; i
>= 1; i
--) {
720 uint32_t addr
= flash_size
>> i
;
722 retval
= target_read_u32(target
, addr
, &dummy
);
723 if (retval
!= ERROR_OK
)
730 static int psoc4_probe(struct flash_bank
*bank
)
732 struct psoc4_flash_bank
*psoc4_info
= bank
->driver_priv
;
733 struct target
*target
= bank
->target
;
738 psoc4_info
->probed
= false;
740 retval
= psoc4_get_family(target
, &family_id
);
741 if (retval
!= ERROR_OK
)
744 const struct psoc4_chip_family
*family
= psoc4_family_by_id(family_id
);
746 if (family
->id
== 0) {
747 LOG_ERROR("Cannot identify PSoC 4 family.");
751 if (family
->flags
& PSOC4_FAMILY_FLAG_LEGACY
) {
752 LOG_INFO("%s legacy family detected.", family
->name
);
753 psoc4_info
->legacy_family
= true;
754 psoc4_info
->cpuss_sysreq_addr
= PSOC4_CPUSS_SYSREQ_LEGACY
;
755 psoc4_info
->cpuss_sysarg_addr
= PSOC4_CPUSS_SYSARG_LEGACY
;
756 psoc4_info
->spcif_geometry_addr
= PSOC4_SPCIF_GEOMETRY_LEGACY
;
758 LOG_INFO("%s family detected.", family
->name
);
759 psoc4_info
->legacy_family
= false;
760 psoc4_info
->cpuss_sysreq_addr
= PSOC4_CPUSS_SYSREQ_NEW
;
761 psoc4_info
->cpuss_sysarg_addr
= PSOC4_CPUSS_SYSARG_NEW
;
762 psoc4_info
->spcif_geometry_addr
= PSOC4_SPCIF_GEOMETRY_NEW
;
765 uint32_t spcif_geometry
;
766 retval
= target_read_u32(target
, psoc4_info
->spcif_geometry_addr
, &spcif_geometry
);
767 if (retval
!= ERROR_OK
)
770 uint32_t flash_size_in_kb
= spcif_geometry
& 0x3fff;
771 /* TRM of legacy, M and L version describes FLASH field as 16-bit.
772 * S-series and PSoC Analog Coprocessor changes spec to 14-bit only.
773 * Impose PSoC Analog Coprocessor limit to all devices as it
774 * does not make any harm: flash size is safely below 4 MByte limit
776 uint32_t row_size
= (spcif_geometry
>> 22) & 3;
777 uint32_t num_macros
= (spcif_geometry
>> 20) & 3;
779 if (psoc4_info
->legacy_family
) {
780 flash_size_in_kb
= flash_size_in_kb
* 256 / 1024;
783 flash_size_in_kb
= (flash_size_in_kb
+ 1) * 256 / 1024;
784 row_size
= 64 * (row_size
+ 1);
788 LOG_DEBUG("SPCIF geometry: %" PRIu32
" kb flash, row %" PRIu32
" bytes.",
789 flash_size_in_kb
, row_size
);
791 /* if the user sets the size manually then ignore the probed value
792 * this allows us to work around devices that have a invalid flash size register value */
793 if (psoc4_info
->user_bank_size
) {
794 LOG_INFO("ignoring flash probed value, using configured bank size");
795 flash_size_in_kb
= psoc4_info
->user_bank_size
/ 1024;
798 char macros_txt
[20] = "";
800 snprintf(macros_txt
, sizeof(macros_txt
), " in %" PRIu32
" macros", num_macros
);
802 LOG_INFO("flash size = %" PRIu32
" kbytes%s", flash_size_in_kb
, macros_txt
);
804 /* calculate number of pages */
805 uint32_t num_rows
= flash_size_in_kb
* 1024 / row_size
;
807 /* check number of flash macros */
808 if (num_macros
!= (num_rows
+ PSOC4_ROWS_PER_MACRO
- 1) / PSOC4_ROWS_PER_MACRO
)
809 LOG_WARNING("Number of macros does not correspond with flash size!");
811 if (!psoc4_info
->legacy_family
) {
812 int wounding
= psoc4_test_flash_wounding(target
, num_rows
* row_size
);
814 flash_size_in_kb
= flash_size_in_kb
>> wounding
;
815 num_rows
= num_rows
>> wounding
;
816 LOG_INFO("WOUNDING detected: accessible flash size %" PRIu32
" kbytes", flash_size_in_kb
);
822 psoc4_info
->family_id
= family_id
;
823 psoc4_info
->num_macros
= num_macros
;
824 psoc4_info
->row_size
= row_size
;
825 bank
->base
= 0x00000000;
826 bank
->size
= num_rows
* row_size
;
827 bank
->num_sectors
= num_rows
;
828 bank
->sectors
= alloc_block_array(0, row_size
, num_rows
);
832 LOG_DEBUG("flash bank set %" PRIu32
" rows", num_rows
);
833 psoc4_info
->probed
= true;
838 static int psoc4_auto_probe(struct flash_bank
*bank
)
840 struct psoc4_flash_bank
*psoc4_info
= bank
->driver_priv
;
841 if (psoc4_info
->probed
)
843 return psoc4_probe(bank
);
847 static int get_psoc4_info(struct flash_bank
*bank
, struct command_invocation
*cmd
)
849 struct target
*target
= bank
->target
;
850 struct psoc4_flash_bank
*psoc4_info
= bank
->driver_priv
;
852 if (!psoc4_info
->probed
)
855 const struct psoc4_chip_family
*family
= psoc4_family_by_id(psoc4_info
->family_id
);
856 uint32_t size_in_kb
= bank
->size
/ 1024;
858 if (target
->state
!= TARGET_HALTED
) {
859 command_print_sameline(cmd
, "%s, flash %" PRIu32
" kb"
860 " (halt target to see details)", family
->name
, size_in_kb
);
868 int retval
= psoc4_get_silicon_id(bank
, &silicon_id
, &family_id
, &protection
);
869 if (retval
!= ERROR_OK
)
872 if (family_id
!= psoc4_info
->family_id
)
873 command_print_sameline(cmd
, "Family id mismatch 0x%02" PRIx16
874 "/0x%02" PRIx16
", silicon id 0x%08" PRIx32
,
875 psoc4_info
->family_id
, family_id
, silicon_id
);
877 command_print_sameline(cmd
, "%s silicon id 0x%08" PRIx32
"",
878 family
->name
, silicon_id
);
881 const char *prot_txt
= psoc4_decode_chip_protection(protection
);
882 command_print_sameline(cmd
, ", flash %" PRIu32
" kb %s", size_in_kb
, prot_txt
);
887 COMMAND_HANDLER(psoc4_handle_mass_erase_command
)
890 return ERROR_COMMAND_SYNTAX_ERROR
;
892 struct flash_bank
*bank
;
893 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
894 if (retval
!= ERROR_OK
)
897 retval
= psoc4_mass_erase(bank
);
898 if (retval
== ERROR_OK
)
899 command_print(CMD
, "psoc mass erase complete");
901 command_print(CMD
, "psoc mass erase failed");
907 static const struct command_registration psoc4_exec_command_handlers
[] = {
909 .name
= "mass_erase",
910 .handler
= psoc4_handle_mass_erase_command
,
911 .mode
= COMMAND_EXEC
,
913 .help
= "Erase entire flash device.",
916 .name
= "flash_autoerase",
917 .handler
= psoc4_handle_flash_autoerase_command
,
918 .mode
= COMMAND_EXEC
,
919 .usage
= "bank_id on|off",
920 .help
= "Set autoerase mode for flash bank.",
922 COMMAND_REGISTRATION_DONE
925 static const struct command_registration psoc4_command_handlers
[] = {
929 .help
= "PSoC 4 flash command group",
931 .chain
= psoc4_exec_command_handlers
,
933 COMMAND_REGISTRATION_DONE
936 const struct flash_driver psoc4_flash
= {
938 .commands
= psoc4_command_handlers
,
939 .flash_bank_command
= psoc4_flash_bank_command
,
940 .erase
= psoc4_erase
,
941 .protect
= psoc4_protect
,
942 .write
= psoc4_write
,
943 .read
= default_flash_read
,
944 .probe
= psoc4_probe
,
945 .auto_probe
= psoc4_auto_probe
,
946 .erase_check
= default_flash_blank_check
,
947 .protect_check
= psoc4_protect_check
,
948 .info
= get_psoc4_info
,
949 .free_driver_priv
= default_flash_free_driver_priv
,
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