1 // SPDX-License-Identifier: GPL-2.0-or-later
3 /***************************************************************************
4 * Copyright (C) 2008 by *
5 * Karl RobinSod <karl.robinsod@gmail.com> *
6 ***************************************************************************/
8 /***************************************************************************
9 * There are some things to notice
11 * You need to unprotect flash sectors each time you connect the OpenOCD
12 * Dumping 1MB takes about 60 Seconds
13 * Full erase (sectors 0-22 inclusive) takes 2-4 seconds
14 * Writing 1MB takes 88 seconds
16 ***************************************************************************/
22 #include <helper/binarybuffer.h>
24 #define LOAD_TIMER_ERASE 0
25 #define LOAD_TIMER_WRITE 1
27 #define FLASH_PAGE_SIZE 512
29 /* LPC288X control registers */
30 #define DBGU_CIDR 0x8000507C
31 /* LPC288X flash registers */
32 #define F_CTRL 0x80102000 /* Flash control register R/W 0x5 */
33 #define F_STAT 0x80102004 /* Flash status register RO 0x45 */
34 #define F_PROG_TIME 0x80102008 /* Flash program time register R/W 0 */
35 #define F_WAIT 0x80102010 /* Flash read wait state register R/W 0xC004 */
36 #define F_CLK_TIME 0x8010201C /* Flash clock divider for 66 kHz generation R/W 0
38 #define F_INTEN_CLR 0x80102FD8 /* Clear interrupt enable bits WO - */
39 #define F_INTEN_SET 0x80102FDC /* Set interrupt enable bits WO - */
40 #define F_INT_STAT 0x80102FE0 /* Interrupt status bits RO 0 */
41 #define F_INTEN 0x80102FE4 /* Interrupt enable bits RO 0 */
42 #define F_INT_CLR 0x80102FE8 /* Clear interrupt status bits WO */
43 #define F_INT_SET 0x80102FEC /* Set interrupt status bits WO - */
44 #define FLASH_PD 0x80005030 /* Allows turning off the Flash memory for power
46 #define FLASH_INIT 0x80005034 /* Monitors Flash readiness, such as recovery from
47 *Power Down mode. R/W -*/
51 #define FC_FUNC 0x0002
53 #define FC_RD_LATCH 0x0020
54 #define FC_PROTECT 0x0080
55 #define FC_SET_DATA 0x0400
56 #define FC_RSSL 0x0800
57 #define FC_PROG_REQ 0x1000
58 #define FC_CLR_BUF 0x4000
59 #define FC_LOAD_REQ 0x8000
61 #define FS_DONE 0x0001
62 #define FS_PROGGNT 0x0002
66 #define FPT_TIME_MASK 0x7FFF
68 #define FPT_ENABLE 0x8000
70 #define FW_WAIT_STATES_MASK 0x00FF
71 #define FW_SET_MASK 0xC000
74 #define FCT_CLK_DIV_MASK 0x0FFF
76 struct lpc288x_flash_bank
{
77 uint32_t working_area
;
78 uint32_t working_area_size
;
80 /* chip id register */
82 const char *target_name
;
85 uint32_t sector_size_break
;
88 static uint32_t lpc288x_wait_status_busy(struct flash_bank
*bank
, int timeout
);
89 static void lpc288x_load_timer(int erase
, struct target
*target
);
90 static void lpc288x_set_flash_clk(struct flash_bank
*bank
);
91 static uint32_t lpc288x_system_ready(struct flash_bank
*bank
);
93 static uint32_t lpc288x_wait_status_busy(struct flash_bank
*bank
, int timeout
)
96 struct target
*target
= bank
->target
;
100 target_read_u32(target
, F_STAT
, &status
);
101 } while (((status
& FS_DONE
) == 0) && timeout
);
104 LOG_DEBUG("Timedout!");
105 return ERROR_FLASH_OPERATION_FAILED
;
110 /* Read device id register and fill in driver info structure */
111 static int lpc288x_read_part_info(struct flash_bank
*bank
)
113 struct lpc288x_flash_bank
*lpc288x_info
= bank
->driver_priv
;
114 struct target
*target
= bank
->target
;
120 if (lpc288x_info
->cidr
== 0x0102100A)
121 return ERROR_OK
;/* already probed, multiple probes may cause memory leak, not
124 /* Read and parse chip identification register */
125 target_read_u32(target
, DBGU_CIDR
, &cidr
);
127 if (cidr
!= 0x0102100A) {
128 LOG_WARNING("Cannot identify target as an LPC288X (%08" PRIx32
")", cidr
);
129 return ERROR_FLASH_OPERATION_FAILED
;
132 lpc288x_info
->cidr
= cidr
;
133 lpc288x_info
->sector_size_break
= 0x000F0000;
134 lpc288x_info
->target_name
= "LPC288x";
136 /* setup the sector info... */
138 bank
->num_sectors
= 23;
139 bank
->sectors
= malloc(sizeof(struct flash_sector
) * 23);
141 for (i
= 0; i
< 15; i
++) {
142 bank
->sectors
[i
].offset
= offset
;
143 bank
->sectors
[i
].size
= 64 * 1024;
144 offset
+= bank
->sectors
[i
].size
;
145 bank
->sectors
[i
].is_erased
= -1;
146 bank
->sectors
[i
].is_protected
= 1;
148 for (i
= 15; i
< 23; i
++) {
149 bank
->sectors
[i
].offset
= offset
;
150 bank
->sectors
[i
].size
= 8 * 1024;
151 offset
+= bank
->sectors
[i
].size
;
152 bank
->sectors
[i
].is_erased
= -1;
153 bank
->sectors
[i
].is_protected
= 1;
159 /* TODO: Revisit! Is it impossible to read protection status? */
160 static int lpc288x_protect_check(struct flash_bank
*bank
)
165 /* flash_bank LPC288x 0 0 0 0 <target#> <cclk> */
166 FLASH_BANK_COMMAND_HANDLER(lpc288x_flash_bank_command
)
168 struct lpc288x_flash_bank
*lpc288x_info
;
171 return ERROR_COMMAND_SYNTAX_ERROR
;
173 lpc288x_info
= malloc(sizeof(struct lpc288x_flash_bank
));
174 bank
->driver_priv
= lpc288x_info
;
176 /* part wasn't probed for info yet */
177 lpc288x_info
->cidr
= 0;
178 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[6], lpc288x_info
->cclk
);
183 /* The frequency is the AHB clock frequency divided by (CLK_DIV ×3) + 1.
184 * This must be programmed such that the Flash Programming clock frequency is 66 kHz ± 20%.
186 * 12000000/66000 = 182
188 static void lpc288x_set_flash_clk(struct flash_bank
*bank
)
191 struct lpc288x_flash_bank
*lpc288x_info
= bank
->driver_priv
;
192 clk_time
= (lpc288x_info
->cclk
/ 66000) / 3;
193 target_write_u32(bank
->target
, F_CTRL
, FC_CS
| FC_WEN
);
194 target_write_u32(bank
->target
, F_CLK_TIME
, clk_time
);
197 /* AHB tcyc (in ns) 83 ns
198 * LOAD_TIMER_ERASE FPT_TIME = ((400,000,000 / AHB tcyc (in ns)) - 2) / 512
199 * = 9412 (9500) (AN10548 9375)
200 * LOAD_TIMER_WRITE FPT_TIME = ((1,000,000 / AHB tcyc (in ns)) - 2) / 512
201 * = 23 (75) (AN10548 72 - is this wrong?)
202 * TODO: Sort out timing calcs ;) */
203 static void lpc288x_load_timer(int erase
, struct target
*target
)
205 if (erase
== LOAD_TIMER_ERASE
)
206 target_write_u32(target
, F_PROG_TIME
, FPT_ENABLE
| 9500);
208 target_write_u32(target
, F_PROG_TIME
, FPT_ENABLE
| 75);
211 static uint32_t lpc288x_system_ready(struct flash_bank
*bank
)
213 struct lpc288x_flash_bank
*lpc288x_info
= bank
->driver_priv
;
214 if (lpc288x_info
->cidr
== 0)
215 return ERROR_FLASH_BANK_NOT_PROBED
;
217 if (bank
->target
->state
!= TARGET_HALTED
) {
218 LOG_ERROR("Target not halted");
219 return ERROR_TARGET_NOT_HALTED
;
224 static int lpc288x_erase(struct flash_bank
*bank
, unsigned int first
,
228 struct target
*target
= bank
->target
;
230 status
= lpc288x_system_ready(bank
); /* probed? halted? */
231 if (status
!= ERROR_OK
)
234 if ((last
< first
) || (last
>= bank
->num_sectors
)) {
235 LOG_INFO("Bad sector range");
236 return ERROR_FLASH_SECTOR_INVALID
;
239 /* Configure the flash controller timing */
240 lpc288x_set_flash_clk(bank
);
242 for (unsigned int sector
= first
; sector
<= last
; sector
++) {
243 if (lpc288x_wait_status_busy(bank
, 1000) != ERROR_OK
)
244 return ERROR_FLASH_OPERATION_FAILED
;
246 lpc288x_load_timer(LOAD_TIMER_ERASE
, target
);
248 target_write_u32(target
, bank
->sectors
[sector
].offset
, 0x00);
250 target_write_u32(target
, F_CTRL
, FC_PROG_REQ
| FC_PROTECT
| FC_CS
);
252 if (lpc288x_wait_status_busy(bank
, 1000) != ERROR_OK
)
253 return ERROR_FLASH_OPERATION_FAILED
;
257 static int lpc288x_write(struct flash_bank
*bank
, const uint8_t *buffer
, uint32_t offset
, uint32_t count
)
259 uint8_t page_buffer
[FLASH_PAGE_SIZE
];
260 uint32_t status
, source_offset
, dest_offset
;
261 struct target
*target
= bank
->target
;
262 uint32_t bytes_remaining
= count
;
263 uint32_t first_sector
, last_sector
, sector
, page
;
265 /* probed? halted? */
266 status
= lpc288x_system_ready(bank
);
267 if (status
!= ERROR_OK
)
270 /* Initialise search indices */
271 first_sector
= last_sector
= 0xffffffff;
273 /* validate the write range... */
274 for (unsigned int i
= 0; i
< bank
->num_sectors
; i
++) {
275 if ((offset
>= bank
->sectors
[i
].offset
) &&
276 (offset
< (bank
->sectors
[i
].offset
+ bank
->sectors
[i
].size
)) &&
277 (first_sector
== 0xffffffff)) {
279 /* all writes must start on a sector boundary... */
280 if (offset
% bank
->sectors
[i
].size
) {
282 "offset 0x%" PRIx32
" breaks required alignment 0x%" PRIx32
"",
284 bank
->sectors
[i
].size
);
285 return ERROR_FLASH_DST_BREAKS_ALIGNMENT
;
288 if (((offset
+ count
) > bank
->sectors
[i
].offset
) &&
289 ((offset
+ count
) <= (bank
->sectors
[i
].offset
+ bank
->sectors
[i
].size
)) &&
290 (last_sector
== 0xffffffff))
295 if (first_sector
== 0xffffffff || last_sector
== 0xffffffff) {
296 LOG_INFO("Range check failed %" PRIx32
" %" PRIx32
"", offset
, count
);
297 return ERROR_FLASH_DST_OUT_OF_BANK
;
300 /* Configure the flash controller timing */
301 lpc288x_set_flash_clk(bank
);
303 /* initialise the offsets */
307 for (sector
= first_sector
; sector
<= last_sector
; sector
++) {
308 for (page
= 0; page
< bank
->sectors
[sector
].size
/ FLASH_PAGE_SIZE
; page
++) {
309 if (bytes_remaining
== 0) {
311 memset(page_buffer
, 0xFF, FLASH_PAGE_SIZE
);
312 } else if (bytes_remaining
< FLASH_PAGE_SIZE
) {
313 count
= bytes_remaining
;
314 memset(page_buffer
, 0xFF, FLASH_PAGE_SIZE
);
315 memcpy(page_buffer
, &buffer
[source_offset
], count
);
317 count
= FLASH_PAGE_SIZE
;
318 memcpy(page_buffer
, &buffer
[source_offset
], count
);
321 /* Wait for flash to become ready */
322 if (lpc288x_wait_status_busy(bank
, 1000) != ERROR_OK
)
323 return ERROR_FLASH_OPERATION_FAILED
;
325 /* fill flash data latches with 1's */
326 target_write_u32(target
, F_CTRL
, FC_CS
| FC_SET_DATA
| FC_WEN
| FC_FUNC
);
328 target_write_u32(target
, F_CTRL
, FC_CS
| FC_WEN
| FC_FUNC
);
330 if (target_write_buffer(target
, offset
+ dest_offset
, FLASH_PAGE_SIZE
,
331 page_buffer
) != ERROR_OK
) {
332 LOG_INFO("Write to flash buffer failed");
333 return ERROR_FLASH_OPERATION_FAILED
;
336 dest_offset
+= FLASH_PAGE_SIZE
;
337 source_offset
+= count
;
338 bytes_remaining
-= count
;
340 lpc288x_load_timer(LOAD_TIMER_WRITE
, target
);
342 target_write_u32(target
, F_CTRL
, FC_PROG_REQ
| FC_PROTECT
| FC_FUNC
|
350 static int lpc288x_probe(struct flash_bank
*bank
)
352 /* we only deal with LPC2888 so flash config is fixed */
353 struct lpc288x_flash_bank
*lpc288x_info
= bank
->driver_priv
;
356 if (lpc288x_info
->cidr
!= 0)
357 return ERROR_OK
;/* already probed */
359 if (bank
->target
->state
!= TARGET_HALTED
) {
360 LOG_ERROR("Target not halted");
361 return ERROR_TARGET_NOT_HALTED
;
364 retval
= lpc288x_read_part_info(bank
);
365 if (retval
!= ERROR_OK
)
370 static int lpc288x_protect(struct flash_bank
*bank
, int set
, unsigned int first
,
375 struct target
*target
= bank
->target
;
377 /* probed? halted? */
378 status
= lpc288x_system_ready(bank
);
379 if (status
!= ERROR_OK
)
382 if ((last
< first
) || (last
>= bank
->num_sectors
))
383 return ERROR_FLASH_SECTOR_INVALID
;
385 /* Configure the flash controller timing */
386 lpc288x_set_flash_clk(bank
);
388 for (unsigned int lockregion
= first
; lockregion
<= last
; lockregion
++) {
390 /* write an odd value to base address to protect... */
393 /* write an even value to base address to unprotect... */
396 target_write_u32(target
, bank
->sectors
[lockregion
].offset
, value
);
397 target_write_u32(target
, F_CTRL
, FC_LOAD_REQ
| FC_PROTECT
| FC_WEN
| FC_FUNC
|
404 const struct flash_driver lpc288x_flash
= {
406 .flash_bank_command
= lpc288x_flash_bank_command
,
407 .erase
= lpc288x_erase
,
408 .protect
= lpc288x_protect
,
409 .write
= lpc288x_write
,
410 .read
= default_flash_read
,
411 .probe
= lpc288x_probe
,
412 .auto_probe
= lpc288x_probe
,
413 .erase_check
= default_flash_blank_check
,
414 .protect_check
= lpc288x_protect_check
,
415 .free_driver_priv
= default_flash_free_driver_priv
,
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