1 /***************************************************************************
2 * Copyright (C) 2005, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * Copyright (C) 2009 Michael Schwingen *
5 * michael@schwingen.org *
6 * Copyright (C) 2010 Øyvind Harboe <oyvind.harboe@zylin.com> *
7 * Copyright (C) 2010 by Antonio Borneo <borneo.antonio@gmail.com> *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
23 ***************************************************************************/
31 #include <target/arm.h>
32 #include <helper/binarybuffer.h>
33 #include <target/algorithm.h>
36 #define CFI_MAX_BUS_WIDTH 4
37 #define CFI_MAX_CHIP_WIDTH 4
39 /* defines internal maximum size for code fragment in cfi_intel_write_block() */
40 #define CFI_MAX_INTEL_CODESIZE 256
42 static struct cfi_unlock_addresses cfi_unlock_addresses
[] =
44 [CFI_UNLOCK_555_2AA
] = { .unlock1
= 0x555, .unlock2
= 0x2aa },
45 [CFI_UNLOCK_5555_2AAA
] = { .unlock1
= 0x5555, .unlock2
= 0x2aaa },
48 /* CFI fixups foward declarations */
49 static void cfi_fixup_0002_erase_regions(struct flash_bank
*flash
, void *param
);
50 static void cfi_fixup_0002_unlock_addresses(struct flash_bank
*flash
, void *param
);
51 static void cfi_fixup_atmel_reversed_erase_regions(struct flash_bank
*flash
, void *param
);
53 /* fixup after reading cmdset 0002 primary query table */
54 static const struct cfi_fixup cfi_0002_fixups
[] = {
55 {CFI_MFR_SST
, 0x00D4, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
56 {CFI_MFR_SST
, 0x00D5, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
57 {CFI_MFR_SST
, 0x00D6, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
58 {CFI_MFR_SST
, 0x00D7, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
59 {CFI_MFR_SST
, 0x2780, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
60 {CFI_MFR_ATMEL
, 0x00C8, cfi_fixup_atmel_reversed_erase_regions
, NULL
},
61 {CFI_MFR_FUJITSU
, 0x22ea, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
]},
62 {CFI_MFR_FUJITSU
, 0x226b, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
63 {CFI_MFR_AMIC
, 0xb31a, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
]},
64 {CFI_MFR_MX
, 0x225b, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
]},
65 {CFI_MFR_AMD
, 0x225b, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
]},
66 {CFI_MFR_ANY
, CFI_ID_ANY
, cfi_fixup_0002_erase_regions
, NULL
},
70 /* fixup after reading cmdset 0001 primary query table */
71 static const struct cfi_fixup cfi_0001_fixups
[] = {
75 static void cfi_fixup(struct flash_bank
*bank
, const struct cfi_fixup
*fixups
)
77 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
78 const struct cfi_fixup
*f
;
80 for (f
= fixups
; f
->fixup
; f
++)
82 if (((f
->mfr
== CFI_MFR_ANY
) || (f
->mfr
== cfi_info
->manufacturer
)) &&
83 ((f
->id
== CFI_ID_ANY
) || (f
->id
== cfi_info
->device_id
)))
85 f
->fixup(bank
, f
->param
);
90 /* inline uint32_t flash_address(struct flash_bank *bank, int sector, uint32_t offset) */
91 static __inline__
uint32_t flash_address(struct flash_bank
*bank
, int sector
, uint32_t offset
)
93 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
95 if (cfi_info
->x16_as_x8
) offset
*= 2;
97 /* while the sector list isn't built, only accesses to sector 0 work */
99 return bank
->base
+ offset
* bank
->bus_width
;
104 LOG_ERROR("BUG: sector list not yet built");
107 return bank
->base
+ bank
->sectors
[sector
].offset
+ offset
* bank
->bus_width
;
111 static void cfi_command(struct flash_bank
*bank
, uint8_t cmd
, uint8_t *cmd_buf
)
115 /* clear whole buffer, to ensure bits that exceed the bus_width
118 for (i
= 0; i
< CFI_MAX_BUS_WIDTH
; i
++)
121 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
123 for (i
= bank
->bus_width
; i
> 0; i
--)
125 *cmd_buf
++ = (i
& (bank
->chip_width
- 1)) ? 0x0 : cmd
;
130 for (i
= 1; i
<= bank
->bus_width
; i
++)
132 *cmd_buf
++ = (i
& (bank
->chip_width
- 1)) ? 0x0 : cmd
;
137 static int cfi_send_command(struct flash_bank
*bank
, uint8_t cmd
, uint32_t address
)
139 uint8_t command
[CFI_MAX_BUS_WIDTH
];
141 cfi_command(bank
, cmd
, command
);
142 return target_write_memory(bank
->target
, address
, bank
->bus_width
, 1, command
);
145 /* read unsigned 8-bit value from the bank
146 * flash banks are expected to be made of similar chips
147 * the query result should be the same for all
149 static int cfi_query_u8(struct flash_bank
*bank
, int sector
, uint32_t offset
, uint8_t *val
)
151 struct target
*target
= bank
->target
;
152 uint8_t data
[CFI_MAX_BUS_WIDTH
];
155 retval
= target_read_memory(target
, flash_address(bank
, sector
, offset
), bank
->bus_width
, 1, data
);
156 if (retval
!= ERROR_OK
)
159 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
162 *val
= data
[bank
->bus_width
- 1];
167 /* read unsigned 8-bit value from the bank
168 * in case of a bank made of multiple chips,
169 * the individual values are ORed
171 static int cfi_get_u8(struct flash_bank
*bank
, int sector
, uint32_t offset
, uint8_t *val
)
173 struct target
*target
= bank
->target
;
174 uint8_t data
[CFI_MAX_BUS_WIDTH
];
178 retval
= target_read_memory(target
, flash_address(bank
, sector
, offset
), bank
->bus_width
, 1, data
);
179 if (retval
!= ERROR_OK
)
182 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
184 for (i
= 0; i
< bank
->bus_width
/ bank
->chip_width
; i
++)
192 for (i
= 0; i
< bank
->bus_width
/ bank
->chip_width
; i
++)
193 value
|= data
[bank
->bus_width
- 1 - i
];
200 static int cfi_query_u16(struct flash_bank
*bank
, int sector
, uint32_t offset
, uint16_t *val
)
202 struct target
*target
= bank
->target
;
203 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
204 uint8_t data
[CFI_MAX_BUS_WIDTH
* 2];
207 if (cfi_info
->x16_as_x8
)
210 for (i
= 0;i
< 2;i
++)
212 retval
= target_read_memory(target
, flash_address(bank
, sector
, offset
+ i
), bank
->bus_width
, 1,
213 &data
[i
*bank
->bus_width
]);
214 if (retval
!= ERROR_OK
)
219 retval
= target_read_memory(target
, flash_address(bank
, sector
, offset
), bank
->bus_width
, 2, data
);
220 if (retval
!= ERROR_OK
)
224 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
225 *val
= data
[0] | data
[bank
->bus_width
] << 8;
227 *val
= data
[bank
->bus_width
- 1] | data
[(2 * bank
->bus_width
) - 1] << 8;
232 static int cfi_query_u32(struct flash_bank
*bank
, int sector
, uint32_t offset
, uint32_t *val
)
234 struct target
*target
= bank
->target
;
235 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
236 uint8_t data
[CFI_MAX_BUS_WIDTH
* 4];
239 if (cfi_info
->x16_as_x8
)
242 for (i
= 0;i
< 4;i
++)
244 retval
= target_read_memory(target
, flash_address(bank
, sector
, offset
+ i
), bank
->bus_width
, 1,
245 &data
[i
*bank
->bus_width
]);
246 if (retval
!= ERROR_OK
)
252 retval
= target_read_memory(target
, flash_address(bank
, sector
, offset
), bank
->bus_width
, 4, data
);
253 if (retval
!= ERROR_OK
)
257 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
258 *val
= data
[0] | data
[bank
->bus_width
] << 8 | data
[bank
->bus_width
* 2] << 16 | data
[bank
->bus_width
* 3] << 24;
260 *val
= data
[bank
->bus_width
- 1] | data
[(2* bank
->bus_width
) - 1] << 8 |
261 data
[(3 * bank
->bus_width
) - 1] << 16 | data
[(4 * bank
->bus_width
) - 1] << 24;
266 static int cfi_reset(struct flash_bank
*bank
)
268 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
269 int retval
= ERROR_OK
;
271 if ((retval
= cfi_send_command(bank
, 0xf0, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
276 if ((retval
= cfi_send_command(bank
, 0xff, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
281 if (cfi_info
->manufacturer
== 0x20 &&
282 (cfi_info
->device_id
== 0x227E || cfi_info
->device_id
== 0x7E))
284 /* Numonix M29W128G is cmd 0xFF intolerant - causes internal undefined state
285 * so we send an extra 0xF0 reset to fix the bug */
286 if ((retval
= cfi_send_command(bank
, 0xf0, flash_address(bank
, 0, 0x00))) != ERROR_OK
)
295 static void cfi_intel_clear_status_register(struct flash_bank
*bank
)
297 struct target
*target
= bank
->target
;
299 if (target
->state
!= TARGET_HALTED
)
301 LOG_ERROR("BUG: attempted to clear status register while target wasn't halted");
305 cfi_send_command(bank
, 0x50, flash_address(bank
, 0, 0x0));
308 static int cfi_intel_wait_status_busy(struct flash_bank
*bank
, int timeout
, uint8_t *val
)
312 int retval
= ERROR_OK
;
318 LOG_ERROR("timeout while waiting for WSM to become ready");
322 retval
= cfi_get_u8(bank
, 0, 0x0, &status
);
323 if (retval
!= ERROR_OK
)
332 /* mask out bit 0 (reserved) */
333 status
= status
& 0xfe;
335 LOG_DEBUG("status: 0x%x", status
);
339 LOG_ERROR("status register: 0x%x", status
);
341 LOG_ERROR("Block Lock-Bit Detected, Operation Abort");
343 LOG_ERROR("Program suspended");
345 LOG_ERROR("Low Programming Voltage Detected, Operation Aborted");
347 LOG_ERROR("Program Error / Error in Setting Lock-Bit");
349 LOG_ERROR("Error in Block Erasure or Clear Lock-Bits");
351 LOG_ERROR("Block Erase Suspended");
353 cfi_intel_clear_status_register(bank
);
362 static int cfi_spansion_wait_status_busy(struct flash_bank
*bank
, int timeout
)
364 uint8_t status
, oldstatus
;
365 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
368 retval
= cfi_get_u8(bank
, 0, 0x0, &oldstatus
);
369 if (retval
!= ERROR_OK
)
373 retval
= cfi_get_u8(bank
, 0, 0x0, &status
);
375 if (retval
!= ERROR_OK
)
378 if ((status
^ oldstatus
) & 0x40) {
379 if (status
& cfi_info
->status_poll_mask
& 0x20) {
380 retval
= cfi_get_u8(bank
, 0, 0x0, &oldstatus
);
381 if (retval
!= ERROR_OK
)
383 retval
= cfi_get_u8(bank
, 0, 0x0, &status
);
384 if (retval
!= ERROR_OK
)
386 if ((status
^ oldstatus
) & 0x40) {
387 LOG_ERROR("dq5 timeout, status: 0x%x", status
);
388 return(ERROR_FLASH_OPERATION_FAILED
);
390 LOG_DEBUG("status: 0x%x", status
);
394 } else { /* no toggle: finished, OK */
395 LOG_DEBUG("status: 0x%x", status
);
401 } while (timeout
-- > 0);
403 LOG_ERROR("timeout, status: 0x%x", status
);
405 return(ERROR_FLASH_BUSY
);
408 static int cfi_read_intel_pri_ext(struct flash_bank
*bank
)
411 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
412 struct cfi_intel_pri_ext
*pri_ext
;
414 if (cfi_info
->pri_ext
)
415 free(cfi_info
->pri_ext
);
417 pri_ext
= malloc(sizeof(struct cfi_intel_pri_ext
));
420 LOG_ERROR("Out of memory");
423 cfi_info
->pri_ext
= pri_ext
;
425 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0, &pri_ext
->pri
[0]);
426 if (retval
!= ERROR_OK
)
428 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 1, &pri_ext
->pri
[1]);
429 if (retval
!= ERROR_OK
)
431 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 2, &pri_ext
->pri
[2]);
432 if (retval
!= ERROR_OK
)
435 if ((pri_ext
->pri
[0] != 'P') || (pri_ext
->pri
[1] != 'R') || (pri_ext
->pri
[2] != 'I'))
437 if ((retval
= cfi_reset(bank
)) != ERROR_OK
)
441 LOG_ERROR("Could not read bank flash bank information");
442 return ERROR_FLASH_BANK_INVALID
;
445 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 3, &pri_ext
->major_version
);
446 if (retval
!= ERROR_OK
)
448 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 4, &pri_ext
->minor_version
);
449 if (retval
!= ERROR_OK
)
452 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext
->pri
[0], pri_ext
->pri
[1], pri_ext
->pri
[2], pri_ext
->major_version
, pri_ext
->minor_version
);
454 retval
= cfi_query_u32(bank
, 0, cfi_info
->pri_addr
+ 5, &pri_ext
->feature_support
);
455 if (retval
!= ERROR_OK
)
457 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 9, &pri_ext
->suspend_cmd_support
);
458 if (retval
!= ERROR_OK
)
460 retval
= cfi_query_u16(bank
, 0, cfi_info
->pri_addr
+ 0xa, &pri_ext
->blk_status_reg_mask
);
461 if (retval
!= ERROR_OK
)
464 LOG_DEBUG("feature_support: 0x%" PRIx32
", suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x",
465 pri_ext
->feature_support
,
466 pri_ext
->suspend_cmd_support
,
467 pri_ext
->blk_status_reg_mask
);
469 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0xc, &pri_ext
->vcc_optimal
);
470 if (retval
!= ERROR_OK
)
472 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0xd, &pri_ext
->vpp_optimal
);
473 if (retval
!= ERROR_OK
)
476 LOG_DEBUG("Vcc opt: %x.%x, Vpp opt: %u.%x",
477 (pri_ext
->vcc_optimal
& 0xf0) >> 4, pri_ext
->vcc_optimal
& 0x0f,
478 (pri_ext
->vpp_optimal
& 0xf0) >> 4, pri_ext
->vpp_optimal
& 0x0f);
480 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0xe, &pri_ext
->num_protection_fields
);
481 if (retval
!= ERROR_OK
)
483 if (pri_ext
->num_protection_fields
!= 1)
485 LOG_WARNING("expected one protection register field, but found %i", pri_ext
->num_protection_fields
);
488 retval
= cfi_query_u16(bank
, 0, cfi_info
->pri_addr
+ 0xf, &pri_ext
->prot_reg_addr
);
489 if (retval
!= ERROR_OK
)
491 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0x11, &pri_ext
->fact_prot_reg_size
);
492 if (retval
!= ERROR_OK
)
494 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0x12, &pri_ext
->user_prot_reg_size
);
495 if (retval
!= ERROR_OK
)
498 LOG_DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i", pri_ext
->num_protection_fields
, pri_ext
->prot_reg_addr
, 1 << pri_ext
->fact_prot_reg_size
, 1 << pri_ext
->user_prot_reg_size
);
503 static int cfi_read_spansion_pri_ext(struct flash_bank
*bank
)
506 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
507 struct cfi_spansion_pri_ext
*pri_ext
;
509 if (cfi_info
->pri_ext
)
510 free(cfi_info
->pri_ext
);
512 pri_ext
= malloc(sizeof(struct cfi_spansion_pri_ext
));
515 LOG_ERROR("Out of memory");
518 cfi_info
->pri_ext
= pri_ext
;
520 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0, &pri_ext
->pri
[0]);
521 if (retval
!= ERROR_OK
)
523 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 1, &pri_ext
->pri
[1]);
524 if (retval
!= ERROR_OK
)
526 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 2, &pri_ext
->pri
[2]);
527 if (retval
!= ERROR_OK
)
530 if ((pri_ext
->pri
[0] != 'P') || (pri_ext
->pri
[1] != 'R') || (pri_ext
->pri
[2] != 'I'))
532 if ((retval
= cfi_send_command(bank
, 0xf0, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
536 LOG_ERROR("Could not read spansion bank information");
537 return ERROR_FLASH_BANK_INVALID
;
540 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 3, &pri_ext
->major_version
);
541 if (retval
!= ERROR_OK
)
543 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 4, &pri_ext
->minor_version
);
544 if (retval
!= ERROR_OK
)
547 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext
->pri
[0], pri_ext
->pri
[1], pri_ext
->pri
[2], pri_ext
->major_version
, pri_ext
->minor_version
);
549 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 5, &pri_ext
->SiliconRevision
);
550 if (retval
!= ERROR_OK
)
552 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 6, &pri_ext
->EraseSuspend
);
553 if (retval
!= ERROR_OK
)
555 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 7, &pri_ext
->BlkProt
);
556 if (retval
!= ERROR_OK
)
558 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 8, &pri_ext
->TmpBlkUnprotect
);
559 if (retval
!= ERROR_OK
)
561 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 9, &pri_ext
->BlkProtUnprot
);
562 if (retval
!= ERROR_OK
)
564 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 10, &pri_ext
->SimultaneousOps
);
565 if (retval
!= ERROR_OK
)
567 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 11, &pri_ext
->BurstMode
);
568 if (retval
!= ERROR_OK
)
570 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 12, &pri_ext
->PageMode
);
571 if (retval
!= ERROR_OK
)
573 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 13, &pri_ext
->VppMin
);
574 if (retval
!= ERROR_OK
)
576 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 14, &pri_ext
->VppMax
);
577 if (retval
!= ERROR_OK
)
579 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 15, &pri_ext
->TopBottom
);
580 if (retval
!= ERROR_OK
)
583 LOG_DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x", pri_ext
->SiliconRevision
,
584 pri_ext
->EraseSuspend
, pri_ext
->BlkProt
);
586 LOG_DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, Simultaneous Ops: 0x%x", pri_ext
->TmpBlkUnprotect
,
587 pri_ext
->BlkProtUnprot
, pri_ext
->SimultaneousOps
);
589 LOG_DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext
->BurstMode
, pri_ext
->PageMode
);
592 LOG_DEBUG("Vpp min: %u.%x, Vpp max: %u.%x",
593 (pri_ext
->VppMin
& 0xf0) >> 4, pri_ext
->VppMin
& 0x0f,
594 (pri_ext
->VppMax
& 0xf0) >> 4, pri_ext
->VppMax
& 0x0f);
596 LOG_DEBUG("WP# protection 0x%x", pri_ext
->TopBottom
);
598 /* default values for implementation specific workarounds */
599 pri_ext
->_unlock1
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock1
;
600 pri_ext
->_unlock2
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock2
;
601 pri_ext
->_reversed_geometry
= 0;
606 static int cfi_read_atmel_pri_ext(struct flash_bank
*bank
)
609 struct cfi_atmel_pri_ext atmel_pri_ext
;
610 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
611 struct cfi_spansion_pri_ext
*pri_ext
;
613 if (cfi_info
->pri_ext
)
614 free(cfi_info
->pri_ext
);
616 pri_ext
= malloc(sizeof(struct cfi_spansion_pri_ext
));
619 LOG_ERROR("Out of memory");
623 /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
624 * but a different primary extended query table.
625 * We read the atmel table, and prepare a valid AMD/Spansion query table.
628 memset(pri_ext
, 0, sizeof(struct cfi_spansion_pri_ext
));
630 cfi_info
->pri_ext
= pri_ext
;
632 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0, &atmel_pri_ext
.pri
[0]);
633 if (retval
!= ERROR_OK
)
635 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 1, &atmel_pri_ext
.pri
[1]);
636 if (retval
!= ERROR_OK
)
638 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 2, &atmel_pri_ext
.pri
[2]);
639 if (retval
!= ERROR_OK
)
642 if ((atmel_pri_ext
.pri
[0] != 'P') || (atmel_pri_ext
.pri
[1] != 'R') || (atmel_pri_ext
.pri
[2] != 'I'))
644 if ((retval
= cfi_send_command(bank
, 0xf0, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
648 LOG_ERROR("Could not read atmel bank information");
649 return ERROR_FLASH_BANK_INVALID
;
652 pri_ext
->pri
[0] = atmel_pri_ext
.pri
[0];
653 pri_ext
->pri
[1] = atmel_pri_ext
.pri
[1];
654 pri_ext
->pri
[2] = atmel_pri_ext
.pri
[2];
656 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 3, &atmel_pri_ext
.major_version
);
657 if (retval
!= ERROR_OK
)
659 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 4, &atmel_pri_ext
.minor_version
);
660 if (retval
!= ERROR_OK
)
663 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext
.pri
[0], atmel_pri_ext
.pri
[1], atmel_pri_ext
.pri
[2], atmel_pri_ext
.major_version
, atmel_pri_ext
.minor_version
);
665 pri_ext
->major_version
= atmel_pri_ext
.major_version
;
666 pri_ext
->minor_version
= atmel_pri_ext
.minor_version
;
668 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 5, &atmel_pri_ext
.features
);
669 if (retval
!= ERROR_OK
)
671 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 6, &atmel_pri_ext
.bottom_boot
);
672 if (retval
!= ERROR_OK
)
674 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 7, &atmel_pri_ext
.burst_mode
);
675 if (retval
!= ERROR_OK
)
677 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 8, &atmel_pri_ext
.page_mode
);
678 if (retval
!= ERROR_OK
)
681 LOG_DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
682 atmel_pri_ext
.features
, atmel_pri_ext
.bottom_boot
, atmel_pri_ext
.burst_mode
, atmel_pri_ext
.page_mode
);
684 if (atmel_pri_ext
.features
& 0x02)
685 pri_ext
->EraseSuspend
= 2;
687 if (atmel_pri_ext
.bottom_boot
)
688 pri_ext
->TopBottom
= 2;
690 pri_ext
->TopBottom
= 3;
692 pri_ext
->_unlock1
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock1
;
693 pri_ext
->_unlock2
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock2
;
698 static int cfi_read_0002_pri_ext(struct flash_bank
*bank
)
700 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
702 if (cfi_info
->manufacturer
== CFI_MFR_ATMEL
)
704 return cfi_read_atmel_pri_ext(bank
);
708 return cfi_read_spansion_pri_ext(bank
);
712 static int cfi_spansion_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
715 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
716 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
718 printed
= snprintf(buf
, buf_size
, "\nSpansion primary algorithm extend information:\n");
722 printed
= snprintf(buf
, buf_size
, "pri: '%c%c%c', version: %c.%c\n", pri_ext
->pri
[0],
723 pri_ext
->pri
[1], pri_ext
->pri
[2],
724 pri_ext
->major_version
, pri_ext
->minor_version
);
728 printed
= snprintf(buf
, buf_size
, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
729 (pri_ext
->SiliconRevision
) >> 2,
730 (pri_ext
->SiliconRevision
) & 0x03);
734 printed
= snprintf(buf
, buf_size
, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
735 pri_ext
->EraseSuspend
,
740 printed
= snprintf(buf
, buf_size
, "VppMin: %u.%x, VppMax: %u.%x\n",
741 (pri_ext
->VppMin
& 0xf0) >> 4, pri_ext
->VppMin
& 0x0f,
742 (pri_ext
->VppMax
& 0xf0) >> 4, pri_ext
->VppMax
& 0x0f);
747 static int cfi_intel_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
750 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
751 struct cfi_intel_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
753 printed
= snprintf(buf
, buf_size
, "\nintel primary algorithm extend information:\n");
757 printed
= snprintf(buf
, buf_size
, "pri: '%c%c%c', version: %c.%c\n", pri_ext
->pri
[0], pri_ext
->pri
[1], pri_ext
->pri
[2], pri_ext
->major_version
, pri_ext
->minor_version
);
761 printed
= snprintf(buf
, buf_size
, "feature_support: 0x%" PRIx32
", suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n", pri_ext
->feature_support
, pri_ext
->suspend_cmd_support
, pri_ext
->blk_status_reg_mask
);
765 printed
= snprintf(buf
, buf_size
, "Vcc opt: %x.%x, Vpp opt: %u.%x\n",
766 (pri_ext
->vcc_optimal
& 0xf0) >> 4, pri_ext
->vcc_optimal
& 0x0f,
767 (pri_ext
->vpp_optimal
& 0xf0) >> 4, pri_ext
->vpp_optimal
& 0x0f);
771 printed
= snprintf(buf
, buf_size
, "protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i\n", pri_ext
->num_protection_fields
, pri_ext
->prot_reg_addr
, 1 << pri_ext
->fact_prot_reg_size
, 1 << pri_ext
->user_prot_reg_size
);
776 /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
778 FLASH_BANK_COMMAND_HANDLER(cfi_flash_bank_command
)
780 struct cfi_flash_bank
*cfi_info
;
784 LOG_WARNING("incomplete flash_bank cfi configuration");
785 return ERROR_FLASH_BANK_INVALID
;
789 * - not exceed max value;
791 * - be equal to a power of 2.
792 * bus must be wide enought to hold one chip */
793 if ((bank
->chip_width
> CFI_MAX_CHIP_WIDTH
)
794 || (bank
->bus_width
> CFI_MAX_BUS_WIDTH
)
795 || (bank
->chip_width
== 0)
796 || (bank
->bus_width
== 0)
797 || (bank
->chip_width
& (bank
->chip_width
- 1))
798 || (bank
->bus_width
& (bank
->bus_width
- 1))
799 || (bank
->chip_width
> bank
->bus_width
))
801 LOG_ERROR("chip and bus width have to specified in bytes");
802 return ERROR_FLASH_BANK_INVALID
;
805 cfi_info
= malloc(sizeof(struct cfi_flash_bank
));
806 cfi_info
->probed
= 0;
807 cfi_info
->erase_region_info
= 0;
808 cfi_info
->pri_ext
= NULL
;
809 bank
->driver_priv
= cfi_info
;
811 cfi_info
->write_algorithm
= NULL
;
813 cfi_info
->x16_as_x8
= 0;
814 cfi_info
->jedec_probe
= 0;
815 cfi_info
->not_cfi
= 0;
817 for (unsigned i
= 6; i
< CMD_ARGC
; i
++)
819 if (strcmp(CMD_ARGV
[i
], "x16_as_x8") == 0)
821 cfi_info
->x16_as_x8
= 1;
823 else if (strcmp(CMD_ARGV
[i
], "jedec_probe") == 0)
825 cfi_info
->jedec_probe
= 1;
829 cfi_info
->write_algorithm
= NULL
;
831 /* bank wasn't probed yet */
832 cfi_info
->qry
[0] = 0xff;
837 static int cfi_intel_erase(struct flash_bank
*bank
, int first
, int last
)
840 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
843 cfi_intel_clear_status_register(bank
);
845 for (i
= first
; i
<= last
; i
++)
847 if ((retval
= cfi_send_command(bank
, 0x20, flash_address(bank
, i
, 0x0))) != ERROR_OK
)
852 if ((retval
= cfi_send_command(bank
, 0xd0, flash_address(bank
, i
, 0x0))) != ERROR_OK
)
858 retval
= cfi_intel_wait_status_busy(bank
, 1000 * (1 << cfi_info
->block_erase_timeout_typ
), &status
);
859 if (retval
!= ERROR_OK
)
863 bank
->sectors
[i
].is_erased
= 1;
866 if ((retval
= cfi_send_command(bank
, 0xff, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
871 LOG_ERROR("couldn't erase block %i of flash bank at base 0x%" PRIx32
, i
, bank
->base
);
872 return ERROR_FLASH_OPERATION_FAILED
;
876 return cfi_send_command(bank
, 0xff, flash_address(bank
, 0, 0x0));
879 static int cfi_spansion_erase(struct flash_bank
*bank
, int first
, int last
)
882 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
883 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
886 for (i
= first
; i
<= last
; i
++)
888 if ((retval
= cfi_send_command(bank
, 0xaa, flash_address(bank
, 0, pri_ext
->_unlock1
))) != ERROR_OK
)
893 if ((retval
= cfi_send_command(bank
, 0x55, flash_address(bank
, 0, pri_ext
->_unlock2
))) != ERROR_OK
)
898 if ((retval
= cfi_send_command(bank
, 0x80, flash_address(bank
, 0, pri_ext
->_unlock1
))) != ERROR_OK
)
903 if ((retval
= cfi_send_command(bank
, 0xaa, flash_address(bank
, 0, pri_ext
->_unlock1
))) != ERROR_OK
)
908 if ((retval
= cfi_send_command(bank
, 0x55, flash_address(bank
, 0, pri_ext
->_unlock2
))) != ERROR_OK
)
913 if ((retval
= cfi_send_command(bank
, 0x30, flash_address(bank
, i
, 0x0))) != ERROR_OK
)
918 if (cfi_spansion_wait_status_busy(bank
, 1000 * (1 << cfi_info
->block_erase_timeout_typ
)) == ERROR_OK
)
919 bank
->sectors
[i
].is_erased
= 1;
922 if ((retval
= cfi_send_command(bank
, 0xf0, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
927 LOG_ERROR("couldn't erase block %i of flash bank at base 0x%" PRIx32
, i
, bank
->base
);
928 return ERROR_FLASH_OPERATION_FAILED
;
932 return cfi_send_command(bank
, 0xf0, flash_address(bank
, 0, 0x0));
935 static int cfi_erase(struct flash_bank
*bank
, int first
, int last
)
937 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
939 if (bank
->target
->state
!= TARGET_HALTED
)
941 LOG_ERROR("Target not halted");
942 return ERROR_TARGET_NOT_HALTED
;
945 if ((first
< 0) || (last
< first
) || (last
>= bank
->num_sectors
))
947 return ERROR_FLASH_SECTOR_INVALID
;
950 if (cfi_info
->qry
[0] != 'Q')
951 return ERROR_FLASH_BANK_NOT_PROBED
;
953 switch (cfi_info
->pri_id
)
957 return cfi_intel_erase(bank
, first
, last
);
960 return cfi_spansion_erase(bank
, first
, last
);
963 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
970 static int cfi_intel_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
973 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
974 struct cfi_intel_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
978 /* if the device supports neither legacy lock/unlock (bit 3) nor
979 * instant individual block locking (bit 5).
981 if (!(pri_ext
->feature_support
& 0x28))
982 return ERROR_FLASH_OPERATION_FAILED
;
984 cfi_intel_clear_status_register(bank
);
986 for (i
= first
; i
<= last
; i
++)
988 if ((retval
= cfi_send_command(bank
, 0x60, flash_address(bank
, i
, 0x0))) != ERROR_OK
)
994 if ((retval
= cfi_send_command(bank
, 0x01, flash_address(bank
, i
, 0x0))) != ERROR_OK
)
998 bank
->sectors
[i
].is_protected
= 1;
1002 if ((retval
= cfi_send_command(bank
, 0xd0, flash_address(bank
, i
, 0x0))) != ERROR_OK
)
1006 bank
->sectors
[i
].is_protected
= 0;
1009 /* instant individual block locking doesn't require reading of the status register */
1010 if (!(pri_ext
->feature_support
& 0x20))
1012 /* Clear lock bits operation may take up to 1.4s */
1014 retval
= cfi_intel_wait_status_busy(bank
, 1400, &status
);
1015 if (retval
!= ERROR_OK
)
1020 uint8_t block_status
;
1021 /* read block lock bit, to verify status */
1022 if ((retval
= cfi_send_command(bank
, 0x90, flash_address(bank
, 0, 0x55))) != ERROR_OK
)
1026 retval
= cfi_get_u8(bank
, i
, 0x2, &block_status
);
1027 if (retval
!= ERROR_OK
)
1030 if ((block_status
& 0x1) != set
)
1032 LOG_ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set
, block_status
);
1033 if ((retval
= cfi_send_command(bank
, 0x70, flash_address(bank
, 0, 0x55))) != ERROR_OK
)
1038 retval
= cfi_intel_wait_status_busy(bank
, 10, &status
);
1039 if (retval
!= ERROR_OK
)
1043 return ERROR_FLASH_OPERATION_FAILED
;
1053 /* if the device doesn't support individual block lock bits set/clear,
1054 * all blocks have been unlocked in parallel, so we set those that should be protected
1056 if ((!set
) && (!(pri_ext
->feature_support
& 0x20)))
1058 /* FIX!!! this code path is broken!!!
1060 * The correct approach is:
1062 * 1. read out current protection status
1064 * 2. override read out protection status w/unprotected.
1066 * 3. re-protect what should be protected.
1069 for (i
= 0; i
< bank
->num_sectors
; i
++)
1071 if (bank
->sectors
[i
].is_protected
== 1)
1073 cfi_intel_clear_status_register(bank
);
1075 if ((retval
= cfi_send_command(bank
, 0x60, flash_address(bank
, i
, 0x0))) != ERROR_OK
)
1080 if ((retval
= cfi_send_command(bank
, 0x01, flash_address(bank
, i
, 0x0))) != ERROR_OK
)
1086 retval
= cfi_intel_wait_status_busy(bank
, 100, &status
);
1087 if (retval
!= ERROR_OK
)
1093 return cfi_send_command(bank
, 0xff, flash_address(bank
, 0, 0x0));
1096 static int cfi_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
1098 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1100 if (bank
->target
->state
!= TARGET_HALTED
)
1102 LOG_ERROR("Target not halted");
1103 return ERROR_TARGET_NOT_HALTED
;
1106 if ((first
< 0) || (last
< first
) || (last
>= bank
->num_sectors
))
1108 LOG_ERROR("Invalid sector range");
1109 return ERROR_FLASH_SECTOR_INVALID
;
1112 if (cfi_info
->qry
[0] != 'Q')
1113 return ERROR_FLASH_BANK_NOT_PROBED
;
1115 switch (cfi_info
->pri_id
)
1119 return cfi_intel_protect(bank
, set
, first
, last
);
1122 LOG_ERROR("protect: cfi primary command set %i unsupported", cfi_info
->pri_id
);
1127 /* Convert code image to target endian */
1128 /* FIXME create general block conversion fcts in target.c?) */
1129 static void cfi_fix_code_endian(struct target
*target
, uint8_t *dest
, const uint32_t *src
, uint32_t count
)
1132 for (i
= 0; i
< count
; i
++)
1134 target_buffer_set_u32(target
, dest
, *src
);
1140 static uint32_t cfi_command_val(struct flash_bank
*bank
, uint8_t cmd
)
1142 struct target
*target
= bank
->target
;
1144 uint8_t buf
[CFI_MAX_BUS_WIDTH
];
1145 cfi_command(bank
, cmd
, buf
);
1146 switch (bank
->bus_width
)
1152 return target_buffer_get_u16(target
, buf
);
1155 return target_buffer_get_u32(target
, buf
);
1158 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank
->bus_width
);
1163 static int cfi_intel_write_block(struct flash_bank
*bank
, uint8_t *buffer
, uint32_t address
, uint32_t count
)
1165 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1166 struct target
*target
= bank
->target
;
1167 struct reg_param reg_params
[7];
1168 struct arm_algorithm armv4_5_info
;
1169 struct working_area
*source
;
1170 uint32_t buffer_size
= 32768;
1171 uint32_t write_command_val
, busy_pattern_val
, error_pattern_val
;
1173 /* algorithm register usage:
1174 * r0: source address (in RAM)
1175 * r1: target address (in Flash)
1177 * r3: flash write command
1178 * r4: status byte (returned to host)
1179 * r5: busy test pattern
1180 * r6: error test pattern
1183 static const uint32_t word_32_code
[] = {
1184 0xe4904004, /* loop: ldr r4, [r0], #4 */
1185 0xe5813000, /* str r3, [r1] */
1186 0xe5814000, /* str r4, [r1] */
1187 0xe5914000, /* busy: ldr r4, [r1] */
1188 0xe0047005, /* and r7, r4, r5 */
1189 0xe1570005, /* cmp r7, r5 */
1190 0x1afffffb, /* bne busy */
1191 0xe1140006, /* tst r4, r6 */
1192 0x1a000003, /* bne done */
1193 0xe2522001, /* subs r2, r2, #1 */
1194 0x0a000001, /* beq done */
1195 0xe2811004, /* add r1, r1 #4 */
1196 0xeafffff2, /* b loop */
1197 0xeafffffe /* done: b -2 */
1200 static const uint32_t word_16_code
[] = {
1201 0xe0d040b2, /* loop: ldrh r4, [r0], #2 */
1202 0xe1c130b0, /* strh r3, [r1] */
1203 0xe1c140b0, /* strh r4, [r1] */
1204 0xe1d140b0, /* busy ldrh r4, [r1] */
1205 0xe0047005, /* and r7, r4, r5 */
1206 0xe1570005, /* cmp r7, r5 */
1207 0x1afffffb, /* bne busy */
1208 0xe1140006, /* tst r4, r6 */
1209 0x1a000003, /* bne done */
1210 0xe2522001, /* subs r2, r2, #1 */
1211 0x0a000001, /* beq done */
1212 0xe2811002, /* add r1, r1 #2 */
1213 0xeafffff2, /* b loop */
1214 0xeafffffe /* done: b -2 */
1217 static const uint32_t word_8_code
[] = {
1218 0xe4d04001, /* loop: ldrb r4, [r0], #1 */
1219 0xe5c13000, /* strb r3, [r1] */
1220 0xe5c14000, /* strb r4, [r1] */
1221 0xe5d14000, /* busy ldrb r4, [r1] */
1222 0xe0047005, /* and r7, r4, r5 */
1223 0xe1570005, /* cmp r7, r5 */
1224 0x1afffffb, /* bne busy */
1225 0xe1140006, /* tst r4, r6 */
1226 0x1a000003, /* bne done */
1227 0xe2522001, /* subs r2, r2, #1 */
1228 0x0a000001, /* beq done */
1229 0xe2811001, /* add r1, r1 #1 */
1230 0xeafffff2, /* b loop */
1231 0xeafffffe /* done: b -2 */
1233 uint8_t target_code
[4*CFI_MAX_INTEL_CODESIZE
];
1234 const uint32_t *target_code_src
;
1235 uint32_t target_code_size
;
1236 int retval
= ERROR_OK
;
1239 cfi_intel_clear_status_register(bank
);
1241 armv4_5_info
.common_magic
= ARM_COMMON_MAGIC
;
1242 armv4_5_info
.core_mode
= ARM_MODE_SVC
;
1243 armv4_5_info
.core_state
= ARM_STATE_ARM
;
1245 /* If we are setting up the write_algorith, we need target_code_src */
1246 /* if not we only need target_code_size. */
1248 /* However, we don't want to create multiple code paths, so we */
1249 /* do the unecessary evaluation of target_code_src, which the */
1250 /* compiler will probably nicely optimize away if not needed */
1252 /* prepare algorithm code for target endian */
1253 switch (bank
->bus_width
)
1256 target_code_src
= word_8_code
;
1257 target_code_size
= sizeof(word_8_code
);
1260 target_code_src
= word_16_code
;
1261 target_code_size
= sizeof(word_16_code
);
1264 target_code_src
= word_32_code
;
1265 target_code_size
= sizeof(word_32_code
);
1268 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank
->bus_width
);
1269 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1272 /* flash write code */
1273 if (!cfi_info
->write_algorithm
)
1275 if (target_code_size
> sizeof(target_code
))
1277 LOG_WARNING("Internal error - target code buffer to small. Increase CFI_MAX_INTEL_CODESIZE and recompile.");
1278 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1280 cfi_fix_code_endian(target
, target_code
, target_code_src
, target_code_size
/ 4);
1282 /* Get memory for block write handler */
1283 retval
= target_alloc_working_area(target
, target_code_size
, &cfi_info
->write_algorithm
);
1284 if (retval
!= ERROR_OK
)
1286 LOG_WARNING("No working area available, can't do block memory writes");
1287 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1290 /* write algorithm code to working area */
1291 retval
= target_write_buffer(target
, cfi_info
->write_algorithm
->address
, target_code_size
, target_code
);
1292 if (retval
!= ERROR_OK
)
1294 LOG_ERROR("Unable to write block write code to target");
1299 /* Get a workspace buffer for the data to flash starting with 32k size.
1300 Half size until buffer would be smaller 256 Bytem then fail back */
1301 /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */
1302 while (target_alloc_working_area_try(target
, buffer_size
, &source
) != ERROR_OK
)
1305 if (buffer_size
<= 256)
1307 LOG_WARNING("no large enough working area available, can't do block memory writes");
1308 retval
= ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1313 /* setup algo registers */
1314 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
1315 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
1316 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
1317 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
);
1318 init_reg_param(®_params
[4], "r4", 32, PARAM_IN
);
1319 init_reg_param(®_params
[5], "r5", 32, PARAM_OUT
);
1320 init_reg_param(®_params
[6], "r6", 32, PARAM_OUT
);
1322 /* prepare command and status register patterns */
1323 write_command_val
= cfi_command_val(bank
, 0x40);
1324 busy_pattern_val
= cfi_command_val(bank
, 0x80);
1325 error_pattern_val
= cfi_command_val(bank
, 0x7e);
1327 LOG_DEBUG("Using target buffer at 0x%08" PRIx32
" and of size 0x%04" PRIx32
, source
->address
, buffer_size
);
1329 /* Programming main loop */
1332 uint32_t thisrun_count
= (count
> buffer_size
) ? buffer_size
: count
;
1335 if ((retval
= target_write_buffer(target
, source
->address
, thisrun_count
, buffer
)) != ERROR_OK
)
1340 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
1341 buf_set_u32(reg_params
[1].value
, 0, 32, address
);
1342 buf_set_u32(reg_params
[2].value
, 0, 32, thisrun_count
/ bank
->bus_width
);
1344 buf_set_u32(reg_params
[3].value
, 0, 32, write_command_val
);
1345 buf_set_u32(reg_params
[5].value
, 0, 32, busy_pattern_val
);
1346 buf_set_u32(reg_params
[6].value
, 0, 32, error_pattern_val
);
1348 LOG_DEBUG("Write 0x%04" PRIx32
" bytes to flash at 0x%08" PRIx32
, thisrun_count
, address
);
1350 /* Execute algorithm, assume breakpoint for last instruction */
1351 retval
= target_run_algorithm(target
, 0, NULL
, 7, reg_params
,
1352 cfi_info
->write_algorithm
->address
,
1353 cfi_info
->write_algorithm
->address
+ target_code_size
- sizeof(uint32_t),
1354 10000, /* 10s should be enough for max. 32k of data */
1357 /* On failure try a fall back to direct word writes */
1358 if (retval
!= ERROR_OK
)
1360 cfi_intel_clear_status_register(bank
);
1361 LOG_ERROR("Execution of flash algorythm failed. Can't fall back. Please report.");
1362 retval
= ERROR_FLASH_OPERATION_FAILED
;
1363 /* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
1364 /* FIXME To allow fall back or recovery, we must save the actual status
1365 somewhere, so that a higher level code can start recovery. */
1369 /* Check return value from algo code */
1370 wsm_error
= buf_get_u32(reg_params
[4].value
, 0, 32) & error_pattern_val
;
1373 /* read status register (outputs debug inforation) */
1375 cfi_intel_wait_status_busy(bank
, 100, &status
);
1376 cfi_intel_clear_status_register(bank
);
1377 retval
= ERROR_FLASH_OPERATION_FAILED
;
1381 buffer
+= thisrun_count
;
1382 address
+= thisrun_count
;
1383 count
-= thisrun_count
;
1388 /* free up resources */
1391 target_free_working_area(target
, source
);
1393 if (cfi_info
->write_algorithm
)
1395 target_free_working_area(target
, cfi_info
->write_algorithm
);
1396 cfi_info
->write_algorithm
= NULL
;
1399 destroy_reg_param(®_params
[0]);
1400 destroy_reg_param(®_params
[1]);
1401 destroy_reg_param(®_params
[2]);
1402 destroy_reg_param(®_params
[3]);
1403 destroy_reg_param(®_params
[4]);
1404 destroy_reg_param(®_params
[5]);
1405 destroy_reg_param(®_params
[6]);
1410 static int cfi_spansion_write_block(struct flash_bank
*bank
, uint8_t *buffer
, uint32_t address
, uint32_t count
)
1412 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1413 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
1414 struct target
*target
= bank
->target
;
1415 struct reg_param reg_params
[10];
1416 struct arm_algorithm armv4_5_info
;
1417 struct working_area
*source
;
1418 uint32_t buffer_size
= 32768;
1420 int retval
= ERROR_OK
;
1422 /* input parameters - */
1423 /* R0 = source address */
1424 /* R1 = destination address */
1425 /* R2 = number of writes */
1426 /* R3 = flash write command */
1427 /* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
1428 /* output parameters - */
1429 /* R5 = 0x80 ok 0x00 bad */
1430 /* temp registers - */
1431 /* R6 = value read from flash to test status */
1432 /* R7 = holding register */
1433 /* unlock registers - */
1434 /* R8 = unlock1_addr */
1435 /* R9 = unlock1_cmd */
1436 /* R10 = unlock2_addr */
1437 /* R11 = unlock2_cmd */
1439 static const uint32_t word_32_code
[] = {
1440 /* 00008100 <sp_32_code>: */
1441 0xe4905004, /* ldr r5, [r0], #4 */
1442 0xe5889000, /* str r9, [r8] */
1443 0xe58ab000, /* str r11, [r10] */
1444 0xe5883000, /* str r3, [r8] */
1445 0xe5815000, /* str r5, [r1] */
1446 0xe1a00000, /* nop */
1448 /* 00008110 <sp_32_busy>: */
1449 0xe5916000, /* ldr r6, [r1] */
1450 0xe0257006, /* eor r7, r5, r6 */
1451 0xe0147007, /* ands r7, r4, r7 */
1452 0x0a000007, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1453 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1454 0x0afffff9, /* beq 8110 <sp_32_busy> ; b if DQ5 low */
1455 0xe5916000, /* ldr r6, [r1] */
1456 0xe0257006, /* eor r7, r5, r6 */
1457 0xe0147007, /* ands r7, r4, r7 */
1458 0x0a000001, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1459 0xe3a05000, /* mov r5, #0 ; 0x0 - return 0x00, error */
1460 0x1a000004, /* bne 8154 <sp_32_done> */
1462 /* 00008140 <sp_32_cont>: */
1463 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1464 0x03a05080, /* moveq r5, #128 ; 0x80 */
1465 0x0a000001, /* beq 8154 <sp_32_done> */
1466 0xe2811004, /* add r1, r1, #4 ; 0x4 */
1467 0xeaffffe8, /* b 8100 <sp_32_code> */
1469 /* 00008154 <sp_32_done>: */
1470 0xeafffffe /* b 8154 <sp_32_done> */
1473 static const uint32_t word_16_code
[] = {
1474 /* 00008158 <sp_16_code>: */
1475 0xe0d050b2, /* ldrh r5, [r0], #2 */
1476 0xe1c890b0, /* strh r9, [r8] */
1477 0xe1cab0b0, /* strh r11, [r10] */
1478 0xe1c830b0, /* strh r3, [r8] */
1479 0xe1c150b0, /* strh r5, [r1] */
1480 0xe1a00000, /* nop (mov r0,r0) */
1482 /* 00008168 <sp_16_busy>: */
1483 0xe1d160b0, /* ldrh r6, [r1] */
1484 0xe0257006, /* eor r7, r5, r6 */
1485 0xe0147007, /* ands r7, r4, r7 */
1486 0x0a000007, /* beq 8198 <sp_16_cont> */
1487 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1488 0x0afffff9, /* beq 8168 <sp_16_busy> */
1489 0xe1d160b0, /* ldrh r6, [r1] */
1490 0xe0257006, /* eor r7, r5, r6 */
1491 0xe0147007, /* ands r7, r4, r7 */
1492 0x0a000001, /* beq 8198 <sp_16_cont> */
1493 0xe3a05000, /* mov r5, #0 ; 0x0 */
1494 0x1a000004, /* bne 81ac <sp_16_done> */
1496 /* 00008198 <sp_16_cont>: */
1497 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1498 0x03a05080, /* moveq r5, #128 ; 0x80 */
1499 0x0a000001, /* beq 81ac <sp_16_done> */
1500 0xe2811002, /* add r1, r1, #2 ; 0x2 */
1501 0xeaffffe8, /* b 8158 <sp_16_code> */
1503 /* 000081ac <sp_16_done>: */
1504 0xeafffffe /* b 81ac <sp_16_done> */
1507 static const uint32_t word_16_code_dq7only
[] = {
1509 0xe0d050b2, /* ldrh r5, [r0], #2 */
1510 0xe1c890b0, /* strh r9, [r8] */
1511 0xe1cab0b0, /* strh r11, [r10] */
1512 0xe1c830b0, /* strh r3, [r8] */
1513 0xe1c150b0, /* strh r5, [r1] */
1514 0xe1a00000, /* nop (mov r0,r0) */
1517 0xe1d160b0, /* ldrh r6, [r1] */
1518 0xe0257006, /* eor r7, r5, r6 */
1519 0xe2177080, /* ands r7, #0x80 */
1520 0x1afffffb, /* bne 8168 <sp_16_busy> */
1522 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1523 0x03a05080, /* moveq r5, #128 ; 0x80 */
1524 0x0a000001, /* beq 81ac <sp_16_done> */
1525 0xe2811002, /* add r1, r1, #2 ; 0x2 */
1526 0xeafffff0, /* b 8158 <sp_16_code> */
1528 /* 000081ac <sp_16_done>: */
1529 0xeafffffe /* b 81ac <sp_16_done> */
1532 static const uint32_t word_8_code
[] = {
1533 /* 000081b0 <sp_16_code_end>: */
1534 0xe4d05001, /* ldrb r5, [r0], #1 */
1535 0xe5c89000, /* strb r9, [r8] */
1536 0xe5cab000, /* strb r11, [r10] */
1537 0xe5c83000, /* strb r3, [r8] */
1538 0xe5c15000, /* strb r5, [r1] */
1539 0xe1a00000, /* nop (mov r0,r0) */
1541 /* 000081c0 <sp_8_busy>: */
1542 0xe5d16000, /* ldrb r6, [r1] */
1543 0xe0257006, /* eor r7, r5, r6 */
1544 0xe0147007, /* ands r7, r4, r7 */
1545 0x0a000007, /* beq 81f0 <sp_8_cont> */
1546 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1547 0x0afffff9, /* beq 81c0 <sp_8_busy> */
1548 0xe5d16000, /* ldrb r6, [r1] */
1549 0xe0257006, /* eor r7, r5, r6 */
1550 0xe0147007, /* ands r7, r4, r7 */
1551 0x0a000001, /* beq 81f0 <sp_8_cont> */
1552 0xe3a05000, /* mov r5, #0 ; 0x0 */
1553 0x1a000004, /* bne 8204 <sp_8_done> */
1555 /* 000081f0 <sp_8_cont>: */
1556 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1557 0x03a05080, /* moveq r5, #128 ; 0x80 */
1558 0x0a000001, /* beq 8204 <sp_8_done> */
1559 0xe2811001, /* add r1, r1, #1 ; 0x1 */
1560 0xeaffffe8, /* b 81b0 <sp_16_code_end> */
1562 /* 00008204 <sp_8_done>: */
1563 0xeafffffe /* b 8204 <sp_8_done> */
1566 armv4_5_info
.common_magic
= ARM_COMMON_MAGIC
;
1567 armv4_5_info
.core_mode
= ARM_MODE_SVC
;
1568 armv4_5_info
.core_state
= ARM_STATE_ARM
;
1570 int target_code_size
;
1571 const uint32_t *target_code_src
;
1573 switch (bank
->bus_width
)
1576 target_code_src
= word_8_code
;
1577 target_code_size
= sizeof(word_8_code
);
1580 /* Check for DQ5 support */
1581 if( cfi_info
->status_poll_mask
& (1 << 5) )
1583 target_code_src
= word_16_code
;
1584 target_code_size
= sizeof(word_16_code
);
1588 /* No DQ5 support. Use DQ7 DATA# polling only. */
1589 target_code_src
= word_16_code_dq7only
;
1590 target_code_size
= sizeof(word_16_code_dq7only
);
1594 target_code_src
= word_32_code
;
1595 target_code_size
= sizeof(word_32_code
);
1598 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank
->bus_width
);
1599 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1602 /* flash write code */
1603 if (!cfi_info
->write_algorithm
)
1605 uint8_t *target_code
;
1607 /* convert bus-width dependent algorithm code to correct endiannes */
1608 target_code
= malloc(target_code_size
);
1609 if (target_code
== NULL
)
1611 LOG_ERROR("Out of memory");
1614 cfi_fix_code_endian(target
, target_code
, target_code_src
, target_code_size
/ 4);
1616 /* allocate working area */
1617 retval
= target_alloc_working_area(target
, target_code_size
,
1618 &cfi_info
->write_algorithm
);
1619 if (retval
!= ERROR_OK
)
1625 /* write algorithm code to working area */
1626 if ((retval
= target_write_buffer(target
, cfi_info
->write_algorithm
->address
,
1627 target_code_size
, target_code
)) != ERROR_OK
)
1635 /* the following code still assumes target code is fixed 24*4 bytes */
1637 while (target_alloc_working_area_try(target
, buffer_size
, &source
) != ERROR_OK
)
1640 if (buffer_size
<= 256)
1642 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
1643 if (cfi_info
->write_algorithm
)
1644 target_free_working_area(target
, cfi_info
->write_algorithm
);
1646 LOG_WARNING("not enough working area available, can't do block memory writes");
1647 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1651 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
1652 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
1653 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
1654 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
);
1655 init_reg_param(®_params
[4], "r4", 32, PARAM_OUT
);
1656 init_reg_param(®_params
[5], "r5", 32, PARAM_IN
);
1657 init_reg_param(®_params
[6], "r8", 32, PARAM_OUT
);
1658 init_reg_param(®_params
[7], "r9", 32, PARAM_OUT
);
1659 init_reg_param(®_params
[8], "r10", 32, PARAM_OUT
);
1660 init_reg_param(®_params
[9], "r11", 32, PARAM_OUT
);
1664 uint32_t thisrun_count
= (count
> buffer_size
) ? buffer_size
: count
;
1666 retval
= target_write_buffer(target
, source
->address
, thisrun_count
, buffer
);
1667 if (retval
!= ERROR_OK
)
1672 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
1673 buf_set_u32(reg_params
[1].value
, 0, 32, address
);
1674 buf_set_u32(reg_params
[2].value
, 0, 32, thisrun_count
/ bank
->bus_width
);
1675 buf_set_u32(reg_params
[3].value
, 0, 32, cfi_command_val(bank
, 0xA0));
1676 buf_set_u32(reg_params
[4].value
, 0, 32, cfi_command_val(bank
, 0x80));
1677 buf_set_u32(reg_params
[6].value
, 0, 32, flash_address(bank
, 0, pri_ext
->_unlock1
));
1678 buf_set_u32(reg_params
[7].value
, 0, 32, 0xaaaaaaaa);
1679 buf_set_u32(reg_params
[8].value
, 0, 32, flash_address(bank
, 0, pri_ext
->_unlock2
));
1680 buf_set_u32(reg_params
[9].value
, 0, 32, 0x55555555);
1682 retval
= target_run_algorithm(target
, 0, NULL
, 10, reg_params
,
1683 cfi_info
->write_algorithm
->address
,
1684 cfi_info
->write_algorithm
->address
+ ((target_code_size
) - 4),
1685 10000, &armv4_5_info
);
1686 if (retval
!= ERROR_OK
)
1691 status
= buf_get_u32(reg_params
[5].value
, 0, 32);
1694 LOG_ERROR("flash write block failed status: 0x%" PRIx32
, status
);
1695 retval
= ERROR_FLASH_OPERATION_FAILED
;
1699 buffer
+= thisrun_count
;
1700 address
+= thisrun_count
;
1701 count
-= thisrun_count
;
1704 target_free_all_working_areas(target
);
1706 destroy_reg_param(®_params
[0]);
1707 destroy_reg_param(®_params
[1]);
1708 destroy_reg_param(®_params
[2]);
1709 destroy_reg_param(®_params
[3]);
1710 destroy_reg_param(®_params
[4]);
1711 destroy_reg_param(®_params
[5]);
1712 destroy_reg_param(®_params
[6]);
1713 destroy_reg_param(®_params
[7]);
1714 destroy_reg_param(®_params
[8]);
1715 destroy_reg_param(®_params
[9]);
1720 static int cfi_intel_write_word(struct flash_bank
*bank
, uint8_t *word
, uint32_t address
)
1723 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1724 struct target
*target
= bank
->target
;
1726 cfi_intel_clear_status_register(bank
);
1727 if ((retval
= cfi_send_command(bank
, 0x40, address
)) != ERROR_OK
)
1732 if ((retval
= target_write_memory(target
, address
, bank
->bus_width
, 1, word
)) != ERROR_OK
)
1738 retval
= cfi_intel_wait_status_busy(bank
, 1000 * (1 << cfi_info
->word_write_timeout_max
), &status
);
1741 if ((retval
= cfi_send_command(bank
, 0xff, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
1746 LOG_ERROR("couldn't write word at base 0x%" PRIx32
", address %" PRIx32
, bank
->base
, address
);
1747 return ERROR_FLASH_OPERATION_FAILED
;
1753 static int cfi_intel_write_words(struct flash_bank
*bank
, uint8_t *word
, uint32_t wordcount
, uint32_t address
)
1756 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1757 struct target
*target
= bank
->target
;
1759 /* Calculate buffer size and boundary mask */
1760 /* buffersize is (buffer size per chip) * (number of chips) */
1761 /* bufferwsize is buffersize in words */
1762 uint32_t buffersize
= (1UL << cfi_info
->max_buf_write_size
) * (bank
->bus_width
/ bank
->chip_width
);
1763 uint32_t buffermask
= buffersize
-1;
1764 uint32_t bufferwsize
= buffersize
/ bank
->bus_width
;
1766 /* Check for valid range */
1767 if (address
& buffermask
)
1769 LOG_ERROR("Write address at base 0x%" PRIx32
", address %" PRIx32
" not aligned to 2^%d boundary",
1770 bank
->base
, address
, cfi_info
->max_buf_write_size
);
1771 return ERROR_FLASH_OPERATION_FAILED
;
1774 /* Check for valid size */
1775 if (wordcount
> bufferwsize
)
1777 LOG_ERROR("Number of data words %" PRId32
" exceeds available buffersize %" PRId32
, wordcount
, buffersize
);
1778 return ERROR_FLASH_OPERATION_FAILED
;
1781 /* Write to flash buffer */
1782 cfi_intel_clear_status_register(bank
);
1784 /* Initiate buffer operation _*/
1785 if ((retval
= cfi_send_command(bank
, 0xe8, address
)) != ERROR_OK
)
1790 retval
= cfi_intel_wait_status_busy(bank
, 1000 * (1 << cfi_info
->buf_write_timeout_max
), &status
);
1791 if (retval
!= ERROR_OK
)
1795 if ((retval
= cfi_send_command(bank
, 0xff, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
1800 LOG_ERROR("couldn't start buffer write operation at base 0x%" PRIx32
", address %" PRIx32
, bank
->base
, address
);
1801 return ERROR_FLASH_OPERATION_FAILED
;
1804 /* Write buffer wordcount-1 and data words */
1805 if ((retval
= cfi_send_command(bank
, bufferwsize
-1, address
)) != ERROR_OK
)
1810 if ((retval
= target_write_memory(target
, address
, bank
->bus_width
, bufferwsize
, word
)) != ERROR_OK
)
1815 /* Commit write operation */
1816 if ((retval
= cfi_send_command(bank
, 0xd0, address
)) != ERROR_OK
)
1821 retval
= cfi_intel_wait_status_busy(bank
, 1000 * (1 << cfi_info
->buf_write_timeout_max
), &status
);
1822 if (retval
!= ERROR_OK
)
1827 if ((retval
= cfi_send_command(bank
, 0xff, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
1832 LOG_ERROR("Buffer write at base 0x%" PRIx32
", address %" PRIx32
" failed.", bank
->base
, address
);
1833 return ERROR_FLASH_OPERATION_FAILED
;
1839 static int cfi_spansion_write_word(struct flash_bank
*bank
, uint8_t *word
, uint32_t address
)
1842 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1843 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
1844 struct target
*target
= bank
->target
;
1846 if ((retval
= cfi_send_command(bank
, 0xaa, flash_address(bank
, 0, pri_ext
->_unlock1
))) != ERROR_OK
)
1851 if ((retval
= cfi_send_command(bank
, 0x55, flash_address(bank
, 0, pri_ext
->_unlock2
))) != ERROR_OK
)
1856 if ((retval
= cfi_send_command(bank
, 0xa0, flash_address(bank
, 0, pri_ext
->_unlock1
))) != ERROR_OK
)
1861 if ((retval
= target_write_memory(target
, address
, bank
->bus_width
, 1, word
)) != ERROR_OK
)
1866 if (cfi_spansion_wait_status_busy(bank
, 1000 * (1 << cfi_info
->word_write_timeout_max
)) != ERROR_OK
)
1868 if ((retval
= cfi_send_command(bank
, 0xf0, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
1873 LOG_ERROR("couldn't write word at base 0x%" PRIx32
", address %" PRIx32
, bank
->base
, address
);
1874 return ERROR_FLASH_OPERATION_FAILED
;
1880 static int cfi_spansion_write_words(struct flash_bank
*bank
, uint8_t *word
, uint32_t wordcount
, uint32_t address
)
1883 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1884 struct target
*target
= bank
->target
;
1885 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
1887 /* Calculate buffer size and boundary mask */
1888 /* buffersize is (buffer size per chip) * (number of chips) */
1889 /* bufferwsize is buffersize in words */
1890 uint32_t buffersize
= (1UL << cfi_info
->max_buf_write_size
) * (bank
->bus_width
/ bank
->chip_width
);
1891 uint32_t buffermask
= buffersize
-1;
1892 uint32_t bufferwsize
= buffersize
/ bank
->bus_width
;
1894 /* Check for valid range */
1895 if (address
& buffermask
)
1897 LOG_ERROR("Write address at base 0x%" PRIx32
", address %" PRIx32
" not aligned to 2^%d boundary", bank
->base
, address
, cfi_info
->max_buf_write_size
);
1898 return ERROR_FLASH_OPERATION_FAILED
;
1901 /* Check for valid size */
1902 if (wordcount
> bufferwsize
)
1904 LOG_ERROR("Number of data words %" PRId32
" exceeds available buffersize %" PRId32
, wordcount
, buffersize
);
1905 return ERROR_FLASH_OPERATION_FAILED
;
1909 if ((retval
= cfi_send_command(bank
, 0xaa, flash_address(bank
, 0, pri_ext
->_unlock1
))) != ERROR_OK
)
1914 if ((retval
= cfi_send_command(bank
, 0x55, flash_address(bank
, 0, pri_ext
->_unlock2
))) != ERROR_OK
)
1919 // Buffer load command
1920 if ((retval
= cfi_send_command(bank
, 0x25, address
)) != ERROR_OK
)
1925 /* Write buffer wordcount-1 and data words */
1926 if ((retval
= cfi_send_command(bank
, bufferwsize
-1, address
)) != ERROR_OK
)
1931 if ((retval
= target_write_memory(target
, address
, bank
->bus_width
, bufferwsize
, word
)) != ERROR_OK
)
1936 /* Commit write operation */
1937 if ((retval
= cfi_send_command(bank
, 0x29, address
)) != ERROR_OK
)
1942 if (cfi_spansion_wait_status_busy(bank
, 1000 * (1 << cfi_info
->word_write_timeout_max
)) != ERROR_OK
)
1944 if ((retval
= cfi_send_command(bank
, 0xf0, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
1949 LOG_ERROR("couldn't write block at base 0x%" PRIx32
", address %" PRIx32
", size %" PRIx32
, bank
->base
, address
, bufferwsize
);
1950 return ERROR_FLASH_OPERATION_FAILED
;
1956 static int cfi_write_word(struct flash_bank
*bank
, uint8_t *word
, uint32_t address
)
1958 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1960 switch (cfi_info
->pri_id
)
1964 return cfi_intel_write_word(bank
, word
, address
);
1967 return cfi_spansion_write_word(bank
, word
, address
);
1970 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
1974 return ERROR_FLASH_OPERATION_FAILED
;
1977 static int cfi_write_words(struct flash_bank
*bank
, uint8_t *word
, uint32_t wordcount
, uint32_t address
)
1979 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1981 switch (cfi_info
->pri_id
)
1985 return cfi_intel_write_words(bank
, word
, wordcount
, address
);
1988 return cfi_spansion_write_words(bank
, word
, wordcount
, address
);
1991 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
1995 return ERROR_FLASH_OPERATION_FAILED
;
1998 static int cfi_read(struct flash_bank
*bank
, uint8_t *buffer
, uint32_t offset
, uint32_t count
)
2000 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2001 struct target
*target
= bank
->target
;
2002 uint32_t address
= bank
->base
+ offset
;
2004 int align
; /* number of unaligned bytes */
2005 uint8_t current_word
[CFI_MAX_BUS_WIDTH
];
2009 LOG_DEBUG("reading buffer of %i byte at 0x%8.8x",
2010 (int)count
, (unsigned)offset
);
2012 if (bank
->target
->state
!= TARGET_HALTED
)
2014 LOG_ERROR("Target not halted");
2015 return ERROR_TARGET_NOT_HALTED
;
2018 if (offset
+ count
> bank
->size
)
2019 return ERROR_FLASH_DST_OUT_OF_BANK
;
2021 if (cfi_info
->qry
[0] != 'Q')
2022 return ERROR_FLASH_BANK_NOT_PROBED
;
2024 /* start at the first byte of the first word (bus_width size) */
2025 read_p
= address
& ~(bank
->bus_width
- 1);
2026 if ((align
= address
- read_p
) != 0)
2028 LOG_INFO("Fixup %d unaligned read head bytes", align
);
2030 /* read a complete word from flash */
2031 if ((retval
= target_read_memory(target
, read_p
, bank
->bus_width
, 1, current_word
)) != ERROR_OK
)
2034 /* take only bytes we need */
2035 for (i
= align
; (i
< bank
->bus_width
) && (count
> 0); i
++, count
--)
2036 *buffer
++ = current_word
[i
];
2038 read_p
+= bank
->bus_width
;
2041 align
= count
/ bank
->bus_width
;
2044 if ((retval
= target_read_memory(target
, read_p
, bank
->bus_width
, align
, buffer
)) != ERROR_OK
)
2047 read_p
+= align
* bank
->bus_width
;
2048 buffer
+= align
* bank
->bus_width
;
2049 count
-= align
* bank
->bus_width
;
2054 LOG_INFO("Fixup %d unaligned read tail bytes", count
);
2056 /* read a complete word from flash */
2057 if ((retval
= target_read_memory(target
, read_p
, bank
->bus_width
, 1, current_word
)) != ERROR_OK
)
2060 /* take only bytes we need */
2061 for (i
= 0; (i
< bank
->bus_width
) && (count
> 0); i
++, count
--)
2062 *buffer
++ = current_word
[i
];
2068 static int cfi_write(struct flash_bank
*bank
, uint8_t *buffer
, uint32_t offset
, uint32_t count
)
2070 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2071 struct target
*target
= bank
->target
;
2072 uint32_t address
= bank
->base
+ offset
; /* address of first byte to be programmed */
2074 int align
; /* number of unaligned bytes */
2075 int blk_count
; /* number of bus_width bytes for block copy */
2076 uint8_t current_word
[CFI_MAX_BUS_WIDTH
* 4]; /* word (bus_width size) currently being programmed */
2080 if (bank
->target
->state
!= TARGET_HALTED
)
2082 LOG_ERROR("Target not halted");
2083 return ERROR_TARGET_NOT_HALTED
;
2086 if (offset
+ count
> bank
->size
)
2087 return ERROR_FLASH_DST_OUT_OF_BANK
;
2089 if (cfi_info
->qry
[0] != 'Q')
2090 return ERROR_FLASH_BANK_NOT_PROBED
;
2092 /* start at the first byte of the first word (bus_width size) */
2093 write_p
= address
& ~(bank
->bus_width
- 1);
2094 if ((align
= address
- write_p
) != 0)
2096 LOG_INFO("Fixup %d unaligned head bytes", align
);
2098 /* read a complete word from flash */
2099 if ((retval
= target_read_memory(target
, write_p
, bank
->bus_width
, 1, current_word
)) != ERROR_OK
)
2102 /* replace only bytes that must be written */
2103 for (i
= align
; (i
< bank
->bus_width
) && (count
> 0); i
++, count
--)
2104 current_word
[i
] = *buffer
++;
2106 retval
= cfi_write_word(bank
, current_word
, write_p
);
2107 if (retval
!= ERROR_OK
)
2109 write_p
+= bank
->bus_width
;
2112 /* handle blocks of bus_size aligned bytes */
2113 blk_count
= count
& ~(bank
->bus_width
- 1); /* round down, leave tail bytes */
2114 switch (cfi_info
->pri_id
)
2116 /* try block writes (fails without working area) */
2119 retval
= cfi_intel_write_block(bank
, buffer
, write_p
, blk_count
);
2122 retval
= cfi_spansion_write_block(bank
, buffer
, write_p
, blk_count
);
2125 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2126 retval
= ERROR_FLASH_OPERATION_FAILED
;
2129 if (retval
== ERROR_OK
)
2131 /* Increment pointers and decrease count on succesful block write */
2132 buffer
+= blk_count
;
2133 write_p
+= blk_count
;
2138 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
)
2140 /* Calculate buffer size and boundary mask */
2141 /* buffersize is (buffer size per chip) * (number of chips) */
2142 /* bufferwsize is buffersize in words */
2143 uint32_t buffersize
= (1UL << cfi_info
->max_buf_write_size
) * (bank
->bus_width
/ bank
->chip_width
);
2144 uint32_t buffermask
= buffersize
-1;
2145 uint32_t bufferwsize
= buffersize
/ bank
->bus_width
;
2147 /* fall back to memory writes */
2148 while (count
>= (uint32_t)bank
->bus_width
)
2151 if ((write_p
& 0xff) == 0)
2153 LOG_INFO("Programming at %08" PRIx32
", count %08" PRIx32
" bytes remaining", write_p
, count
);
2156 if ((bufferwsize
> 0) && (count
>= buffersize
) && !(write_p
& buffermask
))
2158 retval
= cfi_write_words(bank
, buffer
, bufferwsize
, write_p
);
2159 if (retval
== ERROR_OK
)
2161 buffer
+= buffersize
;
2162 write_p
+= buffersize
;
2163 count
-= buffersize
;
2167 /* try the slow way? */
2170 for (i
= 0; i
< bank
->bus_width
; i
++)
2171 current_word
[i
] = *buffer
++;
2173 retval
= cfi_write_word(bank
, current_word
, write_p
);
2174 if (retval
!= ERROR_OK
)
2177 write_p
+= bank
->bus_width
;
2178 count
-= bank
->bus_width
;
2186 /* return to read array mode, so we can read from flash again for padding */
2187 if ((retval
= cfi_reset(bank
)) != ERROR_OK
)
2192 /* handle unaligned tail bytes */
2195 LOG_INFO("Fixup %" PRId32
" unaligned tail bytes", count
);
2197 /* read a complete word from flash */
2198 if ((retval
= target_read_memory(target
, write_p
, bank
->bus_width
, 1, current_word
)) != ERROR_OK
)
2201 /* replace only bytes that must be written */
2202 for (i
= 0; (i
< bank
->bus_width
) && (count
> 0); i
++, count
--)
2203 current_word
[i
] = *buffer
++;
2205 retval
= cfi_write_word(bank
, current_word
, write_p
);
2206 if (retval
!= ERROR_OK
)
2210 /* return to read array mode */
2211 return cfi_reset(bank
);
2214 static void cfi_fixup_atmel_reversed_erase_regions(struct flash_bank
*bank
, void *param
)
2217 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2218 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
2220 pri_ext
->_reversed_geometry
= 1;
2223 static void cfi_fixup_0002_erase_regions(struct flash_bank
*bank
, void *param
)
2226 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2227 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
2230 if ((pri_ext
->_reversed_geometry
) || (pri_ext
->TopBottom
== 3))
2232 LOG_DEBUG("swapping reversed erase region information on cmdset 0002 device");
2234 for (i
= 0; i
< cfi_info
->num_erase_regions
/ 2; i
++)
2236 int j
= (cfi_info
->num_erase_regions
- 1) - i
;
2239 swap
= cfi_info
->erase_region_info
[i
];
2240 cfi_info
->erase_region_info
[i
] = cfi_info
->erase_region_info
[j
];
2241 cfi_info
->erase_region_info
[j
] = swap
;
2246 static void cfi_fixup_0002_unlock_addresses(struct flash_bank
*bank
, void *param
)
2248 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2249 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
2250 struct cfi_unlock_addresses
*unlock_addresses
= param
;
2252 pri_ext
->_unlock1
= unlock_addresses
->unlock1
;
2253 pri_ext
->_unlock2
= unlock_addresses
->unlock2
;
2257 static int cfi_query_string(struct flash_bank
*bank
, int address
)
2259 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2262 if ((retval
= cfi_send_command(bank
, 0x98, flash_address(bank
, 0, address
))) != ERROR_OK
)
2267 retval
= cfi_query_u8(bank
, 0, 0x10, &cfi_info
->qry
[0]);
2268 if (retval
!= ERROR_OK
)
2270 retval
= cfi_query_u8(bank
, 0, 0x11, &cfi_info
->qry
[1]);
2271 if (retval
!= ERROR_OK
)
2273 retval
= cfi_query_u8(bank
, 0, 0x12, &cfi_info
->qry
[2]);
2274 if (retval
!= ERROR_OK
)
2277 LOG_DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info
->qry
[0], cfi_info
->qry
[1], cfi_info
->qry
[2]);
2279 if ((cfi_info
->qry
[0] != 'Q') || (cfi_info
->qry
[1] != 'R') || (cfi_info
->qry
[2] != 'Y'))
2281 if ((retval
= cfi_reset(bank
)) != ERROR_OK
)
2285 LOG_ERROR("Could not probe bank: no QRY");
2286 return ERROR_FLASH_BANK_INVALID
;
2292 static int cfi_probe(struct flash_bank
*bank
)
2294 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2295 struct target
*target
= bank
->target
;
2296 int num_sectors
= 0;
2299 uint32_t unlock1
= 0x555;
2300 uint32_t unlock2
= 0x2aa;
2302 uint8_t value_buf0
[CFI_MAX_BUS_WIDTH
], value_buf1
[CFI_MAX_BUS_WIDTH
];
2304 if (bank
->target
->state
!= TARGET_HALTED
)
2306 LOG_ERROR("Target not halted");
2307 return ERROR_TARGET_NOT_HALTED
;
2310 cfi_info
->probed
= 0;
2313 free(bank
->sectors
);
2314 bank
->sectors
= NULL
;
2316 if(cfi_info
->erase_region_info
)
2318 free(cfi_info
->erase_region_info
);
2319 cfi_info
->erase_region_info
= NULL
;
2322 /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
2323 * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
2325 if (cfi_info
->jedec_probe
)
2331 /* switch to read identifier codes mode ("AUTOSELECT") */
2332 if ((retval
= cfi_send_command(bank
, 0xaa, flash_address(bank
, 0, unlock1
))) != ERROR_OK
)
2336 if ((retval
= cfi_send_command(bank
, 0x55, flash_address(bank
, 0, unlock2
))) != ERROR_OK
)
2340 if ((retval
= cfi_send_command(bank
, 0x90, flash_address(bank
, 0, unlock1
))) != ERROR_OK
)
2345 if ((retval
= target_read_memory(target
, flash_address(bank
, 0, 0x00), bank
->bus_width
, 1, value_buf0
)) != ERROR_OK
)
2349 if ((retval
= target_read_memory(target
, flash_address(bank
, 0, 0x01), bank
->bus_width
, 1, value_buf1
)) != ERROR_OK
)
2353 switch (bank
->chip_width
) {
2355 cfi_info
->manufacturer
= *value_buf0
;
2356 cfi_info
->device_id
= *value_buf1
;
2359 cfi_info
->manufacturer
= target_buffer_get_u16(target
, value_buf0
);
2360 cfi_info
->device_id
= target_buffer_get_u16(target
, value_buf1
);
2363 cfi_info
->manufacturer
= target_buffer_get_u32(target
, value_buf0
);
2364 cfi_info
->device_id
= target_buffer_get_u32(target
, value_buf1
);
2367 LOG_ERROR("Unsupported bank chipwidth %d, can't probe memory", bank
->chip_width
);
2368 return ERROR_FLASH_OPERATION_FAILED
;
2371 LOG_INFO("Flash Manufacturer/Device: 0x%04x 0x%04x", cfi_info
->manufacturer
, cfi_info
->device_id
);
2372 /* switch back to read array mode */
2373 if ((retval
= cfi_reset(bank
)) != ERROR_OK
)
2378 /* check device/manufacturer ID for known non-CFI flashes. */
2379 cfi_fixup_non_cfi(bank
);
2381 /* query only if this is a CFI compatible flash,
2382 * otherwise the relevant info has already been filled in
2384 if (cfi_info
->not_cfi
== 0)
2386 /* enter CFI query mode
2387 * according to JEDEC Standard No. 68.01,
2388 * a single bus sequence with address = 0x55, data = 0x98 should put
2389 * the device into CFI query mode.
2391 * SST flashes clearly violate this, and we will consider them incompatbile for now
2394 retval
= cfi_query_string(bank
, 0x55);
2395 if (retval
!= ERROR_OK
)
2398 * Spansion S29WS-N CFI query fix is to try 0x555 if 0x55 fails. Should
2399 * be harmless enough:
2401 * http://www.infradead.org/pipermail/linux-mtd/2005-September/013618.html
2403 LOG_USER("Try workaround w/0x555 instead of 0x55 to get QRY.");
2404 retval
= cfi_query_string(bank
, 0x555);
2406 if (retval
!= ERROR_OK
)
2409 retval
= cfi_query_u16(bank
, 0, 0x13, &cfi_info
->pri_id
);
2410 if (retval
!= ERROR_OK
)
2412 retval
= cfi_query_u16(bank
, 0, 0x15, &cfi_info
->pri_addr
);
2413 if (retval
!= ERROR_OK
)
2415 retval
= cfi_query_u16(bank
, 0, 0x17, &cfi_info
->alt_id
);
2416 if (retval
!= ERROR_OK
)
2418 retval
= cfi_query_u16(bank
, 0, 0x19, &cfi_info
->alt_addr
);
2419 if (retval
!= ERROR_OK
)
2422 LOG_DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", cfi_info
->qry
[0], cfi_info
->qry
[1], cfi_info
->qry
[2], cfi_info
->pri_id
, cfi_info
->pri_addr
, cfi_info
->alt_id
, cfi_info
->alt_addr
);
2424 retval
= cfi_query_u8(bank
, 0, 0x1b, &cfi_info
->vcc_min
);
2425 if (retval
!= ERROR_OK
)
2427 retval
= cfi_query_u8(bank
, 0, 0x1c, &cfi_info
->vcc_max
);
2428 if (retval
!= ERROR_OK
)
2430 retval
= cfi_query_u8(bank
, 0, 0x1d, &cfi_info
->vpp_min
);
2431 if (retval
!= ERROR_OK
)
2433 retval
= cfi_query_u8(bank
, 0, 0x1e, &cfi_info
->vpp_max
);
2434 if (retval
!= ERROR_OK
)
2436 retval
= cfi_query_u8(bank
, 0, 0x1f, &cfi_info
->word_write_timeout_typ
);
2437 if (retval
!= ERROR_OK
)
2439 retval
= cfi_query_u8(bank
, 0, 0x20, &cfi_info
->buf_write_timeout_typ
);
2440 if (retval
!= ERROR_OK
)
2442 retval
= cfi_query_u8(bank
, 0, 0x21, &cfi_info
->block_erase_timeout_typ
);
2443 if (retval
!= ERROR_OK
)
2445 retval
= cfi_query_u8(bank
, 0, 0x22, &cfi_info
->chip_erase_timeout_typ
);
2446 if (retval
!= ERROR_OK
)
2448 retval
= cfi_query_u8(bank
, 0, 0x23, &cfi_info
->word_write_timeout_max
);
2449 if (retval
!= ERROR_OK
)
2451 retval
= cfi_query_u8(bank
, 0, 0x24, &cfi_info
->buf_write_timeout_max
);
2452 if (retval
!= ERROR_OK
)
2454 retval
= cfi_query_u8(bank
, 0, 0x25, &cfi_info
->block_erase_timeout_max
);
2455 if (retval
!= ERROR_OK
)
2457 retval
= cfi_query_u8(bank
, 0, 0x26, &cfi_info
->chip_erase_timeout_max
);
2458 if (retval
!= ERROR_OK
)
2461 LOG_DEBUG("Vcc min: %x.%x, Vcc max: %x.%x, Vpp min: %u.%x, Vpp max: %u.%x",
2462 (cfi_info
->vcc_min
& 0xf0) >> 4, cfi_info
->vcc_min
& 0x0f,
2463 (cfi_info
->vcc_max
& 0xf0) >> 4, cfi_info
->vcc_max
& 0x0f,
2464 (cfi_info
->vpp_min
& 0xf0) >> 4, cfi_info
->vpp_min
& 0x0f,
2465 (cfi_info
->vpp_max
& 0xf0) >> 4, cfi_info
->vpp_max
& 0x0f);
2466 LOG_DEBUG("typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u", 1 << cfi_info
->word_write_timeout_typ
, 1 << cfi_info
->buf_write_timeout_typ
,
2467 1 << cfi_info
->block_erase_timeout_typ
, 1 << cfi_info
->chip_erase_timeout_typ
);
2468 LOG_DEBUG("max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u", (1 << cfi_info
->word_write_timeout_max
) * (1 << cfi_info
->word_write_timeout_typ
),
2469 (1 << cfi_info
->buf_write_timeout_max
) * (1 << cfi_info
->buf_write_timeout_typ
),
2470 (1 << cfi_info
->block_erase_timeout_max
) * (1 << cfi_info
->block_erase_timeout_typ
),
2471 (1 << cfi_info
->chip_erase_timeout_max
) * (1 << cfi_info
->chip_erase_timeout_typ
));
2474 retval
= cfi_query_u8(bank
, 0, 0x27, &data
);
2475 if (retval
!= ERROR_OK
)
2477 cfi_info
->dev_size
= 1 << data
;
2479 retval
= cfi_query_u16(bank
, 0, 0x28, &cfi_info
->interface_desc
);
2480 if (retval
!= ERROR_OK
)
2482 retval
= cfi_query_u16(bank
, 0, 0x2a, &cfi_info
->max_buf_write_size
);
2483 if (retval
!= ERROR_OK
)
2485 retval
= cfi_query_u8(bank
, 0, 0x2c, &cfi_info
->num_erase_regions
);
2486 if (retval
!= ERROR_OK
)
2489 LOG_DEBUG("size: 0x%" PRIx32
", interface desc: %i, max buffer write size: %x", cfi_info
->dev_size
, cfi_info
->interface_desc
, (1 << cfi_info
->max_buf_write_size
));
2491 if (cfi_info
->num_erase_regions
)
2493 cfi_info
->erase_region_info
= malloc(4 * cfi_info
->num_erase_regions
);
2494 for (i
= 0; i
< cfi_info
->num_erase_regions
; i
++)
2496 retval
= cfi_query_u32(bank
, 0, 0x2d + (4 * i
), &cfi_info
->erase_region_info
[i
]);
2497 if (retval
!= ERROR_OK
)
2499 LOG_DEBUG("erase region[%i]: %" PRIu32
" blocks of size 0x%" PRIx32
"",
2501 (cfi_info
->erase_region_info
[i
] & 0xffff) + 1,
2502 (cfi_info
->erase_region_info
[i
] >> 16) * 256);
2507 cfi_info
->erase_region_info
= NULL
;
2510 /* We need to read the primary algorithm extended query table before calculating
2511 * the sector layout to be able to apply fixups
2513 switch (cfi_info
->pri_id
)
2515 /* Intel command set (standard and extended) */
2518 cfi_read_intel_pri_ext(bank
);
2520 /* AMD/Spansion, Atmel, ... command set */
2522 cfi_info
->status_poll_mask
= CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7
; /* default for all CFI flashs */
2523 cfi_read_0002_pri_ext(bank
);
2526 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2530 /* return to read array mode
2531 * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
2533 if ((retval
= cfi_reset(bank
)) != ERROR_OK
)
2537 } /* end CFI case */
2539 /* apply fixups depending on the primary command set */
2540 switch (cfi_info
->pri_id
)
2542 /* Intel command set (standard and extended) */
2545 cfi_fixup(bank
, cfi_0001_fixups
);
2547 /* AMD/Spansion, Atmel, ... command set */
2549 cfi_fixup(bank
, cfi_0002_fixups
);
2552 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2556 if ((cfi_info
->dev_size
* bank
->bus_width
/ bank
->chip_width
) != bank
->size
)
2558 LOG_WARNING("configuration specifies 0x%" PRIx32
" size, but a 0x%" PRIx32
" size flash was found", bank
->size
, cfi_info
->dev_size
);
2561 if (cfi_info
->num_erase_regions
== 0)
2563 /* a device might have only one erase block, spanning the whole device */
2564 bank
->num_sectors
= 1;
2565 bank
->sectors
= malloc(sizeof(struct flash_sector
));
2567 bank
->sectors
[sector
].offset
= 0x0;
2568 bank
->sectors
[sector
].size
= bank
->size
;
2569 bank
->sectors
[sector
].is_erased
= -1;
2570 bank
->sectors
[sector
].is_protected
= -1;
2574 uint32_t offset
= 0;
2576 for (i
= 0; i
< cfi_info
->num_erase_regions
; i
++)
2578 num_sectors
+= (cfi_info
->erase_region_info
[i
] & 0xffff) + 1;
2581 bank
->num_sectors
= num_sectors
;
2582 bank
->sectors
= malloc(sizeof(struct flash_sector
) * num_sectors
);
2584 for (i
= 0; i
< cfi_info
->num_erase_regions
; i
++)
2587 for (j
= 0; j
< (cfi_info
->erase_region_info
[i
] & 0xffff) + 1; j
++)
2589 bank
->sectors
[sector
].offset
= offset
;
2590 bank
->sectors
[sector
].size
= ((cfi_info
->erase_region_info
[i
] >> 16) * 256) * bank
->bus_width
/ bank
->chip_width
;
2591 offset
+= bank
->sectors
[sector
].size
;
2592 bank
->sectors
[sector
].is_erased
= -1;
2593 bank
->sectors
[sector
].is_protected
= -1;
2597 if (offset
!= (cfi_info
->dev_size
* bank
->bus_width
/ bank
->chip_width
))
2599 LOG_WARNING("CFI size is 0x%" PRIx32
", but total sector size is 0x%" PRIx32
"", \
2600 (cfi_info
->dev_size
* bank
->bus_width
/ bank
->chip_width
), offset
);
2604 cfi_info
->probed
= 1;
2609 static int cfi_auto_probe(struct flash_bank
*bank
)
2611 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2612 if (cfi_info
->probed
)
2614 return cfi_probe(bank
);
2617 static int cfi_intel_protect_check(struct flash_bank
*bank
)
2620 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2621 struct cfi_intel_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
2624 /* check if block lock bits are supported on this device */
2625 if (!(pri_ext
->blk_status_reg_mask
& 0x1))
2626 return ERROR_FLASH_OPERATION_FAILED
;
2628 if ((retval
= cfi_send_command(bank
, 0x90, flash_address(bank
, 0, 0x55))) != ERROR_OK
)
2633 for (i
= 0; i
< bank
->num_sectors
; i
++)
2635 uint8_t block_status
;
2636 retval
= cfi_get_u8(bank
, i
, 0x2, &block_status
);
2637 if (retval
!= ERROR_OK
)
2640 if (block_status
& 1)
2641 bank
->sectors
[i
].is_protected
= 1;
2643 bank
->sectors
[i
].is_protected
= 0;
2646 return cfi_send_command(bank
, 0xff, flash_address(bank
, 0, 0x0));
2649 static int cfi_spansion_protect_check(struct flash_bank
*bank
)
2652 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2653 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
2656 if ((retval
= cfi_send_command(bank
, 0xaa, flash_address(bank
, 0, pri_ext
->_unlock1
))) != ERROR_OK
)
2661 if ((retval
= cfi_send_command(bank
, 0x55, flash_address(bank
, 0, pri_ext
->_unlock2
))) != ERROR_OK
)
2666 if ((retval
= cfi_send_command(bank
, 0x90, flash_address(bank
, 0, pri_ext
->_unlock1
))) != ERROR_OK
)
2671 for (i
= 0; i
< bank
->num_sectors
; i
++)
2673 uint8_t block_status
;
2674 retval
= cfi_get_u8(bank
, i
, 0x2, &block_status
);
2675 if (retval
!= ERROR_OK
)
2678 if (block_status
& 1)
2679 bank
->sectors
[i
].is_protected
= 1;
2681 bank
->sectors
[i
].is_protected
= 0;
2684 return cfi_send_command(bank
, 0xf0, flash_address(bank
, 0, 0x0));
2687 static int cfi_protect_check(struct flash_bank
*bank
)
2689 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2691 if (bank
->target
->state
!= TARGET_HALTED
)
2693 LOG_ERROR("Target not halted");
2694 return ERROR_TARGET_NOT_HALTED
;
2697 if (cfi_info
->qry
[0] != 'Q')
2698 return ERROR_FLASH_BANK_NOT_PROBED
;
2700 switch (cfi_info
->pri_id
)
2704 return cfi_intel_protect_check(bank
);
2707 return cfi_spansion_protect_check(bank
);
2710 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2717 static int get_cfi_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
2720 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2722 if (cfi_info
->qry
[0] == 0xff)
2724 printed
= snprintf(buf
, buf_size
, "\ncfi flash bank not probed yet\n");
2728 if (cfi_info
->not_cfi
== 0)
2729 printed
= snprintf(buf
, buf_size
, "\ncfi information:\n");
2731 printed
= snprintf(buf
, buf_size
, "\nnon-cfi flash:\n");
2733 buf_size
-= printed
;
2735 printed
= snprintf(buf
, buf_size
, "\nmfr: 0x%4.4x, id:0x%4.4x\n",
2736 cfi_info
->manufacturer
, cfi_info
->device_id
);
2738 buf_size
-= printed
;
2740 if (cfi_info
->not_cfi
== 0)
2742 printed
= snprintf(buf
, buf_size
, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n", cfi_info
->qry
[0], cfi_info
->qry
[1], cfi_info
->qry
[2], cfi_info
->pri_id
, cfi_info
->pri_addr
, cfi_info
->alt_id
, cfi_info
->alt_addr
);
2744 buf_size
-= printed
;
2746 printed
= snprintf(buf
, buf_size
, "Vcc min: %x.%x, Vcc max: %x.%x, Vpp min: %u.%x, Vpp max: %u.%x\n",
2747 (cfi_info
->vcc_min
& 0xf0) >> 4, cfi_info
->vcc_min
& 0x0f,
2748 (cfi_info
->vcc_max
& 0xf0) >> 4, cfi_info
->vcc_max
& 0x0f,
2749 (cfi_info
->vpp_min
& 0xf0) >> 4, cfi_info
->vpp_min
& 0x0f,
2750 (cfi_info
->vpp_max
& 0xf0) >> 4, cfi_info
->vpp_max
& 0x0f);
2752 buf_size
-= printed
;
2754 printed
= snprintf(buf
, buf_size
, "typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u\n",
2755 1 << cfi_info
->word_write_timeout_typ
,
2756 1 << cfi_info
->buf_write_timeout_typ
,
2757 1 << cfi_info
->block_erase_timeout_typ
,
2758 1 << cfi_info
->chip_erase_timeout_typ
);
2760 buf_size
-= printed
;
2762 printed
= snprintf(buf
, buf_size
, "max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u\n",
2763 (1 << cfi_info
->word_write_timeout_max
) * (1 << cfi_info
->word_write_timeout_typ
),
2764 (1 << cfi_info
->buf_write_timeout_max
) * (1 << cfi_info
->buf_write_timeout_typ
),
2765 (1 << cfi_info
->block_erase_timeout_max
) * (1 << cfi_info
->block_erase_timeout_typ
),
2766 (1 << cfi_info
->chip_erase_timeout_max
) * (1 << cfi_info
->chip_erase_timeout_typ
));
2768 buf_size
-= printed
;
2770 printed
= snprintf(buf
, buf_size
, "size: 0x%" PRIx32
", interface desc: %i, max buffer write size: %x\n",
2772 cfi_info
->interface_desc
,
2773 1 << cfi_info
->max_buf_write_size
);
2775 buf_size
-= printed
;
2777 switch (cfi_info
->pri_id
)
2781 cfi_intel_info(bank
, buf
, buf_size
);
2784 cfi_spansion_info(bank
, buf
, buf_size
);
2787 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2795 struct flash_driver cfi_flash
= {
2797 .flash_bank_command
= cfi_flash_bank_command
,
2799 .protect
= cfi_protect
,
2803 .auto_probe
= cfi_auto_probe
,
2804 /* FIXME: access flash at bus_width size */
2805 .erase_check
= default_flash_blank_check
,
2806 .protect_check
= cfi_protect_check
,
2807 .info
= get_cfi_info
,
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