1 /***************************************************************************
2 * Copyright (C) 2013 by Andrey Yurovsky *
3 * Andrey Yurovsky <yurovsky@gmail.com> *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
17 ***************************************************************************/
25 #include <target/cortex_m.h>
27 /* At this time, the SAM4L Flash is available in these capacities:
28 * ATSAM4Lx4xx: 256KB (512 pages)
29 * ATSAM4Lx2xx: 128KB (256 pages)
30 * ATSAM4Lx8xx: 512KB (1024 pages)
33 /* There are 16 lockable regions regardless of overall capacity. The number
34 * of pages per sector is therefore dependant on capacity. */
35 #define SAM4L_NUM_SECTORS 16
37 /* Locations in memory map */
38 #define SAM4L_FLASH ((uint32_t)0x00000000) /* Flash region */
39 #define SAM4L_FLASH_USER 0x00800000 /* Flash user page region */
40 #define SAM4L_FLASHCALW 0x400A0000 /* Flash controller */
41 #define SAM4L_CHIPID 0x400E0740 /* Chip Identification */
43 /* Offsets from SAM4L_FLASHCALW */
44 #define SAM4L_FCR 0x00 /* Flash Control Register (RW) */
45 #define SAM4L_FCMD 0x04 /* Flash Command Register (RW) */
46 #define SAM4L_FSR 0x08 /* Flash Status Register (RO) */
47 #define SAM4L_FPR 0x0C /* Flash Parameter Register (RO) */
48 #define SAM4L_FVR 0x10 /* Flash Version Register (RO) */
49 #define SAM4L_FGPFRHI 0x14 /* Flash General Purpose Register High (RO) */
50 #define SAM4L_FGPFRLO 0x18 /* Flash General Purpose Register Low (RO) */
52 /* Offsets from SAM4L_CHIPID */
53 #define SAM4L_CIDR 0x00 /* Chip ID Register (RO) */
54 #define SAM4L_EXID 0x04 /* Chip ID Extension Register (RO) */
56 /* Flash commands (for SAM4L_FCMD), see Table 14-5 */
57 #define SAM4L_FCMD_NOP 0 /* No Operation */
58 #define SAM4L_FCMD_WP 1 /* Write Page */
59 #define SAM4L_FCMD_EP 2 /* Erase Page */
60 #define SAM4L_FCMD_CPB 3 /* Clear Page Buffer */
61 #define SAM4L_FCMD_LP 4 /* Lock region containing given page */
62 #define SAM4L_FCMD_UP 5 /* Unlock region containing given page */
63 #define SAM4L_FCMD_EA 6 /* Erase All */
64 #define SAM4L_FCMD_WGPB 7 /* Write general-purpose fuse bit */
65 #define SAM4L_FCMD_EGPB 8 /* Erase general-purpose fuse bit */
66 #define SAM4L_FCMD_SSB 9 /* Set security fuses */
67 #define SAM4L_FCMD_PGPFB 10 /* Program general-purpose fuse byte */
68 #define SAM4L_FCMD_EAGPF 11 /* Erase all general-purpose fuse bits */
69 #define SAM4L_FCMD_QPR 12 /* Quick page read */
70 #define SAM4L_FCMD_WUP 13 /* Write user page */
71 #define SAM4L_FCMD_EUP 14 /* Erase user page */
72 #define SAM4L_FCMD_QPRUP 15 /* Quick page read (user page) */
73 #define SAM4L_FCMD_HSEN 16 /* High speed mode enable */
74 #define SAM4L_FCMD_HSDIS 17 /* High speed mode disable */
76 #define SAM4L_FMCD_CMDKEY 0xA5UL /* 'key' to issue commands, see 14.10.2 */
79 /* SMAP registers and bits */
80 #define SMAP_BASE 0x400A3000
82 #define SMAP_SCR (SMAP_BASE + 8)
83 #define SMAP_SCR_HCR (1 << 1)
86 struct sam4l_chip_info
{
92 /* These are taken from Table 9-1 in 42023E-SAM-07/2013 */
93 static const struct sam4l_chip_info sam4l_known_chips
[] = {
94 { 0xAB0B0AE0, 0x1400000F, "ATSAM4LC8C" },
95 { 0xAB0A09E0, 0x0400000F, "ATSAM4LC4C" },
96 { 0xAB0A07E0, 0x0400000F, "ATSAM4LC2C" },
97 { 0xAB0B0AE0, 0x1300000F, "ATSAM4LC8B" },
98 { 0xAB0A09E0, 0x0300000F, "ATSAM4LC4B" },
99 { 0xAB0A07E0, 0x0300000F, "ATSAM4LC2B" },
100 { 0xAB0B0AE0, 0x1200000F, "ATSAM4LC8A" },
101 { 0xAB0A09E0, 0x0200000F, "ATSAM4LC4A" },
102 { 0xAB0A07E0, 0x0200000F, "ATSAM4LC2A" },
103 { 0xAB0B0AE0, 0x14000002, "ATSAM4LS8C" },
104 { 0xAB0A09E0, 0x04000002, "ATSAM4LS4C" },
105 { 0xAB0A07E0, 0x04000002, "ATSAM4LS2C" },
106 { 0xAB0B0AE0, 0x13000002, "ATSAM4LS8B" },
107 { 0xAB0A09E0, 0x03000002, "ATSAM4LS4B" },
108 { 0xAB0A07E0, 0x03000002, "ATSAM4LS2B" },
109 { 0xAB0B0AE0, 0x12000002, "ATSAM4LS8A" },
110 { 0xAB0A09E0, 0x02000002, "ATSAM4LS4A" },
111 { 0xAB0A07E0, 0x02000002, "ATSAM4LS2A" },
114 /* Meaning of SRAMSIZ field in CHIPID, see 9.3.1 in 42023E-SAM-07/2013 */
115 static const uint16_t sam4l_ram_sizes
[16] = { 48, 1, 2, 6, 24, 4, 80, 160, 8, 16, 32, 64, 128, 256, 96, 512 };
117 /* Meaning of PSZ field in FPR, see 14.10.4 in 42023E-SAM-07/2013 */
118 static const uint16_t sam4l_page_sizes
[8] = { 32, 64, 128, 256, 512, 1024, 2048, 4096 };
121 const struct sam4l_chip_info
*details
;
128 unsigned int pages_per_sector
;
131 struct target
*target
;
135 static int sam4l_flash_wait_until_ready(struct target
*target
)
137 volatile unsigned int t
= 0;
141 /* Poll the status register until the FRDY bit is set */
143 res
= target_read_u32(target
, SAM4L_FLASHCALW
+ SAM4L_FSR
, &st
);
144 } while (res
== ERROR_OK
&& !(st
& (1<<0)) && ++t
< 10);
149 static int sam4l_flash_check_error(struct target
*target
, uint32_t *err
)
154 res
= target_read_u32(target
, SAM4L_FLASHCALW
+ SAM4L_FSR
, &st
);
157 *err
= st
& ((1<<3) | (1<<2)); /* grab PROGE and LOCKE bits */
162 static int sam4l_flash_command(struct target
*target
, uint8_t cmd
, int page
)
168 res
= sam4l_flash_wait_until_ready(target
);
173 /* Set the page number. For some commands, the page number is just an
174 * argument (ex: fuse bit number). */
175 fcmd
= (SAM4L_FMCD_CMDKEY
<< 24) | ((page
& 0xFFFF) << 8) | (cmd
& 0x3F);
177 /* Reuse the page number that was read from the flash command register. */
178 res
= target_read_u32(target
, SAM4L_FLASHCALW
+ SAM4L_FCMD
, &fcmd
);
182 fcmd
&= ~0x3F; /* clear out the command code */
183 fcmd
|= (SAM4L_FMCD_CMDKEY
<< 24) | (cmd
& 0x3F);
186 /* Send the command */
187 res
= target_write_u32(target
, SAM4L_FLASHCALW
+ SAM4L_FCMD
, fcmd
);
191 res
= sam4l_flash_check_error(target
, &err
);
196 LOG_ERROR("%s got error status 0x%08" PRIx32
, __func__
, err
);
198 res
= sam4l_flash_wait_until_ready(target
);
203 FLASH_BANK_COMMAND_HANDLER(sam4l_flash_bank_command
)
205 if (bank
->base
!= SAM4L_FLASH
) {
206 LOG_ERROR("Address " TARGET_ADDR_FMT
207 " invalid bank address (try 0x%08" PRIx32
208 "[at91sam4l series] )",
209 bank
->base
, SAM4L_FLASH
);
213 struct sam4l_info
*chip
;
214 chip
= calloc(1, sizeof(*chip
));
216 LOG_ERROR("No memory for flash bank chip info");
220 chip
->target
= bank
->target
;
221 chip
->probed
= false;
223 bank
->driver_priv
= chip
;
228 static const struct sam4l_chip_info
*sam4l_find_chip_name(uint32_t id
, uint32_t exid
)
234 for (i
= 0; i
< ARRAY_SIZE(sam4l_known_chips
); i
++) {
235 if (sam4l_known_chips
[i
].id
== id
&& sam4l_known_chips
[i
].exid
== exid
)
236 return &sam4l_known_chips
[i
];
242 static int sam4l_check_page_erased(struct flash_bank
*bank
, uint32_t pn
,
248 /* Issue a quick page read to verify that we've erased this page */
249 res
= sam4l_flash_command(bank
->target
, SAM4L_FCMD_QPR
, pn
);
250 if (res
!= ERROR_OK
) {
251 LOG_ERROR("Quick page read %" PRIu32
" failed", pn
);
255 /* Retrieve the flash status */
256 res
= target_read_u32(bank
->target
, SAM4L_FLASHCALW
+ SAM4L_FSR
, &st
);
257 if (res
!= ERROR_OK
) {
258 LOG_ERROR("Couldn't read erase status");
262 /* Is the page in question really erased? */
263 *is_erased_p
= !!(st
& (1<<5));
268 static int sam4l_probe(struct flash_bank
*bank
)
270 uint32_t id
, exid
, param
;
272 struct sam4l_info
*chip
= (struct sam4l_info
*)bank
->driver_priv
;
277 res
= target_read_u32(bank
->target
, SAM4L_CHIPID
+ SAM4L_CIDR
, &id
);
278 if (res
!= ERROR_OK
) {
279 LOG_ERROR("Couldn't read chip ID");
283 res
= target_read_u32(bank
->target
, SAM4L_CHIPID
+ SAM4L_EXID
, &exid
);
284 if (res
!= ERROR_OK
) {
285 LOG_ERROR("Couldn't read extended chip ID");
289 chip
->details
= sam4l_find_chip_name(id
, exid
);
291 /* The RAM capacity is in a lookup table. */
292 chip
->ram_kb
= sam4l_ram_sizes
[0xF & (id
>> 16)];
294 switch (0xF & (id
>> 8)) {
296 chip
->flash_kb
= 128;
299 chip
->flash_kb
= 256;
302 chip
->flash_kb
= 512;
305 LOG_ERROR("Unknown flash size (chip ID is %08" PRIx32
"), assuming 128K", id
);
306 chip
->flash_kb
= 128;
310 /* Retrieve the Flash parameters */
311 res
= target_read_u32(bank
->target
, SAM4L_FLASHCALW
+ SAM4L_FPR
, ¶m
);
312 if (res
!= ERROR_OK
) {
313 LOG_ERROR("Couldn't read Flash parameters");
317 /* Fetch the page size from the parameter register. Technically the flash
318 * capacity is there too though the manual mentions that not all parts will
319 * have it set so we use the Chip ID capacity information instead. */
320 chip
->page_size
= sam4l_page_sizes
[0x7 & (param
>> 8)];
321 assert(chip
->page_size
);
322 chip
->num_pages
= chip
->flash_kb
* 1024 / chip
->page_size
;
324 chip
->sector_size
= (chip
->flash_kb
* 1024) / SAM4L_NUM_SECTORS
;
325 chip
->pages_per_sector
= chip
->sector_size
/ chip
->page_size
;
327 /* Make sure the bank size is correct */
328 bank
->size
= chip
->flash_kb
* 1024;
330 /* Allocate the sector table. */
331 bank
->num_sectors
= SAM4L_NUM_SECTORS
;
332 bank
->sectors
= calloc(bank
->num_sectors
, (sizeof((bank
->sectors
)[0])));
336 /* Fill out the sector information: all SAM4L sectors are the same size and
337 * there is always a fixed number of them. */
338 for (unsigned int i
= 0; i
< bank
->num_sectors
; i
++) {
339 bank
->sectors
[i
].size
= chip
->sector_size
;
340 bank
->sectors
[i
].offset
= i
* chip
->sector_size
;
341 /* mark as unknown */
342 bank
->sectors
[i
].is_erased
= -1;
343 bank
->sectors
[i
].is_protected
= -1;
349 LOG_INFO("SAM4L MCU: %s (Rev %c) (%" PRIu32
"KB Flash with %d %" PRIu32
"B pages, %" PRIu32
"KB RAM)",
350 chip
->details
? chip
->details
->name
: "unknown", (char)('A' + (id
& 0xF)),
351 chip
->flash_kb
, chip
->num_pages
, chip
->page_size
, chip
->ram_kb
);
356 static int sam4l_protect_check(struct flash_bank
*bank
)
360 struct sam4l_info
*chip
= (struct sam4l_info
*)bank
->driver_priv
;
362 if (bank
->target
->state
!= TARGET_HALTED
) {
363 LOG_ERROR("Target not halted");
365 return ERROR_TARGET_NOT_HALTED
;
369 if (sam4l_probe(bank
) != ERROR_OK
)
370 return ERROR_FLASH_BANK_NOT_PROBED
;
373 res
= target_read_u32(bank
->target
, SAM4L_FLASHCALW
+ SAM4L_FSR
, &st
);
377 st
>>= 16; /* There are 16 lock region bits in the upper half word */
378 for (unsigned int i
= 0; i
< bank
->num_sectors
; i
++)
379 bank
->sectors
[i
].is_protected
= !!(st
& (1<<i
));
384 static int sam4l_protect(struct flash_bank
*bank
, int set
, unsigned int first
,
387 struct sam4l_info
*chip
= (struct sam4l_info
*)bank
->driver_priv
;
389 if (bank
->target
->state
!= TARGET_HALTED
) {
390 LOG_ERROR("Target not halted");
392 return ERROR_TARGET_NOT_HALTED
;
396 if (sam4l_probe(bank
) != ERROR_OK
)
397 return ERROR_FLASH_BANK_NOT_PROBED
;
400 /* Make sure the pages make sense. */
401 if (first
>= bank
->num_sectors
|| last
>= bank
->num_sectors
) {
402 LOG_ERROR("Protect range %u - %u not valid (%u sectors total)", first
, last
,
407 /* Try to lock or unlock each sector in the range. This is done by locking
408 * a region containing one page in that sector, we arbitrarily choose the 0th
409 * page in the sector. */
410 for (unsigned int i
= first
; i
<= last
; i
++) {
413 res
= sam4l_flash_command(bank
->target
,
414 set
? SAM4L_FCMD_LP
: SAM4L_FCMD_UP
, i
* chip
->pages_per_sector
);
415 if (res
!= ERROR_OK
) {
416 LOG_ERROR("Can't %slock region containing page %d", set
? "" : "un", i
);
424 static int sam4l_erase(struct flash_bank
*bank
, unsigned int first
,
428 struct sam4l_info
*chip
= (struct sam4l_info
*)bank
->driver_priv
;
430 if (bank
->target
->state
!= TARGET_HALTED
) {
431 LOG_ERROR("Target not halted");
433 return ERROR_TARGET_NOT_HALTED
;
437 if (sam4l_probe(bank
) != ERROR_OK
)
438 return ERROR_FLASH_BANK_NOT_PROBED
;
441 /* Make sure the pages make sense. */
442 if (first
>= bank
->num_sectors
|| last
>= bank
->num_sectors
) {
443 LOG_ERROR("Erase range %u - %u not valid (%u sectors total)", first
, last
,
449 if ((first
== 0) && ((last
+ 1) == bank
->num_sectors
)) {
450 LOG_DEBUG("Erasing the whole chip");
452 ret
= sam4l_flash_command(bank
->target
, SAM4L_FCMD_EA
, -1);
453 if (ret
!= ERROR_OK
) {
454 LOG_ERROR("Erase All failed");
458 LOG_DEBUG("Erasing sectors %u through %u...\n", first
, last
);
460 /* For each sector... */
461 for (unsigned int i
= first
; i
<= last
; i
++) {
462 /* For each page in that sector... */
463 for (unsigned int j
= 0; j
< chip
->pages_per_sector
; j
++) {
464 unsigned int pn
= i
* chip
->pages_per_sector
+ j
;
465 bool is_erased
= false;
467 /* Issue the page erase */
468 ret
= sam4l_flash_command(bank
->target
, SAM4L_FCMD_EP
, pn
);
469 if (ret
!= ERROR_OK
) {
470 LOG_ERROR("Erasing page %u failed", pn
);
474 ret
= sam4l_check_page_erased(bank
, pn
, &is_erased
);
479 LOG_DEBUG("Page %u was not erased.", pn
);
489 /* Write an entire page from host buffer 'buf' to page-aligned 'address' in the
491 static int sam4l_write_page(struct sam4l_info
*chip
, struct target
*target
,
492 uint32_t address
, const uint8_t *buf
)
496 LOG_DEBUG("sam4l_write_page address=%08" PRIx32
, address
);
498 /* Clear the page buffer before we write to it */
499 res
= sam4l_flash_command(target
, SAM4L_FCMD_CPB
, -1);
500 if (res
!= ERROR_OK
) {
501 LOG_ERROR("%s: can't clear page buffer", __func__
);
505 /* Write the modified page back to the target's page buffer */
506 res
= target_write_memory(target
, address
, 4, chip
->page_size
/ 4, buf
);
508 if (res
!= ERROR_OK
) {
509 LOG_ERROR("%s: %d", __func__
, __LINE__
);
513 /* Commit the page contents to Flash: erase the current page and then
515 res
= sam4l_flash_command(target
, SAM4L_FCMD_EP
, -1);
518 res
= sam4l_flash_command(target
, SAM4L_FCMD_WP
, -1);
523 /* Write partial contents into page-aligned 'address' on the Flash from host
524 * buffer 'buf' by writing 'nb' of 'buf' at 'offset' into the Flash page. */
525 static int sam4l_write_page_partial(struct sam4l_info
*chip
,
526 struct flash_bank
*bank
, uint32_t address
, const uint8_t *buf
,
527 uint32_t page_offset
, uint32_t nb
)
530 uint8_t *pg
= malloc(chip
->page_size
);
534 LOG_DEBUG("sam4l_write_page_partial address=%08" PRIx32
" nb=%08" PRIx32
, address
, nb
);
536 assert(page_offset
+ nb
< chip
->page_size
);
537 assert((address
% chip
->page_size
) == 0);
539 /* Retrieve the full page contents from Flash */
540 res
= target_read_memory(bank
->target
, address
, 4,
541 chip
->page_size
/ 4, pg
);
542 if (res
!= ERROR_OK
) {
547 /* Insert our partial page over the data from Flash */
548 memcpy(pg
+ (page_offset
% chip
->page_size
), buf
, nb
);
550 /* Write the page back out */
551 res
= sam4l_write_page(chip
, bank
->target
, address
, pg
);
557 static int sam4l_write(struct flash_bank
*bank
, const uint8_t *buffer
,
558 uint32_t offset
, uint32_t count
)
562 struct sam4l_info
*chip
= (struct sam4l_info
*)bank
->driver_priv
;
564 LOG_DEBUG("sam4l_write offset=%08" PRIx32
" count=%08" PRIx32
, offset
, count
);
566 if (bank
->target
->state
!= TARGET_HALTED
) {
567 LOG_ERROR("Target not halted");
569 return ERROR_TARGET_NOT_HALTED
;
573 if (sam4l_probe(bank
) != ERROR_OK
)
574 return ERROR_FLASH_BANK_NOT_PROBED
;
577 if (offset
% chip
->page_size
) {
578 /* We're starting at an unaligned offset so we'll write a partial page
579 * comprising that offset and up to the end of that page. */
580 nb
= chip
->page_size
- (offset
% chip
->page_size
);
583 } else if (count
< chip
->page_size
) {
584 /* We're writing an aligned but partial page. */
589 res
= sam4l_write_page_partial(chip
, bank
,
590 (offset
/ chip
->page_size
) * chip
->page_size
+ bank
->base
,
592 offset
% chip
->page_size
, nb
);
596 /* We're done with the page contents */
601 /* There's at least one aligned page to write out. */
602 if (count
>= chip
->page_size
) {
603 assert(chip
->page_size
> 0);
604 int np
= count
/ chip
->page_size
+ ((count
% chip
->page_size
) ? 1 : 0);
606 for (int i
= 0; i
< np
; i
++) {
607 if (count
>= chip
->page_size
) {
608 res
= sam4l_write_page(chip
, bank
->target
,
610 buffer
+ (i
* chip
->page_size
));
611 /* Advance one page */
612 offset
+= chip
->page_size
;
613 count
-= chip
->page_size
;
615 res
= sam4l_write_page_partial(chip
, bank
,
617 buffer
+ (i
* chip
->page_size
), 0, count
);
618 /* We're done after this. */
632 COMMAND_HANDLER(sam4l_handle_reset_deassert
)
634 struct target
*target
= get_current_target(CMD_CTX
);
635 int retval
= ERROR_OK
;
636 enum reset_types jtag_reset_config
= jtag_get_reset_config();
638 /* If the target has been unresponsive before, try to re-establish
639 * communication now - CPU is held in reset by DSU, DAP is working */
640 if (!target_was_examined(target
))
641 target_examine_one(target
);
644 /* In case of sysresetreq, debug retains state set in cortex_m_assert_reset()
645 * so we just release reset held by SMAP
647 * n_RESET (srst) clears the DP, so reenable debug and set vector catch here
649 * After vectreset SMAP release is not needed however makes no harm
651 if (target
->reset_halt
&& (jtag_reset_config
& RESET_HAS_SRST
)) {
652 retval
= target_write_u32(target
, DCB_DHCSR
, DBGKEY
| C_HALT
| C_DEBUGEN
);
653 if (retval
== ERROR_OK
)
654 retval
= target_write_u32(target
, DCB_DEMCR
,
655 TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
656 /* do not return on error here, releasing SMAP reset is more important */
659 int retval2
= target_write_u32(target
, SMAP_SCR
, SMAP_SCR_HCR
);
660 if (retval2
!= ERROR_OK
)
666 static const struct command_registration at91sam4l_exec_command_handlers
[] = {
668 .name
= "smap_reset_deassert",
669 .handler
= sam4l_handle_reset_deassert
,
670 .mode
= COMMAND_EXEC
,
671 .help
= "deassert internal reset held by SMAP",
674 COMMAND_REGISTRATION_DONE
677 static const struct command_registration at91sam4l_command_handlers
[] = {
681 .help
= "at91sam4l flash command group",
683 .chain
= at91sam4l_exec_command_handlers
,
685 COMMAND_REGISTRATION_DONE
688 const struct flash_driver at91sam4l_flash
= {
690 .commands
= at91sam4l_command_handlers
,
691 .flash_bank_command
= sam4l_flash_bank_command
,
692 .erase
= sam4l_erase
,
693 .protect
= sam4l_protect
,
694 .write
= sam4l_write
,
695 .read
= default_flash_read
,
696 .probe
= sam4l_probe
,
697 .auto_probe
= sam4l_probe
,
698 .erase_check
= default_flash_blank_check
,
699 .protect_check
= sam4l_protect_check
,
700 .free_driver_priv
= default_flash_free_driver_priv
,
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