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Author: David Brownell <david-b@pacbell.net>
[openocd.git] / src / flash / nand.c
1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Partially based on drivers/mtd/nand_ids.c from Linux. *
6 * Copyright (C) 2002 Thomas Gleixner <tglx@linutronix.de> *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
23 #ifdef HAVE_CONFIG_H
24 #include "config.h"
25 #endif
26
27 #include "nand.h"
28 #include "time_support.h"
29 #include "fileio.h"
30
31 #include <inttypes.h>
32
33
34 static int handle_nand_list_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
35 static int handle_nand_probe_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
36 static int handle_nand_check_bad_blocks_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
37 static int handle_nand_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
38 static int handle_nand_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
39 static int handle_nand_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
40 static int handle_nand_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
41
42 static int handle_nand_raw_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
43
44 static int nand_read_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
45 //static int nand_read_plain(struct nand_device_s *device, u32 address, u8 *data, u32 data_size);
46
47 static int nand_write_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
48
49 /* NAND flash controller
50 */
51 extern nand_flash_controller_t lpc3180_nand_controller;
52 extern nand_flash_controller_t orion_nand_controller;
53 extern nand_flash_controller_t s3c2410_nand_controller;
54 extern nand_flash_controller_t s3c2412_nand_controller;
55 extern nand_flash_controller_t s3c2440_nand_controller;
56 extern nand_flash_controller_t s3c2443_nand_controller;
57
58 /* extern nand_flash_controller_t boundary_scan_nand_controller; */
59
60 static nand_flash_controller_t *nand_flash_controllers[] =
61 {
62 &lpc3180_nand_controller,
63 &orion_nand_controller,
64 &s3c2410_nand_controller,
65 &s3c2412_nand_controller,
66 &s3c2440_nand_controller,
67 &s3c2443_nand_controller,
68 /* &boundary_scan_nand_controller, */
69 NULL
70 };
71
72 /* configured NAND devices and NAND Flash command handler */
73 static nand_device_t *nand_devices = NULL;
74 static command_t *nand_cmd;
75
76 /* Chip ID list
77 *
78 * Name, ID code, pagesize, chipsize in MegaByte, eraseblock size,
79 * options
80 *
81 * Pagesize; 0, 256, 512
82 * 0 get this information from the extended chip ID
83 * 256 256 Byte page size
84 * 512 512 Byte page size
85 */
86 static nand_info_t nand_flash_ids[] =
87 {
88 /* start "museum" IDs */
89 {"NAND 1MiB 5V 8-bit", 0x6e, 256, 1, 0x1000, 0},
90 {"NAND 2MiB 5V 8-bit", 0x64, 256, 2, 0x1000, 0},
91 {"NAND 4MiB 5V 8-bit", 0x6b, 512, 4, 0x2000, 0},
92 {"NAND 1MiB 3,3V 8-bit", 0xe8, 256, 1, 0x1000, 0},
93 {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0},
94 {"NAND 2MiB 3,3V 8-bit", 0xea, 256, 2, 0x1000, 0},
95 {"NAND 4MiB 3,3V 8-bit", 0xd5, 512, 4, 0x2000, 0},
96 {"NAND 4MiB 3,3V 8-bit", 0xe3, 512, 4, 0x2000, 0},
97 {"NAND 4MiB 3,3V 8-bit", 0xe5, 512, 4, 0x2000, 0},
98 {"NAND 8MiB 3,3V 8-bit", 0xd6, 512, 8, 0x2000, 0},
99
100 {"NAND 8MiB 1,8V 8-bit", 0x39, 512, 8, 0x2000, 0},
101 {"NAND 8MiB 3,3V 8-bit", 0xe6, 512, 8, 0x2000, 0},
102 {"NAND 8MiB 1,8V 16-bit", 0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16},
103 {"NAND 8MiB 3,3V 16-bit", 0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16},
104 /* end "museum" IDs */
105
106 {"NAND 16MiB 1,8V 8-bit", 0x33, 512, 16, 0x4000, 0},
107 {"NAND 16MiB 3,3V 8-bit", 0x73, 512, 16, 0x4000, 0},
108 {"NAND 16MiB 1,8V 16-bit", 0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16},
109 {"NAND 16MiB 3,3V 16-bit", 0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16},
110
111 {"NAND 32MiB 1,8V 8-bit", 0x35, 512, 32, 0x4000, 0},
112 {"NAND 32MiB 3,3V 8-bit", 0x75, 512, 32, 0x4000, 0},
113 {"NAND 32MiB 1,8V 16-bit", 0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16},
114 {"NAND 32MiB 3,3V 16-bit", 0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16},
115
116 {"NAND 64MiB 1,8V 8-bit", 0x36, 512, 64, 0x4000, 0},
117 {"NAND 64MiB 3,3V 8-bit", 0x76, 512, 64, 0x4000, 0},
118 {"NAND 64MiB 1,8V 16-bit", 0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16},
119 {"NAND 64MiB 3,3V 16-bit", 0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16},
120
121 {"NAND 128MiB 1,8V 8-bit", 0x78, 512, 128, 0x4000, 0},
122 {"NAND 128MiB 1,8V 8-bit", 0x39, 512, 128, 0x4000, 0},
123 {"NAND 128MiB 3,3V 8-bit", 0x79, 512, 128, 0x4000, 0},
124 {"NAND 128MiB 1,8V 16-bit", 0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16},
125 {"NAND 128MiB 1,8V 16-bit", 0x49, 512, 128, 0x4000, NAND_BUSWIDTH_16},
126 {"NAND 128MiB 3,3V 16-bit", 0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16},
127 {"NAND 128MiB 3,3V 16-bit", 0x59, 512, 128, 0x4000, NAND_BUSWIDTH_16},
128
129 {"NAND 256MiB 3,3V 8-bit", 0x71, 512, 256, 0x4000, 0},
130
131 {"NAND 64MiB 1,8V 8-bit", 0xA2, 0, 64, 0, LP_OPTIONS},
132 {"NAND 64MiB 3,3V 8-bit", 0xF2, 0, 64, 0, LP_OPTIONS},
133 {"NAND 64MiB 1,8V 16-bit", 0xB2, 0, 64, 0, LP_OPTIONS16},
134 {"NAND 64MiB 3,3V 16-bit", 0xC2, 0, 64, 0, LP_OPTIONS16},
135
136 {"NAND 128MiB 1,8V 8-bit", 0xA1, 0, 128, 0, LP_OPTIONS},
137 {"NAND 128MiB 3,3V 8-bit", 0xF1, 0, 128, 0, LP_OPTIONS},
138 {"NAND 128MiB 1,8V 16-bit", 0xB1, 0, 128, 0, LP_OPTIONS16},
139 {"NAND 128MiB 3,3V 16-bit", 0xC1, 0, 128, 0, LP_OPTIONS16},
140
141 {"NAND 256MiB 1,8V 8-bit", 0xAA, 0, 256, 0, LP_OPTIONS},
142 {"NAND 256MiB 3,3V 8-bit", 0xDA, 0, 256, 0, LP_OPTIONS},
143 {"NAND 256MiB 1,8V 16-bit", 0xBA, 0, 256, 0, LP_OPTIONS16},
144 {"NAND 256MiB 3,3V 16-bit", 0xCA, 0, 256, 0, LP_OPTIONS16},
145
146 {"NAND 512MiB 1,8V 8-bit", 0xAC, 0, 512, 0, LP_OPTIONS},
147 {"NAND 512MiB 3,3V 8-bit", 0xDC, 0, 512, 0, LP_OPTIONS},
148 {"NAND 512MiB 1,8V 16-bit", 0xBC, 0, 512, 0, LP_OPTIONS16},
149 {"NAND 512MiB 3,3V 16-bit", 0xCC, 0, 512, 0, LP_OPTIONS16},
150
151 {"NAND 1GiB 1,8V 8-bit", 0xA3, 0, 1024, 0, LP_OPTIONS},
152 {"NAND 1GiB 3,3V 8-bit", 0xD3, 0, 1024, 0, LP_OPTIONS},
153 {"NAND 1GiB 1,8V 16-bit", 0xB3, 0, 1024, 0, LP_OPTIONS16},
154 {"NAND 1GiB 3,3V 16-bit", 0xC3, 0, 1024, 0, LP_OPTIONS16},
155
156 {"NAND 2GiB 1,8V 8-bit", 0xA5, 0, 2048, 0, LP_OPTIONS},
157 {"NAND 2GiB 3,3V 8-bit", 0xD5, 0, 2048, 0, LP_OPTIONS},
158 {"NAND 2GiB 1,8V 16-bit", 0xB5, 0, 2048, 0, LP_OPTIONS16},
159 {"NAND 2GiB 3,3V 16-bit", 0xC5, 0, 2048, 0, LP_OPTIONS16},
160
161 {NULL, 0, 0, 0, 0, 0 }
162 };
163
164 /* Manufacturer ID list
165 */
166 static nand_manufacturer_t nand_manuf_ids[] =
167 {
168 {0x0, "unknown"},
169 {NAND_MFR_TOSHIBA, "Toshiba"},
170 {NAND_MFR_SAMSUNG, "Samsung"},
171 {NAND_MFR_FUJITSU, "Fujitsu"},
172 {NAND_MFR_NATIONAL, "National"},
173 {NAND_MFR_RENESAS, "Renesas"},
174 {NAND_MFR_STMICRO, "ST Micro"},
175 {NAND_MFR_HYNIX, "Hynix"},
176 {NAND_MFR_MICRON, "Micron"},
177 {0x0, NULL},
178 };
179
180 /*
181 * Define default oob placement schemes for large and small page devices
182 */
183
184 #if 0
185 static nand_ecclayout_t nand_oob_8 = {
186 .eccbytes = 3,
187 .eccpos = {0, 1, 2},
188 .oobfree = {
189 {.offset = 3,
190 .length = 2},
191 {.offset = 6,
192 .length = 2}}
193 };
194 #endif
195
196 static nand_ecclayout_t nand_oob_16 = {
197 .eccbytes = 6,
198 .eccpos = {0, 1, 2, 3, 6, 7},
199 .oobfree = {
200 {.offset = 8,
201 . length = 8}}
202 };
203
204 static nand_ecclayout_t nand_oob_64 = {
205 .eccbytes = 24,
206 .eccpos = {
207 40, 41, 42, 43, 44, 45, 46, 47,
208 48, 49, 50, 51, 52, 53, 54, 55,
209 56, 57, 58, 59, 60, 61, 62, 63},
210 .oobfree = {
211 {.offset = 2,
212 .length = 38}}
213 };
214
215 /* nand device <nand_controller> [controller options]
216 */
217 static int handle_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
218 {
219 int i;
220 int retval;
221
222 if (argc < 1)
223 {
224 LOG_WARNING("incomplete flash device nand configuration");
225 return ERROR_FLASH_BANK_INVALID;
226 }
227
228 for (i = 0; nand_flash_controllers[i]; i++)
229 {
230 nand_device_t *p, *c;
231
232 if (strcmp(args[0], nand_flash_controllers[i]->name) == 0)
233 {
234 /* register flash specific commands */
235 if ((retval = nand_flash_controllers[i]->register_commands(cmd_ctx)) != ERROR_OK)
236 {
237 LOG_ERROR("couldn't register '%s' commands", args[0]);
238 return retval;
239 }
240
241 c = malloc(sizeof(nand_device_t));
242
243 c->controller = nand_flash_controllers[i];
244 c->controller_priv = NULL;
245 c->manufacturer = NULL;
246 c->device = NULL;
247 c->bus_width = 0;
248 c->address_cycles = 0;
249 c->page_size = 0;
250 c->use_raw = 0;
251 c->next = NULL;
252
253 if ((retval = nand_flash_controllers[i]->nand_device_command(cmd_ctx, cmd, args, argc, c)) != ERROR_OK)
254 {
255 LOG_ERROR("'%s' driver rejected nand flash", c->controller->name);
256 free(c);
257 return ERROR_OK;
258 }
259
260 /* put NAND device in linked list */
261 if (nand_devices)
262 {
263 /* find last flash device */
264 for (p = nand_devices; p && p->next; p = p->next);
265 if (p)
266 p->next = c;
267 }
268 else
269 {
270 nand_devices = c;
271 }
272
273 return ERROR_OK;
274 }
275 }
276
277 /* no valid NAND controller was found (i.e. the configuration option,
278 * didn't match one of the compiled-in controllers)
279 */
280 LOG_ERROR("No valid NAND flash controller found (%s)", args[0]);
281 LOG_ERROR("compiled-in NAND flash controllers:");
282 for (i = 0; nand_flash_controllers[i]; i++)
283 {
284 LOG_ERROR("%i: %s", i, nand_flash_controllers[i]->name);
285 }
286
287 return ERROR_OK;
288 }
289
290 int nand_register_commands(struct command_context_s *cmd_ctx)
291 {
292 nand_cmd = register_command(cmd_ctx, NULL, "nand", NULL, COMMAND_ANY, "NAND specific commands");
293
294 register_command(cmd_ctx, nand_cmd, "device", handle_nand_device_command, COMMAND_CONFIG, NULL);
295
296 return ERROR_OK;
297 }
298
299 int nand_init(struct command_context_s *cmd_ctx)
300 {
301 if (nand_devices)
302 {
303 register_command(cmd_ctx, nand_cmd, "list", handle_nand_list_command, COMMAND_EXEC,
304 "list configured NAND flash devices");
305 register_command(cmd_ctx, nand_cmd, "info", handle_nand_info_command, COMMAND_EXEC,
306 "print info about NAND flash device <num>");
307 register_command(cmd_ctx, nand_cmd, "probe", handle_nand_probe_command, COMMAND_EXEC,
308 "identify NAND flash device <num>");
309 register_command(cmd_ctx, nand_cmd, "check_bad_blocks", handle_nand_check_bad_blocks_command, COMMAND_EXEC,
310 "check NAND flash device <num> for bad blocks [<first> <last>]");
311 register_command(cmd_ctx, nand_cmd, "erase", handle_nand_erase_command, COMMAND_EXEC,
312 "erase blocks on NAND flash device <num> <first> <last>");
313 register_command(cmd_ctx, nand_cmd, "dump", handle_nand_dump_command, COMMAND_EXEC,
314 "dump from NAND flash device <num> <filename> "
315 "<offset> <size> [oob_raw|oob_only]");
316 register_command(cmd_ctx, nand_cmd, "write", handle_nand_write_command, COMMAND_EXEC,
317 "write to NAND flash device <num> <filename> <offset> [oob_raw|oob_only|oob_softecc|oob_softecc_kw]");
318 register_command(cmd_ctx, nand_cmd, "raw_access", handle_nand_raw_access_command, COMMAND_EXEC,
319 "raw access to NAND flash device <num> ['enable'|'disable']");
320 }
321
322 return ERROR_OK;
323 }
324
325 nand_device_t *get_nand_device_by_num(int num)
326 {
327 nand_device_t *p;
328 int i = 0;
329
330 for (p = nand_devices; p; p = p->next)
331 {
332 if (i++ == num)
333 {
334 return p;
335 }
336 }
337
338 return NULL;
339 }
340
341 static int nand_build_bbt(struct nand_device_s *device, int first, int last)
342 {
343 u32 page = 0x0;
344 int i;
345 u8 oob[6];
346
347 if ((first < 0) || (first >= device->num_blocks))
348 first = 0;
349
350 if ((last >= device->num_blocks) || (last == -1))
351 last = device->num_blocks - 1;
352
353 for (i = first; i < last; i++)
354 {
355 nand_read_page(device, page, NULL, 0, oob, 6);
356
357 if (((device->device->options & NAND_BUSWIDTH_16) && ((oob[0] & oob[1]) != 0xff))
358 || (((device->page_size == 512) && (oob[5] != 0xff)) ||
359 ((device->page_size == 2048) && (oob[0] != 0xff))))
360 {
361 LOG_WARNING("invalid block: %i", i);
362 device->blocks[i].is_bad = 1;
363 }
364 else
365 {
366 device->blocks[i].is_bad = 0;
367 }
368
369 page += (device->erase_size / device->page_size);
370 }
371
372 return ERROR_OK;
373 }
374
375 int nand_read_status(struct nand_device_s *device, u8 *status)
376 {
377 if (!device->device)
378 return ERROR_NAND_DEVICE_NOT_PROBED;
379
380 /* Send read status command */
381 device->controller->command(device, NAND_CMD_STATUS);
382
383 alive_sleep(1);
384
385 /* read status */
386 if (device->device->options & NAND_BUSWIDTH_16)
387 {
388 u16 data;
389 device->controller->read_data(device, &data);
390 *status = data & 0xff;
391 }
392 else
393 {
394 device->controller->read_data(device, status);
395 }
396
397 return ERROR_OK;
398 }
399
400 static int nand_poll_ready(struct nand_device_s *device, int timeout)
401 {
402 u8 status;
403
404 device->controller->command(device, NAND_CMD_STATUS);
405 do {
406 if (device->device->options & NAND_BUSWIDTH_16) {
407 u16 data;
408 device->controller->read_data(device, &data);
409 status = data & 0xff;
410 } else {
411 device->controller->read_data(device, &status);
412 }
413 if (status & NAND_STATUS_READY)
414 break;
415 alive_sleep(1);
416 } while (timeout--);
417
418 return (status & NAND_STATUS_READY) != 0;
419 }
420
421 int nand_probe(struct nand_device_s *device)
422 {
423 u8 manufacturer_id, device_id;
424 u8 id_buff[6];
425 int retval;
426 int i;
427
428 /* clear device data */
429 device->device = NULL;
430 device->manufacturer = NULL;
431
432 /* clear device parameters */
433 device->bus_width = 0;
434 device->address_cycles = 0;
435 device->page_size = 0;
436 device->erase_size = 0;
437
438 /* initialize controller (device parameters are zero, use controller default) */
439 if ((retval = device->controller->init(device) != ERROR_OK))
440 {
441 switch (retval)
442 {
443 case ERROR_NAND_OPERATION_FAILED:
444 LOG_DEBUG("controller initialization failed");
445 return ERROR_NAND_OPERATION_FAILED;
446 case ERROR_NAND_OPERATION_NOT_SUPPORTED:
447 LOG_ERROR("BUG: controller reported that it doesn't support default parameters");
448 return ERROR_NAND_OPERATION_FAILED;
449 default:
450 LOG_ERROR("BUG: unknown controller initialization failure");
451 return ERROR_NAND_OPERATION_FAILED;
452 }
453 }
454
455 device->controller->command(device, NAND_CMD_RESET);
456 device->controller->reset(device);
457
458 device->controller->command(device, NAND_CMD_READID);
459 device->controller->address(device, 0x0);
460
461 if (device->bus_width == 8)
462 {
463 device->controller->read_data(device, &manufacturer_id);
464 device->controller->read_data(device, &device_id);
465 }
466 else
467 {
468 u16 data_buf;
469 device->controller->read_data(device, &data_buf);
470 manufacturer_id = data_buf & 0xff;
471 device->controller->read_data(device, &data_buf);
472 device_id = data_buf & 0xff;
473 }
474
475 for (i = 0; nand_flash_ids[i].name; i++)
476 {
477 if (nand_flash_ids[i].id == device_id)
478 {
479 device->device = &nand_flash_ids[i];
480 break;
481 }
482 }
483
484 for (i = 0; nand_manuf_ids[i].name; i++)
485 {
486 if (nand_manuf_ids[i].id == manufacturer_id)
487 {
488 device->manufacturer = &nand_manuf_ids[i];
489 break;
490 }
491 }
492
493 if (!device->manufacturer)
494 {
495 device->manufacturer = &nand_manuf_ids[0];
496 device->manufacturer->id = manufacturer_id;
497 }
498
499 if (!device->device)
500 {
501 LOG_ERROR("unknown NAND flash device found, manufacturer id: 0x%2.2x device id: 0x%2.2x",
502 manufacturer_id, device_id);
503 return ERROR_NAND_OPERATION_FAILED;
504 }
505
506 LOG_DEBUG("found %s (%s)", device->device->name, device->manufacturer->name);
507
508 /* initialize device parameters */
509
510 /* bus width */
511 if (device->device->options & NAND_BUSWIDTH_16)
512 device->bus_width = 16;
513 else
514 device->bus_width = 8;
515
516 /* Do we need extended device probe information? */
517 if (device->device->page_size == 0 ||
518 device->device->erase_size == 0)
519 {
520 if (device->bus_width == 8)
521 {
522 device->controller->read_data(device, id_buff+3);
523 device->controller->read_data(device, id_buff+4);
524 device->controller->read_data(device, id_buff+5);
525 }
526 else
527 {
528 u16 data_buf;
529
530 device->controller->read_data(device, &data_buf);
531 id_buff[3] = data_buf;
532
533 device->controller->read_data(device, &data_buf);
534 id_buff[4] = data_buf;
535
536 device->controller->read_data(device, &data_buf);
537 id_buff[5] = data_buf >> 8;
538 }
539 }
540
541 /* page size */
542 if (device->device->page_size == 0)
543 {
544 device->page_size = 1 << (10 + (id_buff[4] & 3));
545 }
546 else if (device->device->page_size == 256)
547 {
548 LOG_ERROR("NAND flashes with 256 byte pagesize are not supported");
549 return ERROR_NAND_OPERATION_FAILED;
550 }
551 else
552 {
553 device->page_size = device->device->page_size;
554 }
555
556 /* number of address cycles */
557 if (device->page_size <= 512)
558 {
559 /* small page devices */
560 if (device->device->chip_size <= 32)
561 device->address_cycles = 3;
562 else if (device->device->chip_size <= 8*1024)
563 device->address_cycles = 4;
564 else
565 {
566 LOG_ERROR("BUG: small page NAND device with more than 8 GiB encountered");
567 device->address_cycles = 5;
568 }
569 }
570 else
571 {
572 /* large page devices */
573 if (device->device->chip_size <= 128)
574 device->address_cycles = 4;
575 else if (device->device->chip_size <= 32*1024)
576 device->address_cycles = 5;
577 else
578 {
579 LOG_ERROR("BUG: large page NAND device with more than 32 GiB encountered");
580 device->address_cycles = 6;
581 }
582 }
583
584 /* erase size */
585 if (device->device->erase_size == 0)
586 {
587 switch ((id_buff[4] >> 4) & 3) {
588 case 0:
589 device->erase_size = 64 << 10;
590 break;
591 case 1:
592 device->erase_size = 128 << 10;
593 break;
594 case 2:
595 device->erase_size = 256 << 10;
596 break;
597 case 3:
598 device->erase_size =512 << 10;
599 break;
600 }
601 }
602 else
603 {
604 device->erase_size = device->device->erase_size;
605 }
606
607 /* initialize controller, but leave parameters at the controllers default */
608 if ((retval = device->controller->init(device) != ERROR_OK))
609 {
610 switch (retval)
611 {
612 case ERROR_NAND_OPERATION_FAILED:
613 LOG_DEBUG("controller initialization failed");
614 return ERROR_NAND_OPERATION_FAILED;
615 case ERROR_NAND_OPERATION_NOT_SUPPORTED:
616 LOG_ERROR("controller doesn't support requested parameters (buswidth: %i, address cycles: %i, page size: %i)",
617 device->bus_width, device->address_cycles, device->page_size);
618 return ERROR_NAND_OPERATION_FAILED;
619 default:
620 LOG_ERROR("BUG: unknown controller initialization failure");
621 return ERROR_NAND_OPERATION_FAILED;
622 }
623 }
624
625 device->num_blocks = (device->device->chip_size * 1024) / (device->erase_size / 1024);
626 device->blocks = malloc(sizeof(nand_block_t) * device->num_blocks);
627
628 for (i = 0; i < device->num_blocks; i++)
629 {
630 device->blocks[i].size = device->erase_size;
631 device->blocks[i].offset = i * device->erase_size;
632 device->blocks[i].is_erased = -1;
633 device->blocks[i].is_bad = -1;
634 }
635
636 return ERROR_OK;
637 }
638
639 int nand_erase(struct nand_device_s *device, int first_block, int last_block)
640 {
641 int i;
642 u32 page;
643 u8 status;
644 int retval;
645
646 if (!device->device)
647 return ERROR_NAND_DEVICE_NOT_PROBED;
648
649 if ((first_block < 0) || (last_block > device->num_blocks))
650 return ERROR_INVALID_ARGUMENTS;
651
652 /* make sure we know if a block is bad before erasing it */
653 for (i = first_block; i <= last_block; i++)
654 {
655 if (device->blocks[i].is_bad == -1)
656 {
657 nand_build_bbt(device, i, last_block);
658 break;
659 }
660 }
661
662 for (i = first_block; i <= last_block; i++)
663 {
664 /* Send erase setup command */
665 device->controller->command(device, NAND_CMD_ERASE1);
666
667 page = i * (device->erase_size / device->page_size);
668
669 /* Send page address */
670 if (device->page_size <= 512)
671 {
672 /* row */
673 device->controller->address(device, page & 0xff);
674 device->controller->address(device, (page >> 8) & 0xff);
675
676 /* 3rd cycle only on devices with more than 32 MiB */
677 if (device->address_cycles >= 4)
678 device->controller->address(device, (page >> 16) & 0xff);
679
680 /* 4th cycle only on devices with more than 8 GiB */
681 if (device->address_cycles >= 5)
682 device->controller->address(device, (page >> 24) & 0xff);
683 }
684 else
685 {
686 /* row */
687 device->controller->address(device, page & 0xff);
688 device->controller->address(device, (page >> 8) & 0xff);
689
690 /* 3rd cycle only on devices with more than 128 MiB */
691 if (device->address_cycles >= 5)
692 device->controller->address(device, (page >> 16) & 0xff);
693 }
694
695 /* Send erase confirm command */
696 device->controller->command(device, NAND_CMD_ERASE2);
697
698 retval = device->controller->nand_ready ?
699 device->controller->nand_ready(device, 1000) :
700 nand_poll_ready(device, 1000);
701 if (!retval) {
702 LOG_ERROR("timeout waiting for NAND flash block erase to complete");
703 return ERROR_NAND_OPERATION_TIMEOUT;
704 }
705
706 if ((retval = nand_read_status(device, &status)) != ERROR_OK)
707 {
708 LOG_ERROR("couldn't read status");
709 return ERROR_NAND_OPERATION_FAILED;
710 }
711
712 if (status & 0x1)
713 {
714 LOG_ERROR("erase operation didn't pass, status: 0x%2.2x", status);
715 return ERROR_NAND_OPERATION_FAILED;
716 }
717
718 device->blocks[i].is_erased = 1;
719 }
720
721 return ERROR_OK;
722 }
723
724 #if 0
725 static int nand_read_plain(struct nand_device_s *device, u32 address, u8 *data, u32 data_size)
726 {
727 u8 *page;
728
729 if (!device->device)
730 return ERROR_NAND_DEVICE_NOT_PROBED;
731
732 if (address % device->page_size)
733 {
734 LOG_ERROR("reads need to be page aligned");
735 return ERROR_NAND_OPERATION_FAILED;
736 }
737
738 page = malloc(device->page_size);
739
740 while (data_size > 0 )
741 {
742 u32 thisrun_size = (data_size > device->page_size) ? device->page_size : data_size;
743 u32 page_address;
744
745
746 page_address = address / device->page_size;
747
748 nand_read_page(device, page_address, page, device->page_size, NULL, 0);
749
750 memcpy(data, page, thisrun_size);
751
752 address += thisrun_size;
753 data += thisrun_size;
754 data_size -= thisrun_size;
755 }
756
757 free(page);
758
759 return ERROR_OK;
760 }
761
762 static int nand_write_plain(struct nand_device_s *device, u32 address, u8 *data, u32 data_size)
763 {
764 u8 *page;
765
766 if (!device->device)
767 return ERROR_NAND_DEVICE_NOT_PROBED;
768
769 if (address % device->page_size)
770 {
771 LOG_ERROR("writes need to be page aligned");
772 return ERROR_NAND_OPERATION_FAILED;
773 }
774
775 page = malloc(device->page_size);
776
777 while (data_size > 0 )
778 {
779 u32 thisrun_size = (data_size > device->page_size) ? device->page_size : data_size;
780 u32 page_address;
781
782 memset(page, 0xff, device->page_size);
783 memcpy(page, data, thisrun_size);
784
785 page_address = address / device->page_size;
786
787 nand_write_page(device, page_address, page, device->page_size, NULL, 0);
788
789 address += thisrun_size;
790 data += thisrun_size;
791 data_size -= thisrun_size;
792 }
793
794 free(page);
795
796 return ERROR_OK;
797 }
798 #endif
799
800 int nand_write_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
801 {
802 u32 block;
803
804 if (!device->device)
805 return ERROR_NAND_DEVICE_NOT_PROBED;
806
807 block = page / (device->erase_size / device->page_size);
808 if (device->blocks[block].is_erased == 1)
809 device->blocks[block].is_erased = 0;
810
811 if (device->use_raw || device->controller->write_page == NULL)
812 return nand_write_page_raw(device, page, data, data_size, oob, oob_size);
813 else
814 return device->controller->write_page(device, page, data, data_size, oob, oob_size);
815 }
816
817 static int nand_read_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
818 {
819 if (!device->device)
820 return ERROR_NAND_DEVICE_NOT_PROBED;
821
822 if (device->use_raw || device->controller->read_page == NULL)
823 return nand_read_page_raw(device, page, data, data_size, oob, oob_size);
824 else
825 return device->controller->read_page(device, page, data, data_size, oob, oob_size);
826 }
827
828 int nand_read_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
829 {
830 u32 i;
831
832 if (!device->device)
833 return ERROR_NAND_DEVICE_NOT_PROBED;
834
835 if (device->page_size <= 512)
836 {
837 /* small page device */
838 if (data)
839 device->controller->command(device, NAND_CMD_READ0);
840 else
841 device->controller->command(device, NAND_CMD_READOOB);
842
843 /* column (always 0, we start at the beginning of a page/OOB area) */
844 device->controller->address(device, 0x0);
845
846 /* row */
847 device->controller->address(device, page & 0xff);
848 device->controller->address(device, (page >> 8) & 0xff);
849
850 /* 4th cycle only on devices with more than 32 MiB */
851 if (device->address_cycles >= 4)
852 device->controller->address(device, (page >> 16) & 0xff);
853
854 /* 5th cycle only on devices with more than 8 GiB */
855 if (device->address_cycles >= 5)
856 device->controller->address(device, (page >> 24) & 0xff);
857 }
858 else
859 {
860 /* large page device */
861 device->controller->command(device, NAND_CMD_READ0);
862
863 /* column (0 when we start at the beginning of a page,
864 * or 2048 for the beginning of OOB area)
865 */
866 device->controller->address(device, 0x0);
867 if (data)
868 device->controller->address(device, 0x0);
869 else
870 device->controller->address(device, 0x8);
871
872 /* row */
873 device->controller->address(device, page & 0xff);
874 device->controller->address(device, (page >> 8) & 0xff);
875
876 /* 5th cycle only on devices with more than 128 MiB */
877 if (device->address_cycles >= 5)
878 device->controller->address(device, (page >> 16) & 0xff);
879
880 /* large page devices need a start command */
881 device->controller->command(device, NAND_CMD_READSTART);
882 }
883
884 if (device->controller->nand_ready) {
885 if (!device->controller->nand_ready(device, 100))
886 return ERROR_NAND_OPERATION_TIMEOUT;
887 } else {
888 alive_sleep(1);
889 }
890
891 if (data)
892 {
893 if (device->controller->read_block_data != NULL)
894 (device->controller->read_block_data)(device, data, data_size);
895 else
896 {
897 for (i = 0; i < data_size;)
898 {
899 if (device->device->options & NAND_BUSWIDTH_16)
900 {
901 device->controller->read_data(device, data);
902 data += 2;
903 i += 2;
904 }
905 else
906 {
907 device->controller->read_data(device, data);
908 data += 1;
909 i += 1;
910 }
911 }
912 }
913 }
914
915 if (oob)
916 {
917 if (device->controller->read_block_data != NULL)
918 (device->controller->read_block_data)(device, oob, oob_size);
919 else
920 {
921 for (i = 0; i < oob_size;)
922 {
923 if (device->device->options & NAND_BUSWIDTH_16)
924 {
925 device->controller->read_data(device, oob);
926 oob += 2;
927 i += 2;
928 }
929 else
930 {
931 device->controller->read_data(device, oob);
932 oob += 1;
933 i += 1;
934 }
935 }
936 }
937 }
938
939 return ERROR_OK;
940 }
941
942 int nand_write_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
943 {
944 u32 i;
945 int retval;
946 u8 status;
947
948 if (!device->device)
949 return ERROR_NAND_DEVICE_NOT_PROBED;
950
951 device->controller->command(device, NAND_CMD_SEQIN);
952
953 if (device->page_size <= 512)
954 {
955 /* column (always 0, we start at the beginning of a page/OOB area) */
956 device->controller->address(device, 0x0);
957
958 /* row */
959 device->controller->address(device, page & 0xff);
960 device->controller->address(device, (page >> 8) & 0xff);
961
962 /* 4th cycle only on devices with more than 32 MiB */
963 if (device->address_cycles >= 4)
964 device->controller->address(device, (page >> 16) & 0xff);
965
966 /* 5th cycle only on devices with more than 8 GiB */
967 if (device->address_cycles >= 5)
968 device->controller->address(device, (page >> 24) & 0xff);
969 }
970 else
971 {
972 /* column (0 when we start at the beginning of a page,
973 * or 2048 for the beginning of OOB area)
974 */
975 device->controller->address(device, 0x0);
976 if (data)
977 device->controller->address(device, 0x0);
978 else
979 device->controller->address(device, 0x8);
980
981 /* row */
982 device->controller->address(device, page & 0xff);
983 device->controller->address(device, (page >> 8) & 0xff);
984
985 /* 5th cycle only on devices with more than 128 MiB */
986 if (device->address_cycles >= 5)
987 device->controller->address(device, (page >> 16) & 0xff);
988 }
989
990 if (data)
991 {
992 if (device->controller->write_block_data != NULL)
993 (device->controller->write_block_data)(device, data, data_size);
994 else
995 {
996 for (i = 0; i < data_size;)
997 {
998 if (device->device->options & NAND_BUSWIDTH_16)
999 {
1000 u16 data_buf = le_to_h_u16(data);
1001 device->controller->write_data(device, data_buf);
1002 data += 2;
1003 i += 2;
1004 }
1005 else
1006 {
1007 device->controller->write_data(device, *data);
1008 data += 1;
1009 i += 1;
1010 }
1011 }
1012 }
1013 }
1014
1015 if (oob)
1016 {
1017 if (device->controller->write_block_data != NULL)
1018 (device->controller->write_block_data)(device, oob, oob_size);
1019 else
1020 {
1021 for (i = 0; i < oob_size;)
1022 {
1023 if (device->device->options & NAND_BUSWIDTH_16)
1024 {
1025 u16 oob_buf = le_to_h_u16(data);
1026 device->controller->write_data(device, oob_buf);
1027 oob += 2;
1028 i += 2;
1029 }
1030 else
1031 {
1032 device->controller->write_data(device, *oob);
1033 oob += 1;
1034 i += 1;
1035 }
1036 }
1037 }
1038 }
1039
1040 device->controller->command(device, NAND_CMD_PAGEPROG);
1041
1042 retval = device->controller->nand_ready ?
1043 device->controller->nand_ready(device, 100) :
1044 nand_poll_ready(device, 100);
1045 if (!retval)
1046 return ERROR_NAND_OPERATION_TIMEOUT;
1047
1048 if ((retval = nand_read_status(device, &status)) != ERROR_OK)
1049 {
1050 LOG_ERROR("couldn't read status");
1051 return ERROR_NAND_OPERATION_FAILED;
1052 }
1053
1054 if (status & NAND_STATUS_FAIL)
1055 {
1056 LOG_ERROR("write operation didn't pass, status: 0x%2.2x", status);
1057 return ERROR_NAND_OPERATION_FAILED;
1058 }
1059
1060 return ERROR_OK;
1061 }
1062
1063 int handle_nand_list_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1064 {
1065 nand_device_t *p;
1066 int i;
1067
1068 if (!nand_devices)
1069 {
1070 command_print(cmd_ctx, "no NAND flash devices configured");
1071 return ERROR_OK;
1072 }
1073
1074 for (p = nand_devices, i = 0; p; p = p->next, i++)
1075 {
1076 if (p->device)
1077 command_print(cmd_ctx, "#%i: %s (%s) pagesize: %i, buswidth: %i, erasesize: %i",
1078 i, p->device->name, p->manufacturer->name, p->page_size, p->bus_width, p->erase_size);
1079 else
1080 command_print(cmd_ctx, "#%i: not probed", i);
1081 }
1082
1083 return ERROR_OK;
1084 }
1085
1086 static int handle_nand_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1087 {
1088 nand_device_t *p;
1089 int i = 0;
1090 int j = 0;
1091 int first = -1;
1092 int last = -1;
1093
1094 if ((argc < 1) || (argc > 3))
1095 {
1096 return ERROR_COMMAND_SYNTAX_ERROR;
1097
1098 }
1099
1100 if (argc == 2)
1101 {
1102 first = last = strtoul(args[1], NULL, 0);
1103 }
1104 else if (argc == 3)
1105 {
1106 first = strtoul(args[1], NULL, 0);
1107 last = strtoul(args[2], NULL, 0);
1108 }
1109
1110 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1111 if (p)
1112 {
1113 if (p->device)
1114 {
1115 if (first >= p->num_blocks)
1116 first = p->num_blocks - 1;
1117
1118 if (last >= p->num_blocks)
1119 last = p->num_blocks - 1;
1120
1121 command_print(cmd_ctx, "#%i: %s (%s) pagesize: %i, buswidth: %i, erasesize: %i",
1122 i++, p->device->name, p->manufacturer->name, p->page_size, p->bus_width, p->erase_size);
1123
1124 for (j = first; j <= last; j++)
1125 {
1126 char *erase_state, *bad_state;
1127
1128 if (p->blocks[j].is_erased == 0)
1129 erase_state = "not erased";
1130 else if (p->blocks[j].is_erased == 1)
1131 erase_state = "erased";
1132 else
1133 erase_state = "erase state unknown";
1134
1135 if (p->blocks[j].is_bad == 0)
1136 bad_state = "";
1137 else if (p->blocks[j].is_bad == 1)
1138 bad_state = " (marked bad)";
1139 else
1140 bad_state = " (block condition unknown)";
1141
1142 command_print(cmd_ctx, "\t#%i: 0x%8.8x (0x%xkB) %s%s",
1143 j, p->blocks[j].offset, p->blocks[j].size / 1024,
1144 erase_state, bad_state);
1145 }
1146 }
1147 else
1148 {
1149 command_print(cmd_ctx, "#%s: not probed", args[0]);
1150 }
1151 }
1152
1153 return ERROR_OK;
1154 }
1155
1156 static int handle_nand_probe_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1157 {
1158 nand_device_t *p;
1159 int retval;
1160
1161 if (argc != 1)
1162 {
1163 return ERROR_COMMAND_SYNTAX_ERROR;
1164 }
1165
1166 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1167 if (p)
1168 {
1169 if ((retval = nand_probe(p)) == ERROR_OK)
1170 {
1171 command_print(cmd_ctx, "NAND flash device '%s' found", p->device->name);
1172 }
1173 else if (retval == ERROR_NAND_OPERATION_FAILED)
1174 {
1175 command_print(cmd_ctx, "probing failed for NAND flash device");
1176 }
1177 else
1178 {
1179 command_print(cmd_ctx, "unknown error when probing NAND flash device");
1180 }
1181 }
1182 else
1183 {
1184 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1185 }
1186
1187 return ERROR_OK;
1188 }
1189
1190 static int handle_nand_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1191 {
1192 nand_device_t *p;
1193 int retval;
1194
1195 if (argc != 3)
1196 {
1197 return ERROR_COMMAND_SYNTAX_ERROR;
1198
1199 }
1200
1201 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1202 if (p)
1203 {
1204 int first = strtoul(args[1], NULL, 0);
1205 int last = strtoul(args[2], NULL, 0);
1206
1207 if ((retval = nand_erase(p, first, last)) == ERROR_OK)
1208 {
1209 command_print(cmd_ctx, "successfully erased blocks %i to %i on NAND flash device '%s'", first, last, p->device->name);
1210 }
1211 else if (retval == ERROR_NAND_OPERATION_FAILED)
1212 {
1213 command_print(cmd_ctx, "erase failed");
1214 }
1215 else
1216 {
1217 command_print(cmd_ctx, "unknown error when erasing NAND flash device");
1218 }
1219 }
1220 else
1221 {
1222 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1223 }
1224
1225 return ERROR_OK;
1226 }
1227
1228 int handle_nand_check_bad_blocks_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1229 {
1230 nand_device_t *p;
1231 int retval;
1232 int first = -1;
1233 int last = -1;
1234
1235 if ((argc < 1) || (argc > 3) || (argc == 2))
1236 {
1237 return ERROR_COMMAND_SYNTAX_ERROR;
1238
1239 }
1240
1241 if (argc == 3)
1242 {
1243 first = strtoul(args[1], NULL, 0);
1244 last = strtoul(args[2], NULL, 0);
1245 }
1246
1247 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1248 if (p)
1249 {
1250 if ((retval = nand_build_bbt(p, first, last)) == ERROR_OK)
1251 {
1252 command_print(cmd_ctx, "checked NAND flash device for bad blocks, use \"nand info\" command to list blocks");
1253 }
1254 else if (retval == ERROR_NAND_OPERATION_FAILED)
1255 {
1256 command_print(cmd_ctx, "error when checking for bad blocks on NAND flash device");
1257 }
1258 else
1259 {
1260 command_print(cmd_ctx, "unknown error when checking for bad blocks on NAND flash device");
1261 }
1262 }
1263 else
1264 {
1265 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1266 }
1267
1268 return ERROR_OK;
1269 }
1270
1271 static int handle_nand_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1272 {
1273 u32 offset;
1274 u32 binary_size;
1275 u32 buf_cnt;
1276 enum oob_formats oob_format = NAND_OOB_NONE;
1277
1278 fileio_t fileio;
1279
1280 duration_t duration;
1281 char *duration_text;
1282
1283 nand_device_t *p;
1284
1285 if (argc < 3)
1286 {
1287 return ERROR_COMMAND_SYNTAX_ERROR;
1288
1289 }
1290
1291 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1292 if (p)
1293 {
1294 u8 *page = NULL;
1295 u32 page_size = 0;
1296 u8 *oob = NULL;
1297 u32 oob_size = 0;
1298 const int *eccpos = NULL;
1299
1300 offset = strtoul(args[2], NULL, 0);
1301
1302 if (argc > 3)
1303 {
1304 int i;
1305 for (i = 3; i < argc; i++)
1306 {
1307 if (!strcmp(args[i], "oob_raw"))
1308 oob_format |= NAND_OOB_RAW;
1309 else if (!strcmp(args[i], "oob_only"))
1310 oob_format |= NAND_OOB_RAW | NAND_OOB_ONLY;
1311 else if (!strcmp(args[i], "oob_softecc"))
1312 oob_format |= NAND_OOB_SW_ECC;
1313 else if (!strcmp(args[i], "oob_softecc_kw"))
1314 oob_format |= NAND_OOB_SW_ECC_KW;
1315 else
1316 {
1317 command_print(cmd_ctx, "unknown option: %s", args[i]);
1318 return ERROR_COMMAND_SYNTAX_ERROR;
1319 }
1320 }
1321 }
1322
1323 duration_start_measure(&duration);
1324
1325 if (fileio_open(&fileio, args[1], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1326 {
1327 return ERROR_OK;
1328 }
1329
1330 buf_cnt = binary_size = fileio.size;
1331
1332 if (!(oob_format & NAND_OOB_ONLY))
1333 {
1334 page_size = p->page_size;
1335 page = malloc(p->page_size);
1336 }
1337
1338 if (oob_format & (NAND_OOB_RAW | NAND_OOB_SW_ECC | NAND_OOB_SW_ECC_KW))
1339 {
1340 if (p->page_size == 512) {
1341 oob_size = 16;
1342 eccpos = nand_oob_16.eccpos;
1343 } else if (p->page_size == 2048) {
1344 oob_size = 64;
1345 eccpos = nand_oob_64.eccpos;
1346 }
1347 oob = malloc(oob_size);
1348 }
1349
1350 if (offset % p->page_size)
1351 {
1352 command_print(cmd_ctx, "only page size aligned offsets and sizes are supported");
1353 fileio_close(&fileio);
1354 free(oob);
1355 free(page);
1356 return ERROR_OK;
1357 }
1358
1359 while (buf_cnt > 0)
1360 {
1361 u32 size_read;
1362
1363 if (NULL != page)
1364 {
1365 fileio_read(&fileio, page_size, page, &size_read);
1366 buf_cnt -= size_read;
1367 if (size_read < page_size)
1368 {
1369 memset(page + size_read, 0xff, page_size - size_read);
1370 }
1371 }
1372
1373 if (oob_format & NAND_OOB_SW_ECC)
1374 {
1375 u32 i, j;
1376 u8 ecc[3];
1377 memset(oob, 0xff, oob_size);
1378 for (i = 0, j = 0; i < page_size; i += 256) {
1379 nand_calculate_ecc(p, page+i, ecc);
1380 oob[eccpos[j++]] = ecc[0];
1381 oob[eccpos[j++]] = ecc[1];
1382 oob[eccpos[j++]] = ecc[2];
1383 }
1384 } else if (oob_format & NAND_OOB_SW_ECC_KW)
1385 {
1386 /*
1387 * In this case eccpos is not used as
1388 * the ECC data is always stored contigously
1389 * at the end of the OOB area. It consists
1390 * of 10 bytes per 512-byte data block.
1391 */
1392 u32 i;
1393 u8 *ecc = oob + oob_size - page_size/512 * 10;
1394 memset(oob, 0xff, oob_size);
1395 for (i = 0; i < page_size; i += 512) {
1396 nand_calculate_ecc_kw(p, page+i, ecc);
1397 ecc += 10;
1398 }
1399 }
1400 else if (NULL != oob)
1401 {
1402 fileio_read(&fileio, oob_size, oob, &size_read);
1403 buf_cnt -= size_read;
1404 if (size_read < oob_size)
1405 {
1406 memset(oob + size_read, 0xff, oob_size - size_read);
1407 }
1408 }
1409
1410 if (nand_write_page(p, offset / p->page_size, page, page_size, oob, oob_size) != ERROR_OK)
1411 {
1412 command_print(cmd_ctx, "failed writing file %s to NAND flash %s at offset 0x%8.8x",
1413 args[1], args[0], offset);
1414
1415 fileio_close(&fileio);
1416 free(oob);
1417 free(page);
1418
1419 return ERROR_OK;
1420 }
1421 offset += page_size;
1422 }
1423
1424 fileio_close(&fileio);
1425 free(oob);
1426 free(page);
1427 oob = NULL;
1428 page = NULL;
1429 duration_stop_measure(&duration, &duration_text);
1430 command_print(cmd_ctx, "wrote file %s to NAND flash %s up to offset 0x%8.8x in %s",
1431 args[1], args[0], offset, duration_text);
1432 free(duration_text);
1433 duration_text = NULL;
1434 }
1435 else
1436 {
1437 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1438 }
1439
1440 return ERROR_OK;
1441 }
1442
1443 static int handle_nand_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1444 {
1445 nand_device_t *p;
1446
1447 if (argc < 4)
1448 {
1449 return ERROR_COMMAND_SYNTAX_ERROR;
1450 }
1451
1452 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1453 if (p)
1454 {
1455 if (p->device)
1456 {
1457 fileio_t fileio;
1458 duration_t duration;
1459 char *duration_text;
1460 int retval;
1461
1462 u8 *page = NULL;
1463 u32 page_size = 0;
1464 u8 *oob = NULL;
1465 u32 oob_size = 0;
1466 u32 address = strtoul(args[2], NULL, 0);
1467 u32 size = strtoul(args[3], NULL, 0);
1468 u32 bytes_done = 0;
1469 enum oob_formats oob_format = NAND_OOB_NONE;
1470
1471 if (argc > 4)
1472 {
1473 int i;
1474 for (i = 4; i < argc; i++)
1475 {
1476 if (!strcmp(args[i], "oob_raw"))
1477 oob_format |= NAND_OOB_RAW;
1478 else if (!strcmp(args[i], "oob_only"))
1479 oob_format |= NAND_OOB_RAW | NAND_OOB_ONLY;
1480 else
1481 command_print(cmd_ctx, "unknown option: '%s'", args[i]);
1482 }
1483 }
1484
1485 if ((address % p->page_size) || (size % p->page_size))
1486 {
1487 command_print(cmd_ctx, "only page size aligned addresses and sizes are supported");
1488 return ERROR_OK;
1489 }
1490
1491 if (!(oob_format & NAND_OOB_ONLY))
1492 {
1493 page_size = p->page_size;
1494 page = malloc(p->page_size);
1495 }
1496
1497 if (oob_format & NAND_OOB_RAW)
1498 {
1499 if (p->page_size == 512)
1500 oob_size = 16;
1501 else if (p->page_size == 2048)
1502 oob_size = 64;
1503 oob = malloc(oob_size);
1504 }
1505
1506 if (fileio_open(&fileio, args[1], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1507 {
1508 return ERROR_OK;
1509 }
1510
1511 duration_start_measure(&duration);
1512
1513 while (size > 0)
1514 {
1515 u32 size_written;
1516 if ((retval = nand_read_page(p, address / p->page_size, page, page_size, oob, oob_size)) != ERROR_OK)
1517 {
1518 command_print(cmd_ctx, "reading NAND flash page failed");
1519 free(page);
1520 free(oob);
1521 fileio_close(&fileio);
1522 return ERROR_OK;
1523 }
1524
1525 if (NULL != page)
1526 {
1527 fileio_write(&fileio, page_size, page, &size_written);
1528 bytes_done += page_size;
1529 }
1530
1531 if (NULL != oob)
1532 {
1533 fileio_write(&fileio, oob_size, oob, &size_written);
1534 bytes_done += oob_size;
1535 }
1536
1537 size -= p->page_size;
1538 address += p->page_size;
1539 }
1540
1541 free(page);
1542 page = NULL;
1543 free(oob);
1544 oob = NULL;
1545 fileio_close(&fileio);
1546
1547 duration_stop_measure(&duration, &duration_text);
1548 command_print(cmd_ctx, "dumped %lld byte in %s", fileio.size, duration_text);
1549 free(duration_text);
1550 duration_text = NULL;
1551 }
1552 else
1553 {
1554 command_print(cmd_ctx, "#%s: not probed", args[0]);
1555 }
1556 }
1557 else
1558 {
1559 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1560 }
1561
1562 return ERROR_OK;
1563 }
1564
1565 static int handle_nand_raw_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1566 {
1567 nand_device_t *p;
1568
1569 if ((argc < 1) || (argc > 2))
1570 {
1571 return ERROR_COMMAND_SYNTAX_ERROR;
1572 }
1573
1574 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1575 if (p)
1576 {
1577 if (p->device)
1578 {
1579 if (argc == 2)
1580 {
1581 if (strcmp("enable", args[1]) == 0)
1582 {
1583 p->use_raw = 1;
1584 }
1585 else if (strcmp("disable", args[1]) == 0)
1586 {
1587 p->use_raw = 0;
1588 }
1589 else
1590 {
1591 return ERROR_COMMAND_SYNTAX_ERROR;
1592 }
1593 }
1594
1595 command_print(cmd_ctx, "raw access is %s", (p->use_raw) ? "enabled" : "disabled");
1596 }
1597 else
1598 {
1599 command_print(cmd_ctx, "#%s: not probed", args[0]);
1600 }
1601 }
1602 else
1603 {
1604 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1605 }
1606
1607 return ERROR_OK;
1608 }
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