1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2010 richard vegh <vegh.ricsi@gmail.com> *
6 * Copyright (C) 2010 Oyvind Harboe <oyvind.harboe@zylin.com> *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
20 ***************************************************************************/
28 #include <target/target.h>
30 static int lpc3180_reset(struct nand_device
*nand
);
31 static int lpc3180_controller_ready(struct nand_device
*nand
, int timeout
);
32 static int lpc3180_tc_ready(struct nand_device
*nand
, int timeout
);
34 #define ECC_OFFS 0x120
35 #define SPARE_OFFS 0x140
36 #define DATA_OFFS 0x200
38 /* nand device lpc3180 <target#> <oscillator_frequency>
40 NAND_DEVICE_COMMAND_HANDLER(lpc3180_nand_device_command
)
43 return ERROR_COMMAND_SYNTAX_ERROR
;
46 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[2], osc_freq
);
48 struct lpc3180_nand_controller
*lpc3180_info
;
49 lpc3180_info
= malloc(sizeof(struct lpc3180_nand_controller
));
50 nand
->controller_priv
= lpc3180_info
;
52 lpc3180_info
->osc_freq
= osc_freq
;
54 if ((lpc3180_info
->osc_freq
< 1000) || (lpc3180_info
->osc_freq
> 20000))
56 "LPC3180 oscillator frequency should be between 1000 and 20000 kHz, was %i",
57 lpc3180_info
->osc_freq
);
58 lpc3180_info
->selected_controller
= LPC3180_NO_CONTROLLER
;
59 lpc3180_info
->sw_write_protection
= 0;
60 lpc3180_info
->sw_wp_lower_bound
= 0x0;
61 lpc3180_info
->sw_wp_upper_bound
= 0x0;
66 static int lpc3180_pll(int fclkin
, uint32_t pll_ctrl
)
68 int bypass
= (pll_ctrl
& 0x8000) >> 15;
69 int direct
= (pll_ctrl
& 0x4000) >> 14;
70 int feedback
= (pll_ctrl
& 0x2000) >> 13;
71 int p
= (1 << ((pll_ctrl
& 0x1800) >> 11) * 2);
72 int n
= ((pll_ctrl
& 0x0600) >> 9) + 1;
73 int m
= ((pll_ctrl
& 0x01fe) >> 1) + 1;
74 int lock
= (pll_ctrl
& 0x1);
77 LOG_WARNING("PLL is not locked");
79 if (!bypass
&& direct
) /* direct mode */
80 return (m
* fclkin
) / n
;
82 if (bypass
&& !direct
) /* bypass mode */
83 return fclkin
/ (2 * p
);
85 if (bypass
& direct
) /* direct bypass mode */
88 if (feedback
) /* integer mode */
89 return m
* (fclkin
/ n
);
90 else /* non-integer mode */
91 return (m
/ (2 * p
)) * (fclkin
/ n
);
94 static float lpc3180_cycle_time(struct nand_device
*nand
)
96 struct lpc3180_nand_controller
*lpc3180_info
= nand
->controller_priv
;
97 struct target
*target
= nand
->target
;
98 uint32_t sysclk_ctrl
, pwr_ctrl
, hclkdiv_ctrl
, hclkpll_ctrl
;
104 /* calculate timings */
106 /* determine current SYSCLK (13'MHz or main oscillator) */
107 target_read_u32(target
, 0x40004050, &sysclk_ctrl
);
109 if ((sysclk_ctrl
& 1) == 0)
110 sysclk
= lpc3180_info
->osc_freq
;
114 /* determine selected HCLK source */
115 target_read_u32(target
, 0x40004044, &pwr_ctrl
);
117 if ((pwr_ctrl
& (1 << 2)) == 0) /* DIRECT RUN mode */
120 target_read_u32(target
, 0x40004058, &hclkpll_ctrl
);
121 hclk_pll
= lpc3180_pll(sysclk
, hclkpll_ctrl
);
123 target_read_u32(target
, 0x40004040, &hclkdiv_ctrl
);
125 if (pwr_ctrl
& (1 << 10)) /* ARM_CLK and HCLK use PERIPH_CLK */
126 hclk
= hclk_pll
/ (((hclkdiv_ctrl
& 0x7c) >> 2) + 1);
127 else /* HCLK uses HCLK_PLL */
128 hclk
= hclk_pll
/ (1 << (hclkdiv_ctrl
& 0x3));
131 LOG_DEBUG("LPC3180 HCLK currently clocked at %i kHz", hclk
);
133 cycle
= (1.0 / hclk
) * 1000000.0;
138 static int lpc3180_init(struct nand_device
*nand
)
140 struct lpc3180_nand_controller
*lpc3180_info
= nand
->controller_priv
;
141 struct target
*target
= nand
->target
;
142 int bus_width
= nand
->bus_width
? : 8;
143 int address_cycles
= nand
->address_cycles
? : 3;
144 int page_size
= nand
->page_size
? : 512;
146 if (target
->state
!= TARGET_HALTED
) {
147 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
148 return ERROR_NAND_OPERATION_FAILED
;
151 /* sanitize arguments */
152 if ((bus_width
!= 8) && (bus_width
!= 16)) {
153 LOG_ERROR("LPC3180 only supports 8 or 16 bit bus width, not %i", bus_width
);
154 return ERROR_NAND_OPERATION_NOT_SUPPORTED
;
157 /* The LPC3180 only brings out 8 bit NAND data bus, but the controller
158 * would support 16 bit, too, so we just warn about this for now
161 LOG_WARNING("LPC3180 only supports 8 bit bus width");
163 /* inform calling code about selected bus width */
164 nand
->bus_width
= bus_width
;
166 if ((address_cycles
!= 3) && (address_cycles
!= 4)) {
167 LOG_ERROR("LPC3180 only supports 3 or 4 address cycles, not %i", address_cycles
);
168 return ERROR_NAND_OPERATION_NOT_SUPPORTED
;
171 if ((page_size
!= 512) && (page_size
!= 2048)) {
172 LOG_ERROR("LPC3180 only supports 512 or 2048 byte pages, not %i", page_size
);
173 return ERROR_NAND_OPERATION_NOT_SUPPORTED
;
176 /* select MLC controller if none is currently selected */
177 if (lpc3180_info
->selected_controller
== LPC3180_NO_CONTROLLER
) {
178 LOG_DEBUG("no LPC3180 NAND flash controller selected, using default 'mlc'");
179 lpc3180_info
->selected_controller
= LPC3180_MLC_CONTROLLER
;
182 if (lpc3180_info
->selected_controller
== LPC3180_MLC_CONTROLLER
) {
183 uint32_t mlc_icr_value
= 0x0;
185 int twp
, twh
, trp
, treh
, trhz
, trbwb
, tcea
;
187 /* FLASHCLK_CTRL = 0x22 (enable clock for MLC flash controller) */
188 target_write_u32(target
, 0x400040c8, 0x22);
190 /* MLC_CEH = 0x0 (Force nCE assert) */
191 target_write_u32(target
, 0x200b804c, 0x0);
193 /* MLC_LOCK = 0xa25e (unlock protected registers) */
194 target_write_u32(target
, 0x200b8044, 0xa25e);
196 /* MLC_ICR = configuration */
197 if (lpc3180_info
->sw_write_protection
)
198 mlc_icr_value
|= 0x8;
199 if (page_size
== 2048)
200 mlc_icr_value
|= 0x4;
201 if (address_cycles
== 4)
202 mlc_icr_value
|= 0x2;
204 mlc_icr_value
|= 0x1;
205 target_write_u32(target
, 0x200b8030, mlc_icr_value
);
207 /* calculate NAND controller timings */
208 cycle
= lpc3180_cycle_time(nand
);
210 twp
= ((40 / cycle
) + 1);
211 twh
= ((20 / cycle
) + 1);
212 trp
= ((30 / cycle
) + 1);
213 treh
= ((15 / cycle
) + 1);
214 trhz
= ((30 / cycle
) + 1);
215 trbwb
= ((100 / cycle
) + 1);
216 tcea
= ((45 / cycle
) + 1);
218 /* MLC_LOCK = 0xa25e (unlock protected registers) */
219 target_write_u32(target
, 0x200b8044, 0xa25e);
222 target_write_u32(target
, 0x200b8034, (twp
& 0xf) | ((twh
& 0xf) << 4) |
223 ((trp
& 0xf) << 8) | ((treh
& 0xf) << 12) | ((trhz
& 0x7) << 16) |
224 ((trbwb
& 0x1f) << 19) | ((tcea
& 0x3) << 24));
227 } else if (lpc3180_info
->selected_controller
== LPC3180_SLC_CONTROLLER
) {
229 int r_setup
, r_hold
, r_width
, r_rdy
;
230 int w_setup
, w_hold
, w_width
, w_rdy
;
232 /* FLASHCLK_CTRL = 0x05 (enable clock for SLC flash controller) */
233 target_write_u32(target
, 0x400040c8, 0x05);
235 /* after reset set other registers of SLC so reset calling is here at the begining*/
238 /* SLC_CFG = 0x (Force nCE assert, DMA ECC enabled, ECC enabled, DMA burst enabled,
239 *DMA read from SLC, WIDTH = bus_width) */
240 target_write_u32(target
, 0x20020014, 0x3e | ((bus_width
== 16) ? 1 : 0));
242 /* SLC_IEN = 3 (INT_RDY_EN = 1) ,(INT_TC_STAT = 1) */
243 target_write_u32(target
, 0x20020020, 0x03);
246 * DMACLK_CTRL = 0x01 (enable clock for DMA controller) */
247 target_write_u32(target
, 0x400040e8, 0x01);
248 /* DMACConfig = DMA enabled*/
249 target_write_u32(target
, 0x31000030, 0x01);
252 /* calculate NAND controller timings */
253 cycle
= lpc3180_cycle_time(nand
);
255 r_setup
= w_setup
= 0;
256 r_hold
= w_hold
= 10 / cycle
;
257 r_width
= 30 / cycle
;
258 w_width
= 40 / cycle
;
259 r_rdy
= w_rdy
= 100 / cycle
;
261 /* SLC_TAC: SLC timing arcs register */
262 target_write_u32(target
, 0x2002002c, (r_setup
& 0xf) | ((r_hold
& 0xf) << 4) |
263 ((r_width
& 0xf) << 8) | ((r_rdy
& 0xf) << 12) | ((w_setup
& 0xf) << 16) |
264 ((w_hold
& 0xf) << 20) | ((w_width
& 0xf) << 24) | ((w_rdy
& 0xf) << 28));
271 static int lpc3180_reset(struct nand_device
*nand
)
273 struct lpc3180_nand_controller
*lpc3180_info
= nand
->controller_priv
;
274 struct target
*target
= nand
->target
;
276 if (target
->state
!= TARGET_HALTED
) {
277 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
278 return ERROR_NAND_OPERATION_FAILED
;
281 if (lpc3180_info
->selected_controller
== LPC3180_NO_CONTROLLER
) {
282 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
283 return ERROR_NAND_OPERATION_FAILED
;
284 } else if (lpc3180_info
->selected_controller
== LPC3180_MLC_CONTROLLER
) {
285 /* MLC_CMD = 0xff (reset controller and NAND device) */
286 target_write_u32(target
, 0x200b8000, 0xff);
288 if (!lpc3180_controller_ready(nand
, 100)) {
289 LOG_ERROR("LPC3180 NAND controller timed out after reset");
290 return ERROR_NAND_OPERATION_TIMEOUT
;
292 } else if (lpc3180_info
->selected_controller
== LPC3180_SLC_CONTROLLER
) {
293 /* SLC_CTRL = 0x6 (ECC_CLEAR, SW_RESET) */
294 target_write_u32(target
, 0x20020010, 0x6);
296 if (!lpc3180_controller_ready(nand
, 100)) {
297 LOG_ERROR("LPC3180 NAND controller timed out after reset");
298 return ERROR_NAND_OPERATION_TIMEOUT
;
305 static int lpc3180_command(struct nand_device
*nand
, uint8_t command
)
307 struct lpc3180_nand_controller
*lpc3180_info
= nand
->controller_priv
;
308 struct target
*target
= nand
->target
;
310 if (target
->state
!= TARGET_HALTED
) {
311 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
312 return ERROR_NAND_OPERATION_FAILED
;
315 if (lpc3180_info
->selected_controller
== LPC3180_NO_CONTROLLER
) {
316 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
317 return ERROR_NAND_OPERATION_FAILED
;
318 } else if (lpc3180_info
->selected_controller
== LPC3180_MLC_CONTROLLER
) {
319 /* MLC_CMD = command */
320 target_write_u32(target
, 0x200b8000, command
);
321 } else if (lpc3180_info
->selected_controller
== LPC3180_SLC_CONTROLLER
) {
322 /* SLC_CMD = command */
323 target_write_u32(target
, 0x20020008, command
);
329 static int lpc3180_address(struct nand_device
*nand
, uint8_t address
)
331 struct lpc3180_nand_controller
*lpc3180_info
= nand
->controller_priv
;
332 struct target
*target
= nand
->target
;
334 if (target
->state
!= TARGET_HALTED
) {
335 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
336 return ERROR_NAND_OPERATION_FAILED
;
339 if (lpc3180_info
->selected_controller
== LPC3180_NO_CONTROLLER
) {
340 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
341 return ERROR_NAND_OPERATION_FAILED
;
342 } else if (lpc3180_info
->selected_controller
== LPC3180_MLC_CONTROLLER
) {
343 /* MLC_ADDR = address */
344 target_write_u32(target
, 0x200b8004, address
);
345 } else if (lpc3180_info
->selected_controller
== LPC3180_SLC_CONTROLLER
) {
346 /* SLC_ADDR = address */
347 target_write_u32(target
, 0x20020004, address
);
353 static int lpc3180_write_data(struct nand_device
*nand
, uint16_t data
)
355 struct lpc3180_nand_controller
*lpc3180_info
= nand
->controller_priv
;
356 struct target
*target
= nand
->target
;
358 if (target
->state
!= TARGET_HALTED
) {
359 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
360 return ERROR_NAND_OPERATION_FAILED
;
363 if (lpc3180_info
->selected_controller
== LPC3180_NO_CONTROLLER
) {
364 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
365 return ERROR_NAND_OPERATION_FAILED
;
366 } else if (lpc3180_info
->selected_controller
== LPC3180_MLC_CONTROLLER
) {
367 /* MLC_DATA = data */
368 target_write_u32(target
, 0x200b0000, data
);
369 } else if (lpc3180_info
->selected_controller
== LPC3180_SLC_CONTROLLER
) {
370 /* SLC_DATA = data */
371 target_write_u32(target
, 0x20020000, data
);
377 static int lpc3180_read_data(struct nand_device
*nand
, void *data
)
379 struct lpc3180_nand_controller
*lpc3180_info
= nand
->controller_priv
;
380 struct target
*target
= nand
->target
;
382 if (target
->state
!= TARGET_HALTED
) {
383 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
384 return ERROR_NAND_OPERATION_FAILED
;
387 if (lpc3180_info
->selected_controller
== LPC3180_NO_CONTROLLER
) {
388 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
389 return ERROR_NAND_OPERATION_FAILED
;
390 } else if (lpc3180_info
->selected_controller
== LPC3180_MLC_CONTROLLER
) {
391 /* data = MLC_DATA, use sized access */
392 if (nand
->bus_width
== 8) {
393 uint8_t *data8
= data
;
394 target_read_u8(target
, 0x200b0000, data8
);
395 } else if (nand
->bus_width
== 16) {
396 uint16_t *data16
= data
;
397 target_read_u16(target
, 0x200b0000, data16
);
399 LOG_ERROR("BUG: bus_width neither 8 nor 16 bit");
400 return ERROR_NAND_OPERATION_FAILED
;
402 } else if (lpc3180_info
->selected_controller
== LPC3180_SLC_CONTROLLER
) {
405 /* data = SLC_DATA, must use 32-bit access */
406 target_read_u32(target
, 0x20020000, &data32
);
408 if (nand
->bus_width
== 8) {
409 uint8_t *data8
= data
;
410 *data8
= data32
& 0xff;
411 } else if (nand
->bus_width
== 16) {
412 uint16_t *data16
= data
;
413 *data16
= data32
& 0xffff;
415 LOG_ERROR("BUG: bus_width neither 8 nor 16 bit");
416 return ERROR_NAND_OPERATION_FAILED
;
423 static int lpc3180_write_page(struct nand_device
*nand
,
430 struct lpc3180_nand_controller
*lpc3180_info
= nand
->controller_priv
;
431 struct target
*target
= nand
->target
;
434 uint8_t *page_buffer
;
436 if (target
->state
!= TARGET_HALTED
) {
437 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
438 return ERROR_NAND_OPERATION_FAILED
;
441 if (lpc3180_info
->selected_controller
== LPC3180_NO_CONTROLLER
) {
442 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
443 return ERROR_NAND_OPERATION_FAILED
;
444 } else if (lpc3180_info
->selected_controller
== LPC3180_MLC_CONTROLLER
) {
446 int quarter
, num_quarters
;
449 LOG_ERROR("LPC3180 MLC controller can't write OOB data only");
450 return ERROR_NAND_OPERATION_NOT_SUPPORTED
;
453 if (oob
&& (oob_size
> 24)) {
454 LOG_ERROR("LPC3180 MLC controller can't write more "
455 "than 6 bytes for each quarter's OOB data");
456 return ERROR_NAND_OPERATION_NOT_SUPPORTED
;
459 if (data_size
> (uint32_t)nand
->page_size
) {
460 LOG_ERROR("data size exceeds page size");
461 return ERROR_NAND_OPERATION_NOT_SUPPORTED
;
464 /* MLC_CMD = sequential input */
465 target_write_u32(target
, 0x200b8000, NAND_CMD_SEQIN
);
467 page_buffer
= malloc(512);
468 oob_buffer
= malloc(6);
470 if (nand
->page_size
== 512) {
471 /* MLC_ADDR = 0x0 (one column cycle) */
472 target_write_u32(target
, 0x200b8004, 0x0);
475 target_write_u32(target
, 0x200b8004, page
& 0xff);
476 target_write_u32(target
, 0x200b8004, (page
>> 8) & 0xff);
478 if (nand
->address_cycles
== 4)
479 target_write_u32(target
, 0x200b8004, (page
>> 16) & 0xff);
481 /* MLC_ADDR = 0x0 (two column cycles) */
482 target_write_u32(target
, 0x200b8004, 0x0);
483 target_write_u32(target
, 0x200b8004, 0x0);
486 target_write_u32(target
, 0x200b8004, page
& 0xff);
487 target_write_u32(target
, 0x200b8004, (page
>> 8) & 0xff);
490 /* when using the MLC controller, we have to treat a large page device
491 * as being made out of four quarters, each the size of a small page device
493 num_quarters
= (nand
->page_size
== 2048) ? 4 : 1;
495 for (quarter
= 0; quarter
< num_quarters
; quarter
++) {
496 int thisrun_data_size
= (data_size
> 512) ? 512 : data_size
;
497 int thisrun_oob_size
= (oob_size
> 6) ? 6 : oob_size
;
499 memset(page_buffer
, 0xff, 512);
501 memcpy(page_buffer
, data
, thisrun_data_size
);
502 data_size
-= thisrun_data_size
;
503 data
+= thisrun_data_size
;
506 memset(oob_buffer
, 0xff, 6);
508 memcpy(oob_buffer
, oob
, thisrun_oob_size
);
509 oob_size
-= thisrun_oob_size
;
510 oob
+= thisrun_oob_size
;
513 /* write MLC_ECC_ENC_REG to start encode cycle */
514 target_write_u32(target
, 0x200b8008, 0x0);
516 target_write_memory(target
, 0x200a8000,
517 4, 128, page_buffer
);
518 target_write_memory(target
, 0x200a8000,
521 /* write MLC_ECC_AUTO_ENC_REG to start auto encode */
522 target_write_u32(target
, 0x200b8010, 0x0);
524 if (!lpc3180_controller_ready(nand
, 1000)) {
525 LOG_ERROR("timeout while waiting for completion of auto encode cycle");
528 return ERROR_NAND_OPERATION_FAILED
;
532 /* MLC_CMD = auto program command */
533 target_write_u32(target
, 0x200b8000, NAND_CMD_PAGEPROG
);
535 retval
= nand_read_status(nand
, &status
);
536 if (retval
!= ERROR_OK
) {
537 LOG_ERROR("couldn't read status");
540 return ERROR_NAND_OPERATION_FAILED
;
543 if (status
& NAND_STATUS_FAIL
) {
544 LOG_ERROR("write operation didn't pass, status: 0x%2.2x", status
);
547 return ERROR_NAND_OPERATION_FAILED
;
552 } else if (lpc3180_info
->selected_controller
== LPC3180_SLC_CONTROLLER
) {
554 /**********************************************************************
555 * Write both SLC NAND flash page main area and spare area.
557 * ------------------------------------------
558 * | 512 bytes main | 16 bytes spare |
559 * ------------------------------------------
561 * ------------------------------------------
562 * | 2048 bytes main | 64 bytes spare |
563 * ------------------------------------------
564 * If DMA & ECC enabled, then the ECC generated for the 1st 256-byte
565 * data is written to the 3rd word of the spare area. The ECC
566 * generated for the 2nd 256-byte data is written to the 4th word
567 * of the spare area. The ECC generated for the 3rd 256-byte data is
568 * written to the 7th word of the spare area. The ECC generated
569 * for the 4th 256-byte data is written to the 8th word of the
570 * spare area and so on.
572 **********************************************************************/
574 int i
= 0, target_mem_base
;
575 uint8_t *ecc_flash_buffer
;
576 struct working_area
*pworking_area
;
578 if (lpc3180_info
->is_bulk
) {
581 /*if oob only mode is active original method is used as SLC
582 *controller hangs during DMA interworking. Anyway the code supports
583 *the oob only mode below. */
584 return nand_write_page_raw(nand
,
591 retval
= nand_page_command(nand
, page
, NAND_CMD_SEQIN
, !data
);
592 if (ERROR_OK
!= retval
)
595 /* allocate a working area */
596 if (target
->working_area_size
< (uint32_t) nand
->page_size
+ 0x200) {
597 LOG_ERROR("Reserve at least 0x%x physical target working area",
598 nand
->page_size
+ 0x200);
599 return ERROR_FLASH_OPERATION_FAILED
;
601 if (target
->working_area_phys
%4) {
603 "Reserve the physical target working area at word boundary");
604 return ERROR_FLASH_OPERATION_FAILED
;
606 if (target_alloc_working_area(target
, target
->working_area_size
,
607 &pworking_area
) != ERROR_OK
) {
608 LOG_ERROR("no working area specified, can't read LPC internal flash");
609 return ERROR_FLASH_OPERATION_FAILED
;
611 target_mem_base
= target
->working_area_phys
;
613 if (nand
->page_size
== 2048)
614 page_buffer
= malloc(2048);
616 page_buffer
= malloc(512);
618 ecc_flash_buffer
= malloc(64);
620 /* SLC_CFG = 0x (Force nCE assert, DMA ECC enabled, ECC enabled, DMA burst
621 *enabled, DMA write to SLC, WIDTH = bus_width) */
622 target_write_u32(target
, 0x20020014, 0x3c);
625 /* set DMA LLI-s in target memory and in DMA*/
626 for (i
= 0; i
< nand
->page_size
/0x100; i
++) {
629 /* -------LLI for 256 byte block---------
630 * DMACC0SrcAddr = SRAM */
631 target_write_u32(target
,
632 target_mem_base
+0+i
*32,
633 target_mem_base
+DATA_OFFS
+i
*256);
635 target_write_u32(target
,
637 target_mem_base
+DATA_OFFS
);
638 /* DMACCxDestAddr = SLC_DMA_DATA */
639 target_write_u32(target
, target_mem_base
+4+i
*32, 0x20020038);
641 target_write_u32(target
, 0x31000104, 0x20020038);
642 /* DMACCxLLI = next element */
643 tmp
= (target_mem_base
+(1+i
*2)*16)&0xfffffffc;
644 target_write_u32(target
, target_mem_base
+8+i
*32, tmp
);
646 target_write_u32(target
, 0x31000108, tmp
);
647 /* DMACCxControl = TransferSize =64, Source burst size =16,
648 * Destination burst size = 16, Source transfer width = 32 bit,
649 * Destination transfer width = 32 bit, Source AHB master select = M0,
650 * Destination AHB master select = M0, Source increment = 1,
651 * Destination increment = 0, Terminal count interrupt enable bit = 0*/
652 target_write_u32(target
,
653 target_mem_base
+12+i
*32,
654 0x40 | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 1<<26 |
657 target_write_u32(target
,
659 0x40 | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 1<<26 |
662 /* -------LLI for 3 byte ECC---------
663 * DMACC0SrcAddr = SLC_ECC*/
664 target_write_u32(target
, target_mem_base
+16+i
*32, 0x20020034);
665 /* DMACCxDestAddr = SRAM */
666 target_write_u32(target
,
667 target_mem_base
+20+i
*32,
668 target_mem_base
+SPARE_OFFS
+8+16*(i
>>1)+(i
%2)*4);
669 /* DMACCxLLI = next element */
670 tmp
= (target_mem_base
+(2+i
*2)*16)&0xfffffffc;
671 target_write_u32(target
, target_mem_base
+24+i
*32, tmp
);
672 /* DMACCxControl = TransferSize =1, Source burst size =4,
673 * Destination burst size = 4, Source transfer width = 32 bit,
674 * Destination transfer width = 32 bit, Source AHB master select = M0,
675 * Destination AHB master select = M0, Source increment = 0,
676 * Destination increment = 1, Terminal count interrupt enable bit = 0*/
677 target_write_u32(target
,
678 target_mem_base
+28+i
*32,
679 0x01 | 1<<12 | 1<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 0<<26 | 1<<27 | 0<<
682 } else if (data
&& oob
) {
683 /* -------LLI for 512 or 2048 bytes page---------
684 * DMACC0SrcAddr = SRAM */
685 target_write_u32(target
, target_mem_base
, target_mem_base
+DATA_OFFS
);
686 target_write_u32(target
, 0x31000100, target_mem_base
+DATA_OFFS
);
687 /* DMACCxDestAddr = SLC_DMA_DATA */
688 target_write_u32(target
, target_mem_base
+4, 0x20020038);
689 target_write_u32(target
, 0x31000104, 0x20020038);
690 /* DMACCxLLI = next element */
691 target_write_u32(target
,
693 (target_mem_base
+32)&0xfffffffc);
694 target_write_u32(target
, 0x31000108,
695 (target_mem_base
+32)&0xfffffffc);
696 /* DMACCxControl = TransferSize =512 or 128, Source burst size =16,
697 * Destination burst size = 16, Source transfer width = 32 bit,
698 * Destination transfer width = 32 bit, Source AHB master select = M0,
699 * Destination AHB master select = M0, Source increment = 1,
700 * Destination increment = 0, Terminal count interrupt enable bit = 0*/
701 target_write_u32(target
,
704 2048 ? 512 : 128) | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 |
705 1<<26 | 0<<27 | 0<<31);
706 target_write_u32(target
,
709 2048 ? 512 : 128) | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 |
710 1<<26 | 0<<27 | 0<<31);
712 } else if (!data
&& oob
)
715 /* -------LLI for spare area---------
716 * DMACC0SrcAddr = SRAM*/
717 target_write_u32(target
, target_mem_base
+0+i
*32, target_mem_base
+SPARE_OFFS
);
719 target_write_u32(target
, 0x31000100, target_mem_base
+SPARE_OFFS
);
720 /* DMACCxDestAddr = SLC_DMA_DATA */
721 target_write_u32(target
, target_mem_base
+4+i
*32, 0x20020038);
723 target_write_u32(target
, 0x31000104, 0x20020038);
724 /* DMACCxLLI = next element = NULL */
725 target_write_u32(target
, target_mem_base
+8+i
*32, 0);
727 target_write_u32(target
, 0x31000108, 0);
728 /* DMACCxControl = TransferSize =16 for large page or 4 for small page,
729 * Source burst size =16, Destination burst size = 16, Source transfer width = 32 bit,
730 * Destination transfer width = 32 bit, Source AHB master select = M0,
731 * Destination AHB master select = M0, Source increment = 1,
732 * Destination increment = 0, Terminal count interrupt enable bit = 0*/
733 target_write_u32(target
,
734 target_mem_base
+12+i
*32,
736 2048 ? 0x10 : 0x04) | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 1<<26 |
739 target_write_u32(target
, 0x3100010c,
740 (nand
->page_size
== 2048 ?
741 0x10 : 0x04) | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 |
742 0<<25 | 1<<26 | 0<<27 | 0<<31);
744 memset(ecc_flash_buffer
, 0xff, 64);
746 memcpy(ecc_flash_buffer
, oob
, oob_size
);
747 target_write_memory(target
,
748 target_mem_base
+SPARE_OFFS
,
754 memset(page_buffer
, 0xff, nand
->page_size
== 2048 ? 2048 : 512);
755 memcpy(page_buffer
, data
, data_size
);
756 target_write_memory(target
,
757 target_mem_base
+DATA_OFFS
,
759 nand
->page_size
== 2048 ? 512 : 128,
764 free(ecc_flash_buffer
);
766 /* Enable DMA after channel set up !
767 LLI only works when DMA is the flow controller!
769 /* DMACCxConfig= E=1, SrcPeripheral = 1 (SLC), DestPeripheral = 1 (SLC),
770 *FlowCntrl = 2 (Pher -> Mem, DMA), IE = 0, ITC = 0, L= 0, H=0*/
771 target_write_u32(target
,
773 1 | 1<<1 | 1<<6 | 2<<11 | 0<<14 | 0<<15 | 0<<16 | 0<<18);
775 /* SLC_CTRL = 3 (START DMA), ECC_CLEAR */
776 target_write_u32(target
, 0x20020010, 0x3);
778 /* SLC_ICR = 2, INT_TC_CLR, clear pending TC*/
779 target_write_u32(target
, 0x20020028, 2);
783 target_write_u32(target
, 0x20020030,
784 (nand
->page_size
== 2048 ? 0x10 : 0x04));
786 target_write_u32(target
, 0x20020030,
787 (nand
->page_size
== 2048 ? 0x840 : 0x210));
789 nand_write_finish(nand
);
791 if (!lpc3180_tc_ready(nand
, 1000)) {
792 LOG_ERROR("timeout while waiting for completion of DMA");
793 return ERROR_NAND_OPERATION_FAILED
;
796 target_free_working_area(target
, pworking_area
);
798 LOG_INFO("Page = 0x%" PRIx32
" was written.", page
);
801 return nand_write_page_raw(nand
, page
, data
, data_size
, oob
, oob_size
);
807 static int lpc3180_read_page(struct nand_device
*nand
,
814 struct lpc3180_nand_controller
*lpc3180_info
= nand
->controller_priv
;
815 struct target
*target
= nand
->target
;
816 uint8_t *page_buffer
;
818 if (target
->state
!= TARGET_HALTED
) {
819 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
820 return ERROR_NAND_OPERATION_FAILED
;
823 if (lpc3180_info
->selected_controller
== LPC3180_NO_CONTROLLER
) {
824 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
825 return ERROR_NAND_OPERATION_FAILED
;
826 } else if (lpc3180_info
->selected_controller
== LPC3180_MLC_CONTROLLER
) {
828 uint32_t page_bytes_done
= 0;
829 uint32_t oob_bytes_done
= 0;
833 if (oob
&& (oob_size
> 6)) {
834 LOG_ERROR("LPC3180 MLC controller can't read more than 6 bytes of OOB data");
835 return ERROR_NAND_OPERATION_NOT_SUPPORTED
;
839 if (data_size
> (uint32_t)nand
->page_size
) {
840 LOG_ERROR("data size exceeds page size");
841 return ERROR_NAND_OPERATION_NOT_SUPPORTED
;
844 if (nand
->page_size
== 2048) {
845 page_buffer
= malloc(2048);
846 oob_buffer
= malloc(64);
848 page_buffer
= malloc(512);
849 oob_buffer
= malloc(16);
853 /* MLC_CMD = Read OOB
854 * we can use the READOOB command on both small and large page devices,
855 * as the controller translates the 0x50 command to a 0x0 with appropriate
856 * positioning of the serial buffer read pointer
858 target_write_u32(target
, 0x200b8000, NAND_CMD_READOOB
);
860 /* MLC_CMD = Read0 */
861 target_write_u32(target
, 0x200b8000, NAND_CMD_READ0
);
864 if (nand
->page_size
== 512) {
866 * MLC_ADDR = 0x0 (one column cycle) */
867 target_write_u32(target
, 0x200b8004, 0x0);
870 target_write_u32(target
, 0x200b8004, page
& 0xff);
871 target_write_u32(target
, 0x200b8004, (page
>> 8) & 0xff);
873 if (nand
->address_cycles
== 4)
874 target_write_u32(target
, 0x200b8004, (page
>> 16) & 0xff);
877 * MLC_ADDR = 0x0 (two column cycles) */
878 target_write_u32(target
, 0x200b8004, 0x0);
879 target_write_u32(target
, 0x200b8004, 0x0);
882 target_write_u32(target
, 0x200b8004, page
& 0xff);
883 target_write_u32(target
, 0x200b8004, (page
>> 8) & 0xff);
885 /* MLC_CMD = Read Start */
886 target_write_u32(target
, 0x200b8000, NAND_CMD_READSTART
);
889 while (page_bytes_done
< (uint32_t)nand
->page_size
) {
890 /* MLC_ECC_AUTO_DEC_REG = dummy */
891 target_write_u32(target
, 0x200b8014, 0xaa55aa55);
893 if (!lpc3180_controller_ready(nand
, 1000)) {
894 LOG_ERROR("timeout while waiting for completion of auto decode cycle");
897 return ERROR_NAND_OPERATION_FAILED
;
900 target_read_u32(target
, 0x200b8048, &mlc_isr
);
903 if (mlc_isr
& 0x40) {
904 LOG_ERROR("uncorrectable error detected: 0x%2.2x",
908 return ERROR_NAND_OPERATION_FAILED
;
911 LOG_WARNING("%i symbol error detected and corrected",
912 ((int)(((mlc_isr
& 0x30) >> 4) + 1)));
916 target_read_memory(target
,
920 page_buffer
+ page_bytes_done
);
923 target_read_memory(target
,
927 oob_buffer
+ oob_bytes_done
);
929 page_bytes_done
+= 512;
930 oob_bytes_done
+= 16;
934 memcpy(data
, page_buffer
, data_size
);
937 memcpy(oob
, oob_buffer
, oob_size
);
941 } else if (lpc3180_info
->selected_controller
== LPC3180_SLC_CONTROLLER
) {
943 /**********************************************************************
944 * Read both SLC NAND flash page main area and spare area.
946 * ------------------------------------------
947 * | 512 bytes main | 16 bytes spare |
948 * ------------------------------------------
950 * ------------------------------------------
951 * | 2048 bytes main | 64 bytes spare |
952 * ------------------------------------------
953 * If DMA & ECC enabled, then the ECC generated for the 1st 256-byte
954 * data is compared with the 3rd word of the spare area. The ECC
955 * generated for the 2nd 256-byte data is compared with the 4th word
956 * of the spare area. The ECC generated for the 3rd 256-byte data is
957 * compared with the 7th word of the spare area. The ECC generated
958 * for the 4th 256-byte data is compared with the 8th word of the
959 * spare area and so on.
961 **********************************************************************/
963 int retval
, i
, target_mem_base
;
964 uint8_t *ecc_hw_buffer
;
965 uint8_t *ecc_flash_buffer
;
966 struct working_area
*pworking_area
;
968 if (lpc3180_info
->is_bulk
) {
970 /* read always the data and also oob areas*/
972 retval
= nand_page_command(nand
, page
, NAND_CMD_READ0
, 0);
973 if (ERROR_OK
!= retval
)
976 /* allocate a working area */
977 if (target
->working_area_size
< (uint32_t) nand
->page_size
+ 0x200) {
978 LOG_ERROR("Reserve at least 0x%x physical target working area",
979 nand
->page_size
+ 0x200);
980 return ERROR_FLASH_OPERATION_FAILED
;
982 if (target
->working_area_phys
%4) {
984 "Reserve the physical target working area at word boundary");
985 return ERROR_FLASH_OPERATION_FAILED
;
987 if (target_alloc_working_area(target
, target
->working_area_size
,
988 &pworking_area
) != ERROR_OK
) {
989 LOG_ERROR("no working area specified, can't read LPC internal flash");
990 return ERROR_FLASH_OPERATION_FAILED
;
992 target_mem_base
= target
->working_area_phys
;
994 if (nand
->page_size
== 2048)
995 page_buffer
= malloc(2048);
997 page_buffer
= malloc(512);
999 ecc_hw_buffer
= malloc(32);
1000 ecc_flash_buffer
= malloc(64);
1002 /* SLC_CFG = 0x (Force nCE assert, DMA ECC enabled, ECC enabled, DMA burst
1003 *enabled, DMA read from SLC, WIDTH = bus_width) */
1004 target_write_u32(target
, 0x20020014, 0x3e);
1006 /* set DMA LLI-s in target memory and in DMA*/
1007 for (i
= 0; i
< nand
->page_size
/0x100; i
++) {
1009 /* -------LLI for 256 byte block---------
1010 * DMACC0SrcAddr = SLC_DMA_DATA*/
1011 target_write_u32(target
, target_mem_base
+0+i
*32, 0x20020038);
1013 target_write_u32(target
, 0x31000100, 0x20020038);
1014 /* DMACCxDestAddr = SRAM */
1015 target_write_u32(target
,
1016 target_mem_base
+4+i
*32,
1017 target_mem_base
+DATA_OFFS
+i
*256);
1019 target_write_u32(target
,
1021 target_mem_base
+DATA_OFFS
);
1022 /* DMACCxLLI = next element */
1023 tmp
= (target_mem_base
+(1+i
*2)*16)&0xfffffffc;
1024 target_write_u32(target
, target_mem_base
+8+i
*32, tmp
);
1026 target_write_u32(target
, 0x31000108, tmp
);
1027 /* DMACCxControl = TransferSize =64, Source burst size =16,
1028 * Destination burst size = 16, Source transfer width = 32 bit,
1029 * Destination transfer width = 32 bit, Source AHB master select = M0,
1030 * Destination AHB master select = M0, Source increment = 0,
1031 * Destination increment = 1, Terminal count interrupt enable bit = 0*/
1032 target_write_u32(target
,
1033 target_mem_base
+12+i
*32,
1034 0x40 | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 0<<26 | 1<<27 | 0<<
1037 target_write_u32(target
,
1039 0x40 | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 0<<26 | 1<<27 | 0<<
1042 /* -------LLI for 3 byte ECC---------
1043 * DMACC0SrcAddr = SLC_ECC*/
1044 target_write_u32(target
, target_mem_base
+16+i
*32, 0x20020034);
1045 /* DMACCxDestAddr = SRAM */
1046 target_write_u32(target
,
1047 target_mem_base
+20+i
*32,
1048 target_mem_base
+ECC_OFFS
+i
*4);
1049 /* DMACCxLLI = next element */
1050 tmp
= (target_mem_base
+(2+i
*2)*16)&0xfffffffc;
1051 target_write_u32(target
, target_mem_base
+24+i
*32, tmp
);
1052 /* DMACCxControl = TransferSize =1, Source burst size =4,
1053 * Destination burst size = 4, Source transfer width = 32 bit,
1054 * Destination transfer width = 32 bit, Source AHB master select = M0,
1055 * Destination AHB master select = M0, Source increment = 0,
1056 * Destination increment = 1, Terminal count interrupt enable bit = 0*/
1057 target_write_u32(target
,
1058 target_mem_base
+28+i
*32,
1059 0x01 | 1<<12 | 1<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 0<<26 | 1<<27 | 0<<
1063 /* -------LLI for spare area---------
1064 * DMACC0SrcAddr = SLC_DMA_DATA*/
1065 target_write_u32(target
, target_mem_base
+0+i
*32, 0x20020038);
1066 /* DMACCxDestAddr = SRAM */
1067 target_write_u32(target
, target_mem_base
+4+i
*32, target_mem_base
+SPARE_OFFS
);
1068 /* DMACCxLLI = next element = NULL */
1069 target_write_u32(target
, target_mem_base
+8+i
*32, 0);
1070 /* DMACCxControl = TransferSize =16 for large page or 4 for small page,
1071 * Source burst size =16, Destination burst size = 16, Source transfer width = 32 bit,
1072 * Destination transfer width = 32 bit, Source AHB master select = M0,
1073 * Destination AHB master select = M0, Source increment = 0,
1074 * Destination increment = 1, Terminal count interrupt enable bit = 0*/
1075 target_write_u32(target
,
1076 target_mem_base
+ 12 + i
* 32,
1077 (nand
->page_size
== 2048 ? 0x10 : 0x04) | 3<<12 | 3<<15 | 2<<18 | 2<<21 |
1078 0<<24 | 0<<25 | 0<<26 | 1<<27 | 0<<31);
1080 /* Enable DMA after channel set up !
1081 LLI only works when DMA is the flow controller!
1083 /* DMACCxConfig= E=1, SrcPeripheral = 1 (SLC), DestPeripheral = 1 (SLC),
1084 *FlowCntrl = 2 (Pher-> Mem, DMA), IE = 0, ITC = 0, L= 0, H=0*/
1085 target_write_u32(target
,
1087 1 | 1<<1 | 1<<6 | 2<<11 | 0<<14 | 0<<15 | 0<<16 | 0<<18);
1089 /* SLC_CTRL = 3 (START DMA), ECC_CLEAR */
1090 target_write_u32(target
, 0x20020010, 0x3);
1092 /* SLC_ICR = 2, INT_TC_CLR, clear pending TC*/
1093 target_write_u32(target
, 0x20020028, 2);
1096 target_write_u32(target
, 0x20020030,
1097 (nand
->page_size
== 2048 ? 0x840 : 0x210));
1099 if (!lpc3180_tc_ready(nand
, 1000)) {
1100 LOG_ERROR("timeout while waiting for completion of DMA");
1102 free(ecc_hw_buffer
);
1103 free(ecc_flash_buffer
);
1104 target_free_working_area(target
, pworking_area
);
1105 return ERROR_NAND_OPERATION_FAILED
;
1109 target_read_memory(target
,
1110 target_mem_base
+DATA_OFFS
,
1112 nand
->page_size
== 2048 ? 512 : 128,
1114 memcpy(data
, page_buffer
, data_size
);
1116 LOG_INFO("Page = 0x%" PRIx32
" was read.", page
);
1118 /* check hw generated ECC for each 256 bytes block with the saved
1119 *ECC in flash spare area*/
1120 int idx
= nand
->page_size
/0x200;
1121 target_read_memory(target
,
1122 target_mem_base
+SPARE_OFFS
,
1126 target_read_memory(target
,
1127 target_mem_base
+ECC_OFFS
,
1131 for (i
= 0; i
< idx
; i
++) {
1132 if ((0x00ffffff & *(uint32_t *)(void *)(ecc_hw_buffer
+i
*8)) !=
1133 (0x00ffffff & *(uint32_t *)(void *)(ecc_flash_buffer
+8+i
*16)))
1135 "ECC mismatch at 256 bytes size block= %d at page= 0x%" PRIx32
,
1137 if ((0x00ffffff & *(uint32_t *)(void *)(ecc_hw_buffer
+4+i
*8)) !=
1138 (0x00ffffff & *(uint32_t *)(void *)(ecc_flash_buffer
+12+i
*16)))
1140 "ECC mismatch at 256 bytes size block= %d at page= 0x%" PRIx32
,
1146 memcpy(oob
, ecc_flash_buffer
, oob_size
);
1149 free(ecc_hw_buffer
);
1150 free(ecc_flash_buffer
);
1152 target_free_working_area(target
, pworking_area
);
1155 return nand_read_page_raw(nand
, page
, data
, data_size
, oob
, oob_size
);
1161 static int lpc3180_controller_ready(struct nand_device
*nand
, int timeout
)
1163 struct lpc3180_nand_controller
*lpc3180_info
= nand
->controller_priv
;
1164 struct target
*target
= nand
->target
;
1166 if (target
->state
!= TARGET_HALTED
) {
1167 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
1168 return ERROR_NAND_OPERATION_FAILED
;
1171 LOG_DEBUG("lpc3180_controller_ready count start=%d", timeout
);
1174 if (lpc3180_info
->selected_controller
== LPC3180_MLC_CONTROLLER
) {
1177 /* Read MLC_ISR, wait for controller to become ready */
1178 target_read_u8(target
, 0x200b8048, &status
);
1181 LOG_DEBUG("lpc3180_controller_ready count=%d",
1185 } else if (lpc3180_info
->selected_controller
== LPC3180_SLC_CONTROLLER
) {
1188 /* Read SLC_STAT and check READY bit */
1189 target_read_u32(target
, 0x20020018, &status
);
1192 LOG_DEBUG("lpc3180_controller_ready count=%d",
1199 } while (timeout
-- > 0);
1204 static int lpc3180_nand_ready(struct nand_device
*nand
, int timeout
)
1206 struct lpc3180_nand_controller
*lpc3180_info
= nand
->controller_priv
;
1207 struct target
*target
= nand
->target
;
1209 if (target
->state
!= TARGET_HALTED
) {
1210 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
1211 return ERROR_NAND_OPERATION_FAILED
;
1214 LOG_DEBUG("lpc3180_nand_ready count start=%d", timeout
);
1217 if (lpc3180_info
->selected_controller
== LPC3180_MLC_CONTROLLER
) {
1218 uint8_t status
= 0x0;
1220 /* Read MLC_ISR, wait for NAND flash device to become ready */
1221 target_read_u8(target
, 0x200b8048, &status
);
1224 LOG_DEBUG("lpc3180_nand_ready count end=%d",
1228 } else if (lpc3180_info
->selected_controller
== LPC3180_SLC_CONTROLLER
) {
1229 uint32_t status
= 0x0;
1231 /* Read SLC_STAT and check READY bit */
1232 target_read_u32(target
, 0x20020018, &status
);
1235 LOG_DEBUG("lpc3180_nand_ready count end=%d",
1242 } while (timeout
-- > 0);
1247 static int lpc3180_tc_ready(struct nand_device
*nand
, int timeout
)
1249 struct lpc3180_nand_controller
*lpc3180_info
= nand
->controller_priv
;
1250 struct target
*target
= nand
->target
;
1252 if (target
->state
!= TARGET_HALTED
) {
1253 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
1254 return ERROR_NAND_OPERATION_FAILED
;
1257 LOG_DEBUG("lpc3180_tc_ready count start=%d",
1261 if (lpc3180_info
->selected_controller
== LPC3180_SLC_CONTROLLER
) {
1262 uint32_t status
= 0x0;
1263 /* Read SLC_INT_STAT and check INT_TC_STAT bit */
1264 target_read_u32(target
, 0x2002001c, &status
);
1267 LOG_DEBUG("lpc3180_tc_ready count=%d",
1274 } while (timeout
-- > 0);
1279 COMMAND_HANDLER(handle_lpc3180_select_command
)
1281 struct lpc3180_nand_controller
*lpc3180_info
= NULL
;
1282 char *selected
[] = {
1286 if ((CMD_ARGC
< 1) || (CMD_ARGC
> 3))
1287 return ERROR_COMMAND_SYNTAX_ERROR
;
1290 COMMAND_PARSE_NUMBER(uint
, CMD_ARGV
[0], num
);
1291 struct nand_device
*nand
= get_nand_device_by_num(num
);
1293 command_print(CMD
, "nand device '#%s' is out of bounds", CMD_ARGV
[0]);
1297 lpc3180_info
= nand
->controller_priv
;
1299 if (CMD_ARGC
>= 2) {
1300 if (strcmp(CMD_ARGV
[1], "mlc") == 0)
1301 lpc3180_info
->selected_controller
= LPC3180_MLC_CONTROLLER
;
1302 else if (strcmp(CMD_ARGV
[1], "slc") == 0) {
1303 lpc3180_info
->selected_controller
= LPC3180_SLC_CONTROLLER
;
1304 if (CMD_ARGC
== 3 && strcmp(CMD_ARGV
[2], "bulk") == 0)
1305 lpc3180_info
->is_bulk
= 1;
1307 lpc3180_info
->is_bulk
= 0;
1309 return ERROR_COMMAND_SYNTAX_ERROR
;
1312 if (lpc3180_info
->selected_controller
== LPC3180_MLC_CONTROLLER
)
1313 command_print(CMD
, "%s controller selected",
1314 selected
[lpc3180_info
->selected_controller
]);
1317 lpc3180_info
->is_bulk
? "%s controller selected bulk mode is available" :
1318 "%s controller selected bulk mode is not available",
1319 selected
[lpc3180_info
->selected_controller
]);
1324 static const struct command_registration lpc3180_exec_command_handlers
[] = {
1327 .handler
= handle_lpc3180_select_command
,
1328 .mode
= COMMAND_EXEC
,
1330 "select MLC or SLC controller (default is MLC), SLC can be set to bulk mode",
1331 .usage
= "bank_id ['mlc'|'slc' ['bulk'] ]",
1333 COMMAND_REGISTRATION_DONE
1335 static const struct command_registration lpc3180_command_handler
[] = {
1338 .mode
= COMMAND_ANY
,
1339 .help
= "LPC3180 NAND flash controller commands",
1341 .chain
= lpc3180_exec_command_handlers
,
1343 COMMAND_REGISTRATION_DONE
1346 struct nand_flash_controller lpc3180_nand_controller
= {
1348 .commands
= lpc3180_command_handler
,
1349 .nand_device_command
= lpc3180_nand_device_command
,
1350 .init
= lpc3180_init
,
1351 .reset
= lpc3180_reset
,
1352 .command
= lpc3180_command
,
1353 .address
= lpc3180_address
,
1354 .write_data
= lpc3180_write_data
,
1355 .read_data
= lpc3180_read_data
,
1356 .write_page
= lpc3180_write_page
,
1357 .read_page
= lpc3180_read_page
,
1358 .nand_ready
= lpc3180_nand_ready
,
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