2 /***************************************************************************
3 * Copyright (C) 2009 by Alexei Babich *
4 * Rezonans plc., Chelyabinsk, Russia *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
24 * Freescale iMX3* OpenOCD NAND Flash controller support.
26 * Many thanks to Ben Dooks for writing s3c24xx driver.
30 driver tested with STMicro NAND512W3A @imx31
31 tested "nand probe #", "nand erase # 0 #", "nand dump # file 0 #", "nand write # file 0"
32 get_next_halfword_from_sram_buffer() not tested
40 static const char target_not_halted_err_msg
[] =
41 "target must be halted to use mx3 NAND flash controller";
42 static const char data_block_size_err_msg
[] =
43 "minimal granularity is one half-word, %" PRId32
" is incorrect";
44 static const char sram_buffer_bounds_err_msg
[] =
45 "trying to access out of SRAM buffer bound (addr=0x%" PRIx32
")";
46 static const char get_status_register_err_msg
[] = "can't get NAND status";
47 static uint32_t in_sram_address
;
48 unsigned char sign_of_sequental_byte_read
;
50 static int test_iomux_settings (struct target
* target
, uint32_t value
,
51 uint32_t mask
, const char *text
);
52 static int initialize_nf_controller (struct nand_device
*nand
);
53 static int get_next_byte_from_sram_buffer (struct target
* target
, uint8_t * value
);
54 static int get_next_halfword_from_sram_buffer (struct target
* target
,
56 static int poll_for_complete_op (struct target
* target
, const char *text
);
57 static int validate_target_state (struct nand_device
*nand
);
58 static int do_data_output (struct nand_device
*nand
);
60 static int imx31_command (struct nand_device
*nand
, uint8_t command
);
61 static int imx31_address (struct nand_device
*nand
, uint8_t address
);
62 static int imx31_controller_ready (struct nand_device
*nand
, int tout
);
64 NAND_DEVICE_COMMAND_HANDLER(imx31_nand_device_command
)
66 struct mx3_nf_controller
*mx3_nf_info
;
67 mx3_nf_info
= malloc (sizeof (struct mx3_nf_controller
));
68 if (mx3_nf_info
== NULL
)
70 LOG_ERROR ("no memory for nand controller");
74 nand
->controller_priv
= mx3_nf_info
;
76 mx3_nf_info
->target
= get_target (args
[1]);
77 if (mx3_nf_info
->target
== NULL
)
79 LOG_ERROR ("target '%s' not defined", args
[1]);
84 LOG_ERROR ("use \"nand device imx31 target noecc|hwecc\"");
88 * check hwecc requirements
92 hwecc_needed
= strcmp (args
[2], "hwecc");
93 if (hwecc_needed
== 0)
95 mx3_nf_info
->flags
.hw_ecc_enabled
= 1;
99 mx3_nf_info
->flags
.hw_ecc_enabled
= 0;
103 mx3_nf_info
->optype
= MX3_NF_DATAOUT_PAGE
;
104 mx3_nf_info
->fin
= MX3_NF_FIN_NONE
;
105 mx3_nf_info
->flags
.target_little_endian
=
106 (mx3_nf_info
->target
->endianness
== TARGET_LITTLE_ENDIAN
);
108 * testing host endianess
112 if (*(char *) &x
== 1)
114 mx3_nf_info
->flags
.host_little_endian
= 1;
118 mx3_nf_info
->flags
.host_little_endian
= 0;
124 static int imx31_init (struct nand_device
*nand
)
126 struct mx3_nf_controller
*mx3_nf_info
= nand
->controller_priv
;
127 struct target
*target
= mx3_nf_info
->target
;
131 * validate target state
133 int validate_target_result
;
134 validate_target_result
= validate_target_state(nand
);
135 if (validate_target_result
!= ERROR_OK
)
137 return validate_target_result
;
142 uint16_t buffsize_register_content
;
143 target_read_u16 (target
, MX3_NF_BUFSIZ
, &buffsize_register_content
);
144 mx3_nf_info
->flags
.one_kb_sram
= !(buffsize_register_content
& 0x000f);
148 uint32_t pcsr_register_content
;
149 target_read_u32 (target
, MX3_PCSR
, &pcsr_register_content
);
150 if (!nand
->bus_width
)
153 (pcsr_register_content
& 0x80000000) ? 16 : 8;
157 pcsr_register_content
|=
158 ((nand
->bus_width
== 16) ? 0x80000000 : 0x00000000);
159 target_write_u32 (target
, MX3_PCSR
, pcsr_register_content
);
162 if (!nand
->page_size
)
165 (pcsr_register_content
& 0x40000000) ? 2048 : 512;
169 pcsr_register_content
|=
170 ((nand
->page_size
== 2048) ? 0x40000000 : 0x00000000);
171 target_write_u32 (target
, MX3_PCSR
, pcsr_register_content
);
173 if (mx3_nf_info
->flags
.one_kb_sram
&& (nand
->page_size
== 2048))
176 ("NAND controller have only 1 kb SRAM, so pagesize 2048 is incompatible with it");
181 uint32_t cgr_register_content
;
182 target_read_u32 (target
, MX3_CCM_CGR2
, &cgr_register_content
);
183 if (!(cgr_register_content
& 0x00000300))
185 LOG_ERROR ("clock gating to EMI disabled");
191 uint32_t gpr_register_content
;
192 target_read_u32 (target
, MX3_GPR
, &gpr_register_content
);
193 if (gpr_register_content
& 0x00000060)
195 LOG_ERROR ("pins mode overrided by GPR");
202 * testing IOMUX settings; must be in "functional-mode output and
203 * functional-mode input" mode
206 test_iomux
= ERROR_OK
;
208 test_iomux_settings (target
, 0x43fac0c0, 0x7f7f7f00, "d0,d1,d2");
210 test_iomux_settings (target
, 0x43fac0c4, 0x7f7f7f7f, "d3,d4,d5,d6");
212 test_iomux_settings (target
, 0x43fac0c8, 0x0000007f, "d7");
213 if (nand
->bus_width
== 16)
216 test_iomux_settings (target
, 0x43fac0c8, 0x7f7f7f00,
219 test_iomux_settings (target
, 0x43fac0cc, 0x7f7f7f7f,
222 test_iomux_settings (target
, 0x43fac0d0, 0x0000007f, "d15");
225 test_iomux_settings (target
, 0x43fac0d0, 0x7f7f7f00,
228 test_iomux_settings (target
, 0x43fac0d4, 0x7f7f7f7f,
229 "nfwe,nfre,nfale,nfcle");
230 if (test_iomux
!= ERROR_OK
)
236 initialize_nf_controller (nand
);
240 uint16_t nand_status_content
;
242 retval
|= imx31_command (nand
, NAND_CMD_STATUS
);
243 retval
|= imx31_address (nand
, 0x00);
244 retval
|= do_data_output (nand
);
245 if (retval
!= ERROR_OK
)
247 LOG_ERROR (get_status_register_err_msg
);
250 target_read_u16 (target
, MX3_NF_MAIN_BUFFER0
, &nand_status_content
);
251 if (!(nand_status_content
& 0x0080))
254 * is host-big-endian correctly ??
256 LOG_INFO ("NAND read-only");
257 mx3_nf_info
->flags
.nand_readonly
= 1;
261 mx3_nf_info
->flags
.nand_readonly
= 0;
267 static int imx31_read_data (struct nand_device
*nand
, void *data
)
269 struct mx3_nf_controller
*mx3_nf_info
= nand
->controller_priv
;
270 struct target
*target
= mx3_nf_info
->target
;
273 * validate target state
275 int validate_target_result
;
276 validate_target_result
= validate_target_state (nand
);
277 if (validate_target_result
!= ERROR_OK
)
279 return validate_target_result
;
285 * get data from nand chip
287 int try_data_output_from_nand_chip
;
288 try_data_output_from_nand_chip
= do_data_output (nand
);
289 if (try_data_output_from_nand_chip
!= ERROR_OK
)
291 return try_data_output_from_nand_chip
;
295 if (nand
->bus_width
== 16)
297 get_next_halfword_from_sram_buffer (target
, data
);
301 get_next_byte_from_sram_buffer (target
, data
);
307 static int imx31_write_data (struct nand_device
*nand
, uint16_t data
)
309 LOG_ERROR ("write_data() not implemented");
310 return ERROR_NAND_OPERATION_FAILED
;
313 static int imx31_nand_ready (struct nand_device
*nand
, int timeout
)
315 return imx31_controller_ready (nand
, timeout
);
318 static int imx31_register_commands (struct command_context
*cmd_ctx
)
323 static int imx31_reset (struct nand_device
*nand
)
326 * validate target state
328 int validate_target_result
;
329 validate_target_result
= validate_target_state (nand
);
330 if (validate_target_result
!= ERROR_OK
)
332 return validate_target_result
;
334 initialize_nf_controller (nand
);
338 static int imx31_command (struct nand_device
*nand
, uint8_t command
)
340 struct mx3_nf_controller
*mx3_nf_info
= nand
->controller_priv
;
341 struct target
*target
= mx3_nf_info
->target
;
344 * validate target state
346 int validate_target_result
;
347 validate_target_result
= validate_target_state (nand
);
348 if (validate_target_result
!= ERROR_OK
)
350 return validate_target_result
;
356 case NAND_CMD_READOOB
:
357 command
= NAND_CMD_READ0
;
358 in_sram_address
= MX3_NF_SPARE_BUFFER0
; /* set read point for
360 * read_block_data() to
365 command
= NAND_CMD_READ0
;
367 * offset == one half of page size
370 MX3_NF_MAIN_BUFFER0
+ (nand
->page_size
>> 1);
372 in_sram_address
= MX3_NF_MAIN_BUFFER0
;
375 target_write_u16 (target
, MX3_NF_FCMD
, command
);
377 * start command input operation (set MX3_NF_BIT_OP_DONE==0)
379 target_write_u16 (target
, MX3_NF_CFG2
, MX3_NF_BIT_OP_FCI
);
382 poll_result
= poll_for_complete_op (target
, "command");
383 if (poll_result
!= ERROR_OK
)
389 * reset cursor to begin of the buffer
391 sign_of_sequental_byte_read
= 0;
394 case NAND_CMD_READID
:
395 mx3_nf_info
->optype
= MX3_NF_DATAOUT_NANDID
;
396 mx3_nf_info
->fin
= MX3_NF_FIN_DATAOUT
;
398 case NAND_CMD_STATUS
:
399 mx3_nf_info
->optype
= MX3_NF_DATAOUT_NANDSTATUS
;
400 mx3_nf_info
->fin
= MX3_NF_FIN_DATAOUT
;
403 mx3_nf_info
->fin
= MX3_NF_FIN_DATAOUT
;
404 mx3_nf_info
->optype
= MX3_NF_DATAOUT_PAGE
;
407 mx3_nf_info
->optype
= MX3_NF_DATAOUT_PAGE
;
412 static int imx31_address (struct nand_device
*nand
, uint8_t address
)
414 struct mx3_nf_controller
*mx3_nf_info
= nand
->controller_priv
;
415 struct target
*target
= mx3_nf_info
->target
;
418 * validate target state
420 int validate_target_result
;
421 validate_target_result
= validate_target_state (nand
);
422 if (validate_target_result
!= ERROR_OK
)
424 return validate_target_result
;
428 target_write_u16 (target
, MX3_NF_FADDR
, address
);
430 * start address input operation (set MX3_NF_BIT_OP_DONE==0)
432 target_write_u16 (target
, MX3_NF_CFG2
, MX3_NF_BIT_OP_FAI
);
435 poll_result
= poll_for_complete_op (target
, "address");
436 if (poll_result
!= ERROR_OK
)
444 static int imx31_controller_ready (struct nand_device
*nand
, int tout
)
446 uint16_t poll_complete_status
;
447 struct mx3_nf_controller
*mx3_nf_info
= nand
->controller_priv
;
448 struct target
*target
= mx3_nf_info
->target
;
452 * validate target state
454 int validate_target_result
;
455 validate_target_result
= validate_target_state (nand
);
456 if (validate_target_result
!= ERROR_OK
)
458 return validate_target_result
;
464 target_read_u16 (target
, MX3_NF_CFG2
, &poll_complete_status
);
465 if (poll_complete_status
& MX3_NF_BIT_OP_DONE
)
475 static int imx31_write_page (struct nand_device
*nand
, uint32_t page
,
476 uint8_t * data
, uint32_t data_size
, uint8_t * oob
,
479 struct mx3_nf_controller
*mx3_nf_info
= nand
->controller_priv
;
480 struct target
*target
= mx3_nf_info
->target
;
484 LOG_ERROR (data_block_size_err_msg
, data_size
);
485 return ERROR_NAND_OPERATION_FAILED
;
489 LOG_ERROR (data_block_size_err_msg
, oob_size
);
490 return ERROR_NAND_OPERATION_FAILED
;
494 LOG_ERROR ("nothing to program");
495 return ERROR_NAND_OPERATION_FAILED
;
499 * validate target state
502 retval
= validate_target_state (nand
);
503 if (retval
!= ERROR_OK
)
509 int retval
= ERROR_OK
;
510 retval
|= imx31_command(nand
, NAND_CMD_SEQIN
);
511 retval
|= imx31_address(nand
, 0x00);
512 retval
|= imx31_address(nand
, page
& 0xff);
513 retval
|= imx31_address(nand
, (page
>> 8) & 0xff);
514 if (nand
->address_cycles
>= 4)
516 retval
|= imx31_address (nand
, (page
>> 16) & 0xff);
517 if (nand
->address_cycles
>= 5)
519 retval
|= imx31_address (nand
, (page
>> 24) & 0xff);
522 target_write_buffer (target
, MX3_NF_MAIN_BUFFER0
, data_size
, data
);
525 if (mx3_nf_info
->flags
.hw_ecc_enabled
)
528 * part of spare block will be overrided by hardware
532 ("part of spare block will be overrided by hardware ECC generator");
534 target_write_buffer (target
, MX3_NF_SPARE_BUFFER0
, oob_size
,
538 * start data input operation (set MX3_NF_BIT_OP_DONE==0)
540 target_write_u16 (target
, MX3_NF_CFG2
, MX3_NF_BIT_OP_FDI
);
543 poll_result
= poll_for_complete_op (target
, "data input");
544 if (poll_result
!= ERROR_OK
)
549 retval
|= imx31_command (nand
, NAND_CMD_PAGEPROG
);
550 if (retval
!= ERROR_OK
)
556 * check status register
559 uint16_t nand_status_content
;
561 retval
|= imx31_command(nand
, NAND_CMD_STATUS
);
562 retval
|= imx31_address(nand
, 0x00);
563 retval
|= do_data_output(nand
);
564 if (retval
!= ERROR_OK
)
566 LOG_ERROR (get_status_register_err_msg
);
569 target_read_u16 (target
, MX3_NF_MAIN_BUFFER0
, &nand_status_content
);
570 if (nand_status_content
& 0x0001)
573 * is host-big-endian correctly ??
575 return ERROR_NAND_OPERATION_FAILED
;
582 static int imx31_read_page (struct nand_device
*nand
, uint32_t page
,
583 uint8_t * data
, uint32_t data_size
, uint8_t * oob
,
586 struct mx3_nf_controller
*mx3_nf_info
= nand
->controller_priv
;
587 struct target
*target
= mx3_nf_info
->target
;
591 LOG_ERROR (data_block_size_err_msg
, data_size
);
592 return ERROR_NAND_OPERATION_FAILED
;
596 LOG_ERROR (data_block_size_err_msg
, oob_size
);
597 return ERROR_NAND_OPERATION_FAILED
;
602 * validate target state
605 retval
= validate_target_state(nand
);
606 if (retval
!= ERROR_OK
)
612 int retval
= ERROR_OK
;
613 retval
|= imx31_command(nand
, NAND_CMD_READ0
);
614 retval
|= imx31_address(nand
, 0x00);
615 retval
|= imx31_address(nand
, page
& 0xff);
616 retval
|= imx31_address(nand
, (page
>> 8) & 0xff);
617 if (nand
->address_cycles
>= 4)
619 retval
|= imx31_address(nand
, (page
>> 16) & 0xff);
620 if (nand
->address_cycles
>= 5)
622 retval
|= imx31_address(nand
, (page
>> 24) & 0xff);
623 retval
|= imx31_command(nand
, NAND_CMD_READSTART
);
626 retval
|= do_data_output (nand
);
627 if (retval
!= ERROR_OK
)
634 target_read_buffer (target
, MX3_NF_MAIN_BUFFER0
, data_size
,
639 target_read_buffer (target
, MX3_NF_SPARE_BUFFER0
, oob_size
,
646 static int test_iomux_settings (struct target
* target
, uint32_t address
,
647 uint32_t mask
, const char *text
)
649 uint32_t register_content
;
650 target_read_u32 (target
, address
, ®ister_content
);
651 if ((register_content
& mask
) != (0x12121212 & mask
))
653 LOG_ERROR ("IOMUX for {%s} is bad", text
);
659 static int initialize_nf_controller (struct nand_device
*nand
)
661 struct mx3_nf_controller
*mx3_nf_info
= nand
->controller_priv
;
662 struct target
*target
= mx3_nf_info
->target
;
664 * resets NAND flash controller in zero time ? I dont know.
666 target_write_u16 (target
, MX3_NF_CFG1
, MX3_NF_BIT_RESET_EN
);
669 work_mode
= MX3_NF_BIT_INT_DIS
; /* disable interrupt */
670 if (target
->endianness
== TARGET_BIG_ENDIAN
)
672 work_mode
|= MX3_NF_BIT_BE_EN
;
674 if (mx3_nf_info
->flags
.hw_ecc_enabled
)
676 work_mode
|= MX3_NF_BIT_ECC_EN
;
678 target_write_u16 (target
, MX3_NF_CFG1
, work_mode
);
681 * unlock SRAM buffer for write; 2 mean "Unlock", other values means "Lock"
683 target_write_u16 (target
, MX3_NF_BUFCFG
, 2);
686 target_read_u16 (target
, MX3_NF_FWP
, &temp
);
687 if ((temp
& 0x0007) == 1)
689 LOG_ERROR ("NAND flash is tight-locked, reset needed");
695 * unlock NAND flash for write
697 target_write_u16 (target
, MX3_NF_FWP
, 4);
698 target_write_u16 (target
, MX3_NF_LOCKSTART
, 0x0000);
699 target_write_u16 (target
, MX3_NF_LOCKEND
, 0xFFFF);
701 * 0x0000 means that first SRAM buffer @0xB800_0000 will be used
703 target_write_u16 (target
, MX3_NF_BUFADDR
, 0x0000);
705 * address of SRAM buffer
707 in_sram_address
= MX3_NF_MAIN_BUFFER0
;
708 sign_of_sequental_byte_read
= 0;
712 static int get_next_byte_from_sram_buffer (struct target
* target
, uint8_t * value
)
714 static uint8_t even_byte
= 0;
718 if (sign_of_sequental_byte_read
== 0)
722 if (in_sram_address
> MX3_NF_LAST_BUFFER_ADDR
)
724 LOG_ERROR (sram_buffer_bounds_err_msg
, in_sram_address
);
726 sign_of_sequental_byte_read
= 0;
728 return ERROR_NAND_OPERATION_FAILED
;
733 target_read_u16 (target
, in_sram_address
, &temp
);
738 in_sram_address
+= 2;
742 *value
= temp
& 0xff;
746 sign_of_sequental_byte_read
= 1;
750 static int get_next_halfword_from_sram_buffer (struct target
* target
,
753 if (in_sram_address
> MX3_NF_LAST_BUFFER_ADDR
)
755 LOG_ERROR (sram_buffer_bounds_err_msg
, in_sram_address
);
757 return ERROR_NAND_OPERATION_FAILED
;
761 target_read_u16 (target
, in_sram_address
, value
);
762 in_sram_address
+= 2;
767 static int poll_for_complete_op (struct target
* target
, const char *text
)
769 uint16_t poll_complete_status
;
770 for (int poll_cycle_count
= 0; poll_cycle_count
< 100; poll_cycle_count
++)
773 target_read_u16 (target
, MX3_NF_CFG2
, &poll_complete_status
);
774 if (poll_complete_status
& MX3_NF_BIT_OP_DONE
)
779 if (!(poll_complete_status
& MX3_NF_BIT_OP_DONE
))
781 LOG_ERROR ("%s sending timeout", text
);
782 return ERROR_NAND_OPERATION_FAILED
;
787 static int validate_target_state (struct nand_device
*nand
)
789 struct mx3_nf_controller
*mx3_nf_info
= nand
->controller_priv
;
790 struct target
*target
= mx3_nf_info
->target
;
792 if (target
->state
!= TARGET_HALTED
)
794 LOG_ERROR (target_not_halted_err_msg
);
795 return ERROR_NAND_OPERATION_FAILED
;
798 if (mx3_nf_info
->flags
.target_little_endian
!=
799 (target
->endianness
== TARGET_LITTLE_ENDIAN
))
802 * endianness changed after NAND controller probed
804 return ERROR_NAND_OPERATION_FAILED
;
809 static int do_data_output (struct nand_device
*nand
)
811 struct mx3_nf_controller
*mx3_nf_info
= nand
->controller_priv
;
812 struct target
*target
= mx3_nf_info
->target
;
813 switch (mx3_nf_info
->fin
)
815 case MX3_NF_FIN_DATAOUT
:
817 * start data output operation (set MX3_NF_BIT_OP_DONE==0)
819 target_write_u16 (target
, MX3_NF_CFG2
,
820 MX3_NF_BIT_DATAOUT_TYPE (mx3_nf_info
->
824 poll_result
= poll_for_complete_op (target
, "data output");
825 if (poll_result
!= ERROR_OK
)
830 mx3_nf_info
->fin
= MX3_NF_FIN_NONE
;
834 if ((mx3_nf_info
->optype
== MX3_NF_DATAOUT_PAGE
)
835 && mx3_nf_info
->flags
.hw_ecc_enabled
)
838 target_read_u16 (target
, MX3_NF_ECCSTATUS
, &ecc_status
);
839 switch (ecc_status
& 0x000c)
843 ("main area readed with 1 (correctable) error");
847 ("main area readed with more than 1 (incorrectable) error");
848 return ERROR_NAND_OPERATION_FAILED
;
851 switch (ecc_status
& 0x0003)
855 ("spare area readed with 1 (correctable) error");
859 ("main area readed with more than 1 (incorrectable) error");
860 return ERROR_NAND_OPERATION_FAILED
;
865 case MX3_NF_FIN_NONE
:
871 struct nand_flash_controller imx31_nand_flash_controller
= {
873 .nand_device_command
= &imx31_nand_device_command
,
874 .register_commands
= &imx31_register_commands
,
876 .reset
= &imx31_reset
,
877 .command
= &imx31_command
,
878 .address
= &imx31_address
,
879 .write_data
= &imx31_write_data
,
880 .read_data
= &imx31_read_data
,
881 .write_page
= &imx31_write_page
,
882 .read_page
= &imx31_read_page
,
883 .controller_ready
= &imx31_controller_ready
,
884 .nand_ready
= &imx31_nand_ready
,
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