1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Gheorghe Guran (atlas) *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the *
15 * GNU General public License for more details. *
17 * You should have received a copy of the GNU General public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ****************************************************************************/
23 /***************************************************************************************************************************************************************************************
25 * New flash setup command:
27 * flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>]
29 * <ext_freq_khz> - MUST be used if clock is from external source,
30 * CAN be used if main oscillator frequency is known (recomended)
32 * flash bank at91sam7 0x00100000 0 0 4 0 0 AT91SAM7XC256 1 16 64 256 3 25000 ==== RECOMENDED ============
33 * flash bank at91sam7 0 0 0 0 0 0 0 0 0 0 0 0 25000 (auto-detection, except for clock) ==== RECOMENDED ============
34 * flash bank at91sam7 0x00100000 0 0 4 0 0 AT91SAM7XC256 1 16 64 256 3 0 ==== NOT RECOMENDED !!! ====
35 * flash bank at91sam7 0 0 0 0 0 (old style, full auto-detection) ==== NOT RECOMENDED !!! ====
36 ****************************************************************************************************************************************************************************************/
43 #include "binarybuffer.h"
46 static int at91sam7_register_commands(struct command_context_s
*cmd_ctx
);
47 static int at91sam7_flash_bank_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct flash_bank_s
*bank
);
48 static int at91sam7_erase(struct flash_bank_s
*bank
, int first
, int last
);
49 static int at91sam7_protect(struct flash_bank_s
*bank
, int set
, int first
, int last
);
50 static int at91sam7_write(struct flash_bank_s
*bank
, u8
*buffer
, u32 offset
, u32 count
);
51 static int at91sam7_probe(struct flash_bank_s
*bank
);
52 //static int at91sam7_auto_probe(struct flash_bank_s *bank);
53 static int at91sam7_erase_check(struct flash_bank_s
*bank
);
54 static int at91sam7_protect_check(struct flash_bank_s
*bank
);
55 static int at91sam7_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
);
57 static u32
at91sam7_get_flash_status(target_t
*target
, int bank_number
);
58 static void at91sam7_set_flash_mode(flash_bank_t
*bank
, int mode
);
59 static u32
at91sam7_wait_status_busy(flash_bank_t
*bank
, u32 waitbits
, int timeout
);
60 static int at91sam7_flash_command(struct flash_bank_s
*bank
, u8 cmd
, u16 pagen
);
61 static int at91sam7_handle_gpnvm_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
63 flash_driver_t at91sam7_flash
=
66 .register_commands
= at91sam7_register_commands
,
67 .flash_bank_command
= at91sam7_flash_bank_command
,
68 .erase
= at91sam7_erase
,
69 .protect
= at91sam7_protect
,
70 .write
= at91sam7_write
,
71 .probe
= at91sam7_probe
,
72 .auto_probe
= at91sam7_probe
,
73 .erase_check
= at91sam7_erase_check
,
74 .protect_check
= at91sam7_protect_check
,
78 static u32 MC_FMR
[4] = { 0xFFFFFF60, 0xFFFFFF70, 0xFFFFFF80, 0xFFFFFF90 };
79 static u32 MC_FCR
[4] = { 0xFFFFFF64, 0xFFFFFF74, 0xFFFFFF84, 0xFFFFFF94 };
80 static u32 MC_FSR
[4] = { 0xFFFFFF68, 0xFFFFFF78, 0xFFFFFF88, 0xFFFFFF98 };
82 static char * EPROC
[8]= {"Unknown","ARM946-E","ARM7TDMI","Unknown","ARM920T","ARM926EJ-S","Unknown","Unknown"};
85 static long SRAMSIZ
[16] = {
105 static int at91sam7_register_commands(struct command_context_s
*cmd_ctx
)
107 command_t
*at91sam7_cmd
= register_command(cmd_ctx
, NULL
, "at91sam7", NULL
, COMMAND_ANY
, NULL
);
109 register_command(cmd_ctx
, at91sam7_cmd
, "gpnvm", at91sam7_handle_gpnvm_command
, COMMAND_EXEC
,
110 "at91sam7 gpnvm <bit> set|clear, set or clear one gpnvm bit");
114 static u32
at91sam7_get_flash_status(target_t
*target
, int bank_number
)
117 target_read_u32(target
, MC_FSR
[bank_number
], &fsr
);
122 /* Read clock configuration and set at91sam7_info->mck_freq */
123 static void at91sam7_read_clock_info(flash_bank_t
*bank
)
125 at91sam7_flash_bank_t
*at91sam7_info
= bank
->driver_priv
;
126 target_t
*target
= bank
->target
;
127 u32 mckr
, mcfr
, pllr
, mor
;
128 unsigned long tmp
= 0, mainfreq
;
130 /* Read Clock Generator Main Oscillator Register */
131 target_read_u32(target
, CKGR_MOR
, &mor
);
132 /* Read Clock Generator Main Clock Frequency Register */
133 target_read_u32(target
, CKGR_MCFR
, &mcfr
);
134 /* Read Master Clock Register*/
135 target_read_u32(target
, PMC_MCKR
, &mckr
);
136 /* Read Clock Generator PLL Register */
137 target_read_u32(target
, CKGR_PLLR
, &pllr
);
139 at91sam7_info
->mck_valid
= 0;
140 at91sam7_info
->mck_freq
= 0;
141 switch (mckr
& PMC_MCKR_CSS
)
143 case 0: /* Slow Clock */
144 at91sam7_info
->mck_valid
= 1;
148 case 1: /* Main Clock */
149 if ((mcfr
& CKGR_MCFR_MAINRDY
) &&
150 (at91sam7_info
->ext_freq
== 0))
152 at91sam7_info
->mck_valid
= 1;
153 tmp
= RC_FREQ
/ 16ul * (mcfr
& 0xffff);
155 else if (at91sam7_info
->ext_freq
!= 0)
157 at91sam7_info
->mck_valid
= 1;
158 tmp
= at91sam7_info
->ext_freq
;
162 case 2: /* Reserved */
165 case 3: /* PLL Clock */
166 if ((mcfr
& CKGR_MCFR_MAINRDY
) &&
167 (at91sam7_info
->ext_freq
== 0))
169 target_read_u32(target
, CKGR_PLLR
, &pllr
);
170 if (!(pllr
& CKGR_PLLR_DIV
))
172 at91sam7_info
->mck_valid
= 1;
173 mainfreq
= RC_FREQ
/ 16ul * (mcfr
& 0xffff);
174 /* Integer arithmetic should have sufficient precision
175 * as long as PLL is properly configured. */
176 tmp
= mainfreq
/ (pllr
& CKGR_PLLR_DIV
)*
177 (((pllr
& CKGR_PLLR_MUL
) >> 16) + 1);
179 else if ((at91sam7_info
->ext_freq
!= 0) &&
180 ((pllr
&CKGR_PLLR_DIV
) != 0))
182 at91sam7_info
->mck_valid
= 1;
183 tmp
= at91sam7_info
->ext_freq
/ (pllr
&CKGR_PLLR_DIV
)*
184 (((pllr
& CKGR_PLLR_MUL
) >> 16) + 1);
189 /* Prescaler adjust */
190 if ( (((mckr
& PMC_MCKR_PRES
) >> 2) == 7) || (tmp
== 0) )
192 at91sam7_info
->mck_valid
= 0;
193 at91sam7_info
->mck_freq
= 0;
195 else if (((mckr
& PMC_MCKR_PRES
) >> 2) != 0)
196 at91sam7_info
->mck_freq
= tmp
>> ((mckr
& PMC_MCKR_PRES
) >> 2);
198 at91sam7_info
->mck_freq
= tmp
;
201 /* Setup the timimg registers for nvbits or normal flash */
202 static void at91sam7_set_flash_mode(flash_bank_t
*bank
, int mode
)
204 u32 fmr
, fmcn
= 0, fws
= 0;
205 at91sam7_flash_bank_t
*at91sam7_info
= bank
->driver_priv
;
206 target_t
*target
= bank
->target
;
208 if (mode
&& (mode
!= at91sam7_info
->flashmode
))
210 /* Always round up (ceil) */
211 if (mode
== FMR_TIMING_NVBITS
)
213 if (at91sam7_info
->cidr_arch
== 0x60)
215 /* AT91SAM7A3 uses master clocks in 100 ns */
216 fmcn
= (at91sam7_info
->mck_freq
/10000000ul)+1;
220 /* master clocks in 1uS for ARCH 0x7 types */
221 fmcn
= (at91sam7_info
->mck_freq
/1000000ul)+1;
224 else if (mode
== FMR_TIMING_FLASH
)
226 /* main clocks in 1.5uS */
227 fmcn
= (at91sam7_info
->mck_freq
/1000000ul)+
228 (at91sam7_info
->mck_freq
/2000000ul)+1;
231 /* hard overclocking */
235 /* Only allow fmcn=0 if clock period is > 30 us = 33kHz. */
236 if (at91sam7_info
->mck_freq
<= 33333ul)
238 /* Only allow fws=0 if clock frequency is < 30 MHz. */
239 if (at91sam7_info
->mck_freq
> 30000000ul)
242 LOG_DEBUG("fmcn[%i]: %i", bank
->bank_number
, fmcn
);
243 fmr
= fmcn
<< 16 | fws
<< 8;
244 target_write_u32(target
, MC_FMR
[bank
->bank_number
], fmr
);
247 at91sam7_info
->flashmode
= mode
;
250 static u32
at91sam7_wait_status_busy(flash_bank_t
*bank
, u32 waitbits
, int timeout
)
254 while ((!((status
= at91sam7_get_flash_status(bank
->target
, bank
->bank_number
)) & waitbits
)) && (timeout
-- > 0))
256 LOG_DEBUG("status[%i]: 0x%x", bank
->bank_number
, status
);
260 LOG_DEBUG("status[%i]: 0x%x", bank
->bank_number
, status
);
264 LOG_ERROR("status register: 0x%x", status
);
266 LOG_ERROR("Lock Error Bit Detected, Operation Abort");
268 LOG_ERROR("Invalid command and/or bad keyword, Operation Abort");
270 LOG_ERROR("Security Bit Set, Operation Abort");
276 /* Send one command to the AT91SAM flash controller */
277 static int at91sam7_flash_command(struct flash_bank_s
*bank
, u8 cmd
, u16 pagen
)
280 at91sam7_flash_bank_t
*at91sam7_info
= bank
->driver_priv
;
281 target_t
*target
= bank
->target
;
283 fcr
= (0x5A<<24) | ((pagen
&0x3FF)<<8) | cmd
;
284 target_write_u32(target
, MC_FCR
[bank
->bank_number
], fcr
);
285 LOG_DEBUG("Flash command: 0x%x, flash bank: %i, page number: %u", fcr
, bank
->bank_number
+1, pagen
);
287 if ((at91sam7_info
->cidr_arch
== 0x60)&&((cmd
==SLB
)|(cmd
==CLB
)))
289 /* Lock bit manipulation on AT91SAM7A3 waits for FC_FSR bit 1, EOL */
290 if (at91sam7_wait_status_busy(bank
, MC_FSR_EOL
, 10)&0x0C)
292 return ERROR_FLASH_OPERATION_FAILED
;
297 if (at91sam7_wait_status_busy(bank
, MC_FSR_FRDY
, 10)&0x0C)
299 return ERROR_FLASH_OPERATION_FAILED
;
305 /* Read device id register, main clock frequency register and fill in driver info structure */
306 static int at91sam7_read_part_info(struct flash_bank_s
*bank
)
308 flash_bank_t
*t_bank
= bank
;
309 at91sam7_flash_bank_t
*at91sam7_info
;
310 target_t
*target
= t_bank
->target
;
318 u16 pages_per_sector
= 0;
322 u32 base_address
= 0;
323 char *target_name
= "Unknown";
325 at91sam7_info
= t_bank
->driver_priv
;
327 if (at91sam7_info
->cidr
!= 0)
329 /* flash already configured, update clock and check for protected sectors */
330 flash_bank_t
*fb
= bank
;
335 /* re-calculate master clock frequency */
336 at91sam7_read_clock_info(t_bank
);
339 at91sam7_set_flash_mode(t_bank
, FMR_TIMING_NONE
);
341 /* check protect state */
342 at91sam7_protect_check(t_bank
);
351 /* Read and parse chip identification register */
352 target_read_u32(target
, DBGU_CIDR
, &cidr
);
355 LOG_WARNING("Cannot identify target as an AT91SAM");
356 return ERROR_FLASH_OPERATION_FAILED
;
359 if (at91sam7_info
->flash_autodetection
== 0)
361 /* banks and sectors are already created, based on data from input file */
362 flash_bank_t
*fb
= bank
;
366 at91sam7_info
= t_bank
->driver_priv
;
368 at91sam7_info
->cidr
= cidr
;
369 at91sam7_info
->cidr_ext
= (cidr
>>31)&0x0001;
370 at91sam7_info
->cidr_nvptyp
= (cidr
>>28)&0x0007;
371 at91sam7_info
->cidr_arch
= (cidr
>>20)&0x00FF;
372 at91sam7_info
->cidr_sramsiz
= (cidr
>>16)&0x000F;
373 at91sam7_info
->cidr_nvpsiz2
= (cidr
>>12)&0x000F;
374 at91sam7_info
->cidr_nvpsiz
= (cidr
>>8)&0x000F;
375 at91sam7_info
->cidr_eproc
= (cidr
>>5)&0x0007;
376 at91sam7_info
->cidr_version
= cidr
&0x001F;
378 /* calculate master clock frequency */
379 at91sam7_read_clock_info(t_bank
);
382 at91sam7_set_flash_mode(t_bank
, FMR_TIMING_NONE
);
384 /* check protect state */
385 at91sam7_protect_check(t_bank
);
394 arch
= (cidr
>>20)&0x00FF;
396 /* check flash size */
397 switch ((cidr
>>8)&0x000F)
402 case FLASH_SIZE_16KB
:
405 pages_per_sector
= 32;
407 base_address
= 0x00100000;
411 target_name
= "AT91SAM7S161/16";
415 case FLASH_SIZE_32KB
:
418 pages_per_sector
= 32;
420 base_address
= 0x00100000;
424 target_name
= "AT91SAM7S321/32";
429 target_name
= "AT91SAM7SE32";
433 case FLASH_SIZE_64KB
:
436 pages_per_sector
= 32;
438 base_address
= 0x00100000;
442 target_name
= "AT91SAM7S64";
446 case FLASH_SIZE_128KB
:
449 pages_per_sector
= 64;
451 base_address
= 0x00100000;
455 target_name
= "AT91SAM7S128";
460 target_name
= "AT91SAM7XC128";
465 target_name
= "AT91SAM7SE128";
470 target_name
= "AT91SAM7X128";
474 case FLASH_SIZE_256KB
:
477 pages_per_sector
= 64;
479 base_address
= 0x00100000;
483 target_name
= "AT91SAM7A3";
488 target_name
= "AT91SAM7S256";
493 target_name
= "AT91SAM7XC256";
498 target_name
= "AT91SAM7SE256";
503 target_name
= "AT91SAM7X256";
507 case FLASH_SIZE_512KB
:
510 pages_per_sector
= 64;
512 base_address
= 0x00100000;
516 target_name
= "AT91SAM7S512";
521 target_name
= "AT91SAM7XC512";
526 target_name
= "AT91SAM7SE512";
531 target_name
= "AT91SAM7X512";
535 case FLASH_SIZE_1024KB
:
538 case FLASH_SIZE_2048KB
:
542 if (strcmp(target_name
, "Unknown") == 0)
544 LOG_ERROR("Target autodetection failed! Please specify target parameters in configuration file");
545 return ERROR_FLASH_OPERATION_FAILED
;
548 ext_freq
= at91sam7_info
->ext_freq
;
550 /* calculate bank size */
551 bank_size
= sectors_num
* pages_per_sector
* page_size
;
553 for (bnk
=0; bnk
<banks_num
; bnk
++)
557 /* create a new flash bank element */
558 flash_bank_t
*fb
= malloc(sizeof(flash_bank_t
));
560 fb
->driver
= &at91sam7_flash
;
561 fb
->driver_priv
= malloc(sizeof(at91sam7_flash_bank_t
));
564 /* link created bank in 'flash_banks' list and redirect t_bank */
569 t_bank
->bank_number
= bnk
;
570 t_bank
->base
= base_address
+ bnk
* bank_size
;
571 t_bank
->size
= bank_size
;
572 t_bank
->chip_width
= 0;
573 t_bank
->bus_width
= 4;
574 t_bank
->num_sectors
= sectors_num
;
576 /* allocate sectors */
577 t_bank
->sectors
= malloc(sectors_num
* sizeof(flash_sector_t
));
578 for (sec
=0; sec
<sectors_num
; sec
++)
580 t_bank
->sectors
[sec
].offset
= sec
* pages_per_sector
* page_size
;
581 t_bank
->sectors
[sec
].size
= pages_per_sector
* page_size
;
582 t_bank
->sectors
[sec
].is_erased
= -1;
583 t_bank
->sectors
[sec
].is_protected
= -1;
586 at91sam7_info
= t_bank
->driver_priv
;
588 at91sam7_info
->cidr
= cidr
;
589 at91sam7_info
->cidr_ext
= (cidr
>>31)&0x0001;
590 at91sam7_info
->cidr_nvptyp
= (cidr
>>28)&0x0007;
591 at91sam7_info
->cidr_arch
= (cidr
>>20)&0x00FF;
592 at91sam7_info
->cidr_sramsiz
= (cidr
>>16)&0x000F;
593 at91sam7_info
->cidr_nvpsiz2
= (cidr
>>12)&0x000F;
594 at91sam7_info
->cidr_nvpsiz
= (cidr
>>8)&0x000F;
595 at91sam7_info
->cidr_eproc
= (cidr
>>5)&0x0007;
596 at91sam7_info
->cidr_version
= cidr
&0x001F;
598 at91sam7_info
->target_name
= target_name
;
599 at91sam7_info
->flashmode
= 0;
600 at91sam7_info
->ext_freq
= ext_freq
;
601 at91sam7_info
->num_nvmbits
= num_nvmbits
;
602 at91sam7_info
->num_nvmbits_on
= 0;
603 at91sam7_info
->pagesize
= page_size
;
604 at91sam7_info
->pages_per_sector
= pages_per_sector
;
606 /* calculate master clock frequency */
607 at91sam7_read_clock_info(t_bank
);
610 at91sam7_set_flash_mode(t_bank
, FMR_TIMING_NONE
);
612 /* check protect state */
613 at91sam7_protect_check(t_bank
);
616 LOG_DEBUG("nvptyp: 0x%3.3x, arch: 0x%4.4x", at91sam7_info
->cidr_nvptyp
, at91sam7_info
->cidr_arch
);
621 static int at91sam7_erase_check(struct flash_bank_s
*bank
)
623 target_t
*target
= bank
->target
;
631 if (bank
->target
->state
!= TARGET_HALTED
)
633 LOG_ERROR("Target not halted");
634 return ERROR_TARGET_NOT_HALTED
;
637 /* Configure the flash controller timing */
638 at91sam7_read_clock_info(bank
);
639 at91sam7_set_flash_mode(bank
, FMR_TIMING_FLASH
);
642 for (nSector
=0; nSector
<bank
->num_sectors
; nSector
++)
644 retval
= target_blank_check_memory(target
, bank
->base
+bank
->sectors
[nSector
].offset
,
645 bank
->sectors
[nSector
].size
, &blank
);
646 if (retval
!= ERROR_OK
)
652 bank
->sectors
[nSector
].is_erased
= 1;
654 bank
->sectors
[nSector
].is_erased
= 0;
662 LOG_USER("Running slow fallback erase check - add working memory");
664 buffer
= malloc(bank
->sectors
[0].size
);
665 for (nSector
=0; nSector
<bank
->num_sectors
; nSector
++)
667 bank
->sectors
[nSector
].is_erased
= 1;
668 retval
= target_read_memory(target
, bank
->base
+bank
->sectors
[nSector
].offset
, 4,
669 bank
->sectors
[nSector
].size
/4, buffer
);
670 if (retval
!= ERROR_OK
)
673 for (nByte
=0; nByte
<bank
->sectors
[nSector
].size
; nByte
++)
675 if (buffer
[nByte
] != 0xFF)
677 bank
->sectors
[nSector
].is_erased
= 0;
687 static int at91sam7_protect_check(struct flash_bank_s
*bank
)
689 u8 lock_pos
, gpnvm_pos
;
692 at91sam7_flash_bank_t
*at91sam7_info
= bank
->driver_priv
;
694 if (at91sam7_info
->cidr
== 0)
696 return ERROR_FLASH_BANK_NOT_PROBED
;
698 if (bank
->target
->state
!= TARGET_HALTED
)
700 LOG_ERROR("Target not halted");
701 return ERROR_TARGET_NOT_HALTED
;
704 status
= at91sam7_get_flash_status(bank
->target
, bank
->bank_number
);
705 at91sam7_info
->lockbits
= (status
>>16);
707 at91sam7_info
->num_lockbits_on
= 0;
708 for (lock_pos
=0; lock_pos
<bank
->num_sectors
; lock_pos
++)
710 if ( ((status
>>(16+lock_pos
))&(0x0001)) == 1)
712 at91sam7_info
->num_lockbits_on
++;
713 bank
->sectors
[lock_pos
].is_protected
= 1;
716 bank
->sectors
[lock_pos
].is_protected
= 0;
719 /* GPNVM and SECURITY bits apply only for MC_FSR of EFC0 */
720 status
= at91sam7_get_flash_status(bank
->target
, 0);
722 at91sam7_info
->securitybit
= (status
>>4)&0x01;
723 at91sam7_info
->nvmbits
= (status
>>8)&0xFF;
725 at91sam7_info
->num_nvmbits_on
= 0;
726 for (gpnvm_pos
=0; gpnvm_pos
<at91sam7_info
->num_nvmbits
; gpnvm_pos
++)
728 if ( ((status
>>(8+gpnvm_pos
))&(0x01)) == 1)
730 at91sam7_info
->num_nvmbits_on
++;
737 /***************************************************************************************************************************************************************************************
738 # flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>]
739 # <ext_freq_khz> - MUST be used if clock is from external source
740 # CAN be used if main oscillator frequency is known
742 # flash bank at91sam7 0x00100000 0 0 4 0 0 AT91SAM7XC256 1 16 64 256 3 25000 ==== RECOMENDED ============
743 # flash bank at91sam7 0 0 0 0 0 0 0 0 0 0 0 0 25000 (auto-detection, except for clock) ==== RECOMENDED ============
744 # flash bank at91sam7 0x00100000 0 0 4 0 0 AT91SAM7XC256 1 16 64 256 3 0 ==== NOT RECOMENDED !!! ====
745 # flash bank at91sam7 0 0 0 0 0 (old style, full auto-detection) ==== NOT RECOMENDED !!! ====
746 ****************************************************************************************************************************************************************************************/
747 static int at91sam7_flash_bank_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct flash_bank_s
*bank
)
749 flash_bank_t
*t_bank
= bank
;
750 at91sam7_flash_bank_t
*at91sam7_info
;
751 target_t
*target
= t_bank
->target
;
762 u16 pages_per_sector
;
770 at91sam7_info
= malloc(sizeof(at91sam7_flash_bank_t
));
771 t_bank
->driver_priv
= at91sam7_info
;
773 /* part wasn't probed for info yet */
774 at91sam7_info
->cidr
= 0;
775 at91sam7_info
->flashmode
= 0;
776 at91sam7_info
->ext_freq
= 0;
777 at91sam7_info
->flash_autodetection
= 0;
781 ext_freq
= atol(args
[13]) * 1000;
782 at91sam7_info
->ext_freq
= ext_freq
;
786 (atoi(args
[4]) == 0) || /* bus width */
787 (atoi(args
[8]) == 0) || /* banks number */
788 (atoi(args
[9]) == 0) || /* sectors per bank */
789 (atoi(args
[10]) == 0) || /* pages per sector */
790 (atoi(args
[11]) == 0) || /* page size */
791 (atoi(args
[12]) == 0)) /* nvmbits number */
793 at91sam7_info
->flash_autodetection
= 1;
797 base_address
= strtoul(args
[1], NULL
, 0);
798 chip_width
= atoi(args
[3]);
799 bus_width
= atoi(args
[4]);
800 banks_num
= atoi(args
[8]);
801 num_sectors
= atoi(args
[9]);
802 pages_per_sector
= atoi(args
[10]);
803 page_size
= atoi(args
[11]);
804 num_nvmbits
= atoi(args
[12]);
806 target_name
= calloc(strlen(args
[7])+1, sizeof(char));
807 strcpy(target_name
, args
[7]);
809 /* calculate bank size */
810 bank_size
= num_sectors
* pages_per_sector
* page_size
;
812 for (bnk
=0; bnk
<banks_num
; bnk
++)
816 /* create a new bank element */
817 flash_bank_t
*fb
= malloc(sizeof(flash_bank_t
));
819 fb
->driver
= &at91sam7_flash
;
820 fb
->driver_priv
= malloc(sizeof(at91sam7_flash_bank_t
));
823 /* link created bank in 'flash_banks' list and redirect t_bank */
828 t_bank
->bank_number
= bnk
;
829 t_bank
->base
= base_address
+ bnk
* bank_size
;
830 t_bank
->size
= bank_size
;
831 t_bank
->chip_width
= chip_width
;
832 t_bank
->bus_width
= bus_width
;
833 t_bank
->num_sectors
= num_sectors
;
835 /* allocate sectors */
836 t_bank
->sectors
= malloc(num_sectors
* sizeof(flash_sector_t
));
837 for (sec
=0; sec
<num_sectors
; sec
++)
839 t_bank
->sectors
[sec
].offset
= sec
* pages_per_sector
* page_size
;
840 t_bank
->sectors
[sec
].size
= pages_per_sector
* page_size
;
841 t_bank
->sectors
[sec
].is_erased
= -1;
842 t_bank
->sectors
[sec
].is_protected
= -1;
845 at91sam7_info
= t_bank
->driver_priv
;
847 at91sam7_info
->target_name
= target_name
;
848 at91sam7_info
->flashmode
= 0;
849 at91sam7_info
->ext_freq
= ext_freq
;
850 at91sam7_info
->num_nvmbits
= num_nvmbits
;
851 at91sam7_info
->num_nvmbits_on
= 0;
852 at91sam7_info
->pagesize
= page_size
;
853 at91sam7_info
->pages_per_sector
= pages_per_sector
;
859 static int at91sam7_erase(struct flash_bank_s
*bank
, int first
, int last
)
861 at91sam7_flash_bank_t
*at91sam7_info
= bank
->driver_priv
;
867 if (at91sam7_info
->cidr
== 0)
869 return ERROR_FLASH_BANK_NOT_PROBED
;
872 if (bank
->target
->state
!= TARGET_HALTED
)
874 LOG_ERROR("Target not halted");
875 return ERROR_TARGET_NOT_HALTED
;
878 if ((first
< 0) || (last
< first
) || (last
>= bank
->num_sectors
))
880 return ERROR_FLASH_SECTOR_INVALID
;
884 if ((first
== 0) && (last
== (bank
->num_sectors
-1)))
889 /* Configure the flash controller timing */
890 at91sam7_read_clock_info(bank
);
891 at91sam7_set_flash_mode(bank
, FMR_TIMING_FLASH
);
895 if (at91sam7_flash_command(bank
, EA
, 0) != ERROR_OK
)
897 return ERROR_FLASH_OPERATION_FAILED
;
902 /* allocate and clean buffer */
903 nbytes
= (last
- first
+ 1) * bank
->sectors
[first
].size
;
904 buffer
= malloc(nbytes
* sizeof(u8
));
905 for (pos
=0; pos
<nbytes
; pos
++)
910 if ( at91sam7_write(bank
, buffer
, bank
->sectors
[first
].offset
, nbytes
) != ERROR_OK
)
912 return ERROR_FLASH_OPERATION_FAILED
;
918 /* mark erased sectors */
919 for (sec
=first
; sec
<=last
; sec
++)
921 bank
->sectors
[sec
].is_erased
= 1;
927 static int at91sam7_protect(struct flash_bank_s
*bank
, int set
, int first
, int last
)
933 at91sam7_flash_bank_t
*at91sam7_info
= bank
->driver_priv
;
935 if (at91sam7_info
->cidr
== 0)
937 return ERROR_FLASH_BANK_NOT_PROBED
;
940 if (bank
->target
->state
!= TARGET_HALTED
)
942 LOG_ERROR("Target not halted");
943 return ERROR_TARGET_NOT_HALTED
;
946 if ((first
< 0) || (last
< first
) || (last
>= bank
->num_sectors
))
948 return ERROR_FLASH_SECTOR_INVALID
;
951 /* Configure the flash controller timing */
952 at91sam7_read_clock_info(bank
);
953 at91sam7_set_flash_mode(bank
, FMR_TIMING_NVBITS
);
955 for (sector
=first
; sector
<=last
; sector
++)
962 /* if we lock a page from one sector then entire sector will be locked, also,
963 * if we unlock a page from a locked sector, entire sector will be unlocked */
964 pagen
= sector
* at91sam7_info
->pages_per_sector
;
966 if (at91sam7_flash_command(bank
, cmd
, pagen
) != ERROR_OK
)
968 return ERROR_FLASH_OPERATION_FAILED
;
972 at91sam7_protect_check(bank
);
977 static int at91sam7_write(struct flash_bank_s
*bank
, u8
*buffer
, u32 offset
, u32 count
)
980 at91sam7_flash_bank_t
*at91sam7_info
= bank
->driver_priv
;
981 target_t
*target
= bank
->target
;
982 u32 dst_min_alignment
, wcount
, bytes_remaining
= count
;
983 u32 first_page
, last_page
, pagen
, buffer_pos
;
985 if (at91sam7_info
->cidr
== 0)
987 return ERROR_FLASH_BANK_NOT_PROBED
;
990 if (bank
->target
->state
!= TARGET_HALTED
)
992 LOG_ERROR("Target not halted");
993 return ERROR_TARGET_NOT_HALTED
;
996 if (offset
+ count
> bank
->size
)
997 return ERROR_FLASH_DST_OUT_OF_BANK
;
999 dst_min_alignment
= at91sam7_info
->pagesize
;
1001 if (offset
% dst_min_alignment
)
1003 LOG_WARNING("offset 0x%x breaks required alignment 0x%x", offset
, dst_min_alignment
);
1004 return ERROR_FLASH_DST_BREAKS_ALIGNMENT
;
1007 if (at91sam7_info
->cidr_arch
== 0)
1008 return ERROR_FLASH_BANK_NOT_PROBED
;
1010 first_page
= offset
/dst_min_alignment
;
1011 last_page
= CEIL(offset
+ count
, dst_min_alignment
);
1013 LOG_DEBUG("first_page: %i, last_page: %i, count %i", first_page
, last_page
, count
);
1015 /* Configure the flash controller timing */
1016 at91sam7_read_clock_info(bank
);
1017 at91sam7_set_flash_mode(bank
, FMR_TIMING_FLASH
);
1019 for (pagen
=first_page
; pagen
<last_page
; pagen
++)
1021 if (bytes_remaining
<dst_min_alignment
)
1022 count
= bytes_remaining
;
1024 count
= dst_min_alignment
;
1025 bytes_remaining
-= count
;
1027 /* Write one block to the PageWriteBuffer */
1028 buffer_pos
= (pagen
-first_page
)*dst_min_alignment
;
1029 wcount
= CEIL(count
,4);
1030 if((retval
= target_write_memory(target
, bank
->base
+pagen
*dst_min_alignment
, 4, wcount
, buffer
+buffer_pos
)) != ERROR_OK
)
1035 /* Send Write Page command to Flash Controller */
1036 if (at91sam7_flash_command(bank
, WP
, pagen
) != ERROR_OK
)
1038 return ERROR_FLASH_OPERATION_FAILED
;
1040 LOG_DEBUG("Write flash bank:%i page number:%i", bank
->bank_number
, pagen
);
1046 static int at91sam7_probe(struct flash_bank_s
*bank
)
1048 /* we can't probe on an at91sam7
1049 * if this is an at91sam7, it has the configured flash */
1052 if (bank
->target
->state
!= TARGET_HALTED
)
1054 LOG_ERROR("Target not halted");
1055 return ERROR_TARGET_NOT_HALTED
;
1058 retval
= at91sam7_read_part_info(bank
);
1059 if (retval
!= ERROR_OK
)
1065 static int at91sam7_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
)
1068 at91sam7_flash_bank_t
*at91sam7_info
= bank
->driver_priv
;
1070 if (at91sam7_info
->cidr
== 0)
1072 return ERROR_FLASH_BANK_NOT_PROBED
;
1075 printed
= snprintf(buf
, buf_size
,
1076 "\n at91sam7 driver information: Chip is %s\n",
1077 at91sam7_info
->target_name
);
1080 buf_size
-= printed
;
1082 printed
= snprintf(buf
, buf_size
,
1083 " Cidr: 0x%8.8x | Arch: 0x%4.4x | Eproc: %s | Version: 0x%3.3x | Flashsize: 0x%8.8x\n",
1084 at91sam7_info
->cidr
, at91sam7_info
->cidr_arch
, EPROC
[at91sam7_info
->cidr_eproc
],
1085 at91sam7_info
->cidr_version
, bank
->size
);
1088 buf_size
-= printed
;
1090 printed
= snprintf(buf
, buf_size
,
1091 " Master clock (estimated): %u KHz | External clock: %u KHz\n",
1092 at91sam7_info
->mck_freq
/ 1000, at91sam7_info
->ext_freq
/ 1000);
1095 buf_size
-= printed
;
1097 printed
= snprintf(buf
, buf_size
,
1098 " Pagesize: %i bytes | Lockbits(%i): %i 0x%4.4x | Pages in lock region: %i \n",
1099 at91sam7_info
->pagesize
, bank
->num_sectors
, at91sam7_info
->num_lockbits_on
,
1100 at91sam7_info
->lockbits
, at91sam7_info
->pages_per_sector
*at91sam7_info
->num_lockbits_on
);
1103 buf_size
-= printed
;
1105 printed
= snprintf(buf
, buf_size
,
1106 " Securitybit: %i | Nvmbits(%i): %i 0x%1.1x\n",
1107 at91sam7_info
->securitybit
, at91sam7_info
->num_nvmbits
,
1108 at91sam7_info
->num_nvmbits_on
, at91sam7_info
->nvmbits
);
1111 buf_size
-= printed
;
1117 * On AT91SAM7S: When the gpnvm bits are set with
1118 * > at91sam7 gpnvm bitnr set
1119 * the changes are not visible in the flash controller status register MC_FSR
1120 * until the processor has been reset.
1121 * On the Olimex board this requires a power cycle.
1122 * Note that the AT91SAM7S has the following errata (doc6175.pdf sec 14.1.3):
1123 * The maximum number of write/erase cycles for Non volatile Memory bits is 100. this includes
1124 * Lock Bits (LOCKx), General Purpose NVM bits (GPNVMx) and the Security Bit.
1126 static int at91sam7_handle_gpnvm_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1132 at91sam7_flash_bank_t
*at91sam7_info
;
1137 command_print(cmd_ctx
, "at91sam7 gpnvm <bit> <set|clear>");
1141 bank
= get_flash_bank_by_num_noprobe(0);
1144 return ERROR_FLASH_BANK_INVALID
;
1146 if (bank
->driver
!= &at91sam7_flash
)
1148 command_print(cmd_ctx
, "not an at91sam7 flash bank '%s'", args
[0]);
1149 return ERROR_FLASH_BANK_INVALID
;
1151 if (bank
->target
->state
!= TARGET_HALTED
)
1153 LOG_ERROR("target has to be halted to perform flash operation");
1154 return ERROR_TARGET_NOT_HALTED
;
1157 if (strcmp(args
[1], "set") == 0)
1161 else if (strcmp(args
[1], "clear") == 0)
1167 return ERROR_COMMAND_SYNTAX_ERROR
;
1170 at91sam7_info
= bank
->driver_priv
;
1171 if (at91sam7_info
->cidr
== 0)
1173 retval
= at91sam7_read_part_info(bank
);
1174 if (retval
!= ERROR_OK
)
1180 bit
= atoi(args
[0]);
1181 if ((bit
< 0) || (bit
>= at91sam7_info
->num_nvmbits
))
1183 command_print(cmd_ctx
, "gpnvm bit '#%s' is out of bounds for target %s", args
[0], at91sam7_info
->target_name
);
1187 /* Configure the flash controller timing */
1188 at91sam7_read_clock_info(bank
);
1189 at91sam7_set_flash_mode(bank
, FMR_TIMING_NVBITS
);
1191 if (at91sam7_flash_command(bank
, flashcmd
, bit
) != ERROR_OK
)
1193 return ERROR_FLASH_OPERATION_FAILED
;
1196 /* GPNVM and SECURITY bits apply only for MC_FSR of EFC0 */
1197 status
= at91sam7_get_flash_status(bank
->target
, 0);
1198 LOG_DEBUG("at91sam7_handle_gpnvm_command: cmd 0x%x, value 0x%x, status 0x%x \n", flashcmd
, bit
, status
);
1200 /* check protect state */
1201 at91sam7_protect_check(bank
);
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