1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Gheorghe Guran (atlas) *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the *
15 * GNU General public License for more details. *
17 * You should have received a copy of the GNU General public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ****************************************************************************/
23 /***************************************************************************
25 * New flash setup command:
27 * flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_id>
28 * [<chip_type> <banks>
29 * <sectors_per_bank> <pages_per_sector>
30 * <page_size> <num_nvmbits>
33 * <ext_freq_khz> - MUST be used if clock is from external source,
34 * CAN be used if main oscillator frequency is known (recommended)
36 * ==== RECOMMENDED (covers clock speed) ============
37 * flash bank at91sam7 0x00100000 0 0 4 $_TARGETNAME AT91SAM7XC256 1 16 64 256 3 25000
38 * (if auto-detect fails; provides clock spec)
39 * flash bank at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 25000
40 * (auto-detect everything except the clock)
41 * ==== NOT RECOMMENDED !!! (clock speed is not configured) ====
42 * flash bank at91sam7 0x00100000 0 0 4 $_TARGETNAME AT91SAM7XC256 1 16 64 256 3 0
43 * (if auto-detect fails)
44 * flash bank at91sam7 0 0 0 0 $_TARGETNAME
45 * (old style, auto-detect everything)
46 ****************************************************************************/
53 #include "binarybuffer.h"
56 static int at91sam7_register_commands(struct command_context_s
*cmd_ctx
);
57 static int at91sam7_flash_bank_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct flash_bank_s
*bank
);
58 static int at91sam7_erase(struct flash_bank_s
*bank
, int first
, int last
);
59 static int at91sam7_protect(struct flash_bank_s
*bank
, int set
, int first
, int last
);
60 static int at91sam7_write(struct flash_bank_s
*bank
, uint8_t *buffer
, uint32_t offset
, uint32_t count
);
61 static int at91sam7_probe(struct flash_bank_s
*bank
);
62 //static int at91sam7_auto_probe(struct flash_bank_s *bank);
63 static int at91sam7_erase_check(struct flash_bank_s
*bank
);
64 static int at91sam7_protect_check(struct flash_bank_s
*bank
);
65 static int at91sam7_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
);
67 static uint32_t at91sam7_get_flash_status(target_t
*target
, int bank_number
);
68 static void at91sam7_set_flash_mode(flash_bank_t
*bank
, int mode
);
69 static uint32_t at91sam7_wait_status_busy(flash_bank_t
*bank
, uint32_t waitbits
, int timeout
);
70 static int at91sam7_flash_command(struct flash_bank_s
*bank
, uint8_t cmd
, uint16_t pagen
);
71 static int at91sam7_handle_gpnvm_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
73 flash_driver_t at91sam7_flash
=
76 .register_commands
= at91sam7_register_commands
,
77 .flash_bank_command
= at91sam7_flash_bank_command
,
78 .erase
= at91sam7_erase
,
79 .protect
= at91sam7_protect
,
80 .write
= at91sam7_write
,
81 .probe
= at91sam7_probe
,
82 .auto_probe
= at91sam7_probe
,
83 .erase_check
= at91sam7_erase_check
,
84 .protect_check
= at91sam7_protect_check
,
88 static uint32_t MC_FMR
[4] = { 0xFFFFFF60, 0xFFFFFF70, 0xFFFFFF80, 0xFFFFFF90 };
89 static uint32_t MC_FCR
[4] = { 0xFFFFFF64, 0xFFFFFF74, 0xFFFFFF84, 0xFFFFFF94 };
90 static uint32_t MC_FSR
[4] = { 0xFFFFFF68, 0xFFFFFF78, 0xFFFFFF88, 0xFFFFFF98 };
92 static char * EPROC
[8]= {"Unknown","ARM946-E","ARM7TDMI","Unknown","ARM920T","ARM926EJ-S","Unknown","Unknown"};
95 static long SRAMSIZ
[16] = {
115 static int at91sam7_register_commands(struct command_context_s
*cmd_ctx
)
117 command_t
*at91sam7_cmd
= register_command(cmd_ctx
, NULL
, "at91sam7", NULL
, COMMAND_ANY
, NULL
);
119 register_command(cmd_ctx
, at91sam7_cmd
, "gpnvm", at91sam7_handle_gpnvm_command
, COMMAND_EXEC
,
120 "at91sam7 gpnvm <bit> set | clear, set or clear one gpnvm bit");
124 static uint32_t at91sam7_get_flash_status(target_t
*target
, int bank_number
)
127 target_read_u32(target
, MC_FSR
[bank_number
], &fsr
);
132 /* Read clock configuration and set at91sam7_info->mck_freq */
133 static void at91sam7_read_clock_info(flash_bank_t
*bank
)
135 at91sam7_flash_bank_t
*at91sam7_info
= bank
->driver_priv
;
136 target_t
*target
= bank
->target
;
137 uint32_t mckr
, mcfr
, pllr
, mor
;
138 unsigned long tmp
= 0, mainfreq
;
140 /* Read Clock Generator Main Oscillator Register */
141 target_read_u32(target
, CKGR_MOR
, &mor
);
142 /* Read Clock Generator Main Clock Frequency Register */
143 target_read_u32(target
, CKGR_MCFR
, &mcfr
);
144 /* Read Master Clock Register*/
145 target_read_u32(target
, PMC_MCKR
, &mckr
);
146 /* Read Clock Generator PLL Register */
147 target_read_u32(target
, CKGR_PLLR
, &pllr
);
149 at91sam7_info
->mck_valid
= 0;
150 at91sam7_info
->mck_freq
= 0;
151 switch (mckr
& PMC_MCKR_CSS
)
153 case 0: /* Slow Clock */
154 at91sam7_info
->mck_valid
= 1;
158 case 1: /* Main Clock */
159 if ((mcfr
& CKGR_MCFR_MAINRDY
) &&
160 (at91sam7_info
->ext_freq
== 0))
162 at91sam7_info
->mck_valid
= 1;
163 tmp
= RC_FREQ
/ 16ul * (mcfr
& 0xffff);
165 else if (at91sam7_info
->ext_freq
!= 0)
167 at91sam7_info
->mck_valid
= 1;
168 tmp
= at91sam7_info
->ext_freq
;
172 case 2: /* Reserved */
175 case 3: /* PLL Clock */
176 if ((mcfr
& CKGR_MCFR_MAINRDY
) &&
177 (at91sam7_info
->ext_freq
== 0))
179 target_read_u32(target
, CKGR_PLLR
, &pllr
);
180 if (!(pllr
& CKGR_PLLR_DIV
))
182 at91sam7_info
->mck_valid
= 1;
183 mainfreq
= RC_FREQ
/ 16ul * (mcfr
& 0xffff);
184 /* Integer arithmetic should have sufficient precision
185 * as long as PLL is properly configured. */
186 tmp
= mainfreq
/ (pllr
& CKGR_PLLR_DIV
)*
187 (((pllr
& CKGR_PLLR_MUL
) >> 16) + 1);
189 else if ((at91sam7_info
->ext_freq
!= 0) &&
190 ((pllr
&CKGR_PLLR_DIV
) != 0))
192 at91sam7_info
->mck_valid
= 1;
193 tmp
= at91sam7_info
->ext_freq
/ (pllr
&CKGR_PLLR_DIV
)*
194 (((pllr
& CKGR_PLLR_MUL
) >> 16) + 1);
199 /* Prescaler adjust */
200 if ((((mckr
& PMC_MCKR_PRES
) >> 2) == 7) || (tmp
== 0))
202 at91sam7_info
->mck_valid
= 0;
203 at91sam7_info
->mck_freq
= 0;
205 else if (((mckr
& PMC_MCKR_PRES
) >> 2) != 0)
206 at91sam7_info
->mck_freq
= tmp
>> ((mckr
& PMC_MCKR_PRES
) >> 2);
208 at91sam7_info
->mck_freq
= tmp
;
211 /* Setup the timimg registers for nvbits or normal flash */
212 static void at91sam7_set_flash_mode(flash_bank_t
*bank
, int mode
)
214 uint32_t fmr
, fmcn
= 0, fws
= 0;
215 at91sam7_flash_bank_t
*at91sam7_info
= bank
->driver_priv
;
216 target_t
*target
= bank
->target
;
218 if (mode
&& (mode
!= at91sam7_info
->flashmode
))
220 /* Always round up (ceil) */
221 if (mode
== FMR_TIMING_NVBITS
)
223 if (at91sam7_info
->cidr_arch
== 0x60)
225 /* AT91SAM7A3 uses master clocks in 100 ns */
226 fmcn
= (at91sam7_info
->mck_freq
/10000000ul) + 1;
230 /* master clocks in 1uS for ARCH 0x7 types */
231 fmcn
= (at91sam7_info
->mck_freq
/1000000ul) + 1;
234 else if (mode
== FMR_TIMING_FLASH
)
236 /* main clocks in 1.5uS */
237 fmcn
= (at91sam7_info
->mck_freq
/1000000ul)+
238 (at91sam7_info
->mck_freq
/2000000ul) + 1;
241 /* hard overclocking */
245 /* Only allow fmcn = 0 if clock period is > 30 us = 33kHz. */
246 if (at91sam7_info
->mck_freq
<= 33333ul)
248 /* Only allow fws = 0 if clock frequency is < 30 MHz. */
249 if (at91sam7_info
->mck_freq
> 30000000ul)
252 LOG_DEBUG("fmcn[%i]: %i", bank
->bank_number
, (int)(fmcn
));
253 fmr
= fmcn
<< 16 | fws
<< 8;
254 target_write_u32(target
, MC_FMR
[bank
->bank_number
], fmr
);
257 at91sam7_info
->flashmode
= mode
;
260 static uint32_t at91sam7_wait_status_busy(flash_bank_t
*bank
, uint32_t waitbits
, int timeout
)
264 while ((!((status
= at91sam7_get_flash_status(bank
->target
, bank
->bank_number
)) & waitbits
)) && (timeout
-- > 0))
266 LOG_DEBUG("status[%i]: 0x%" PRIx32
"", (int)bank
->bank_number
, status
);
270 LOG_DEBUG("status[%i]: 0x%" PRIx32
"", bank
->bank_number
, status
);
274 LOG_ERROR("status register: 0x%" PRIx32
"", status
);
276 LOG_ERROR("Lock Error Bit Detected, Operation Abort");
278 LOG_ERROR("Invalid command and/or bad keyword, Operation Abort");
280 LOG_ERROR("Security Bit Set, Operation Abort");
286 /* Send one command to the AT91SAM flash controller */
287 static int at91sam7_flash_command(struct flash_bank_s
*bank
, uint8_t cmd
, uint16_t pagen
)
290 at91sam7_flash_bank_t
*at91sam7_info
= bank
->driver_priv
;
291 target_t
*target
= bank
->target
;
293 fcr
= (0x5A << 24) | ((pagen
&0x3FF) << 8) | cmd
;
294 target_write_u32(target
, MC_FCR
[bank
->bank_number
], fcr
);
295 LOG_DEBUG("Flash command: 0x%" PRIx32
", flash bank: %i, page number: %u", fcr
, bank
->bank_number
+ 1, pagen
);
297 if ((at91sam7_info
->cidr_arch
== 0x60) && ((cmd
== SLB
) | (cmd
== CLB
)))
299 /* Lock bit manipulation on AT91SAM7A3 waits for FC_FSR bit 1, EOL */
300 if (at91sam7_wait_status_busy(bank
, MC_FSR_EOL
, 10)&0x0C)
302 return ERROR_FLASH_OPERATION_FAILED
;
307 if (at91sam7_wait_status_busy(bank
, MC_FSR_FRDY
, 10)&0x0C)
309 return ERROR_FLASH_OPERATION_FAILED
;
315 /* Read device id register, main clock frequency register and fill in driver info structure */
316 static int at91sam7_read_part_info(struct flash_bank_s
*bank
)
318 flash_bank_t
*t_bank
= bank
;
319 at91sam7_flash_bank_t
*at91sam7_info
;
320 target_t
*target
= t_bank
->target
;
325 uint8_t banks_num
= 0;
326 uint16_t num_nvmbits
= 0;
327 uint16_t sectors_num
= 0;
328 uint16_t pages_per_sector
= 0;
329 uint16_t page_size
= 0;
332 uint32_t base_address
= 0;
333 char *target_name
= "Unknown";
335 at91sam7_info
= t_bank
->driver_priv
;
337 if (at91sam7_info
->cidr
!= 0)
339 /* flash already configured, update clock and check for protected sectors */
340 flash_bank_t
*fb
= bank
;
345 /* re-calculate master clock frequency */
346 at91sam7_read_clock_info(t_bank
);
349 at91sam7_set_flash_mode(t_bank
, FMR_TIMING_NONE
);
351 /* check protect state */
352 at91sam7_protect_check(t_bank
);
361 /* Read and parse chip identification register */
362 target_read_u32(target
, DBGU_CIDR
, &cidr
);
365 LOG_WARNING("Cannot identify target as an AT91SAM");
366 return ERROR_FLASH_OPERATION_FAILED
;
369 if (at91sam7_info
->flash_autodetection
== 0)
371 /* banks and sectors are already created, based on data from input file */
372 flash_bank_t
*fb
= bank
;
376 at91sam7_info
= t_bank
->driver_priv
;
378 at91sam7_info
->cidr
= cidr
;
379 at91sam7_info
->cidr_ext
= (cidr
>> 31)&0x0001;
380 at91sam7_info
->cidr_nvptyp
= (cidr
>> 28)&0x0007;
381 at91sam7_info
->cidr_arch
= (cidr
>> 20)&0x00FF;
382 at91sam7_info
->cidr_sramsiz
= (cidr
>> 16)&0x000F;
383 at91sam7_info
->cidr_nvpsiz2
= (cidr
>> 12)&0x000F;
384 at91sam7_info
->cidr_nvpsiz
= (cidr
>> 8)&0x000F;
385 at91sam7_info
->cidr_eproc
= (cidr
>> 5)&0x0007;
386 at91sam7_info
->cidr_version
= cidr
&0x001F;
388 /* calculate master clock frequency */
389 at91sam7_read_clock_info(t_bank
);
392 at91sam7_set_flash_mode(t_bank
, FMR_TIMING_NONE
);
394 /* check protect state */
395 at91sam7_protect_check(t_bank
);
404 arch
= (cidr
>> 20)&0x00FF;
406 /* check flash size */
407 switch ((cidr
>> 8)&0x000F)
412 case FLASH_SIZE_16KB
:
415 pages_per_sector
= 32;
417 base_address
= 0x00100000;
421 target_name
= "AT91SAM7S161/16";
425 case FLASH_SIZE_32KB
:
428 pages_per_sector
= 32;
430 base_address
= 0x00100000;
434 target_name
= "AT91SAM7S321/32";
439 target_name
= "AT91SAM7SE32";
443 case FLASH_SIZE_64KB
:
446 pages_per_sector
= 32;
448 base_address
= 0x00100000;
452 target_name
= "AT91SAM7S64";
456 case FLASH_SIZE_128KB
:
459 pages_per_sector
= 64;
461 base_address
= 0x00100000;
465 target_name
= "AT91SAM7S128";
470 target_name
= "AT91SAM7XC128";
475 target_name
= "AT91SAM7SE128";
480 target_name
= "AT91SAM7X128";
484 case FLASH_SIZE_256KB
:
487 pages_per_sector
= 64;
489 base_address
= 0x00100000;
493 target_name
= "AT91SAM7A3";
498 target_name
= "AT91SAM7S256";
503 target_name
= "AT91SAM7XC256";
508 target_name
= "AT91SAM7SE256";
513 target_name
= "AT91SAM7X256";
517 case FLASH_SIZE_512KB
:
520 pages_per_sector
= 64;
522 base_address
= 0x00100000;
526 target_name
= "AT91SAM7S512";
531 target_name
= "AT91SAM7XC512";
536 target_name
= "AT91SAM7SE512";
541 target_name
= "AT91SAM7X512";
545 case FLASH_SIZE_1024KB
:
548 case FLASH_SIZE_2048KB
:
552 if (strcmp(target_name
, "Unknown") == 0)
554 LOG_ERROR("Target autodetection failed! Please specify target parameters in configuration file");
555 return ERROR_FLASH_OPERATION_FAILED
;
558 ext_freq
= at91sam7_info
->ext_freq
;
560 /* calculate bank size */
561 bank_size
= sectors_num
* pages_per_sector
* page_size
;
563 for (bnk
= 0; bnk
< banks_num
; bnk
++)
567 /* create a new flash bank element */
568 flash_bank_t
*fb
= malloc(sizeof(flash_bank_t
));
570 fb
->driver
= &at91sam7_flash
;
571 fb
->driver_priv
= malloc(sizeof(at91sam7_flash_bank_t
));
574 /* link created bank in 'flash_banks' list and redirect t_bank */
579 t_bank
->bank_number
= bnk
;
580 t_bank
->base
= base_address
+ bnk
* bank_size
;
581 t_bank
->size
= bank_size
;
582 t_bank
->chip_width
= 0;
583 t_bank
->bus_width
= 4;
584 t_bank
->num_sectors
= sectors_num
;
586 /* allocate sectors */
587 t_bank
->sectors
= malloc(sectors_num
* sizeof(flash_sector_t
));
588 for (sec
= 0; sec
< sectors_num
; sec
++)
590 t_bank
->sectors
[sec
].offset
= sec
* pages_per_sector
* page_size
;
591 t_bank
->sectors
[sec
].size
= pages_per_sector
* page_size
;
592 t_bank
->sectors
[sec
].is_erased
= -1;
593 t_bank
->sectors
[sec
].is_protected
= -1;
596 at91sam7_info
= t_bank
->driver_priv
;
598 at91sam7_info
->cidr
= cidr
;
599 at91sam7_info
->cidr_ext
= (cidr
>> 31)&0x0001;
600 at91sam7_info
->cidr_nvptyp
= (cidr
>> 28)&0x0007;
601 at91sam7_info
->cidr_arch
= (cidr
>> 20)&0x00FF;
602 at91sam7_info
->cidr_sramsiz
= (cidr
>> 16)&0x000F;
603 at91sam7_info
->cidr_nvpsiz2
= (cidr
>> 12)&0x000F;
604 at91sam7_info
->cidr_nvpsiz
= (cidr
>> 8)&0x000F;
605 at91sam7_info
->cidr_eproc
= (cidr
>> 5)&0x0007;
606 at91sam7_info
->cidr_version
= cidr
&0x001F;
608 at91sam7_info
->target_name
= target_name
;
609 at91sam7_info
->flashmode
= 0;
610 at91sam7_info
->ext_freq
= ext_freq
;
611 at91sam7_info
->num_nvmbits
= num_nvmbits
;
612 at91sam7_info
->num_nvmbits_on
= 0;
613 at91sam7_info
->pagesize
= page_size
;
614 at91sam7_info
->pages_per_sector
= pages_per_sector
;
616 /* calculate master clock frequency */
617 at91sam7_read_clock_info(t_bank
);
620 at91sam7_set_flash_mode(t_bank
, FMR_TIMING_NONE
);
622 /* check protect state */
623 at91sam7_protect_check(t_bank
);
626 LOG_DEBUG("nvptyp: 0x%3.3x, arch: 0x%4.4x", at91sam7_info
->cidr_nvptyp
, at91sam7_info
->cidr_arch
);
631 static int at91sam7_erase_check(struct flash_bank_s
*bank
)
633 target_t
*target
= bank
->target
;
641 if (bank
->target
->state
!= TARGET_HALTED
)
643 LOG_ERROR("Target not halted");
644 return ERROR_TARGET_NOT_HALTED
;
647 /* Configure the flash controller timing */
648 at91sam7_read_clock_info(bank
);
649 at91sam7_set_flash_mode(bank
, FMR_TIMING_FLASH
);
652 for (nSector
= 0; nSector
< bank
->num_sectors
; nSector
++)
654 retval
= target_blank_check_memory(target
, bank
->base
+ bank
->sectors
[nSector
].offset
,
655 bank
->sectors
[nSector
].size
, &blank
);
656 if (retval
!= ERROR_OK
)
662 bank
->sectors
[nSector
].is_erased
= 1;
664 bank
->sectors
[nSector
].is_erased
= 0;
672 LOG_USER("Running slow fallback erase check - add working memory");
674 buffer
= malloc(bank
->sectors
[0].size
);
675 for (nSector
= 0; nSector
< bank
->num_sectors
; nSector
++)
677 bank
->sectors
[nSector
].is_erased
= 1;
678 retval
= target_read_memory(target
, bank
->base
+ bank
->sectors
[nSector
].offset
, 4,
679 bank
->sectors
[nSector
].size
/4, buffer
);
680 if (retval
!= ERROR_OK
)
683 for (nByte
= 0; nByte
< bank
->sectors
[nSector
].size
; nByte
++)
685 if (buffer
[nByte
] != 0xFF)
687 bank
->sectors
[nSector
].is_erased
= 0;
697 static int at91sam7_protect_check(struct flash_bank_s
*bank
)
699 uint8_t lock_pos
, gpnvm_pos
;
702 at91sam7_flash_bank_t
*at91sam7_info
= bank
->driver_priv
;
704 if (at91sam7_info
->cidr
== 0)
706 return ERROR_FLASH_BANK_NOT_PROBED
;
708 if (bank
->target
->state
!= TARGET_HALTED
)
710 LOG_ERROR("Target not halted");
711 return ERROR_TARGET_NOT_HALTED
;
714 status
= at91sam7_get_flash_status(bank
->target
, bank
->bank_number
);
715 at91sam7_info
->lockbits
= (status
>> 16);
717 at91sam7_info
->num_lockbits_on
= 0;
718 for (lock_pos
= 0; lock_pos
< bank
->num_sectors
; lock_pos
++)
720 if (((status
>> (16 + lock_pos
))&(0x0001)) == 1)
722 at91sam7_info
->num_lockbits_on
++;
723 bank
->sectors
[lock_pos
].is_protected
= 1;
726 bank
->sectors
[lock_pos
].is_protected
= 0;
729 /* GPNVM and SECURITY bits apply only for MC_FSR of EFC0 */
730 status
= at91sam7_get_flash_status(bank
->target
, 0);
732 at91sam7_info
->securitybit
= (status
>> 4)&0x01;
733 at91sam7_info
->nvmbits
= (status
>> 8)&0xFF;
735 at91sam7_info
->num_nvmbits_on
= 0;
736 for (gpnvm_pos
= 0; gpnvm_pos
< at91sam7_info
->num_nvmbits
; gpnvm_pos
++)
738 if (((status
>> (8 + gpnvm_pos
))&(0x01)) == 1)
740 at91sam7_info
->num_nvmbits_on
++;
747 static int at91sam7_flash_bank_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct flash_bank_s
*bank
)
749 flash_bank_t
*t_bank
= bank
;
750 at91sam7_flash_bank_t
*at91sam7_info
;
751 target_t
*target
= t_bank
->target
;
753 uint32_t base_address
;
755 uint32_t ext_freq
= 0;
762 uint16_t pages_per_sector
;
764 uint16_t num_nvmbits
;
770 at91sam7_info
= malloc(sizeof(at91sam7_flash_bank_t
));
771 t_bank
->driver_priv
= at91sam7_info
;
773 /* part wasn't probed for info yet */
774 at91sam7_info
->cidr
= 0;
775 at91sam7_info
->flashmode
= 0;
776 at91sam7_info
->ext_freq
= 0;
777 at91sam7_info
->flash_autodetection
= 0;
781 at91sam7_info
->flash_autodetection
= 1;
785 COMMAND_PARSE_NUMBER(u32
, args
[1], base_address
);
787 COMMAND_PARSE_NUMBER(int, args
[3], chip_width
);
788 COMMAND_PARSE_NUMBER(int, args
[4], bus_width
);
790 COMMAND_PARSE_NUMBER(int, args
[8], banks_num
);
791 COMMAND_PARSE_NUMBER(int, args
[9], num_sectors
);
792 COMMAND_PARSE_NUMBER(u16
, args
[10], pages_per_sector
);
793 COMMAND_PARSE_NUMBER(u16
, args
[11], page_size
);
794 COMMAND_PARSE_NUMBER(u16
, args
[12], num_nvmbits
);
798 COMMAND_PARSE_NUMBER(ulong
, args
[13], freq
);
799 ext_freq
= freq
* 1000;
800 at91sam7_info
->ext_freq
= ext_freq
;
803 if ((bus_width
== 0) || (banks_num
== 0) || (num_sectors
== 0) ||
804 (pages_per_sector
== 0) || (page_size
== 0) || (num_nvmbits
== 0))
806 at91sam7_info
->flash_autodetection
= 1;
810 target_name
= calloc(strlen(args
[7]) + 1, sizeof(char));
811 strcpy(target_name
, args
[7]);
813 /* calculate bank size */
814 bank_size
= num_sectors
* pages_per_sector
* page_size
;
816 for (bnk
= 0; bnk
< banks_num
; bnk
++)
820 /* create a new bank element */
821 flash_bank_t
*fb
= malloc(sizeof(flash_bank_t
));
823 fb
->driver
= &at91sam7_flash
;
824 fb
->driver_priv
= malloc(sizeof(at91sam7_flash_bank_t
));
827 /* link created bank in 'flash_banks' list and redirect t_bank */
832 t_bank
->bank_number
= bnk
;
833 t_bank
->base
= base_address
+ bnk
* bank_size
;
834 t_bank
->size
= bank_size
;
835 t_bank
->chip_width
= chip_width
;
836 t_bank
->bus_width
= bus_width
;
837 t_bank
->num_sectors
= num_sectors
;
839 /* allocate sectors */
840 t_bank
->sectors
= malloc(num_sectors
* sizeof(flash_sector_t
));
841 for (sec
= 0; sec
< num_sectors
; sec
++)
843 t_bank
->sectors
[sec
].offset
= sec
* pages_per_sector
* page_size
;
844 t_bank
->sectors
[sec
].size
= pages_per_sector
* page_size
;
845 t_bank
->sectors
[sec
].is_erased
= -1;
846 t_bank
->sectors
[sec
].is_protected
= -1;
849 at91sam7_info
= t_bank
->driver_priv
;
851 at91sam7_info
->target_name
= target_name
;
852 at91sam7_info
->flashmode
= 0;
853 at91sam7_info
->ext_freq
= ext_freq
;
854 at91sam7_info
->num_nvmbits
= num_nvmbits
;
855 at91sam7_info
->num_nvmbits_on
= 0;
856 at91sam7_info
->pagesize
= page_size
;
857 at91sam7_info
->pages_per_sector
= pages_per_sector
;
863 static int at91sam7_erase(struct flash_bank_s
*bank
, int first
, int last
)
865 at91sam7_flash_bank_t
*at91sam7_info
= bank
->driver_priv
;
867 uint32_t nbytes
, pos
;
871 if (at91sam7_info
->cidr
== 0)
873 return ERROR_FLASH_BANK_NOT_PROBED
;
876 if (bank
->target
->state
!= TARGET_HALTED
)
878 LOG_ERROR("Target not halted");
879 return ERROR_TARGET_NOT_HALTED
;
882 if ((first
< 0) || (last
< first
) || (last
>= bank
->num_sectors
))
884 return ERROR_FLASH_SECTOR_INVALID
;
888 if ((first
== 0) && (last
== (bank
->num_sectors
-1)))
893 /* Configure the flash controller timing */
894 at91sam7_read_clock_info(bank
);
895 at91sam7_set_flash_mode(bank
, FMR_TIMING_FLASH
);
899 if (at91sam7_flash_command(bank
, EA
, 0) != ERROR_OK
)
901 return ERROR_FLASH_OPERATION_FAILED
;
906 /* allocate and clean buffer */
907 nbytes
= (last
- first
+ 1) * bank
->sectors
[first
].size
;
908 buffer
= malloc(nbytes
* sizeof(uint8_t));
909 for (pos
= 0; pos
< nbytes
; pos
++)
914 if (at91sam7_write(bank
, buffer
, bank
->sectors
[first
].offset
, nbytes
) != ERROR_OK
)
916 return ERROR_FLASH_OPERATION_FAILED
;
922 /* mark erased sectors */
923 for (sec
= first
; sec
<= last
; sec
++)
925 bank
->sectors
[sec
].is_erased
= 1;
931 static int at91sam7_protect(struct flash_bank_s
*bank
, int set
, int first
, int last
)
937 at91sam7_flash_bank_t
*at91sam7_info
= bank
->driver_priv
;
939 if (at91sam7_info
->cidr
== 0)
941 return ERROR_FLASH_BANK_NOT_PROBED
;
944 if (bank
->target
->state
!= TARGET_HALTED
)
946 LOG_ERROR("Target not halted");
947 return ERROR_TARGET_NOT_HALTED
;
950 if ((first
< 0) || (last
< first
) || (last
>= bank
->num_sectors
))
952 return ERROR_FLASH_SECTOR_INVALID
;
955 /* Configure the flash controller timing */
956 at91sam7_read_clock_info(bank
);
957 at91sam7_set_flash_mode(bank
, FMR_TIMING_NVBITS
);
959 for (sector
= first
; sector
<= last
; sector
++)
966 /* if we lock a page from one sector then entire sector will be locked, also,
967 * if we unlock a page from a locked sector, entire sector will be unlocked */
968 pagen
= sector
* at91sam7_info
->pages_per_sector
;
970 if (at91sam7_flash_command(bank
, cmd
, pagen
) != ERROR_OK
)
972 return ERROR_FLASH_OPERATION_FAILED
;
976 at91sam7_protect_check(bank
);
981 static int at91sam7_write(struct flash_bank_s
*bank
, uint8_t *buffer
, uint32_t offset
, uint32_t count
)
984 at91sam7_flash_bank_t
*at91sam7_info
= bank
->driver_priv
;
985 target_t
*target
= bank
->target
;
986 uint32_t dst_min_alignment
, wcount
, bytes_remaining
= count
;
987 uint32_t first_page
, last_page
, pagen
, buffer_pos
;
989 if (at91sam7_info
->cidr
== 0)
991 return ERROR_FLASH_BANK_NOT_PROBED
;
994 if (bank
->target
->state
!= TARGET_HALTED
)
996 LOG_ERROR("Target not halted");
997 return ERROR_TARGET_NOT_HALTED
;
1000 if (offset
+ count
> bank
->size
)
1001 return ERROR_FLASH_DST_OUT_OF_BANK
;
1003 dst_min_alignment
= at91sam7_info
->pagesize
;
1005 if (offset
% dst_min_alignment
)
1007 LOG_WARNING("offset 0x%" PRIx32
" breaks required alignment 0x%" PRIx32
"", offset
, dst_min_alignment
);
1008 return ERROR_FLASH_DST_BREAKS_ALIGNMENT
;
1011 if (at91sam7_info
->cidr_arch
== 0)
1012 return ERROR_FLASH_BANK_NOT_PROBED
;
1014 first_page
= offset
/dst_min_alignment
;
1015 last_page
= CEIL(offset
+ count
, dst_min_alignment
);
1017 LOG_DEBUG("first_page: %i, last_page: %i, count %i", (int)first_page
, (int)last_page
, (int)count
);
1019 /* Configure the flash controller timing */
1020 at91sam7_read_clock_info(bank
);
1021 at91sam7_set_flash_mode(bank
, FMR_TIMING_FLASH
);
1023 for (pagen
= first_page
; pagen
< last_page
; pagen
++)
1025 if (bytes_remaining
< dst_min_alignment
)
1026 count
= bytes_remaining
;
1028 count
= dst_min_alignment
;
1029 bytes_remaining
-= count
;
1031 /* Write one block to the PageWriteBuffer */
1032 buffer_pos
= (pagen
-first_page
)*dst_min_alignment
;
1033 wcount
= CEIL(count
,4);
1034 if ((retval
= target_write_memory(target
, bank
->base
+ pagen
*dst_min_alignment
, 4, wcount
, buffer
+ buffer_pos
)) != ERROR_OK
)
1039 /* Send Write Page command to Flash Controller */
1040 if (at91sam7_flash_command(bank
, WP
, pagen
) != ERROR_OK
)
1042 return ERROR_FLASH_OPERATION_FAILED
;
1044 LOG_DEBUG("Write flash bank:%i page number:%" PRIi32
"", bank
->bank_number
, pagen
);
1050 static int at91sam7_probe(struct flash_bank_s
*bank
)
1052 /* we can't probe on an at91sam7
1053 * if this is an at91sam7, it has the configured flash */
1056 if (bank
->target
->state
!= TARGET_HALTED
)
1058 LOG_ERROR("Target not halted");
1059 return ERROR_TARGET_NOT_HALTED
;
1062 retval
= at91sam7_read_part_info(bank
);
1063 if (retval
!= ERROR_OK
)
1069 static int at91sam7_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
)
1072 at91sam7_flash_bank_t
*at91sam7_info
= bank
->driver_priv
;
1074 if (at91sam7_info
->cidr
== 0)
1076 return ERROR_FLASH_BANK_NOT_PROBED
;
1079 printed
= snprintf(buf
, buf_size
,
1080 "\n at91sam7 driver information: Chip is %s\n",
1081 at91sam7_info
->target_name
);
1084 buf_size
-= printed
;
1086 printed
= snprintf(buf
,
1088 " Cidr: 0x%8.8" PRIx32
" | Arch: 0x%4.4x | Eproc: %s | Version: 0x%3.3x | Flashsize: 0x%8.8" PRIx32
"\n",
1089 at91sam7_info
->cidr
,
1090 at91sam7_info
->cidr_arch
,
1091 EPROC
[at91sam7_info
->cidr_eproc
],
1092 at91sam7_info
->cidr_version
,
1096 buf_size
-= printed
;
1098 printed
= snprintf(buf
, buf_size
,
1099 " Master clock (estimated): %u KHz | External clock: %u KHz\n",
1100 (unsigned)(at91sam7_info
->mck_freq
/ 1000), (unsigned)(at91sam7_info
->ext_freq
/ 1000));
1103 buf_size
-= printed
;
1105 printed
= snprintf(buf
, buf_size
,
1106 " Pagesize: %i bytes | Lockbits(%i): %i 0x%4.4x | Pages in lock region: %i \n",
1107 at91sam7_info
->pagesize
, bank
->num_sectors
, at91sam7_info
->num_lockbits_on
,
1108 at91sam7_info
->lockbits
, at91sam7_info
->pages_per_sector
*at91sam7_info
->num_lockbits_on
);
1111 buf_size
-= printed
;
1113 printed
= snprintf(buf
, buf_size
,
1114 " Securitybit: %i | Nvmbits(%i): %i 0x%1.1x\n",
1115 at91sam7_info
->securitybit
, at91sam7_info
->num_nvmbits
,
1116 at91sam7_info
->num_nvmbits_on
, at91sam7_info
->nvmbits
);
1119 buf_size
-= printed
;
1125 * On AT91SAM7S: When the gpnvm bits are set with
1126 * > at91sam7 gpnvm bitnr set
1127 * the changes are not visible in the flash controller status register MC_FSR
1128 * until the processor has been reset.
1129 * On the Olimex board this requires a power cycle.
1130 * Note that the AT91SAM7S has the following errata (doc6175.pdf sec 14.1.3):
1131 * The maximum number of write/erase cycles for Non volatile Memory bits is 100. this includes
1132 * Lock Bits (LOCKx), General Purpose NVM bits (GPNVMx) and the Security Bit.
1134 static int at91sam7_handle_gpnvm_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1140 at91sam7_flash_bank_t
*at91sam7_info
;
1145 command_print(cmd_ctx
, "at91sam7 gpnvm <bit> <set | clear>");
1149 bank
= get_flash_bank_by_num_noprobe(0);
1152 return ERROR_FLASH_BANK_INVALID
;
1154 if (bank
->driver
!= &at91sam7_flash
)
1156 command_print(cmd_ctx
, "not an at91sam7 flash bank '%s'", args
[0]);
1157 return ERROR_FLASH_BANK_INVALID
;
1159 if (bank
->target
->state
!= TARGET_HALTED
)
1161 LOG_ERROR("target has to be halted to perform flash operation");
1162 return ERROR_TARGET_NOT_HALTED
;
1165 if (strcmp(args
[1], "set") == 0)
1169 else if (strcmp(args
[1], "clear") == 0)
1175 return ERROR_COMMAND_SYNTAX_ERROR
;
1178 at91sam7_info
= bank
->driver_priv
;
1179 if (at91sam7_info
->cidr
== 0)
1181 retval
= at91sam7_read_part_info(bank
);
1182 if (retval
!= ERROR_OK
)
1188 COMMAND_PARSE_NUMBER(int, args
[0], bit
);
1189 if ((bit
< 0) || (bit
>= at91sam7_info
->num_nvmbits
))
1191 command_print(cmd_ctx
, "gpnvm bit '#%s' is out of bounds for target %s", args
[0], at91sam7_info
->target_name
);
1195 /* Configure the flash controller timing */
1196 at91sam7_read_clock_info(bank
);
1197 at91sam7_set_flash_mode(bank
, FMR_TIMING_NVBITS
);
1199 if (at91sam7_flash_command(bank
, flashcmd
, bit
) != ERROR_OK
)
1201 return ERROR_FLASH_OPERATION_FAILED
;
1204 /* GPNVM and SECURITY bits apply only for MC_FSR of EFC0 */
1205 status
= at91sam7_get_flash_status(bank
->target
, 0);
1206 LOG_DEBUG("at91sam7_handle_gpnvm_command: cmd 0x%x, value %d, status 0x%" PRIx32
" \n", flashcmd
, bit
, status
);
1208 /* check protect state */
1209 at91sam7_protect_check(bank
);
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)