1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle Open On-Chip Debugger (OpenOCD)
5 @dircategory Development
7 * OpenOCD: (openocd). Open On-Chip Debugger.
14 Copyright @copyright{} 2007-2008 Spen @email{spen@@spen-soft.co.uk}
15 Copyright @copyright{} 2008 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
17 Permission is granted to copy, distribute and/or modify this document
18 under the terms of the GNU Free Documentation License, Version 1.2 or
19 any later version published by the Free Software Foundation; with no
20 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
21 Texts. A copy of the license is included in the section entitled ``GNU
22 Free Documentation License''.
27 @title Open On-Chip Debugger (OpenOCD)
28 @subtitle Edition @value{EDITION} for OpenOCD version @value{VERSION}
29 @subtitle @value{UPDATED}
31 @vskip 0pt plus 1filll
37 @node Top, About, , (dir)
40 This manual documents edition @value{EDITION} of the Open On-Chip Debugger
41 (OpenOCD) version @value{VERSION}, @value{UPDATED}.
46 * About:: About OpenOCD.
47 * Developers:: OpenOCD developers
48 * Building:: Building OpenOCD
49 * Running:: Running OpenOCD
50 * Configuration:: OpenOCD Configuration.
51 * Target library:: Target library
52 * Commands:: OpenOCD Commands
53 * Sample Scripts:: Sample Target Scripts
54 * GDB and OpenOCD:: Using GDB and OpenOCD
55 * TCL and OpenOCD:: Using TCL and OpenOCD
56 * TCL scripting API:: Tcl scripting API
57 * Upgrading:: Deprecated/Removed Commands
58 * FAQ:: Frequently Asked Questions
59 * License:: GNU Free Documentation License
67 The Open On-Chip Debugger (OpenOCD) aims to provide debugging, in-system programming
68 and boundary-scan testing for embedded target devices. The targets are interfaced
69 using JTAG (IEEE 1149.1) compliant hardware, but this may be extended to other
70 connection types in the future.
72 OpenOCD currently supports Wiggler (clones), FTDI FT2232 based JTAG interfaces, the
73 Amontec JTAG Accelerator, and the Gateworks GW1602. It allows ARM7 (ARM7TDMI and ARM720t),
74 ARM9 (ARM920t, ARM922t, ARM926ej--s, ARM966e--s), XScale (PXA25x, IXP42x) and
75 Cortex-M3 (Luminary Stellaris LM3 and ST STM32) based cores to be debugged.
77 Flash writing is supported for external CFI compatible flashes (Intel and AMD/Spansion
78 command set) and several internal flashes (LPC2000, AT91SAM7, STR7x, STR9x, LM3
79 and STM32x). Preliminary support for using the LPC3180's NAND flash controller is included.
85 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
86 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
87 Others interested in improving the state of free and open debug and testing technology
88 are welcome to participate.
90 Other developers have contributed support for additional targets and flashes as well
91 as numerous bugfixes and enhancements. See the AUTHORS file for regular contributors.
93 The main OpenOCD web site is available at @uref{http://openocd.berlios.de/web/}
97 @cindex building OpenOCD
99 You can download the current SVN version with SVN client of your choice from the
100 following repositories:
102 (@uref{svn://svn.berlios.de/openocd/trunk})
106 (@uref{http://svn.berlios.de/svnroot/repos/openocd/trunk})
108 Using the SVN command line client, you can use the following command to fetch the
109 latest version (make sure there is no (non-svn) directory called "openocd" in the
113 svn checkout svn://svn.berlios.de/openocd/trunk openocd
116 Building OpenOCD requires a recent version of the GNU autotools.
117 On my build system, I'm using autoconf 2.13 and automake 1.9. For building on Windows,
118 you have to use Cygwin. Make sure that your @env{PATH} environment variable contains no
119 other locations with Unix utils (like UnxUtils) - these can't handle the Cygwin
120 paths, resulting in obscure dependency errors (This is an observation I've gathered
121 from the logs of one user - correct me if I'm wrong).
123 You further need the appropriate driver files, if you want to build support for
124 a FTDI FT2232 based interface:
126 @item @b{ftdi2232} libftdi (@uref{http://www.intra2net.com/opensource/ftdi/})
127 @item @b{ftd2xx} libftd2xx (@uref{http://www.ftdichip.com/Drivers/D2XX.htm})
128 @item When using the Amontec JTAGkey, you have to get the drivers from the Amontec
129 homepage (@uref{www.amontec.com}), as the JTAGkey uses a non-standard VID/PID.
132 libftdi is supported under windows. Versions earlier than 0.13 will require patching.
133 see contrib/libftdi for more details.
135 In general, the D2XX driver provides superior performance (several times as fast),
136 but has the draw-back of being binary-only - though that isn't that bad, as it isn't
137 a kernel module, only a user space library.
139 To build OpenOCD (on both Linux and Cygwin), use the following commands:
143 Bootstrap generates the configure script, and prepares building on your system.
147 Configure generates the Makefiles used to build OpenOCD.
151 Make builds OpenOCD, and places the final executable in ./src/.
153 The configure script takes several options, specifying which JTAG interfaces
158 @option{--enable-parport}
160 @option{--enable-parport_ppdev}
162 @option{--enable-parport_giveio}
164 @option{--enable-amtjtagaccel}
166 @option{--enable-ft2232_ftd2xx}
167 @footnote{Using the latest D2XX drivers from FTDI and following their installation
168 instructions, I had to use @option{--enable-ft2232_libftd2xx} for OpenOCD to
171 @option{--enable-ft2232_libftdi}
173 @option{--with-ftd2xx=/path/to/d2xx/}
175 @option{--enable-gw16012}
177 @option{--enable-usbprog}
179 @option{--enable-presto_libftdi}
181 @option{--enable-presto_ftd2xx}
183 @option{--enable-jlink}
186 If you want to access the parallel port using the PPDEV interface you have to specify
187 both the @option{--enable-parport} AND the @option{--enable-parport_ppdev} option since
188 the @option{--enable-parport_ppdev} option actually is an option to the parport driver
189 (see @uref{http://forum.sparkfun.com/viewtopic.php?t=3795} for more info).
191 Cygwin users have to specify the location of the FTDI D2XX package. This should be an
192 absolute path containing no spaces.
194 Linux users should copy the various parts of the D2XX package to the appropriate
195 locations, i.e. /usr/include, /usr/lib.
197 Miscellaneous configure options
201 @option{--enable-gccwarnings} - enable extra gcc warnings during build
206 @cindex running OpenOCD
208 @cindex --debug_level
211 OpenOCD runs as a daemon, waiting for connections from clients (Telnet, GDB, Other).
212 Run with @option{--help} or @option{-h} to view the available command line switches.
214 It reads its configuration by default from the file openocd.cfg located in the current
215 working directory. This may be overwritten with the @option{-f <configfile>} command line
216 switch. The @option{-f} command line switch can be specified multiple times, in which case the config files
217 are executed in order.
219 Also it is possible to interleave commands w/config scripts using the @option{-c} command line switch.
221 To enable debug output (when reporting problems or working on OpenOCD itself), use
222 the @option{-d} command line switch. This sets the debug_level to "3", outputting
223 the most information, including debug messages. The default setting is "2", outputting
224 only informational messages, warnings and errors. You can also change this setting
225 from within a telnet or gdb session (@option{debug_level <n>}).
227 You can redirect all output from the daemon to a file using the @option{-l <logfile>} switch.
229 Search paths for config/script files can be added to OpenOCD by using
230 the @option{-s <search>} switch. The current directory and the OpenOCD target library
231 is in the search path by default.
233 Note! OpenOCD will launch the GDB & telnet server even if it can not establish a connection
234 with the target. In general, it is possible for the JTAG controller to be unresponsive until
235 the target is set up correctly via e.g. GDB monitor commands in a GDB init script.
238 @chapter Configuration
239 @cindex configuration
240 OpenOCD runs as a daemon, and reads it current configuration
241 by default from the file openocd.cfg in the current directory. A different configuration
242 file can be specified with the @option{-f <conf.file>} command line switch specified when starting OpenOCD.
244 The configuration file is used to specify on which ports the daemon listens for new
245 connections, the JTAG interface used to connect to the target, the layout of the JTAG
246 chain, the targets that should be debugged, and connected flashes.
248 @section Daemon configuration
251 @item @b{init} This command terminates the configuration stage and enters the normal
252 command mode. This can be useful to add commands to the startup scripts and commands
253 such as resetting the target, programming flash, etc. To reset the CPU upon startup,
254 add "init" and "reset" at the end of the config script or at the end of the
255 OpenOCD command line using the @option{-c} command line switch.
257 @item @b{telnet_port} <@var{number}>
259 Port on which to listen for incoming telnet connections
260 @item @b{gdb_port} <@var{number}>
262 First port on which to listen for incoming GDB connections. The GDB port for the
263 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
264 @item @b{gdb_breakpoint_override} <@var{hard/soft/disabled}>
265 @cindex gdb_breakpoint_override
266 hard/soft/disabled - force breakpoint type for gdb 'break' commands.
267 The raison d'etre for this option is to support GDB GUI's without
268 a hard/soft breakpoint concept where the default OpenOCD and
269 GDB behaviour is not sufficient. Note that GDB will use hardware
270 breakpoints if the memory map has been set up for flash regions.
272 This option replaces older arm7_9 target commands that addressed
274 @item @b{gdb_detach} <@var{resume|reset|halt|nothing}>
276 Configures what OpenOCD will do when gdb detaches from the daeman.
277 Default behaviour is <@var{resume}>
278 @item @b{gdb_memory_map} <@var{enable|disable}>
279 @cindex gdb_memory_map
280 Set to <@var{enable}> to cause OpenOCD to send the memory configuration to gdb when
281 requested. gdb will then know when to set hardware breakpoints, and program flash
282 using the gdb load command. @option{gdb_flash_program enable} will also need enabling
283 for flash programming to work.
284 Default behaviour is <@var{enable}>
285 @item @b{gdb_flash_program} <@var{enable|disable}>
286 @cindex gdb_flash_program
287 Set to <@var{enable}> to cause OpenOCD to program the flash memory when a
288 vFlash packet is received.
289 Default behaviour is <@var{enable}>
290 at item @b{tcl_port} <@var{number}>
292 Port on which to listen for incoming TCL syntax. This port is intended as
293 a simplified RPC connection that can be used by clients to issue commands
294 and get the output from the TCL engine.
297 @section JTAG interface configuration
300 @item @b{interface} <@var{name}>
302 Use the interface driver <@var{name}> to connect to the target. Currently supported
306 PC parallel port bit-banging (Wigglers, PLD download cable, ...)
309 @item @b{amt_jtagaccel}
310 Amontec Chameleon in its JTAG Accelerator configuration connected to a PC's EPP
315 FTDI FT2232 based devices using either the open-source libftdi or the binary only
316 FTD2XX driver. The FTD2XX is superior in performance, but not available on every
317 platform. The libftdi uses libusb, and should be portable to all systems that provide
322 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
326 ASIX PRESTO USB JTAG programmer.
330 usbprog is a freely programmable USB adapter.
334 Gateworks GW16012 JTAG programmer.
338 Segger jlink usb adapter
343 @item @b{jtag_speed} <@var{reset speed}>
345 Limit the maximum speed of the JTAG interface. Usually, a value of zero means maximum
346 speed. The actual effect of this option depends on the JTAG interface used.
348 The speed used during reset can be adjusted using setting jtag_speed during
349 pre_reset and post_reset events.
352 @item wiggler: maximum speed / @var{number}
353 @item ft2232: 6MHz / (@var{number}+1)
354 @item amt jtagaccel: 8 / 2**@var{number}
355 @item jlink: maximum speed in kHz (0-12000), 0 will use RTCK
358 Note: Make sure the jtag clock is no more than @math{1/6th × CPU-Clock}. This is
359 especially true for synthesized cores (-S).
361 @item @b{jtag_khz} <@var{reset speed kHz}>
363 Same as jtag_speed, except that the speed is specified in maximum kHz. If
364 the device can not support the rate asked for, or can not translate from
365 kHz to jtag_speed, then an error is returned. 0 means RTCK. If RTCK
366 is not supported, then an error is reported.
368 @item @b{reset_config} <@var{signals}> [@var{combination}] [@var{trst_type}] [@var{srst_type}]
370 The configuration of the reset signals available on the JTAG interface AND the target.
371 If the JTAG interface provides SRST, but the target doesn't connect that signal properly,
372 then OpenOCD can't use it. <@var{signals}> can be @option{none}, @option{trst_only},
373 @option{srst_only} or @option{trst_and_srst}.
375 [@var{combination}] is an optional value specifying broken reset signal implementations.
376 @option{srst_pulls_trst} states that the testlogic is reset together with the reset of
377 the system (e.g. Philips LPC2000, "broken" board layout), @option{trst_pulls_srst} says
378 that the system is reset together with the test logic (only hypothetical, I haven't
379 seen hardware with such a bug, and can be worked around).
380 @option{combined} imples both @option{srst_pulls_trst} and @option{trst_pulls_srst}.
381 The default behaviour if no option given is @option{separate}.
383 The [@var{trst_type}] and [@var{srst_type}] parameters allow the driver type of the
384 reset lines to be specified. Possible values are @option{trst_push_pull} (default)
385 and @option{trst_open_drain} for the test reset signal, and @option{srst_open_drain}
386 (default) and @option{srst_push_pull} for the system reset. These values only affect
387 JTAG interfaces with support for different drivers, like the Amontec JTAGkey and JTAGAccelerator.
389 @item @b{jtag_device} <@var{IR length}> <@var{IR capture}> <@var{IR mask}> <@var{IDCODE instruction}>
391 Describes the devices that form the JTAG daisy chain, with the first device being
392 the one closest to TDO. The parameters are the length of the instruction register
393 (4 for all ARM7/9s), the value captured during Capture-IR (0x1 for ARM7/9), and a mask
394 of bits that should be validated when doing IR scans (all four bits (0xf) for ARM7/9).
395 The IDCODE instruction will in future be used to query devices for their JTAG
396 identification code. This line is the same for all ARM7 and ARM9 devices.
397 Other devices, like CPLDs, require different parameters. An example configuration
398 line for a Xilinx XC9500 CPLD would look like this:
400 jtag_device 8 0x01 0x0e3 0xfe
402 The instruction register (IR) is 8 bits long, during Capture-IR 0x01 is loaded into
403 the IR, but only bits 0-1 and 5-7 should be checked, the others (2-4) might vary.
404 The IDCODE instruction is 0xfe.
406 @item @b{jtag_nsrst_delay} <@var{ms}>
407 @cindex jtag_nsrst_delay
408 How long (in milliseconds) OpenOCD should wait after deasserting nSRST before
409 starting new JTAG operations.
410 @item @b{jtag_ntrst_delay} <@var{ms}>
411 @cindex jtag_ntrst_delay
412 How long (in milliseconds) OpenOCD should wait after deasserting nTRST before
413 starting new JTAG operations.
415 The jtag_n[st]rst_delay options are useful if reset circuitry (like a reset supervisor,
416 or on-chip features) keep a reset line asserted for some time after the external reset
420 @section parport options
423 @item @b{parport_port} <@var{number}>
425 Either the address of the I/O port (default: 0x378 for LPT1) or the number of
426 the @file{/dev/parport} device
428 When using PPDEV to access the parallel port, use the number of the parallel port:
429 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
430 you may encounter a problem.
431 @item @b{parport_cable} <@var{name}>
432 @cindex parport_cable
433 The layout of the parallel port cable used to connect to the target.
434 Currently supported cables are
438 The original Wiggler layout, also supported by several clones, such
439 as the Olimex ARM-JTAG
442 Same as original wiggler except an led is fitted on D5.
443 @item @b{wiggler_ntrst_inverted}
444 @cindex wiggler_ntrst_inverted
445 Same as original wiggler except TRST is inverted.
446 @item @b{old_amt_wiggler}
447 @cindex old_amt_wiggler
448 The Wiggler configuration that comes with Amontec's Chameleon Programmer. The new
449 version available from the website uses the original Wiggler layout ('@var{wiggler}')
452 The Amontec Chameleon's CPLD when operated in configuration mode. This is only used to
453 program the Chameleon itself, not a connected target.
456 The Xilinx Parallel cable III.
459 The parallel port adapter found on the 'Karo Triton 1 Development Board'.
460 This is also the layout used by the HollyGates design
461 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
464 The ST Parallel cable.
467 Same as original wiggler except SRST and TRST connections reversed and
468 TRST is also inverted.
471 Altium Universal JTAG cable.
473 @item @b{parport_write_on_exit} <@var{on|off}>
474 @cindex parport_write_on_exit
475 This will configure the parallel driver to write a known value to the parallel
476 interface on exiting OpenOCD
479 @section amt_jtagaccel options
481 @item @b{parport_port} <@var{number}>
483 Either the address of the I/O port (default: 0x378 for LPT1) or the number of the
484 @file{/dev/parport} device
486 @section ft2232 options
489 @item @b{ft2232_device_desc} <@var{description}>
490 @cindex ft2232_device_desc
491 The USB device description of the FTDI FT2232 device. If not specified, the FTDI
492 default value is used. This setting is only valid if compiled with FTD2XX support.
493 @item @b{ft2232_layout} <@var{name}>
494 @cindex ft2232_layout
495 The layout of the FT2232 GPIO signals used to control output-enables and reset
496 signals. Valid layouts are
499 "USBJTAG-1" layout described in the original OpenOCD diploma thesis
501 Amontec JTAGkey and JTAGkey-tiny
504 @item @b{olimex-jtag}
507 American Microsystems M5960
508 @item @b{evb_lm3s811}
509 Luminary Micro EVB_LM3S811 as a JTAG interface (not onboard processor), no TRST or
510 SRST signals on external connector
514 Hitex STM32 Performance Stick
516 Tin Can Tools Flyswatter
517 @item @b{turtelizer2}
518 egnite Software turtelizer2
523 @item @b{ft2232_vid_pid} <@var{vid}> <@var{pid}>
524 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
525 default values are used. Multiple <@var{vid}>, <@var{pid}> pairs may be given, eg.
527 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
529 @item @b{ft2232_latency} <@var{ms}>
530 On some systems using ft2232 based JTAG interfaces the FT_Read function call in
531 ft2232_read() fails to return the expected number of bytes. This can be caused by
532 USB communication delays and has proved hard to reproduce and debug. Setting the
533 FT2232 latency timer to a larger value increases delays for short USB packages but it
534 also reduces the risk of timeouts before receiving the expected number of bytes.
535 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
538 @section ep93xx options
539 @cindex ep93xx options
540 Currently, there are no options available for the ep93xx interface.
543 @section Target configuration
546 @item @b{target} <@var{type}> <@var{endianess}> <@var{JTAG pos}>
549 Defines a target that should be debugged. Currently supported types are:
563 If you want to use a target board that is not on this list, see Adding a new
566 Endianess may be @option{little} or @option{big}.
568 @item @b{target_script} <@var{target#}> <@var{event}> <@var{script_file}>
569 @cindex target_script
570 Event is one of the following:
571 @option{pre_reset}, @option{reset}, @option{post_reset}, @option{post_halt},
572 @option{pre_resume} or @option{gdb_program_config}.
573 @option{post_reset} and @option{reset} will produce the same results.
575 @item @b{working_area} <@var{target#}> <@var{address}> <@var{size}>
576 <@var{backup}|@var{nobackup}>
578 Specifies a working area for the debugger to use. This may be used to speed-up
579 downloads to target memory and flash operations, or to perform otherwise unavailable
580 operations (some coprocessor operations on ARM7/9 systems, for example). The last
581 parameter decides whether the memory should be preserved (<@var{backup}>) or can simply be overwritten (<@var{nobackup}>). If possible, use
582 a working_area that doesn't need to be backed up, as performing a backup slows down operation.
585 @subsection arm7tdmi options
586 @cindex arm7tdmi options
587 target arm7tdmi <@var{endianess}> <@var{jtag#}>
588 The arm7tdmi target definition requires at least one additional argument, specifying
589 the position of the target in the JTAG daisy-chain. The first JTAG device is number 0.
590 The optional [@var{variant}] parameter has been removed in recent versions.
591 The correct feature set is determined at runtime.
593 @subsection arm720t options
594 @cindex arm720t options
595 ARM720t options are similar to ARM7TDMI options.
597 @subsection arm9tdmi options
598 @cindex arm9tdmi options
599 ARM9TDMI options are similar to ARM7TDMI options. Supported variants are
600 @option{arm920t}, @option{arm922t} and @option{arm940t}.
601 This enables the hardware single-stepping support found on these cores.
603 @subsection arm920t options
604 @cindex arm920t options
605 ARM920t options are similar to ARM9TDMI options.
607 @subsection arm966e options
608 @cindex arm966e options
609 ARM966e options are similar to ARM9TDMI options.
611 @subsection cortex_m3 options
612 @cindex cortex_m3 options
613 use variant <@var{variant}> @option{lm3s} when debugging luminary lm3s targets. This will cause
614 openocd to use a software reset rather than asserting SRST to avoid a issue with clearing
615 the debug registers. This is fixed in Fury Rev B, DustDevil Rev B, Tempest, these revisions will
616 be detected and the normal reset behaviour used.
618 @subsection xscale options
619 @cindex xscale options
620 Supported variants are @option{ixp42x}, @option{ixp45x}, @option{ixp46x},
621 @option{pxa250}, @option{pxa255}, @option{pxa26x}.
623 @section Flash configuration
624 @cindex Flash configuration
627 @item @b{flash bank} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}>
628 <@var{bus_width}> <@var{target#}> [@var{driver_options ...}]
630 Configures a flash bank at <@var{base}> of <@var{size}> bytes and <@var{chip_width}>
631 and <@var{bus_width}> bytes using the selected flash <driver>.
634 @subsection lpc2000 options
635 @cindex lpc2000 options
637 @b{flash bank lpc2000} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
638 <@var{clock}> [@var{calc_checksum}]
639 LPC flashes don't require the chip and bus width to be specified. Additional
640 parameters are the <@var{variant}>, which may be @var{lpc2000_v1} (older LPC21xx and LPC22xx)
641 or @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx), the number
642 of the target this flash belongs to (first is 0), the frequency at which the core
643 is currently running (in kHz - must be an integral number), and the optional keyword
644 @var{calc_checksum}, telling the driver to calculate a valid checksum for the exception
647 @subsection cfi options
650 @b{flash bank cfi} <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}>
651 <@var{target#}> [@var{jedec_probe}|@var{x16_as_x8}]
652 CFI flashes require the number of the target they're connected to as an additional
653 argument. The CFI driver makes use of a working area (specified for the target)
654 to significantly speed up operation.
656 @var{chip_width} and @var{bus_width} are specified in bytes.
658 The @var{jedec_probe} option is used to detect certain non-CFI flash roms, like AM29LV010 and similar types.
662 @subsection at91sam7 options
663 @cindex at91sam7 options
665 @b{flash bank at91sam7} 0 0 0 0 <@var{target#}>
666 AT91SAM7 flashes only require the @var{target#}, all other values are looked up after
667 reading the chip-id and type.
669 @subsection str7 options
672 @b{flash bank str7x} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
673 variant can be either STR71x, STR73x or STR75x.
675 @subsection str9 options
678 @b{flash bank str9x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
679 The str9 needs the flash controller to be configured prior to Flash programming, eg.
681 str9x flash_config 0 4 2 0 0x80000
683 This will setup the BBSR, NBBSR, BBADR and NBBADR registers respectively.
685 @subsection str9 options (str9xpec driver)
687 @b{flash bank str9xpec} <@var{base}> <@var{size}> 0 0 <@var{target#}>
688 Before using the flash commands the turbo mode will need enabling using str9xpec
689 @option{enable_turbo} <@var{num>.}
691 Only use this driver for locking/unlocking the device or configuring the option bytes.
692 Use the standard str9 driver for programming.
694 @subsection stellaris (LM3Sxxx) options
695 @cindex stellaris (LM3Sxxx) options
697 @b{flash bank stellaris} <@var{base}> <@var{size}> 0 0 <@var{target#}>
698 stellaris flash plugin only require the @var{target#}.
700 @subsection stm32x options
701 @cindex stm32x options
703 @b{flash bank stm32x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
704 stm32x flash plugin only require the @var{target#}.
707 @chapter Target library
708 @cindex Target library
710 OpenOCD comes with a target configuration script library. These scripts can be
711 used as-is or serve as a starting point.
713 The target library is published together with the openocd executable and
714 the path to the target library is in the OpenOCD script search path.
715 Similarly there are example scripts for configuring the JTAG interface.
717 The command line below uses the example parport configuration scripts
718 that ship with OpenOCD, then configures the str710.cfg target and
719 finally issues the init and reset command. The communication speed
720 is set to 10kHz for reset and 8MHz for post reset.
724 openocd -f interface/parport.cfg -f target/str710.cfg -c "init" -c "reset"
728 To list the target scripts available:
731 $ ls /usr/local/lib/openocd/target
733 arm7_fast.cfg lm3s6965.cfg pxa255.cfg stm32.cfg xba_revA3.cfg
734 at91eb40a.cfg lpc2148.cfg pxa255_sst.cfg str710.cfg zy1000.cfg
735 at91r40008.cfg lpc2294.cfg sam7s256.cfg str912.cfg
736 at91sam9260.cfg nslu2.cfg sam7x256.cfg wi-9c.cfg
744 OpenOCD allows user interaction through a GDB server (default: port 3333),
745 a telnet interface (default: port 4444), and a TCL interface (default: port 5555). The command line interpreter
746 is available from both the telnet interface and a GDB session. To issue commands to the
747 interpreter from within a GDB session, use the @option{monitor} command, e.g. use
748 @option{monitor poll} to issue the @option{poll} command. All output is relayed through the
751 The TCL interface is used as a simplified RPC mechanism that feeds all the
752 input into the TCL interpreter and returns the output from the evaluation of
758 @item @b{sleep} <@var{msec}>
760 Wait for n milliseconds before resuming. Useful in connection with script files
761 (@var{script} command and @var{target_script} configuration).
765 Close the OpenOCD daemon, disconnecting all clients (GDB, Telnet, Other).
767 @item @b{debug_level} [@var{n}]
769 Display or adjust debug level to n<0-3>
771 @item @b{fast} [@var{enable/disable}]
773 Default disabled. Set default behaviour of OpenOCD to be "fast and dangerous". For instance ARM7/9 DCC memory
774 downloads and fast memory access will work if the JTAG interface isn't too fast and
775 the core doesn't run at a too low frequency. Note that this option only changes the default
776 and that the indvidual options, like DCC memory downloads, can be enabled and disabled
779 The target specific "dangerous" optimisation tweaking options may come and go
780 as more robust and user friendly ways are found to ensure maximum throughput
781 and robustness with a minimum of configuration.
783 Typically the "fast enable" is specified first on the command line:
786 openocd -c "fast enable" -c "interface dummy" -f target/str710.cfg
789 @item @b{log_output} <@var{file}>
791 Redirect logging to <file> (default: stderr)
793 @item @b{script} <@var{file}>
795 Execute commands from <file>
799 @subsection Target state handling
801 @item @b{poll} [@option{on}|@option{off}]
803 Poll the target for its current state. If the target is in debug mode, architecture
804 specific information about the current state is printed. An optional parameter
805 allows continuous polling to be enabled and disabled.
807 @item @b{halt} [@option{ms}]
809 Send a halt request to the target and wait for it to halt for up to [@option{ms}] milliseconds.
810 Default [@option{ms}] is 5 seconds if no arg given.
811 Optional arg @option{ms} is a timeout in milliseconds. Using 0 as the [@option{ms}]
812 will stop OpenOCD from waiting.
814 @item @b{wait_halt} [@option{ms}]
816 Wait for the target to enter debug mode. Optional [@option{ms}] is
817 a timeout in milliseconds. Default [@option{ms}] is 5 seconds if no
820 @item @b{resume} [@var{address}]
822 Resume the target at its current code position, or at an optional address.
823 OpenOCD will wait 5 seconds for the target to resume.
825 @item @b{step} [@var{address}]
827 Single-step the target at its current code position, or at an optional address.
829 @item @b{reset} [@option{run}|@option{halt}|@option{init}]
831 Perform a hard-reset. The optional parameter specifies what should happen after the reset.
833 With no arguments a "reset run" is executed
840 Immediately halt the target (works only with certain configurations).
843 Immediately halt the target, and execute the reset script (works only with certain
848 @subsection Memory access commands
849 These commands allow accesses of a specific size to the memory system:
851 @item @b{mdw} <@var{addr}> [@var{count}]
854 @item @b{mdh} <@var{addr}> [@var{count}]
856 display memory half-words
857 @item @b{mdb} <@var{addr}> [@var{count}]
860 @item @b{mww} <@var{addr}> <@var{value}>
863 @item @b{mwh} <@var{addr}> <@var{value}>
865 write memory half-word
866 @item @b{mwb} <@var{addr}> <@var{value}>
870 @item @b{load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
872 Load image <@var{file}> to target memory at <@var{address}>
873 @item @b{dump_image} <@var{file}> <@var{address}> <@var{size}>
875 Dump <@var{size}> bytes of target memory starting at <@var{address}> to a
876 (binary) <@var{file}>.
877 @item @b{verify_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
879 Verify <@var{file}> against target memory starting at <@var{address}>.
880 This will first attempt comparison using a crc checksum, if this fails it will try a binary compare.
883 @subsection Flash commands
884 @cindex Flash commands
886 @item @b{flash banks}
888 List configured flash banks
889 @item @b{flash info} <@var{num}>
891 Print info about flash bank <@option{num}>
892 @item @b{flash probe} <@var{num}>
894 Identify the flash, or validate the parameters of the configured flash. Operation
895 depends on the flash type.
896 @item @b{flash erase_check} <@var{num}>
897 @cindex flash erase_check
898 Check erase state of sectors in flash bank <@var{num}>. This is the only operation that
899 updates the erase state information displayed by @option{flash info}. That means you have
900 to issue an @option{erase_check} command after erasing or programming the device to get
902 @item @b{flash protect_check} <@var{num}>
903 @cindex flash protect_check
904 Check protection state of sectors in flash bank <num>.
905 @option{flash erase_sector} using the same syntax.
906 @item @b{flash erase_sector} <@var{num}> <@var{first}> <@var{last}>
907 @cindex flash erase_sector
908 Erase sectors at bank <@var{num}>, starting at sector <@var{first}> up to and including
909 <@var{last}>. Sector numbering starts at 0. Depending on the flash type, erasing may
910 require the protection to be disabled first (e.g. Intel Advanced Bootblock flash using
912 @item @b{flash erase_address} <@var{address}> <@var{length}>
913 @cindex flash erase_address
914 Erase sectors starting at <@var{address}> for <@var{length}> bytes
915 @item @b{flash write_bank} <@var{num}> <@var{file}> <@var{offset}>
916 @cindex flash write_bank
917 Write the binary <@var{file}> to flash bank <@var{num}>, starting at
918 <@option{offset}> bytes from the beginning of the bank.
919 @item @b{flash write_image} [@var{erase}] <@var{file}> [@var{offset}] [@var{type}]
920 @cindex flash write_image
921 Write the image <@var{file}> to the current target's flash bank(s). A relocation
922 [@var{offset}] can be specified and the file [@var{type}] can be specified
923 explicitly as @option{bin} (binary), @option{ihex} (Intel hex), @option{elf}
924 (ELF file) or @option{s19} (Motorola s19). Flash memory will be erased prior to programming
925 if the @option{erase} parameter is given.
926 @item @b{flash protect} <@var{num}> <@var{first}> <@var{last}> <@option{on}|@option{off}>
927 @cindex flash protect
928 Enable (@var{on}) or disable (@var{off}) protection of flash sectors <@var{first}> to
929 <@var{last}> of @option{flash bank} <@var{num}>.
933 @section Target Specific Commands
934 @cindex Target Specific Commands
936 @subsection AT91SAM7 specific commands
937 @cindex AT91SAM7 specific commands
938 The flash configuration is deduced from the chip identification register. The flash
939 controller handles erases automatically on a page (128/265 byte) basis so erase is
940 not necessary for flash programming. AT91SAM7 processors with less than 512K flash
941 only have a single flash bank embedded on chip. AT91SAM7xx512 have two flash planes
942 that can be erased separatly. Only an EraseAll command is supported by the controller
943 for each flash plane and this is called with
945 @item @b{flash erase} <@var{num}> @var{first_plane} @var{last_plane}
946 bulk erase flash planes first_plane to last_plane.
947 @item @b{at91sam7 gpnvm} <@var{num}> <@var{bit}> <@option{set}|@option{clear}>
948 @cindex at91sam7 gpnvm
949 set or clear a gpnvm bit for the processor
952 @subsection STR9 specific commands
953 @cindex STR9 specific commands
954 These are flash specific commands when using the str9xpec driver.
956 @item @b{str9xpec enable_turbo} <@var{num}>
957 @cindex str9xpec enable_turbo
958 enable turbo mode, simply this will remove the str9 from the chain and talk
959 directly to the embedded flash controller.
960 @item @b{str9xpec disable_turbo} <@var{num}>
961 @cindex str9xpec disable_turbo
962 restore the str9 into jtag chain.
963 @item @b{str9xpec lock} <@var{num}>
964 @cindex str9xpec lock
965 lock str9 device. The str9 will only respond to an unlock command that will
967 @item @b{str9xpec unlock} <@var{num}>
968 @cindex str9xpec unlock
970 @item @b{str9xpec options_read} <@var{num}>
971 @cindex str9xpec options_read
972 read str9 option bytes.
973 @item @b{str9xpec options_write} <@var{num}>
974 @cindex str9xpec options_write
975 write str9 option bytes.
978 @subsection STR9 configuration
979 @cindex STR9 configuration
981 @item @b{str9x flash_config} <@var{bank}> <@var{BBSR}> <@var{NBBSR}>
982 <@var{BBADR}> <@var{NBBADR}>
983 @cindex str9x flash_config
984 Configure str9 flash controller.
986 eg. str9x flash_config 0 4 2 0 0x80000
988 BBSR - Boot Bank Size register
989 NBBSR - Non Boot Bank Size register
990 BBADR - Boot Bank Start Address register
991 NBBADR - Boot Bank Start Address register
995 @subsection STR9 option byte configuration
996 @cindex STR9 option byte configuration
998 @item @b{str9xpec options_cmap} <@var{num}> <@option{bank0}|@option{bank1}>
999 @cindex str9xpec options_cmap
1000 configure str9 boot bank.
1001 @item @b{str9xpec options_lvdthd} <@var{num}> <@option{2.4v}|@option{2.7v}>
1002 @cindex str9xpec options_lvdthd
1003 configure str9 lvd threshold.
1004 @item @b{str9xpec options_lvdsel} <@var{num}> <@option{vdd}|@option{vdd_vddq}>
1005 @cindex str9xpec options_lvdsel
1006 configure str9 lvd source.
1007 @item @b{str9xpec options_lvdwarn} <@var{bank}> <@option{vdd}|@option{vdd_vddq}>
1008 @cindex str9xpec options_lvdwarn
1009 configure str9 lvd reset warning source.
1012 @subsection STM32x specific commands
1013 @cindex STM32x specific commands
1015 These are flash specific commands when using the stm32x driver.
1017 @item @b{stm32x lock} <@var{num}>
1020 @item @b{stm32x unlock} <@var{num}>
1021 @cindex stm32x unlock
1022 unlock stm32 device.
1023 @item @b{stm32x options_read} <@var{num}>
1024 @cindex stm32x options_read
1025 read stm32 option bytes.
1026 @item @b{stm32x options_write} <@var{num}> <@option{SWWDG}|@option{HWWDG}>
1027 <@option{RSTSTNDBY}|@option{NORSTSTNDBY}> <@option{RSTSTOP}|@option{NORSTSTOP}>
1028 @cindex stm32x options_write
1029 write stm32 option bytes.
1030 @item @b{stm32x mass_erase} <@var{num}>
1031 @cindex stm32x mass_erase
1032 mass erase flash memory.
1035 @subsection Stellaris specific commands
1036 @cindex Stellaris specific commands
1038 These are flash specific commands when using the Stellaris driver.
1040 @item @b{stellaris mass_erase} <@var{num}>
1041 @cindex stellaris mass_erase
1042 mass erase flash memory.
1046 @section Architecture Specific Commands
1047 @cindex Architecture Specific Commands
1049 @subsection ARMV4/5 specific commands
1050 @cindex ARMV4/5 specific commands
1052 These commands are specific to ARM architecture v4 and v5, like all ARM7/9 systems
1053 or Intel XScale (XScale isn't supported yet).
1055 @item @b{armv4_5 reg}
1057 Display a list of all banked core registers, fetching the current value from every
1058 core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
1060 @item @b{armv4_5 core_mode} [@var{arm}|@var{thumb}]
1061 @cindex armv4_5 core_mode
1062 Displays the core_mode, optionally changing it to either ARM or Thumb mode.
1063 The target is resumed in the currently set @option{core_mode}.
1066 @subsection ARM7/9 specific commands
1067 @cindex ARM7/9 specific commands
1069 These commands are specific to ARM7 and ARM9 targets, like ARM7TDMI, ARM720t,
1070 ARM920t or ARM926EJ-S.
1072 @item @b{arm7_9 dbgrq} <@var{enable}|@var{disable}>
1073 @cindex arm7_9 dbgrq
1074 Enable use of the DBGRQ bit to force entry into debug mode. This should be
1075 safe for all but ARM7TDMI--S cores (like Philips LPC).
1076 @item @b{arm7_9 fast_memory_access} <@var{enable}|@var{disable}>
1077 @cindex arm7_9 fast_memory_access
1078 Allow OpenOCD to read and write memory without checking completion of
1079 the operation. This provides a huge speed increase, especially with USB JTAG
1080 cables (FT2232), but might be unsafe if used with targets running at a very low
1081 speed, like the 32kHz startup clock of an AT91RM9200.
1082 @item @b{arm7_9 dcc_downloads} <@var{enable}|@var{disable}>
1083 @cindex arm7_9 dcc_downloads
1084 Enable the use of the debug communications channel (DCC) to write larger (>128 byte)
1085 amounts of memory. DCC downloads offer a huge speed increase, but might be potentially
1086 unsafe, especially with targets running at a very low speed. This command was introduced
1087 with OpenOCD rev. 60.
1090 @subsection ARM720T specific commands
1091 @cindex ARM720T specific commands
1094 @item @b{arm720t cp15} <@var{num}> [@var{value}]
1095 @cindex arm720t cp15
1096 display/modify cp15 register <@option{num}> [@option{value}].
1097 @item @b{arm720t md<bhw>_phys} <@var{addr}> [@var{count}]
1098 @cindex arm720t md<bhw>_phys
1099 Display memory at physical address addr.
1100 @item @b{arm720t mw<bhw>_phys} <@var{addr}> <@var{value}>
1101 @cindex arm720t mw<bhw>_phys
1102 Write memory at physical address addr.
1103 @item @b{arm720t virt2phys} <@var{va}>
1104 @cindex arm720t virt2phys
1105 Translate a virtual address to a physical address.
1108 @subsection ARM9TDMI specific commands
1109 @cindex ARM9TDMI specific commands
1112 @item @b{arm9tdmi vector_catch} <@var{all}|@var{none}>
1113 @cindex arm9tdmi vector_catch
1114 Catch arm9 interrupt vectors, can be @option{all} @option{none} or any of the following:
1115 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt} @option{reserved}
1116 @option{irq} @option{fiq}.
1118 Can also be used on other arm9 based cores, arm966, arm920t and arm926ejs.
1121 @subsection ARM966E specific commands
1122 @cindex ARM966E specific commands
1125 @item @b{arm966e cp15} <@var{num}> [@var{value}]
1126 @cindex arm966e cp15
1127 display/modify cp15 register <@option{num}> [@option{value}].
1130 @subsection ARM920T specific commands
1131 @cindex ARM920T specific commands
1134 @item @b{arm920t cp15} <@var{num}> [@var{value}]
1135 @cindex arm920t cp15
1136 display/modify cp15 register <@option{num}> [@option{value}].
1137 @item @b{arm920t cp15i} <@var{num}> [@var{value}] [@var{address}]
1138 @cindex arm920t cp15i
1139 display/modify cp15 (interpreted access) <@option{opcode}> [@option{value}] [@option{address}]
1140 @item @b{arm920t cache_info}
1141 @cindex arm920t cache_info
1142 Print information about the caches found. This allows you to see if your target
1143 is a ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
1144 @item @b{arm920t md<bhw>_phys} <@var{addr}> [@var{count}]
1145 @cindex arm920t md<bhw>_phys
1146 Display memory at physical address addr.
1147 @item @b{arm920t mw<bhw>_phys} <@var{addr}> <@var{value}>
1148 @cindex arm920t mw<bhw>_phys
1149 Write memory at physical address addr.
1150 @item @b{arm920t read_cache} <@var{filename}>
1151 @cindex arm920t read_cache
1152 Dump the content of ICache and DCache to a file.
1153 @item @b{arm920t read_mmu} <@var{filename}>
1154 @cindex arm920t read_mmu
1155 Dump the content of the ITLB and DTLB to a file.
1156 @item @b{arm920t virt2phys} <@var{va}>
1157 @cindex arm920t virt2phys
1158 Translate a virtual address to a physical address.
1161 @subsection ARM926EJS specific commands
1162 @cindex ARM926EJS specific commands
1165 @item @b{arm926ejs cp15} <@var{num}> [@var{value}]
1166 @cindex arm926ejs cp15
1167 display/modify cp15 register <@option{num}> [@option{value}].
1168 @item @b{arm926ejs cache_info}
1169 @cindex arm926ejs cache_info
1170 Print information about the caches found.
1171 @item @b{arm926ejs md<bhw>_phys} <@var{addr}> [@var{count}]
1172 @cindex arm926ejs md<bhw>_phys
1173 Display memory at physical address addr.
1174 @item @b{arm926ejs mw<bhw>_phys} <@var{addr}> <@var{value}>
1175 @cindex arm926ejs mw<bhw>_phys
1176 Write memory at physical address addr.
1177 @item @b{arm926ejs virt2phys} <@var{va}>
1178 @cindex arm926ejs virt2phys
1179 Translate a virtual address to a physical address.
1183 @section Debug commands
1184 @cindex Debug commands
1185 The following commands give direct access to the core, and are most likely
1186 only useful while debugging OpenOCD.
1188 @item @b{arm7_9 write_xpsr} <@var{32-bit value}> <@option{0=cpsr}, @option{1=spsr}>
1189 @cindex arm7_9 write_xpsr
1190 Immediately write either the current program status register (CPSR) or the saved
1191 program status register (SPSR), without changing the register cache (as displayed
1192 by the @option{reg} and @option{armv4_5 reg} commands).
1193 @item @b{arm7_9 write_xpsr_im8} <@var{8-bit value}> <@var{rotate 4-bit}>
1194 <@var{0=cpsr},@var{1=spsr}>
1195 @cindex arm7_9 write_xpsr_im8
1196 Write the 8-bit value rotated right by 2*rotate bits, using an immediate write
1197 operation (similar to @option{write_xpsr}).
1198 @item @b{arm7_9 write_core_reg} <@var{num}> <@var{mode}> <@var{value}>
1199 @cindex arm7_9 write_core_reg
1200 Write a core register, without changing the register cache (as displayed by the
1201 @option{reg} and @option{armv4_5 reg} commands). The <@var{mode}> argument takes the
1202 encoding of the [M4:M0] bits of the PSR.
1206 @section JTAG commands
1207 @cindex JTAG commands
1209 @item @b{scan_chain}
1211 Print current scan chain configuration.
1212 @item @b{jtag_reset} <@var{trst}> <@var{srst}>
1215 @item @b{endstate} <@var{tap_state}>
1217 Finish JTAG operations in <@var{tap_state}>.
1218 @item @b{runtest} <@var{num_cycles}>
1220 Move to Run-Test/Idle, and execute <@var{num_cycles}>
1221 @item @b{statemove} [@var{tap_state}]
1223 Move to current endstate or [@var{tap_state}]
1224 @item @b{irscan} <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
1226 Execute IR scan <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
1227 @item @b{drscan} <@var{device}> [@var{dev2}] [@var{var2}] ...
1229 Execute DR scan <@var{device}> [@var{dev2}] [@var{var2}] ...
1230 @item @b{verify_ircapture} <@option{enable}|@option{disable}>
1231 @cindex verify_ircapture
1232 Verify value captured during Capture-IR. Default is enabled.
1233 @item @b{var} <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
1235 Allocate, display or delete variable <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
1236 @item @b{field} <@var{var}> <@var{field}> [@var{value}|@var{flip}]
1238 Display/modify variable field <@var{var}> <@var{field}> [@var{value}|@var{flip}].
1242 @section Target Requests
1243 @cindex Target Requests
1244 OpenOCD can handle certain target requests, currently debugmsg are only supported for arm7_9 and cortex_m3.
1245 See libdcc in the contrib dir for more details.
1247 @item @b{target_request debugmsgs} <@var{enable}|@var{disable}>
1248 @cindex target_request debugmsgs
1249 Enable/disable target debugmsgs requests. debugmsgs enable messages to be sent to the debugger while the target is running.
1252 @node Sample Scripts
1253 @chapter Sample Scripts
1256 This page shows how to use the target library.
1258 The configuration script can be divided in the following section:
1260 @item daemon configuration
1262 @item jtag scan chain
1263 @item target configuration
1264 @item flash configuration
1267 Detailed information about each section can be found at OpenOCD configuration.
1269 @section AT91R40008 example
1270 @cindex AT91R40008 example
1271 To start OpenOCD with a target script for the AT91R40008 CPU and reset
1272 the CPU upon startup of the OpenOCD daemon.
1274 openocd -f interface/parport.cfg -f target/at91r40008.cfg -c init -c reset
1278 @node GDB and OpenOCD
1279 @chapter GDB and OpenOCD
1280 @cindex GDB and OpenOCD
1281 OpenOCD complies with the remote gdbserver protocol, and as such can be used
1282 to debug remote targets.
1284 @section Connecting to gdb
1285 @cindex Connecting to gdb
1286 A connection is typically started as follows:
1288 target remote localhost:3333
1290 This would cause gdb to connect to the gdbserver on the local pc using port 3333.
1292 To see a list of available OpenOCD commands type @option{monitor help} on the
1295 OpenOCD supports the gdb @option{qSupported} packet, this enables information
1296 to be sent by the gdb server (openocd) to gdb. Typical information includes
1297 packet size and device memory map.
1299 Previous versions of OpenOCD required the following gdb options to increase
1300 the packet size and speed up gdb communication.
1302 set remote memory-write-packet-size 1024
1303 set remote memory-write-packet-size fixed
1304 set remote memory-read-packet-size 1024
1305 set remote memory-read-packet-size fixed
1307 This is now handled in the @option{qSupported} PacketSize.
1309 @section Programming using gdb
1310 @cindex Programming using gdb
1312 By default the target memory map is sent to gdb, this can be disabled by
1313 the following OpenOCD config option:
1315 gdb_memory_map disable
1317 For this to function correctly a valid flash config must also be configured
1318 in OpenOCD. For faster performance you should also configure a valid
1321 Informing gdb of the memory map of the target will enable gdb to protect any
1322 flash area of the target and use hardware breakpoints by default. This means
1323 that the OpenOCD option @option{gdb_breakpoint_override} is not required when
1326 To view the configured memory map in gdb, use the gdb command @option{info mem}
1327 All other unasigned addresses within gdb are treated as RAM.
1329 GDB 6.8 and higher set any memory area not in the memory map as inaccessible,
1330 this can be changed to the old behaviour by using the following gdb command.
1332 set mem inaccessible-by-default off
1335 If @option{gdb_flash_program enable} is also used, gdb will be able to
1336 program any flash memory using the vFlash interface.
1338 gdb will look at the target memory map when a load command is given, if any
1339 areas to be programmed lie within the target flash area the vFlash packets
1342 If the target needs configuring before gdb programming, a script can be executed.
1344 target_script 0 gdb_program_config config.script
1347 To verify any flash programming the gdb command @option{compare-sections}
1350 @node TCL and OpenOCD
1351 @chapter TCL and OpenOCD
1352 @cindex TCL and OpenOCD
1353 OpenOCD embeds a TCL interpreter (see JIM) for command parsing and scripting
1356 The TCL interpreter can be invoked from the interactive command line, files, and a network port.
1358 The command and file interfaces are fairly straightforward, while the network
1359 port is geared toward intergration with external clients. A small example
1360 of an external TCL script that can connect to openocd is shown below.
1363 # Simple tcl client to connect to openocd
1364 puts "Use empty line to exit"
1365 set fo [socket 127.0.0.1 6666]
1366 puts -nonewline stdout "> "
1368 while {[gets stdin line] >= 0} {
1369 if {$line eq {}} break
1374 puts -nonewline stdout "> "
1380 This script can easily be modified to front various GUIs or be a sub
1381 component of a larger framework for control and interaction.
1384 @node TCL scripting API
1385 @chapter TCL scripting API
1386 @cindex TCL scripting API
1389 The commands are stateless. E.g. the telnet command line has a concept
1390 of currently active target, the Tcl API proc's take this sort of state
1391 information as an argument to each proc.
1393 There are three main types of return values: single value, name value
1394 pair list and lists.
1396 Name value pair. The proc 'foo' below returns a name/value pair
1402 > set foo(you) Oyvind
1403 > set foo(mouse) Micky
1404 > set foo(duck) Donald
1412 me Duane you Oyvind mouse Micky duck Donald
1414 Thus, to get the names of the associative array is easy:
1416 foreach { name value } [set foo] {
1417 puts "Name: $name, Value: $value"
1421 Lists returned must be relatively small. Otherwise a range
1422 should be passed in to the proc in question.
1424 Low level commands are prefixed with "openocd_", e.g. openocd_flash_banks
1425 is the low level API upon which "flash banks" is implemented.
1427 OpenOCD commands can consist of two words, e.g. "flash banks". The
1428 startup.tcl "unknown" proc will translate this into a tcl proc
1429 called "flash_banks".
1433 @chapter Deprecated/Removed Commands
1434 @cindex Deprecated/Removed Commands
1435 Certain OpenOCD commands have been deprecated/removed during the various revisions.
1438 @item @b{load_binary}
1440 use @option{load_image} command with same args
1441 @item @b{dump_binary}
1443 use @option{dump_image} command with same args
1444 @item @b{flash erase}
1446 use @option{flash erase_sector} command with same args
1447 @item @b{flash write}
1449 use @option{flash write_bank} command with same args
1450 @item @b{flash write_binary}
1451 @cindex flash write_binary
1452 use @option{flash write_bank} command with same args
1453 @item @b{arm7_9 fast_writes}
1454 @cindex arm7_9 fast_writes
1455 use @option{arm7_9 fast_memory_access} command with same args
1456 @item @b{flash auto_erase}
1457 @cindex flash auto_erase
1458 use @option{flash write_image} command passing @option{erase} as the first parameter.
1459 @item @b{daemon_startup}
1460 @cindex daemon_startup
1461 this config option has been removed, simply adding @option{init} and @option{reset halt} to
1462 the end of your config script will give the same behaviour as using @option{daemon_startup reset}
1463 and @option{target cortex_m3 little reset_halt 0}.
1464 @item @b{arm7_9 sw_bkpts}
1465 @cindex arm7_9 sw_bkpts
1466 On by default. See also @option{gdb_breakpoint_override}.
1467 @item @b{arm7_9 force_hw_bkpts}
1468 @cindex arm7_9 force_hw_bkpts
1469 Use @option{gdb_breakpoint_override} instead. Note that GDB will use hardware breakpoints
1470 for flash if the gdb memory map has been set up(default when flash is declared in
1471 target configuration).
1472 @item @b{run_and_halt_time}
1473 @cindex run_and_halt_time
1474 This command has been removed for simpler reset behaviour, it can be simulated with the
1487 @item OpenOCD complains about a missing cygwin1.dll.
1489 Make sure you have Cygwin installed, or at least a version of OpenOCD that
1490 claims to come with all the necessary dlls. When using Cygwin, try launching
1491 OpenOCD from the Cygwin shell.
1493 @item I'm trying to set a breakpoint using GDB (or a frontend like Insight or
1494 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
1495 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
1497 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
1498 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720t or ARM920t,
1499 software breakpoints consume one of the two available hardware breakpoints.
1501 @item When erasing or writing LPC2000 on-chip flash, the operation fails sometimes
1502 and works sometimes fine.
1504 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
1505 clock at the time you're programming the flash. If you've specified the crystal's
1506 frequency, make sure the PLL is disabled, if you've specified the full core speed
1507 (e.g. 60MHz), make sure the PLL is enabled.
1509 @item When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
1510 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
1511 out while waiting for end of scan, rtck was disabled".
1513 Make sure your PC's parallel port operates in EPP mode. You might have to try several
1514 settings in your PC BIOS (ECP, EPP, and different versions of those).
1516 @item When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
1517 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
1518 memory read caused data abort".
1520 The errors are non-fatal, and are the result of GDB trying to trace stack frames
1521 beyond the last valid frame. It might be possible to prevent this by setting up
1522 a proper "initial" stack frame, if you happen to know what exactly has to
1523 be done, feel free to add this here.
1525 @item I get the following message in the OpenOCD console (or log file):
1526 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
1528 This warning doesn't indicate any serious problem, as long as you don't want to
1529 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
1530 trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
1531 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
1532 independently. With this setup, it's not possible to halt the core right out of
1533 reset, everything else should work fine.
1535 @item When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
1536 Toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
1537 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
1538 quit with an error message. Is there a stability issue with OpenOCD?
1540 No, this is not a stability issue concerning OpenOCD. Most users have solved
1541 this issue by simply using a self-powered USB hub, which they connect their
1542 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
1543 supply stable enough for the Amontec JTAGkey to be operated.
1545 @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
1546 following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
1547 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
1548 What does that mean and what might be the reason for this?
1550 First of all, the reason might be the USB power supply. Try using a self-powered
1551 hub instead of a direct connection to your computer. Secondly, the error code 4
1552 corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
1553 chip ran into some sort of error - this points us to a USB problem.
1555 @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
1556 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
1557 What does that mean and what might be the reason for this?
1559 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
1560 has closed the connection to OpenOCD. This might be a GDB issue.
1562 @item In the configuration file in the section where flash device configurations
1563 are described, there is a parameter for specifying the clock frequency for
1564 LPC2000 internal flash devices (e.g.
1565 @option{flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14746 calc_checksum}),
1566 which must be specified in kilohertz. However, I do have a quartz crystal of a
1567 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz, i.e. 14,745.600 kHz).
1568 Is it possible to specify real numbers for the clock frequency?
1570 No. The clock frequency specified here must be given as an integral number.
1571 However, this clock frequency is used by the In-Application-Programming (IAP)
1572 routines of the LPC2000 family only, which seems to be very tolerant concerning
1573 the given clock frequency, so a slight difference between the specified clock
1574 frequency and the actual clock frequency will not cause any trouble.
1576 @item Do I have to keep a specific order for the commands in the configuration file?
1578 Well, yes and no. Commands can be given in arbitrary order, yet the devices
1579 listed for the JTAG scan chain must be given in the right order (jtag_device),
1580 with the device closest to the TDO-Pin being listed first. In general,
1581 whenever objects of the same type exist which require an index number, then
1582 these objects must be given in the right order (jtag_devices, targets and flash
1583 banks - a target references a jtag_device and a flash bank references a target).
1585 @item Sometimes my debugging session terminates with an error. When I look into the
1586 log file, I can see these error messages: Error: arm7_9_common.c:561
1587 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP