1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle Open On-Chip Debugger (openocd)
10 @title Open On-Chip Debugger (openocd)
11 @subtitle Edition @value{EDITION} for openocd version @value{VERSION}
12 @subtitle @value{UPDATED}
14 @vskip 0pt plus 1filll
19 @node Top, About, , (dir)
22 This is edition @value{EDITION} of the openocd manual for version
23 @value{VERSION}, @value{UPDATED}
26 * About:: About Openocd.
28 * Building:: Building Openocd
29 * Running:: Running Openocd
30 * Configuration:: Openocd Configuration.
31 * Commands:: Openocd Commands
32 * Sample Scripts:: Sample Target Scripts
33 * GDB and Openocd:: Using GDB and Openocd
34 * FAQ:: Frequently Asked Questions
35 * License:: GNU Free Documentation License
43 The Open On-Chip Debugger (openocd) aims to provide debugging, in-system programming
44 and boundary-scan testing for embedded target devices. The targets are interfaced
45 using JTAG (IEEE 1149.1) compliant hardware, but this may be extended to other
46 connection types in the future.
48 Openocd currently supports Wiggler (clones), FTDI FT2232 based JTAG interfaces, the
49 Amontec JTAG Accelerator, and the Gateworks GW1602. It allows ARM7 (ARM7TDMI and ARM720t),
50 ARM9 (ARM920t, ARM922t, ARM926ej--s, ARM966e--s), XScale (PXA25x, IXP42x) and
51 Cortex-M3 (Luminary Stellaris LM3 and ST STM32) based cores to be debugged.
53 Flash writing is supported for external CFI compatible flashes (Intel and AMD/Spansion
54 command set) and several internal flashes (LPC2000, AT91SAM7, STR7x, STR9x, LM3
55 and STM32x). Preliminary support for using the LPC3180's NAND flash controller is included.
61 Openocd has been created by Dominic Rath as part of a diploma thesis written at the
62 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
63 Others interested in improving the state of free and open debug and testing technology
64 are welcome to participate.
66 Other developers have contributed support for additional targets and flashes as well
67 as numerous bugfixes and enhancements. See the AUTHORS file for regular contributors.
71 @cindex building openocd
73 You can download the current SVN version with SVN client of your choice from the
74 following repositories:
76 (@uref{svn://svn.berlios.de/openocd/trunk})
80 (@uref{http://svn.berlios.de/svnroot/repos/openocd/trunk})
82 Using the SVN command line client, you could use the following command to fetch the
83 latest version (make sure there is no (non-svn) directory called "openocd" in the
87 svn checkout svn://svn.berlios.de/openocd/trunk
90 Building the OpenOCD requires a recent version of the GNU autotools.
91 On my build system, I'm using autoconf 2.13 and automake 1.9. For building on Windows,
92 you have to use Cygwin. Make sure that your @env{PATH} environment variable contains no
93 other locations with Unix utils (like UnxUtils) - these can't handle the Cygwin
94 paths, resulting in obscure dependency errors (This is an observation I've gathered
95 from the logs of one user - correct me if I'm wrong).
97 You further need the appropriate driver files, if you want to build support for
98 a FTDI FT2232 based interface:
100 @item @b{ftdi2232} libftdi (@uref{http://www.intra2net.com/opensource/ftdi/})
101 @item @b{ftd2xx} libftd2xx (@uref{http://www.ftdichip.com/Drivers/D2XX.htm})
102 @item When using the Amontec JTAGkey, you have to get the drivers from the Amontec
103 homepage (@uref{www.amontec.com}), as the JTAGkey uses a non-standard VID/PID.
106 Please note that the ftdi2232 variant (using libftdi) isn't supported under Cygwin.
107 You have to use the ftd2xx variant (using FTDI's D2XX) on Cygwin.
109 In general, the D2XX driver provides superior performance (several times as fast),
110 but has the draw-back of being binary-only - though that isn't as worse, as it isn't
111 a kernel module, only a user space library.
113 To build OpenOCD (on both Linux and Cygwin), use the following commands:
117 Bootstrap generates the configure script, and prepares building on your system.
121 Configure generates the Makefiles used to build OpenOCD
125 Make builds the OpenOCD, and places the final executable in ./src/
127 The configure script takes several options, specifying which JTAG interfaces
134 --enable-parport_ppdev
136 --enable-amtjtagaccel
138 --enable-ft2232_ftd2xx
139 @footnote{Using the latest D2XX drivers from FTDI and following their installation
140 instructions, I had to use @option{--enable-ft2232_libftd2xx} for the OpenOCD to
143 --enable-ft2232_libftdi
145 --with-ftd2xx=/path/to/d2xx/
148 If you want to access the parallel port using the PPDEV interface you have to specify
149 both the @option{--enable-parport} AND the @option{--enable-parport_ppdev} option since
150 the @option{--enable-parport_ppdev} option actually is an option to the parport driver
151 (see @uref{http://forum.sparkfun.com/viewtopic.php?t=3795} for more info).
153 Cygwin users have to specify the location of the FTDI D2XX package. This should be an
154 absolute path containing no spaces.
156 Linux users should copy the various parts of the D2XX package to the appropriate
157 locations, i.e. /usr/include, /usr/lib.
161 @cindex running openocd
162 The OpenOCD runs as a daemon, waiting for connections from clients (Telnet or GDB).
163 Run with @option{--help} or @option{-h} to view the available command line arguments.
165 It reads its configuration by default from the file openocd.cfg located in the current
166 working directory. This may be overwritten with the @option{-f <configfile>} command line
169 To enable debug output (when reporting problems or working on OpenOCD itself), use
170 the @option{-d} command line switch. This sets the debug_level to "3", outputting
171 the most information, including debug messages. The default setting is "2", outputting
172 only informational messages, warnings and errors. You can also change this setting
173 from within a telnet or gdb session (@option{debug_level <n>}).
175 You can redirect all output from the daemon to a file using the @option{-l <logfile>} switch.
178 @chapter Configuration
179 @cindex configuration
180 The Open On-Chip Debugger (OpenOCD) runs as a daemon, and reads it current configuration
181 by default from the file openocd.cfg in the current directory. A different configuration
182 file can be specified with the @option{-f <conf.file>} given at the openocd command line.
184 The configuration file is used to specify on which ports the daemon listens for new
185 connections, the JTAG interface used to connect to the target, the layout of the JTAG
186 chain, the targets that should be debugged, and connected flashes.
188 @section Daemon configuration
191 @item @b{telnet_port} <@var{number}>
193 Port on which to listen for incoming telnet connections
194 @item @b{gdb_port} <@var{number}>
196 First port on which to listen for incoming GDB connections. The GDB port for the
197 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
198 @item @b{gdb_detach} <@var{resume|reset|halt|nothing}>
200 Configures what openocd will do when gdb detaches from the daeman.
201 Default behaviour is <@var{resume}>
202 @item @b{gdb_memory_map} <@var{enable|disable}>
203 @cindex gdb_memory_map
204 Set to <@var{enable}> so that openocd will send the memory configuration to gdb when
205 requested. gdb will then know when to set hardware breakpoints, and program flash
206 using the gdb load command. @option{gdb_flash_program enable} will also need enabling
207 for flash programming to work.
208 Default behaviour is <@var{disable}>
209 @item @b{gdb_flash_program} <@var{enable|disable}>
210 @cindex gdb_flash_program
211 Set to <@var{enable}> so that openocd will program the flash memory when a
212 vFlash packet is received.
213 Default behaviour is <@var{disable}>
214 @item @b{daemon_startup} <@var{mode}> either @samp{attach} or @samp{reset}
215 @cindex daemon_startup
216 Tells the OpenOCD whether it should reset the target when the daemon is launched, or
217 if it should just attach to the target.
220 @section JTAG interface configuration
223 @item @b{interface} <@var{name}>
225 Use the interface driver <@var{name}> to connect to the target. Currently supported
229 PC parallel port bit-banging (Wigglers, PLD download cable, ...)
233 Amontec Chameleon in its JTAG Accelerator configuration connected to a PC's EPP
238 FTDI FT2232 based devices using either the open-source libftdi or the binary only
239 FTD2XX driver. The FTD2XX is superior in performance, but not available on every
240 platform. The libftdi uses libusb, and should be portable to all systems that provide
245 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
250 @item @b{jtag_speed} <@var{number}>
252 Limit the maximum speed of the JTAG interface. Usually, a value of zero means maximum
253 speed. The actual effect of this option depends on the JTAG interface used.
256 @item wiggler: maximum speed / @var{number}
257 @item ft2232: 6MHz / (@var{number}+1)
258 @item amt jtagaccel: 8 / 2**@var{number}
261 Note: Make sure the jtag clock is no more than @math{1/6th × CPU-Clock}. This is
262 especially true for synthesized cores (-S).
264 @item @b{reset_config} <@var{signals}> [@var{combination}] [@var{trst_type}] [@var{srst_type}]
266 The configuration of the reset signals available on the JTAG interface AND the target.
267 If the JTAG interface provides SRST, but the target doesn't connect that signal properly,
268 then OpenOCD can't use it. <@var{signals}> can be @samp{none}, @samp{trst_only},
269 @samp{srst_only} or @samp{trst_and_srst}.
270 [@var{combination}] is an optional value specifying broken reset signal implementations.
271 @samp{srst_pulls_trst} states that the testlogic is reset together with the reset of
272 the system (e.g. Philips LPC2000, "broken" board layout), @samp{trst_pulls_srst} says
273 that the system is reset together with the test logic (only hypothetical, I haven't
274 seen hardware with such a bug, and can be worked around).
276 The [@var{trst_type}] and [@var{srst_type}] parameters allow the driver type of the
277 reset lines to be specified. Possible values are @samp{trst_push_pull} (default)
278 and @samp{trst_open_drain} for the test reset signal, and @samp{srst_open_drain}
279 (default) and @samp{srst_push_pull} for the system reset. These values only affect
280 JTAG interfaces with support for different drivers, like the Amontec JTAGkey and JTAGAccelerator.
282 @item @b{jtag_device} <@var{IR length}> <@var{IR capture}> <@var{IR mask}> <@var{IDCODE instruction}>
284 Describes the devices that form the JTAG daisy chain, with the first device being
285 the one closest to TDO. The parameters are the length of the instruction register
286 (4 for all ARM7/9s), the value captured during Capture-IR (0x1 for ARM7/9), and a mask
287 of bits that should be validated when doing IR scans (all four bits (0xf) for ARM7/9).
288 The IDCODE instruction will in future be used to query devices for their JTAG
289 identification code. This line is the same for all ARM7 and ARM9 devices.
290 Other devices, like CPLDs, require different parameters. An example configuration
291 line for a Xilinx XC9500 CPLD would look like this:
293 jtag_device 8 0x01 0x0e3 0xfe
295 The instruction register (IR) is 8 bits long, during Capture-IR 0x01 is loaded into
296 the IR, but only bits 0-1 and 5-7 should be checked, the others (2-4) might vary.
297 The IDCODE instruction is 0xfe.
299 @item @b{jtag_nsrst_delay} <@var{ms}>
300 @cindex jtag_nsrst_delay
301 How long (in miliseconds) the OpenOCD should wait after deasserting nSRST before
302 starting new JTAG operations.
303 @item @b{jtag_ntrst_delay} <@var{ms}>
304 @cindex jtag_ntrst_delay
305 How long (in miliseconds) the OpenOCD should wait after deasserting nTRST before
306 starting new JTAG operations.
308 The jtag_n[st]rst_delay options are useful if reset circuitry (like a reset supervisor,
309 or on-chip features) keep a reset line asserted for some time after the external reset
313 @section parport options
316 @item @b{parport_port} <@var{number}>
318 Either the address of the I/O port (default: 0x378 for LPT1) or the number of
319 the @file{/dev/parport} device
321 When using PPDEV to access the parallel port, use the number of the parallel port:
322 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
323 you may encounter a problem.
324 @item @b{parport_cable} <@var{name}>
325 @cindex parport_cable
326 The layout of the parallel port cable used to connect to the target.
327 Currently supported cables are
331 Original Wiggler layout, also supported by several clones, such
332 as the Olimex ARM-JTAG
333 @item old_amt_wiggler
334 @cindex old_amt_wiggler
335 The Wiggler configuration that comes with Amontec's Chameleon Programmer. The new
336 version available from the website uses the original Wiggler layout ('@var{wiggler}')
339 Describes the connection of the Amontec Chameleon's CPLD when operated in
340 configuration mode. This is only used to program the Chameleon itself, not
344 Xilinx Parallel cable III.
347 The parallel port adapter found on the 'Karo Triton 1 Development Board'.
348 This is also the layout used by the HollyGates design
349 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
354 @item @b{parport_write_on_exit} <@var{on|off}>
355 @cindex parport_write_on_exit
356 This will configure the parallel driver to write a known value to the parallel
357 interface on exiting openocd
360 @section amt_jtagaccel options
362 @item @b{parport_port} <@var{number}>
364 Either the address of the I/O port (default: 0x378 for LPT1) or the number of the
365 @file{/dev/parport} device
367 @section ft2232 options
370 @item @b{ft2232_device_desc} <@var{description}>
371 @cindex ft2232_device_desc
372 The USB device description of the FTDI FT2232 device. If not specified, the FTDI
373 default value is used. This setting is only valid if compiled with FTD2XX support.
374 @item @b{ft2232_layout} <@var{name}>
375 @cindex ft2232_layout
376 The layout of the FT2232 GPIO signals used to control output-enables and reset
377 signals. Valid layouts are
380 The "USBJTAG-1" layout described in the original OpenOCD diploma thesis
382 Amontec JTAGkey and JTAGkey-tiny
388 American Microsystems M5960
390 Luminary Micro EVB_LM3S811 as a JTAG interface (not onboard processor), no TRST or
391 SRST signals on external connector
395 Hitex STM32 Performance Stick
397 Tin Can Tools Flyswatter
399 egnite Software turtelizer2
404 @item @b{ft2232_vid_pid} <@var{vid}> <@var{pid}>
405 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
406 default values are used. This command is not available on Windows.
407 @item @b{ft2232_latency} <@var{ms}>
408 On some systems using ft2232 based JTAG interfaces the FT_Read function call in
409 ft2232_read() fails to return the expected number of bytes. This can be caused by
410 USB communication delays and has proved hard to reproduce and debug. Setting the
411 FT2232 latency timer to a larger value increases delays for short USB packages but it
412 also reduces the risk of timeouts before receiving the expected number of bytes.
413 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
416 @section ep93xx options
417 @cindex ep93xx options
418 Currently, there are no options available for the ep93xx interface.
421 @section Target configuration
424 @item @b{target} <@var{type}> <@var{endianess}> <@var{reset_mode}> <@var{JTAG pos}>
427 Defines a target that should be debugged. Currently supported types are:
440 If you want to use a target board that is not on this list, see Adding a new
443 Endianess may be @option{little} or @option{big}.
445 The reset_mode specifies what should happen to the target when a reset occurs:
449 Immediately request a target halt after reset. This allows targets to be debugged
450 from the very first instruction. This is only possible with targets and JTAG
451 interfaces that correctly implement the reset signals.
454 Similar to @option{reset_halt}, but executes the script file defined to handle the
455 'reset' event for the target. Like @option{reset_halt} this only works with
456 correct reset implementations.
459 Simply let the target run after a reset.
462 Let the target run for some time (default: 1s), and then request halt.
465 A combination of @option{reset_init} and @option{run_and_halt}. The target is allowed
466 to run for some time, then halted, and the @option{reset} event script is executed.
469 On JTAG interfaces / targets where system reset and test-logic reset can't be driven
470 completely independent (like the LPC2000 series), or where the JTAG interface is
471 unavailable for some time during startup (like the STR7 series), you can't use
472 @option{reset_halt} or @option{reset_init}.
474 @item @b{target_script} <@var{target#}> <@var{event}> <@var{script_file}>
475 @cindex target_script
476 Event is either @option{reset}, @option{post_halt}, @option{pre_resume} or @option{gdb_program_config}
478 TODO: describe exact semantic of events
479 @item @b{run_and_halt_time} <@var{target#}> <@var{time_in_ms}>
480 @cindex run_and_halt_time
481 The amount of time the debugger should wait after releasing reset before it asserts
482 a debug request. This is used by the @option{run_and_halt} and @option{run_and_init}
484 @item @b{working_area} <@var{target#}> <@var{address}> <@var{size}>
485 <@var{backup}|@var{nobackup}>
487 Specifies a working area for the debugger to use. This may be used to speed-up
488 downloads to target memory and flash operations, or to perform otherwise unavailable
489 operations (some coprocessor operations on ARM7/9 systems, for example). The last
490 parameter decides whether the memory should be preserved <@var{backup}>. If possible, use
491 a working_area that doesn't need to be backed up, as that slows down operation.
494 @subsection arm7tdmi options
495 @cindex arm7tdmi options
496 target arm7tdmi <@var{endianess}> <@var{reset_mode}> <@var{jtag#}>
497 The arm7tdmi target definition requires at least one additional argument, specifying
498 the position of the target in the JTAG daisy-chain. The first JTAG device is number 0.
499 The optional [@var{variant}] parameter has been removed in recent versions.
500 The correct feature set is determined at runtime.
502 @subsection arm720t options
503 @cindex arm720t options
504 ARM720t options are similar to ARM7TDMI options.
506 @subsection arm9tdmi options
507 @cindex arm9tdmi options
508 ARM9TDMI options are similar to ARM7TDMI options. Supported variants are
509 @option{arm920t}, @option{arm922t} and @option{arm940t}.
510 This enables the hardware single-stepping support found on these cores.
512 @subsection arm920t options
513 @cindex arm920t options
514 ARM920t options are similar to ARM9TDMI options.
516 @subsection arm966e options
517 @cindex arm966e options
518 ARM966e options are similar to ARM9TDMI options.
520 @subsection xscale options
521 @cindex xscale options
522 Supported variants are @option{ixp42x}, @option{ixp45x}, @option{ixp46x},
523 @option{pxa250}, @option{pxa255}, @option{pxa26x}.
525 @section Flash configuration
526 @cindex Flash configuration
529 @item @b{flash bank} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}>
530 <@var{bus_width}> <@var{target#}> [@var{driver_options ...}]
532 Configures a flash bank at <@var{base}> of <@var{size}> bytes and <@var{chip_width}>
533 and <@var{bus_width}> bytes using the selected flash <driver>.
535 @item @b{flash auto_erase} <@option{on}|@option{off}>
536 @cindex flash auto_erase
537 auto erase flash banks prior to writing. Currently only works when using
538 @option{flash write_image} command. Default is @option{off}.
541 @subsection lpc2000 options
542 @cindex lpc2000 options
544 @b{flash bank lpc2000} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
545 <@var{clock}> [@var{calc_checksum}]
546 LPC flashes don't require the chip and bus width to be specified. Additional
547 parameters are the <@var{variant}>, which may be @var{lpc2000_v1} (older LPC21xx and LPC22xx)
548 or @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx), the number
549 of the target this flash belongs to (first is 0), the frequency at which the core
550 is currently running (in kHz - must be an integral number), and the optional keyword
551 @var{calc_checksum}, telling the driver to calculate a valid checksum for the exception
554 @subsection cfi options
557 @b{flash bank cfi} <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}>
559 CFI flashes require the number of the target they're connected to as an additional
560 argument. The CFI driver makes use of a working area (specified for the target)
561 to significantly speed up operation.
563 @var{chip_width} and @var{bus_width} are specified in bytes.
565 @subsection at91sam7 options
566 @cindex at91sam7 options
568 @b{flash bank at91sam7} 0 0 0 0 <@var{target#}>
569 AT91SAM7 flashes only require the @var{target#}, all other values are looked up after
570 reading the chip-id and type.
572 @subsection str7 options
575 @b{flash bank str7x} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
576 variant can be either STR71x, STR73x or STR75x.
578 @subsection str9 options
581 @b{flash bank str9x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
582 The str9 needs the flash controller to be configured prior to Flash programming, eg.
584 str9x flash_config 0 4 2 0 0x80000
586 This will setup the BBSR, NBBSR, BBADR and NBBADR registers respectively.
588 @subsection str9 options (str9xpec driver)
590 @b{flash bank str9xpec} <@var{base}> <@var{size}> 0 0 <@var{target#}>
591 Before using the flash commands the turbo mode will need enabling using str9xpec
592 @option{enable_turbo} <@var{num>.}
594 Only use this driver for locking/unlocking the device or configuring the option bytes.
595 Use the standard str9 driver for programming.
597 @subsection stellaris (LM3Sxxx) options
598 @cindex stellaris (LM3Sxxx) options
600 @b{flash bank stellaris} <@var{base}> <@var{size}> 0 0 <@var{target#}>
601 stellaris flash plugin only require the @var{target#}.
603 @subsection stm32x options
604 @cindex stm32x options
606 @b{flash bank stm32x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
607 stm32x flash plugin only require the @var{target#}.
613 The Open On-Chip Debugger (OpenOCD) allows user interaction through a telnet interface
614 (default: port 4444) and a GDB server (default: port 3333). The command line interpreter
615 is available from both the telnet interface and a GDB session. To issue commands to the
616 interpreter from within a GDB session, use the @option{monitor} command, e.g. use
617 @option{monitor poll} to issue the @option{poll} command. All output is relayed through the
623 @item @b{sleep} <@var{msec}>
625 Wait for n milliseconds before resuming. Useful in connection with script files
626 (@var{script} command and @var{target_script} configuration).
630 Close the OpenOCD daemon, disconnecting all clients (GDB, Telnet).
632 @item @b{debug_level} [@var{n}]
634 Display or adjust debug level to n<0-3>
636 @item @b{log_output} <@var{file}>
638 Redirect logging to <file> (default: stderr)
640 @item @b{script} <@var{file}>
642 Execute commands from <file>
646 @subsection Target state handling
648 @item @b{poll} [@option{on}|@option{off}]
650 Poll the target for its current state. If the target is in debug mode, architecture
651 specific information about the current state are printed. An optional parameter
652 allows continuous polling to be enabled and disabled.
654 @item @b{halt} [@option{ms}]
656 Send a halt request to the target and waits for it to halt for [@option{ms}].
657 Default [@option{ms}] is 5 seconds if no arg given.
658 Optional arg @option{ms} is a timeout in milliseconds. Using 0 as the [@option{ms}]
659 will stop openocd from waiting.
661 @item @b{wait_halt} [@option{ms}]
663 Wait for the target to enter debug mode. Optional [@option{ms}] is
664 a timeout in milliseconds. Default [@option{ms}] is 5 seconds if no
667 @item @b{resume} [@var{address}]
669 Resume the target at its current code position, or at an optional address.
670 Openocd will wait 5 seconds for the target to resume.
672 @item @b{step} [@var{address}]
674 Single-step the target at its current code position, or at an optional address.
676 @item @b{reset} [@option{run}|@option{halt}|@option{init}|@option{run_and_halt}
677 |@option{run_and_init}]
679 Do a hard-reset. The optional parameter specifies what should happen after the reset.
680 This optional parameter overwrites the setting specified in the configuration file,
681 making the new behaviour the default for the @option{reset} command.
688 Immediately halt the target (works only with certain configurations).
691 Immediately halt the target, and execute the reset script (works only with certain
694 @cindex reset run_and_halt
695 Let the target run for a certain amount of time, then request a halt.
697 @cindex reset run_and_init
698 Let the target run for a certain amount of time, then request a halt. Execute the
699 reset script once the target entered debug mode.
703 @subsection Memory access commands
704 These commands allow accesses of a specific size to the memory system:
706 @item @b{mdw} <@var{addr}> [@var{count}]
709 @item @b{mdh} <@var{addr}> [@var{count}]
711 display memory half-words
712 @item @b{mdb} <@var{addr}> [@var{count}]
715 @item @b{mww} <@var{addr}> <@var{value}>
718 @item @b{mwh} <@var{addr}> <@var{value}>
720 write memory half-word
721 @item @b{mwb} <@var{addr}> <@var{value}>
725 @item @b{load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
727 Load image <@var{file}> to target memory at <@var{address}>
728 @item @b{dump_image} <@var{file}> <@var{address}> <@var{size}>
730 Dump <@var{size}> bytes of target memory starting at <@var{address}> to a
731 (binary) <@var{file}>.
732 @item @b{verify_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
734 Verify <@var{file}> to target memory starting at <@var{address}>.
735 This will first attempt using a crc checksum, if this fails it will try a binary compare.
736 @item @b{load_binary} <@var{file}> <@var{address}> [DEPRECATED]
738 Load binary <@var{file}> to target memory at <@var{address}>
739 @item @b{dump_binary} <@var{file}> <@var{address}> <@var{size}> [DEPRECATED]
741 Dump <@var{size}> bytes of target memory starting at <@var{address}> to a
742 (binary) <@var{file}>.
745 @subsection Flash commands
746 @cindex Flash commands
748 @item @b{flash banks}
750 List configured flash banks
751 @item @b{flash info} <@var{num}>
753 Print info about flash bank <@option{num}>
754 @item @b{flash probe} <@var{num}>
756 Identify the flash, or validate the parameters of the configured flash. Operation
757 depends on the flash type.
758 @item @b{flash erase_check} <@var{num}>
759 @cindex flash erase_check
760 Check erase state of sectors in flash bank <@var{num}>. This is the only operation that
761 updates the erase state information displayed by @option{flash info}. That means you have
762 to issue an @option{erase_check} command after erasing or programming the device to get
764 @item @b{flash protect_check} <@var{num}>
765 @cindex flash protect_check
766 Check protection state of sectors in flash bank <num>.
768 @item @b{flash erase} <@var{num}> <@var{first}> <@var{last}> [DEPRECATED]
770 Erase sectors at bank <@var{num}>, starting at sector <@var{first}> up to and including
771 <@var{last}>. Sector numbering starts at 0. Depending on the flash type, erasing might
772 require the protection to be disabled first (e.g. Intel Advanced Bootblock flash using
773 the CFI driver). This command was replaced by the new command
774 @option{flash erase_sector} using the same syntax.
775 @item @b{flash erase_sector} <@var{num}> <@var{first}> <@var{last}>
776 @cindex flash erase_sector
777 Erase sectors at bank <@var{num}>, starting at sector <@var{first}> up to and including
778 <@var{last}>. Sector numbering starts at 0. Depending on the flash type, erasing might
779 require the protection to be disabled first (e.g. Intel Advanced Bootblock flash using
781 @item @b{flash erase_address} <@var{address}> <@var{length}>
782 @cindex flash erase_address
783 Erase sectors starting at <@var{address}> for <@var{length}> number of bytes
784 @item @b{flash write} <@var{num}> <@var{file}> <@var{offset}> [DEPRECATED]
786 Write the binary <@var{file}> to flash bank <@var{num}>, starting at <@var{offset}>
787 bytes from the beginning of the bank. This command was replaced by the new command
788 @option{flash write_binary} using the same syntax.
789 @item @b{flash write_binary} <@var{num}> <@var{file}> <@var{offset}>
790 @cindex flash write_binary
791 Write the binary <@var{file}> to flash bank <@var{num}>, starting at
792 <@option{offset}> bytes from the beginning of the bank.
793 @item @b{flash write_image} <@var{file}> [@var{offset}] [@var{type}]
794 @cindex flash write_image
795 Write the image <@var{file}> to the current target's flash bank(s). A relocation
796 [@var{offset}] can be specified and the file [@var{type}] can be specified
797 explicitly as @option{bin} (binary), @option{ihex} (Intel hex), @option{elf}
798 (ELF file) or @option{s19} (Motorola s19).
799 @item @b{flash protect} <@var{num}> <@var{first}> <@var{last}> <@option{on}|@option{off}>
800 @cindex flash protect
801 Enable (@var{on}) or disable (@var{off}) protection of flash sectors <@var{first}> to
802 <@var{last}> of @option{flash bank} <@var{num}>.
803 @item @b{flash auto_erase} <@var{on}|@var{off}>
804 @cindex flash auto_erase
805 Enable (@option{on}) to erase flash banks prior to writing using the flash @option{write_image} command
806 only. Default is (@option{off}), flash banks have to be erased using @option{flash erase} command.
810 @section Target Specific Commands
811 @cindex Target Specific Commands
813 @subsection AT91SAM7 specific commands
814 @cindex AT91SAM7 specific commands
815 The flash configuration is deduced from the chip identification register. The flash
816 controller handles erases automatically on a page (128/265 byte) basis so erase is
817 not necessary for flash programming. AT91SAM7 processors with less than 512K flash
818 only have a single flash bank embedded on chip. AT91SAM7xx512 have two flash planes
819 that can be erased separatly.Only an EraseAll command is supported by the controller
820 for each flash plane and this is called with
822 @item @b{flash erase} <@var{num}> @var{first_plane} @var{last_plane}
823 bulk erase flash planes first_plane to last_plane.
824 @item @b{at91sam7 gpnvm} <@var{num}> <@var{bit}> <@option{set}|@option{clear}>
825 @cindex at91sam7 gpnvm
826 set or clear a gpnvm bit for the processor
829 @subsection STR9 specific commands
830 @cindex STR9 specific commands
831 These are flash specific commands when using the str9xpec driver.
833 @item @b{str9xpec enable_turbo} <@var{num}>
834 @cindex str9xpec enable_turbo
835 enable turbo mode, simply this will remove the str9 from the chain and talk
836 directly to the embedded flash controller.
837 @item @b{str9xpec disable_turbo} <@var{num}>
838 @cindex str9xpec disable_turbo
839 restore the str9 into jtag chain.
840 @item @b{str9xpec lock} <@var{num}>
841 @cindex str9xpec lock
842 lock str9 device. The str9 will only respond to an unlock command that will
844 @item @b{str9xpec unlock} <@var{num}>
845 @cindex str9xpec unlock
847 @item @b{str9xpec options_read} <@var{num}>
848 @cindex str9xpec options_read
849 read str9 option bytes.
850 @item @b{str9xpec options_write} <@var{num}>
851 @cindex str9xpec options_write
852 write str9 option bytes.
855 @subsection STR9 configuration
856 @cindex STR9 configuration
858 @item @b{str9x flash_config} <@var{bank}> <@var{BBSR}> <@var{NBBSR}>
859 <@var{BBADR}> <@var{NBBADR}>
860 @cindex str9x flash_config
861 Configure str9 flash controller.
863 eg. str9x flash_config 0 4 2 0 0x80000
865 BBSR - Boot Bank Size register
866 NBBSR - Non Boot Bank Size register
867 BBADR - Boot Bank Start Address register
868 NBBADR - Boot Bank Start Address register
872 @subsection STR9 option byte configuration
873 @cindex STR9 option byte configuration
875 @item @b{str9xpec options_cmap} <@var{num}> <@option{bank0}|@option{bank1}>
876 @cindex str9xpec options_cmap
877 configure str9 boot bank.
878 @item @b{str9xpec options_lvdthd} <@var{num}> <@option{2.4v}|@option{2.7v}>
879 @cindex str9xpec options_lvdthd
880 configure str9 lvd threshold.
881 @item @b{str9xpec options_lvdsel} <@var{num}> <@option{vdd}|@option{vdd_vddq}>
882 @cindex str9xpec options_lvdsel
883 configure str9 lvd source.
884 @item @b{str9xpec options_lvdwarn} <@var{bank}> <@option{vdd}|@option{vdd_vddq}>
885 @cindex str9xpec options_lvdwarn
886 configure str9 lvd reset warning source.
889 @subsection STM32x specific commands
890 @cindex STM32x specific commands
892 These are flash specific commands when using the stm32x driver.
894 @item @b{stm32x lock} <@var{num}>
897 @item @b{stm32x unlock} <@var{num}>
898 @cindex stm32x unlock
900 @item @b{stm32x options_read} <@var{num}>
901 @cindex stm32x options_read
902 read stm32 option bytes.
903 @item @b{stm32x options_write} <@var{num}> <@option{SWWDG}|@option{HWWDG}>
904 <@option{RSTSTNDBY}|@option{NORSTSTNDBY}> <@option{RSTSTOP}|@option{NORSTSTOP}>
905 @cindex stm32x options_write
906 write stm32 option bytes.
907 @item @b{stm32x mass_erase} <@var{num}>
908 @cindex stm32x mass_erase
909 mass erase flash memory.
913 @section Architecture Specific Commands
914 @cindex Architecture Specific Commands
916 @subsection ARMV4/5 specific commands
917 @cindex ARMV4/5 specific commands
919 These commands are specific to ARM architecture v4 and v5, like all ARM7/9 systems
920 or Intel XScale (XScale isn't supported yet).
922 @item @b{armv4_5 reg}
924 Display a list of all banked core registers, fetching the current value from every
925 core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
927 @item @b{armv4_5 core_mode} [@option{arm}|@option{thumb}]
928 @cindex armv4_5 core_mode
929 Displays the core_mode, optionally changing it to either ARM or Thumb mode.
930 The target is resumed in the currently set @option{core_mode}.
933 @subsection ARM7/9 specific commands
934 @cindex ARM7/9 specific commands
936 These commands are specific to ARM7 and ARM9 targets, like ARM7TDMI, ARM720t,
937 ARM920t or ARM926EJ-S.
939 @item @b{arm7_9 sw_bkpts} <@option{enable}|@option{disable}>
940 @cindex arm7_9 sw_bkpts
941 Enable/disable use of software breakpoints. On ARMv4 systems, this reserves
942 one of the watchpoint registers to implement software breakpoints. Disabling
943 SW Bkpts frees that register again.
944 @item @b{arm7_9 force_hw_bkpts} <@option{enable}|@option{disable}>
945 @cindex arm7_9 force_hw_bkpts
946 When @option{force_hw_bkpts} is enabled, the @option{sw_bkpts} support is disabled, and all
947 breakpoints are turned into hardware breakpoints.
948 @item @b{arm7_9 dbgrq} <@option{enable}|@option{disable}>
950 Enable use of the DBGRQ bit to force entry into debug mode. This should be
951 safe for all but ARM7TDMI--S cores (like Philips LPC).
952 @item @b{arm7_9 fast_writes} <@option{enable}|@option{disable}>
953 @cindex arm7_9 fast_writes [DEPRECATED]
954 See @option{arm7_9 fast_memory_access} instead.
955 @item @b{arm7_9 fast_memory_access} <@option{enable}|@option{disable}>
956 @cindex arm7_9 fast_memory_access
957 Allow the OpenOCD to read and write memory without checking completion of
958 the operation. This provides a huge speed increase, especially with USB JTAG
959 cables (FT2232), but might be unsafe if used with targets running at a very low
960 speed, like the 32kHz startup clock of an AT91RM9200.
961 @item @b{arm7_9 dcc_downloads} <@option{enable}|@option{disable}>
962 @cindex arm7_9 dcc_downloads
963 Enable the use of the debug communications channel (DCC) to write larger (>128 byte)
964 amounts of memory. DCC downloads offer a huge speed increase, but might be potentially
965 unsafe, especially with targets running at a very low speed. This command was introduced
966 with OpenOCD rev. 60.
969 @subsection ARM920T specific commands
970 @cindex ARM920T specific commands
973 @item @b{arm920t cache_info}
974 @cindex arm920t cache_info
975 Print information about the caches found. This allows you to see if your target
976 is a ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
977 @item @b{arm920t md<bhw>_phys} <@var{addr}> [@var{count}]
978 @cindex arm920t md<bhw>_phys
979 Display memory at physical address addr.
980 @item @b{arm920t mw<bhw>_phys} <@var{addr}> <@var{value}>
981 @cindex arm920t mw<bhw>_phys
982 Write memory at physical address addr.
983 @item @b{arm920t read_cache} <@var{filename}>
984 @cindex arm920t read_cache
985 Dump the content of ICache and DCache to a file.
986 @item @b{arm920t read_mmu} <@var{filename}>
987 @cindex arm920t read_mmu
988 Dump the content of the ITLB and DTLB to a file.
989 @item @b{arm920t virt2phys} <@var{VA}>
990 @cindex arm920t virt2phys
991 Translate a virtual address to a physical address.
995 @section Debug commands
996 @cindex Debug commands
997 The following commands give direct access to the core, and are most likely
998 only useful while debugging the OpenOCD.
1000 @item @b{arm7_9 write_xpsr} <@var{32-bit value}> <@option{0=cpsr}, @option{1=spsr}>
1001 @cindex arm7_9 write_xpsr
1002 Immediately write either the current program status register (CPSR) or the saved
1003 program status register (SPSR), without changing the register cache (as displayed
1004 by the @option{reg} and @option{armv4_5 reg} commands).
1005 @item @b{arm7_9 write_xpsr_im8} <@var{8-bit value}> <@var{rotate 4-bit}>
1006 <@var{0=cpsr},@var{1=spsr}>
1007 @cindex arm7_9 write_xpsr_im8
1008 Write the 8-bit value rotated right by 2*rotate bits, using an immediate write
1009 operation (similar to @option{write_xpsr}).
1010 @item @b{arm7_9 write_core_reg} <@var{num}> <@var{mode}> <@var{value}>
1011 @cindex arm7_9 write_core_reg
1012 Write a core register, without changing the register cache (as displayed by the
1013 @option{reg} and @option{armv4_5 reg} commands). The <@var{mode}> argument takes the
1014 encoding of the [M4:M0] bits of the PSR.
1018 @section JTAG commands
1019 @cindex JTAG commands
1021 @item @b{scan_chain}
1023 Print current scan chain configuration.
1024 @item @b{jtag_reset}
1026 Toggle reset lines <@var{trst}> <@var{srst}>.
1027 @item @b{endstate} <@var{tap_state}>
1029 Finish JTAG operations in <@var{tap_state}>.
1030 @item @b{runtest} <@var{num_cycles}>
1032 Move to Run-Test/Idle, and execute <@var{num_cycles}>
1033 @item @b{statemove} [@var{tap_state}]
1035 Move to current endstate or [@var{tap_state}]
1038 Execute IR scan <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
1041 Execute DR scan <@var{device}> [@var{dev2}] [@var{var2}] ...
1042 @item @b{verify_ircapture}
1043 @cindex verify_ircapture
1044 Verify value captured during Capture-IR <@option{enable}|@option{disable}>
1047 Allocate, display or delete variable <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
1050 Display/modify variable field <@var{var}> <@var{field}> [@var{value}|@var{flip}]
1053 @node Sample Scripts
1054 @chapter Sample Scripts
1057 This page will collect some script examples for different CPUs.
1059 The configuration script can be divided in the following section:
1061 @item daemon configuration
1063 @item jtag scan chain
1064 @item target configuration
1065 @item flash configuration
1068 Detailed information about each section can be found at OpenOCD configuration
1070 @section OMAP5912 Flash Debug
1071 @cindex OMAP5912 Flash Debug
1072 The following two scripts were used with a wiggler PP and and a TI OMAP5912
1073 dual core processor - (@uref{http://www.ti.com}), on a OMAP5912 OSK board
1074 - (@uref{http://www.spectrumdigital.com}).
1075 @subsection Openocd config
1077 #daemon configuration
1084 parport_cable wiggler
1087 #use combined on interfaces or targets that can't set TRST/SRST separately
1088 reset_config trst_and_srst
1091 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1092 jtag_device 38 0x0 0x0 0x0
1093 jtag_device 4 0x1 0x0 0xe
1094 jtag_device 8 0x0 0x0 0x0
1096 #target configuration
1097 daemon_startup reset
1099 #target <type> <endianness> <reset mode> <chainpos> <variant>
1100 target arm926ejs little run_and_init 1 arm926ejs
1101 target_script 0 reset omap5912_osk.init
1102 run_and_halt_time 0 30
1104 # omap5912 lcd frame buffer as working area
1105 working_area 0 0x20000000 0x3e800 nobackup
1107 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1108 flash bank cfi 0x00000000 0x1000000 2 2 0
1111 @subsection Openocd init
1123 mww 0xfffec808 0x000000f5
1124 mww 0xfffec808 0x000000a0
1126 mww 0xfffeb048 0x0000aaaa
1128 mww 0xfffeb048 0x00005555
1137 @section STR71x Script
1138 @cindex STR71x Script
1139 The following script was used with an Amontec JTAGkey and a STR710 / STR711 cpu:
1141 #daemon configuration
1147 ft2232_device_desc "Amontec JTAGkey A"
1148 ft2232_layout jtagkey
1149 ft2232_vid_pid 0x0403 0xcff8
1152 #use combined on interfaces or targets that can't set TRST/SRST separately
1153 reset_config trst_and_srst srst_pulls_trst
1156 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1157 jtag_device 4 0x1 0xf 0xe
1159 #target configuration
1160 daemon_startup reset
1162 #target <type> <startup mode>
1163 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1164 target arm7tdmi little run_and_halt 0 arm7tdmi
1165 run_and_halt_time 0 30
1167 working_area 0 0x2000C000 0x4000 nobackup
1169 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1170 flash bank str7x 0x40000000 0x00040000 0 0 0 STR71x
1173 @section STR750 Script
1174 @cindex STR750 Script
1175 The following script was used with an Amontec JTAGkey and a STR750 cpu:
1177 #daemon configuration
1183 ft2232_device_desc "Amontec JTAGkey A"
1184 ft2232_layout jtagkey
1185 ft2232_vid_pid 0x0403 0xcff8
1188 #use combined on interfaces or targets that can't set TRST/SRST separately
1189 #reset_config trst_and_srst srst_pulls_trst
1190 reset_config trst_and_srst srst_pulls_trst
1193 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1194 jtag_device 4 0x1 0xf 0xe
1196 #jtag nTRST and nSRST delay
1197 jtag_nsrst_delay 500
1198 jtag_ntrst_delay 500
1200 #target configuration
1201 daemon_startup reset
1203 #target <type> <startup mode>
1204 #target arm7tdmi <reset mode> <chainpos> <endianness> <variant>
1205 target arm7tdmi little run_and_halt 0 arm7tdmi
1206 run_and_halt_time 0 30
1208 working_area 0 0x40000000 0x4000 nobackup
1210 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1211 flash bank str7x 0x20000000 0x000040000 0 0 0 STR75x
1214 @section STR912 Script
1215 @cindex STR912 Script
1216 The following script was used with an Amontec JTAGkey and a STR912 cpu:
1218 #daemon configuration
1224 ft2232_device_desc "Amontec JTAGkey A"
1225 ft2232_layout jtagkey
1228 #use combined on interfaces or targets that can't set TRST/SRST separately
1229 reset_config trst_and_srst
1232 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1233 jtag_device 8 0x1 0x1 0xfe
1234 jtag_device 4 0x1 0xf 0xe
1235 jtag_device 5 0x1 0x1 0x1e
1237 #target configuration
1238 daemon_startup reset
1240 #target <type> <startup mode>
1241 #target arm966e <endianness> <reset mode> <chainpos> <variant>
1242 target arm966e little reset_halt 1 arm966e
1243 run_and_halt_time 0 30
1245 working_area 0 0x50000000 16384 nobackup
1247 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1248 flash bank str9x 0x00000000 0x00080000 0 0 0
1251 @section STR912 comstick
1252 @cindex STR912 comstick Script
1253 The following script was used with a Hitex STR9 Comstick:
1255 #daemon configuration
1261 ft2232_device_desc "STR9-comStick A"
1262 ft2232_layout comstick
1265 jtag_nsrst_delay 100
1266 jtag_ntrst_delay 100
1268 #use combined on interfaces or targets that can't set TRST/SRST separately
1269 reset_config trst_and_srst
1272 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1273 jtag_device 8 0x1 0x1 0xfe
1274 jtag_device 4 0x1 0xf 0xe
1275 jtag_device 5 0x1 0x1 0x1e
1277 #target configuration
1278 daemon_startup reset
1280 #target <type> <startup mode>
1281 #target arm966e <endianness> <reset mode> <chainpos> <variant>
1282 target arm966e little reset_halt 1 arm966e
1283 run_and_halt_time 0 30
1285 working_area 0 0x50000000 16384 nobackup
1287 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1288 flash bank str9x 0x00000000 0x00080000 0 0 0
1291 @section STM32x Script
1292 @cindex STM32x Script
1293 The following script was used with an Amontec JTAGkey and a STM32x cpu:
1295 #daemon configuration
1301 ft2232_device_desc "Amontec JTAGkey A"
1302 ft2232_layout jtagkey
1305 jtag_nsrst_delay 100
1306 jtag_ntrst_delay 100
1308 #use combined on interfaces or targets that can't set TRST/SRST separately
1309 reset_config trst_and_srst
1312 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1313 jtag_device 4 0x1 0xf 0xe
1314 jtag_device 5 0x1 0x1 0x1e
1316 #target configuration
1317 daemon_startup reset
1319 #target <type> <startup mode>
1320 #target cortex_m3 <endianness> <reset mode> <chainpos> <variant>
1321 target cortex_m3 little run_and_halt 0
1322 run_and_halt_time 0 30
1324 working_area 0 0x20000000 16384 nobackup
1326 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1327 flash bank stm32x 0x08000000 0x00020000 0 0 0
1330 @section STM32x Performance Stick
1331 @cindex STM32x Performance Stick Script
1332 The following script was used with the Hitex STM32 Performance Stick
1334 #daemon configuration
1340 ft2232_device_desc "STM32-PerformanceStick A"
1341 ft2232_layout stm32stick
1344 jtag_nsrst_delay 100
1345 jtag_ntrst_delay 100
1347 #use combined on interfaces or targets that can't set TRST/SRST separately
1348 reset_config trst_and_srst
1351 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1352 jtag_device 4 0x1 0xf 0xe
1353 jtag_device 5 0x1 0x1 0x1e
1354 jtag_device 4 0x1 0xf 0xe
1356 #target configuration
1357 daemon_startup reset
1359 #target <type> <startup mode>
1360 #target cortex_m3 <endianness> <reset mode> <chainpos> <variant>
1361 target cortex_m3 little run_and_halt 0
1362 run_and_halt_time 0 30
1364 working_area 0 0x20000000 16384 nobackup
1366 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1367 flash bank stm32x 0x08000000 0x00020000 0 0 0
1370 @section LPC2129 Script
1371 @cindex LPC2129 Script
1372 The following script was used with an wiggler PP and a LPC-2129 cpu:
1374 #daemon configuration
1381 parport_cable wiggler
1384 #use combined on interfaces or targets that can't set TRST/SRST separately
1385 reset_config trst_and_srst srst_pulls_trst
1388 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1389 jtag_device 4 0x1 0xf 0xe
1391 #target configuration
1392 daemon_startup reset
1394 #target <type> <startup mode>
1395 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1396 target arm7tdmi little run_and_halt 0 arm7tdmi-s_r4
1397 run_and_halt_time 0 30
1399 working_area 0 0x40000000 0x4000 nobackup
1401 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1402 flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14765 calc_checksum
1405 @section LPC2148 Script
1406 @cindex LPC2148 Script
1407 The following script was used with an Amontec JTAGkey and a LPC2148 cpu:
1409 #daemon configuration
1415 ft2232_device_desc "Amontec JTAGkey A"
1416 ft2232_layout jtagkey
1417 ft2232_vid_pid 0x0403 0xcff8
1420 #use combined on interfaces or targets that can't set TRST/SRST separately
1421 reset_config trst_and_srst srst_pulls_trst
1424 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1425 jtag_device 4 0x1 0xf 0xe
1427 #target configuration
1428 daemon_startup reset
1430 #target <type> <startup mode>
1431 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1432 target arm7tdmi little run_and_halt 0 arm7tdmi-s_r4
1433 run_and_halt_time 0 30
1435 working_area 0 0x40000000 0x8000 nobackup
1437 #flash configuration
1438 flash bank lpc2000 0x0 0x7d000 0 0 0 lpc2000_v1 14765 calc_checksum
1441 @section LPC2294 Script
1442 @cindex LPC2294 Script
1443 The following script was used with an Amontec JTAGkey and a LPC2294 cpu:
1445 #daemon configuration
1451 ft2232_device_desc "Amontec JTAGkey A"
1452 ft2232_layout jtagkey
1453 ft2232_vid_pid 0x0403 0xcff8
1456 #use combined on interfaces or targets that can't set TRST/SRST separately
1457 reset_config trst_and_srst srst_pulls_trst
1460 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1461 jtag_device 4 0x1 0xf 0xe
1463 #target configuration
1464 daemon_startup reset
1466 #target <type> <startup mode>
1467 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1468 target arm7tdmi little run_and_halt 0 arm7tdmi-s_r4
1469 run_and_halt_time 0 30
1471 working_area 0 0x40000000 0x4000 nobackup
1473 #flash configuration
1474 flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14765 calc_checksum
1477 @section AT91R40008 Script
1478 @cindex AT91R40008 Script
1479 The following script was used with an Amontec JTAGkey and a AT91R40008 cpu:
1481 #daemon configuration
1487 ft2232_device_desc "Amontec JTAGkey A"
1488 ft2232_layout jtagkey
1489 ft2232_vid_pid 0x0403 0xcff8
1491 jtag_nsrst_delay 200
1492 jtag_ntrst_delay 200
1494 #use combined on interfaces or targets that can't set TRST/SRST separately
1495 reset_config srst_only srst_pulls_trst
1498 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1499 jtag_device 4 0x1 0xf 0xe
1501 #target configuration
1502 daemon_startup reset
1504 #target <type> <startup mode>
1505 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1506 target arm7tdmi little run_and_halt 0 arm7tdmi
1507 run_and_halt_time 0 30
1510 @section AT91SAM7s Script
1511 @cindex AT91SAM7s Script
1512 The following script was used with an Olimex ARM-JTAG-OCD and a AT91SAM7S64 cpu:
1514 #daemon configuration
1520 ft2232_device_desc "Olimex OpenOCD JTAG A"
1521 ft2232_layout olimex-jtag
1522 ft2232_vid_pid 0x15BA 0x0003
1524 jtag_nsrst_delay 200
1525 jtag_ntrst_delay 200
1527 #use combined on interfaces or targets that can't set TRST/SRST separately
1528 reset_config srst_only srst_pulls_trst
1531 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1532 jtag_device 4 0x1 0xf 0xe
1534 #target configuration
1535 daemon_startup reset
1537 #target <type> <startup mode>
1538 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1539 target arm7tdmi little run_and_halt 0 arm7tdmi
1540 run_and_halt_time 0 30
1542 # flash-options AT91
1543 working_area 0 0x00200000 0x4000 nobackup
1544 flash bank at91sam7 0 0 0 0 0
1547 # erase command (telnet-interface) for complete flash:
1548 # flash erase <num> 0 numlockbits-1 (can be seen from output of flash info 0)
1549 # SAM7S64 with 16 lockbits and bank 0: flash erase 0 0 15
1550 # set/clear NVM-Bits:
1551 # at91sam7 gpnvm <num> <bit> <set|clear>
1552 # disable locking from SAM-BA:
1553 # flash protect 0 0 1 off
1556 @section XSCALE IXP42x Script
1557 @cindex XSCALE IXP42x Script
1558 The following script was used with an Amontec JTAGkey-Tiny and a xscale ixp42x cpu:
1560 #daemon configuration
1566 ft2232_device_desc "Amontec JTAGkey A"
1567 ft2232_layout jtagkey
1568 ft2232_vid_pid 0x0403 0xcff8
1570 jtag_nsrst_delay 200
1571 jtag_ntrst_delay 200
1573 #use combined on interfaces or targets that can't set TRST/SRST separately
1574 reset_config srst_only srst_pulls_trst
1577 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1578 jtag_device 7 0x1 0x7f 0x7e
1580 #target configuration
1581 daemon_startup reset
1583 #target <type> <startup mode>
1584 #target arm7tdmi <reset mode> <chainpos> <endianness> <variant>
1585 target xscale big run_and_halt 0 IXP42x
1586 run_and_halt_time 0 30
1589 @section Cirrus Logic EP9301 Script
1590 @cindex Cirrus Logic EP9301 Script
1591 The following script was used with FT2232 based JTAG interfaces and a
1592 Cirrus Logic EP9301 processor on an Olimex CS-E9301 board.
1594 #daemon configuration
1602 #ft2232_device_desc "Olimex OpenOCD JTAG"
1603 #ft2232_layout olimex-jtag
1604 #ft2232_vid_pid 0x15ba 0x0003
1606 #Amontec JTAGkey (and JTAGkey-Tiny)
1607 #Serial is only necessary if more than one JTAGkey is connected
1608 ft2232_device_desc "Amontec JTAGkey A"
1609 #ft2232_serial AMTJKV31
1610 #ft2232_serial T1P3S2W8
1611 ft2232_layout jtagkey
1612 ft2232_vid_pid 0x0403 0xcff8
1614 #wiggler/parallel port interface
1617 #parport_cable wiggler
1620 reset_config trst_and_srst
1623 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1624 jtag_device 4 0x1 0xf 0xe
1626 jtag_nsrst_delay 100
1627 jtag_ntrst_delay 100
1629 #target configuration
1630 daemon_startup attach
1632 #target <type> <endianess> <reset mode>
1633 target arm920t little reset_halt 0
1634 working_area 0 0x80014000 0x1000 backup
1636 #flash configuration
1637 #flash bank <driver> <base> <size> <chip_width> <bus_width> [driver_options ...]
1638 flash bank cfi 0x60000000 0x1000000 2 2 0
1641 @section Hilscher netX 100 / 500 Script
1642 @cindex Hilscher netX 100 / 500 Script
1643 The following script was used with an Amontec JTAGkey and a Hilscher
1646 #daemon configuration
1652 ft2232_device_desc "Amontec JTAGkey A"
1653 ft2232_layout jtagkey
1654 ft2232_vid_pid 0x0403 0xcff8
1657 #use combined on interfaces or targets that can't set TRST/SRST separately
1658 reset_config trst_and_srst
1661 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1662 jtag_device 4 0x1 0xf 0xe
1664 jtag_nsrst_delay 100
1665 jtag_ntrst_delay 100
1667 #target configuration
1668 daemon_startup reset
1670 #target <type> <endianness> <startup mode> <chainpos> <variant>
1671 target arm926ejs little run_and_halt 0 arm926ejs
1672 run_and_halt_time 0 500
1675 @section Marvell/Intel PXA270 Script
1676 @cindex Marvell/Intel PXA270 Script
1678 # config for Intel PXA270
1679 # not, as of 2007-06-22, openocd only works with the
1680 # libftd2xx library from ftdi. libftdi does not work.
1686 ft2232_layout olimex-jtag
1687 ft2232_vid_pid 0x15BA 0x0003
1688 ft2232_device_desc "Olimex OpenOCD JTAG"
1690 # set jtag_nsrst_delay to the delay introduced by your reset circuit
1691 # the rest of the needed delays are built into the openocd program
1692 jtag_nsrst_delay 260
1693 # set the jtag_ntrst_delay to the delay introduced by a reset circuit
1694 # the rest of the needed delays are built into the openocd program
1697 #use combined on interfaces or targets that can't set TRST/SRST separately
1698 reset_config trst_and_srst separate
1701 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1702 jtag_device 7 0x1 0x7f 0x7e
1704 #target configuration
1705 daemon_startup reset
1707 target xscale little reset_halt 0 pxa27x
1709 # maps to PXA internal RAM. If you are using a PXA255
1710 # you must initialize SDRAM or leave this option off
1711 working_area 0 0x5c000000 0x10000 nobackup
1713 run_and_halt_time 0 30
1715 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1716 # works for P30 flash
1717 flash bank cfi 0x00000000 0x1000000 2 4 0
1720 @node GDB and Openocd
1721 @chapter GDB and Openocd
1722 @cindex GDB and Openocd
1723 Openocd complies with the remote gdbserver protocol, and as such can be used
1724 to debug remote targets.
1726 @section Connecting to gdb
1727 @cindex Connecting to gdb
1728 A connection is typically started as follows:
1730 target remote localhost:3333
1732 This would cause gdb to connect to the gdbserver on the local pc using port 3333.
1734 To see a list of available openocd commands type @option{monitor help} on the
1737 Openocd supports the gdb @option{qSupported} packet, this enables information
1738 to be sent by the gdb server (openocd) to gdb. Typical information includes
1739 packet size and device memory map.
1741 Previous versions of openocd required the following gdb options to increase
1742 the packet size and speed up gdb communication.
1744 set remote memory-write-packet-size 1024
1745 set remote memory-write-packet-size fixed
1746 set remote memory-read-packet-size 1024
1747 set remote memory-read-packet-size fixed
1749 This is now handled in the @option{qSupported} PacketSize.
1751 @section Programming using gdb
1752 @cindex Programming using gdb
1754 By default the target memory map is not sent to gdb, this can be enabled by
1755 the following openocd config option:
1757 gdb_memory_map enable
1759 For this to function correctly a valid flash config must also be configured
1760 in openocd. For speed also configure a valid working area.
1762 Informing gdb of the memory map of the target will enable gdb to protect any
1763 flash area of the target and use hardware breakpoints by default. This means
1764 that the openocd option @option{arm7_9 force_hw_bkpts} is not required when
1767 To view the configured memory map in gdb, use the gdb command @option{info mem}
1768 All other unasigned addresses within gdb are treated as ram.
1770 If @option{gdb_flash_program enable} is also used, gdb will be able to
1771 program any flash memory using the vFlash interface.
1773 gdb will look at the target memory map when a load command is given, if any
1774 areas to be programmed lie within the target flash area the vFlash packets
1777 Incase the target needs configuring before gdb programming, a script can be executed.
1779 target_script 0 gdb_program_config config.script
1782 To verify any flash programming the gdb command @option{compare-sections}
1789 @item OpenOCD complains about a missing cygwin1.dll
1791 Make sure you have Cygwin installed, or at least a version of OpenOCD that
1792 claims to come with all the necessary dlls. When using Cygwin, try launching
1793 the OpenOCD from the Cygwin shell.
1795 @item I'm trying to set a breakpoint using GDB (or a frontend like Insight or
1796 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
1797 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
1799 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
1800 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720t or ARM920t,
1801 software breakpoints consume one of the two available hardware breakpoints,
1802 and are therefor disabled by default. If your code is running from RAM, you
1803 can enable software breakpoints with the @option{arm7_9 sw_bkpts enable} command. If
1804 your code resides in Flash, you can't use software breakpoints, but you can force
1805 OpenOCD to use hardware breakpoints instead: @option{arm7_9 force_hw_bkpts enable}.
1807 @item When erasing or writing LPC2000 on-chip flash, the operation fails sometimes
1808 and works sometimes fine.
1810 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
1811 clock at the time you're programming the flash. If you've specified the crystal's
1812 frequency, make sure the PLL is disabled, if you've specified the full core speed
1813 (e.g. 60MHz), make sure the PLL is enabled.
1815 @item When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
1816 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
1817 out while waiting for end of scan, rtck was disabled".
1819 Make sure your PC's parallel port operates in EPP mode. You might have to try several
1820 settings in your PC Bios (ECP, EPP, and different versions of those).
1822 @item When debugging with the OpenOCD and GDB (plain GDB, Insight, or Eclipse),
1823 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
1824 memory read caused data abort".
1826 The errors are non-fatal, and are the result of GDB trying to trace stack frames
1827 beyond the last valid frame. It might be possible to prevent this by setting up
1828 a proper "initial" stack frame, if you happen to know what exactly has to
1829 be done, feel free to add this here.
1831 @item I get the following message in the OpenOCD console (or log file):
1832 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
1834 This warning doesn't indicate any serious problem, as long as you don't want to
1835 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
1836 trst_and_srst srst_pulls_trst} to tell the OpenOCD that either your board,
1837 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
1838 independently. With this setup, it's not possible to halt the core right out of
1839 reset, everything else should work fine.
1841 @item When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
1842 Toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
1843 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
1844 quit with an error message. Is there a stability issue with OpenOCD?
1846 No, this is not a stability issue concering OpenOCD. Most users have solved
1847 this issue by simply using a self-powered USB Hub, which they connect their
1848 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
1849 supply stable enough for the Amontec JTAGkey to be operated.
1851 @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
1852 following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
1853 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
1854 What does that mean and what might be the reason for this?
1856 First of all, the reason might be the USB power supply. Try using a self-powered
1857 hub instead of a direct connection to your computer. Secondly, the error code 4
1858 corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
1859 Chip ran into some sort of error - this points us to a USB problem.
1861 @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
1862 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
1863 What does that mean and what might be the reason for this?
1865 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
1866 has closed the connection to OpenOCD. This might be a GDB issue.
1868 @item In the configuration file in the section where flash device configurations
1869 are described, there is a parameter for specifying the clock frequency for
1870 LPC2000 internal flash devices (e.g.
1871 @option{flash bank lpc2000 0x0 0x40000 0 0 lpc2000_v1 0 14746 calc_checksum}),
1872 which must be sepcified in kilohertz. However, I do have a quartz crystal of a
1873 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz, i.e. 14,745.600 kHz).
1874 Is it possible to specify real numbers for the clock frequency?
1876 No. The clock frequency specified here must be given as an integral number.
1877 However, this clock frequency is used by the In-Application-Programming (IAP)
1878 routines of the LPC2000 family only, which seems to be very tolerant concerning
1879 the given clock frequency, so a slight difference between the specified clock
1880 frequency and the actual clock frequency will not cause any trouble.
1882 @item Do I have to keep a specific order for the commands in the configuration file?
1884 Well, yes and no. Commands can be given in arbitrary order, yet the devices
1885 listed for the JTAG scan chain must be given in the right order (jtag_device),
1886 with the device closest to the TDO-Pin being listed first. In general,
1887 whenever objects of the same type exist which require an index number, then
1888 these objects must be given in the right order (jtag_devices, targets and flash
1889 banks - a target references a jtag_device and a flash bank references a target).
1891 @item Sometimes my debugging session terminates with an error. When I look into the
1892 log file, I can see these error messages: Error: arm7_9_common.c:561
1893 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP