1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
7 * OpenOCD: (openocd). OpenOCD User's Guide
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
22 @item Copyright @copyright{} 2008-2022 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009-2010 David Brownell
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A
34 copy of the license is included in the section entitled ``GNU Free
35 Documentation License''.
40 @titlefont{@emph{Open On-Chip Debugger:}}
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
47 @vskip 0pt plus 1filll
56 @top OpenOCD User's Guide
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About Jim-Tcl:: About Jim-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Server Configuration:: Server Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * Flash Programming:: Flash Programming
76 * PLD/FPGA Commands:: PLD/FPGA Commands
77 * General Commands:: General Commands
78 * Architecture and Core Commands:: Architecture and Core Commands
79 * JTAG Commands:: JTAG Commands
80 * Boundary Scan Commands:: Boundary Scan Commands
81 * Utility Commands:: Utility Commands
82 * GDB and OpenOCD:: Using GDB and OpenOCD
83 * Tcl Scripting API:: Tcl Scripting API
84 * FAQ:: Frequently Asked Questions
85 * Tcl Crash Course:: Tcl Crash Course
86 * License:: GNU Free Documentation License
88 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
89 @comment case issue with ``Index.html'' and ``index.html''
90 @comment Occurs when creating ``--html --no-split'' output
91 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
92 * OpenOCD Concept Index:: Concept Index
93 * Command and Driver Index:: Command and Driver Index
100 OpenOCD was created by Dominic Rath as part of a 2005 diploma thesis written
101 at the University of Applied Sciences Augsburg (@uref{http://www.hs-augsburg.de}).
102 Since that time, the project has grown into an active open-source project,
103 supported by a diverse community of software and hardware developers from
106 @section What is OpenOCD?
110 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
111 in-system programming and boundary-scan testing for embedded target
114 It does so with the assistance of a @dfn{debug adapter}, which is
115 a small hardware module which helps provide the right kind of
116 electrical signaling to the target being debugged. These are
117 required since the debug host (on which OpenOCD runs) won't
118 usually have native support for such signaling, or the connector
119 needed to hook up to the target.
121 Such debug adapters support one or more @dfn{transport} protocols,
122 each of which involves different electrical signaling (and uses
123 different messaging protocols on top of that signaling). There
124 are many types of debug adapter, and little uniformity in what
125 they are called. (There are also product naming differences.)
127 These adapters are sometimes packaged as discrete dongles, which
128 may generically be called @dfn{hardware interface dongles}.
129 Some development boards also integrate them directly, which may
130 let the development board connect directly to the debug
131 host over USB (and sometimes also to power it over USB).
133 For example, a @dfn{JTAG Adapter} supports JTAG
134 signaling, and is used to communicate
135 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
136 A @dfn{TAP} is a ``Test Access Port'', a module which processes
137 special instructions and data. TAPs are daisy-chained within and
138 between chips and boards. JTAG supports debugging and boundary
141 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
142 signaling to communicate with some newer ARM cores, as well as debug
143 adapters which support both JTAG and SWD transports. SWD supports only
144 debugging, whereas JTAG also supports boundary scan operations.
146 For some chips, there are also @dfn{Programming Adapters} supporting
147 special transports used only to write code to flash memory, without
148 support for on-chip debugging or boundary scan.
149 (At this writing, OpenOCD does not support such non-debug adapters.)
152 @b{Dongles:} OpenOCD currently supports many types of hardware dongles:
153 USB-based, parallel port-based, and other standalone boxes that run
154 OpenOCD internally. @xref{Debug Adapter Hardware}.
156 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
157 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x), Cortex-M3
158 (Stellaris LM3, STMicroelectronics STM32 and Energy Micro EFM32) and
159 Intel Quark (x10xx) based cores to be debugged via the GDB protocol.
161 @b{Flash Programming:} Flash writing is supported for external
162 CFI-compatible NOR flashes (Intel and AMD/Spansion command set) and several
163 internal flashes (LPC1700, LPC1800, LPC2000, LPC4300, AT91SAM7, AT91SAM3U,
164 STR7x, STR9x, LM3, STM32x and EFM32). Preliminary support for various NAND flash
165 controllers (LPC3180, Orion, S3C24xx, more) is included.
167 @section OpenOCD Web Site
169 The OpenOCD web site provides the latest public news from the community:
171 @uref{http://openocd.org/}
173 @section Latest User's Guide:
175 The user's guide you are now reading may not be the latest one
176 available. A version for more recent code may be available.
177 Its HTML form is published regularly at:
179 @uref{http://openocd.org/doc/html/index.html}
181 PDF form is likewise published at:
183 @uref{http://openocd.org/doc/pdf/openocd.pdf}
185 @section OpenOCD User's Forum
187 There is an OpenOCD forum (phpBB) hosted by SparkFun,
188 which might be helpful to you. Note that if you want
189 anything to come to the attention of developers, you
190 should post it to the OpenOCD Developer Mailing List
191 instead of this forum.
193 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
195 @section OpenOCD User's Mailing List
197 The OpenOCD User Mailing List provides the primary means of
198 communication between users:
200 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-user}
204 Support can also be found on irc:
205 @uref{irc://irc.libera.chat/openocd}
208 @chapter OpenOCD Developer Resources
211 If you are interested in improving the state of OpenOCD's debugging and
212 testing support, new contributions will be welcome. Motivated developers
213 can produce new target, flash or interface drivers, improve the
214 documentation, as well as more conventional bug fixes and enhancements.
216 The resources in this chapter are available for developers wishing to explore
217 or expand the OpenOCD source code.
219 @section OpenOCD Git Repository
221 During the 0.3.x release cycle, OpenOCD switched from Subversion to
222 a Git repository hosted at SourceForge. The repository URL is:
224 @uref{git://git.code.sf.net/p/openocd/code}
228 @uref{http://git.code.sf.net/p/openocd/code}
230 You may prefer to use a mirror and the HTTP protocol:
232 @uref{http://repo.or.cz/r/openocd.git}
234 With standard Git tools, use @command{git clone} to initialize
235 a local repository, and @command{git pull} to update it.
236 There are also gitweb pages letting you browse the repository
237 with a web browser, or download arbitrary snapshots without
238 needing a Git client:
240 @uref{http://repo.or.cz/w/openocd.git}
242 The @file{README} file contains the instructions for building the project
243 from the repository or a snapshot.
245 Developers that want to contribute patches to the OpenOCD system are
246 @b{strongly} encouraged to work against mainline.
247 Patches created against older versions may require additional
248 work from their submitter in order to be updated for newer releases.
250 @section Doxygen Developer Manual
252 During the 0.2.x release cycle, the OpenOCD project began
253 providing a Doxygen reference manual. This document contains more
254 technical information about the software internals, development
255 processes, and similar documentation:
257 @uref{http://openocd.org/doc/doxygen/html/index.html}
259 This document is a work-in-progress, but contributions would be welcome
260 to fill in the gaps. All of the source files are provided in-tree,
261 listed in the Doxyfile configuration at the top of the source tree.
263 @section Gerrit Review System
265 All changes in the OpenOCD Git repository go through the web-based Gerrit
268 @uref{https://review.openocd.org/}
270 After a one-time registration and repository setup, anyone can push commits
271 from their local Git repository directly into Gerrit.
272 All users and developers are encouraged to review, test, discuss and vote
273 for changes in Gerrit. The feedback provides the basis for a maintainer to
274 eventually submit the change to the main Git repository.
276 The @file{HACKING} file, also available as the Patch Guide in the Doxygen
277 Developer Manual, contains basic information about how to connect a
278 repository to Gerrit, prepare and push patches. Patch authors are expected to
279 maintain their changes while they're in Gerrit, respond to feedback and if
280 necessary rework and push improved versions of the change.
282 @section OpenOCD Developer Mailing List
284 The OpenOCD Developer Mailing List provides the primary means of
285 communication between developers:
287 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-devel}
289 @section OpenOCD Bug Tracker
291 The OpenOCD Bug Tracker is hosted on SourceForge:
293 @uref{http://bugs.openocd.org/}
296 @node Debug Adapter Hardware
297 @chapter Debug Adapter Hardware
305 Defined: @b{dongle}: A small device that plugs into a computer and serves as
306 an adapter .... [snip]
308 In the OpenOCD case, this generally refers to @b{a small adapter} that
309 attaches to your computer via USB or the parallel port.
312 @section Choosing a Dongle
314 There are several things you should keep in mind when choosing a dongle.
317 @item @b{Transport} Does it support the kind of communication that you need?
318 OpenOCD focuses mostly on JTAG. Your version may also support
319 other ways to communicate with target devices.
320 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
321 Does your dongle support it? You might need a level converter.
322 @item @b{Pinout} What pinout does your target board use?
323 Does your dongle support it? You may be able to use jumper
324 wires, or an "octopus" connector, to convert pinouts.
325 @item @b{Connection} Does your computer have the USB, parallel, or
326 Ethernet port needed?
327 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
328 RTCK support (also known as ``adaptive clocking'')?
331 @section USB FT2232 Based
333 There are many USB JTAG dongles on the market, many of them based
334 on a chip from ``Future Technology Devices International'' (FTDI)
335 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
336 See: @url{http://www.ftdichip.com} for more information.
337 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
338 chips started to become available in JTAG adapters. Around 2012, a new
339 variant appeared - FT232H - this is a single-channel version of FT2232H.
340 (Adapters using those high speed FT2232H or FT232H chips may support adaptive
343 The FT2232 chips are flexible enough to support some other
344 transport options, such as SWD or the SPI variants used to
345 program some chips. They have two communications channels,
346 and one can be used for a UART adapter at the same time the
347 other one is used to provide a debug adapter.
349 Also, some development boards integrate an FT2232 chip to serve as
350 a built-in low-cost debug adapter and USB-to-serial solution.
354 @* Link @url{http://elk.informatik.fh-augsburg.de/hhweb/doc/openocd/usbjtag/usbjtag.html}
356 @* See: @url{http://www.amontec.com/jtagkey.shtml}
358 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
360 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
362 @* See: @url{http://www.signalyzer.com}
363 @item @b{Stellaris Eval Boards}
364 @* See: @url{http://www.ti.com} - The Stellaris eval boards
365 bundle FT2232-based JTAG and SWD support, which can be used to debug
366 the Stellaris chips. Using separate JTAG adapters is optional.
367 These boards can also be used in a "pass through" mode as JTAG adapters
368 to other target boards, disabling the Stellaris chip.
369 @item @b{TI/Luminary ICDI}
370 @* See: @url{http://www.ti.com} - TI/Luminary In-Circuit Debug
371 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
372 Evaluation Kits. Like the non-detachable FT2232 support on the other
373 Stellaris eval boards, they can be used to debug other target boards.
374 @item @b{olimex-jtag}
375 @* See: @url{http://www.olimex.com}
376 @item @b{Flyswatter/Flyswatter2}
377 @* See: @url{http://www.tincantools.com}
378 @item @b{turtelizer2}
380 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
381 @url{http://www.ethernut.de}
383 @* Link: @url{http://www.hitex.com/index.php?id=383}
385 @* Link @url{http://www.hitex.com/stm32-stick}
386 @item @b{axm0432_jtag}
387 @* Axiom AXM-0432 Link @url{http://www.axman.com} - NOTE: This JTAG does not appear
388 to be available anymore as of April 2012.
390 @* Link @url{http://www.hitex.com/index.php?id=cortino}
391 @item @b{dlp-usb1232h}
392 @* Link @url{http://www.dlpdesign.com/usb/usb1232h.shtml}
393 @item @b{digilent-hs1}
394 @* Link @url{http://www.digilentinc.com/Products/Detail.cfm?Prod=JTAG-HS1}
396 @* Link @url{http://code.google.com/p/opendous/wiki/JTAG} FT2232H-based
398 @item @b{JTAG-lock-pick Tiny 2}
399 @* Link @url{http://www.distortec.com/jtag-lock-pick-tiny-2} FT232H-based
402 @* Link: @url{http://shop.gateworks.com/index.php?route=product/product&path=70_80&product_id=64}
406 @section USB-JTAG / Altera USB-Blaster compatibles
408 These devices also show up as FTDI devices, but are not
409 protocol-compatible with the FT2232 devices. They are, however,
410 protocol-compatible among themselves. USB-JTAG devices typically consist
411 of a FT245 followed by a CPLD that understands a particular protocol,
412 or emulates this protocol using some other hardware.
414 They may appear under different USB VID/PID depending on the particular
415 product. The driver can be configured to search for any VID/PID pair
416 (see the section on driver commands).
419 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
420 @* Link: @url{http://ixo-jtag.sourceforge.net/}
421 @item @b{Altera USB-Blaster}
422 @* Link: @url{http://www.altera.com/literature/ug/ug_usb_blstr.pdf}
425 @section USB J-Link based
426 There are several OEM versions of the SEGGER @b{J-Link} adapter. It is
427 an example of a microcontroller based JTAG adapter, it uses an
428 AT91SAM764 internally.
431 @item @b{SEGGER J-Link}
432 @* Link: @url{http://www.segger.com/jlink.html}
433 @item @b{Atmel SAM-ICE} (Only works with Atmel chips!)
434 @* Link: @url{http://www.atmel.com/tools/atmelsam-ice.aspx}
438 @section USB RLINK based
439 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer,
440 permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for
441 SWD and not JTAG, thus not supported.
444 @item @b{Raisonance RLink}
445 @* Link: @url{http://www.mcu-raisonance.com/~rlink-debugger-programmer__@/microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html}
446 @item @b{STM32 Primer}
447 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
448 @item @b{STM32 Primer2}
449 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
452 @section USB ST-LINK based
453 STMicroelectronics has an adapter called @b{ST-LINK}.
454 They only work with STMicroelectronics chips, notably STM32 and STM8.
458 @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
459 @* Link: @url{http://www.st.com/internet/evalboard/product/219866.jsp}
461 @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
462 @* Link: @url{http://www.st.com/internet/evalboard/product/251168.jsp}
464 @* This is available standalone and as part of some kits.
465 @* Link: @url{http://www.st.com/stlink-v3}
466 @item @b{STLINK-V3PWR}
467 @* This is available standalone.
468 Beside the debugger functionality, the probe includes a SMU (source
469 measurement unit) aimed at analyzing power consumption during code
470 execution. The SMU is not supported by OpenOCD.
471 @* Link: @url{http://www.st.com/stlink-v3pwr}
474 For info the original ST-LINK enumerates using the mass storage usb class; however,
475 its implementation is completely broken. The result is this causes issues under Linux.
476 The simplest solution is to get Linux to ignore the ST-LINK using one of the following methods:
478 @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
479 @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
482 @section USB TI/Stellaris ICDI based
483 Texas Instruments has an adapter called @b{ICDI}.
484 It is not to be confused with the FTDI based adapters that were originally fitted to their
485 evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
487 @section USB Nuvoton Nu-Link
488 Nuvoton has an adapter called @b{Nu-Link}.
489 It is available either as stand-alone dongle and embedded on development boards.
490 It supports SWD, serial port bridge and mass storage for firmware update.
491 Both Nu-Link v1 and v2 are supported.
493 @section USB CMSIS-DAP based
494 ARM has released a interface standard called CMSIS-DAP that simplifies connecting
495 debuggers to ARM Cortex based targets @url{http://www.keil.com/support/man/docs/dapdebug/dapdebug_introduction.htm}.
500 @* Link: @url{http://shop.embedded-projects.net/} - which uses an Atmel MEGA32 and a UBN9604
502 @item @b{USB - Presto}
503 @* Link: @url{http://tools.asix.net/prg_presto.htm}
505 @item @b{Versaloon-Link}
506 @* Link: @url{http://www.versaloon.com}
508 @item @b{ARM-JTAG-EW}
509 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
512 @* Link: @url{https://nanoxplore.org/}
515 @* Link: @url{http://dangerousprototypes.com/bus-pirate-manual/}
518 @* Link: @url{http://code.google.com/p/opendous-jtag/} - which uses an AT90USB162
521 @* Link: @url{http://code.google.com/p/estick-jtag/}
523 @item @b{Keil ULINK v1}
524 @* Link: @url{http://www.keil.com/ulink1/}
526 @item @b{TI XDS110 Debug Probe}
527 @* Link: @url{https://software-dl.ti.com/ccs/esd/documents/xdsdebugprobes/emu_xds110.html}
528 @* Link: @url{https://software-dl.ti.com/ccs/esd/documents/xdsdebugprobes/emu_xds_software_package_download.html#xds110-support-utilities}
531 @section IBM PC Parallel Printer Port Based
533 The two well-known ``JTAG Parallel Ports'' cables are the Xilinx DLC5
534 and the Macraigor Wiggler. There are many clones and variations of
537 Note that parallel ports are becoming much less common, so if you
538 have the choice you should probably avoid these adapters in favor
543 @item @b{Wiggler} - There are many clones of this.
544 @* Link: @url{http://www.macraigor.com/wiggler.htm}
546 @item @b{DLC5} - From XILINX - There are many clones of this
547 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
548 produced, PDF schematics are easily found and it is easy to make.
550 @item @b{Amontec - JTAG Accelerator}
551 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
554 @* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
556 @item @b{Wiggler_ntrst_inverted}
557 @* Yet another variation - See the source code, src/jtag/parport.c
559 @item @b{old_amt_wiggler}
560 @* Unknown - probably not on the market today
563 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
566 @* Link: @url{http://www.amontec.com/chameleon.shtml}
572 @* ispDownload from Lattice Semiconductor
573 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
576 @* From STMicroelectronics;
577 @* Link: @url{http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATA_BRIEF/DM00039500.pdf}
585 @* An EP93xx based Linux machine using the GPIO pins directly.
588 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
590 @item @b{bcm2835gpio}
591 @* A BCM2835-based board (e.g. Raspberry Pi) using the GPIO pins of the expansion header.
594 @* A NXP i.MX-based board (e.g. Wandboard) using the GPIO pins (should work on any i.MX processor).
597 @* A Texas Instruments AM335x-based board (e.g. BeagleBone Black) using the GPIO pins of the expansion headers.
600 @* A JTAG driver acting as a client for the JTAG VPI server interface.
601 @* Link: @url{http://github.com/fjullien/jtag_vpi}
604 @* A driver for Cadence virtual Debug Interface to emulated or simulated targets.
605 It implements a client connecting to the vdebug server, which in turn communicates
606 with the emulated or simulated RTL model through a transactor. The driver supports
607 JTAG and DAP-level transports.
610 @* A JTAG driver acting as a client for the SystemVerilog Direct Programming
611 Interface (DPI) for JTAG devices. DPI allows OpenOCD to connect to the JTAG
612 interface of a hardware model written in SystemVerilog, for example, on an
613 emulation model of target hardware.
615 @item @b{xlnx_pcie_xvc}
616 @* A JTAG driver exposing Xilinx Virtual Cable over PCI Express to OpenOCD as JTAG/SWD interface.
619 @* A bitbang JTAG driver using Linux GPIO through library libgpiod.
622 @* A bitbang JTAG driver using Linux legacy sysfs GPIO.
623 This is deprecated from Linux v5.3; prefer using @b{linuxgpiod}.
625 @item @b{esp_usb_jtag}
626 @* A JTAG driver to communicate with builtin debug modules of Espressif ESP32-C3 and ESP32-S3 chips using OpenOCD.
631 @chapter About Jim-Tcl
635 OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
636 This programming language provides a simple and extensible
639 All commands presented in this Guide are extensions to Jim-Tcl.
640 You can use them as simple commands, without needing to learn
641 much of anything about Tcl.
642 Alternatively, you can write Tcl programs with them.
644 You can learn more about Jim at its website, @url{http://jim.tcl.tk}.
645 There is an active and responsive community, get on the mailing list
646 if you have any questions. Jim-Tcl maintainers also lurk on the
647 OpenOCD mailing list.
650 @item @b{Jim vs. Tcl}
651 @* Jim-Tcl is a stripped down version of the well known Tcl language,
652 which can be found here: @url{http://www.tcl.tk}. Jim-Tcl has far
653 fewer features. Jim-Tcl is several dozens of .C files and .H files and
654 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
655 4.2 MB .zip file containing 1540 files.
657 @item @b{Missing Features}
658 @* Our practice has been: Add/clone the real Tcl feature if/when
659 needed. We welcome Jim-Tcl improvements, not bloat. Also there
660 are a large number of optional Jim-Tcl features that are not
664 @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
665 command interpreter today is a mixture of (newer)
666 Jim-Tcl commands, and the (older) original command interpreter.
669 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
670 can type a Tcl for() loop, set variables, etc.
671 Some of the commands documented in this guide are implemented
672 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
674 @item @b{Historical Note}
675 @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
676 before OpenOCD 0.5 release, OpenOCD switched to using Jim-Tcl
677 as a Git submodule, which greatly simplified upgrading Jim-Tcl
678 to benefit from new features and bugfixes in Jim-Tcl.
680 @item @b{Need a crash course in Tcl?}
681 @*@xref{Tcl Crash Course}.
686 @cindex command line options
688 @cindex directory search
690 Properly installing OpenOCD sets up your operating system to grant it access
691 to the debug adapters. On Linux, this usually involves installing a file
692 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. An example rules file
693 that works for many common adapters is shipped with OpenOCD in the
694 @file{contrib} directory. MS-Windows needs
695 complex and confusing driver configuration for every peripheral. Such issues
696 are unique to each operating system, and are not detailed in this User's Guide.
698 Then later you will invoke the OpenOCD server, with various options to
699 tell it how each debug session should work.
700 The @option{--help} option shows:
704 --help | -h display this help
705 --version | -v display OpenOCD version
706 --file | -f use configuration file <name>
707 --search | -s dir to search for config files and scripts
708 --debug | -d set debug level to 3
709 | -d<n> set debug level to <level>
710 --log_output | -l redirect log output to file <name>
711 --command | -c run <command>
714 If you don't give any @option{-f} or @option{-c} options,
715 OpenOCD tries to read the configuration file @file{openocd.cfg}.
716 To specify one or more different
717 configuration files, use @option{-f} options. For example:
720 openocd -f config1.cfg -f config2.cfg -f config3.cfg
723 Configuration files and scripts are searched for in
725 @item the current directory,
726 @item any search dir specified on the command line using the @option{-s} option,
727 @item any search dir specified using the @command{add_script_search_dir} command,
728 @item a directory in the @env{OPENOCD_SCRIPTS} environment variable (if set),
729 @item @file{%APPDATA%/OpenOCD} (only on Windows),
730 @item @file{$HOME/Library/Preferences/org.openocd} (only on Darwin),
731 @item @file{$XDG_CONFIG_HOME/openocd} (@env{$XDG_CONFIG_HOME} defaults to @file{$HOME/.config}),
732 @item @file{$HOME/.openocd},
733 @item the site wide script library @file{$pkgdatadir/site} and
734 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
736 The first found file with a matching file name will be used.
739 Don't try to use configuration script names or paths which
740 include the "#" character. That character begins Tcl comments.
743 @section Simple setup, no customization
745 In the best case, you can use two scripts from one of the script
746 libraries, hook up your JTAG adapter, and start the server ... and
747 your JTAG setup will just work "out of the box". Always try to
748 start by reusing those scripts, but assume you'll need more
749 customization even if this works. @xref{OpenOCD Project Setup}.
751 If you find a script for your JTAG adapter, and for your board or
752 target, you may be able to hook up your JTAG adapter then start
753 the server with some variation of one of the following:
756 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
757 openocd -f interface/ftdi/ADAPTER.cfg -f board/MYBOARD.cfg
760 You might also need to configure which reset signals are present,
761 using @option{-c 'reset_config trst_and_srst'} or something similar.
762 If all goes well you'll see output something like
765 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
766 For bug reports, read
767 http://openocd.org/doc/doxygen/bugs.html
768 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
769 (mfg: 0x23b, part: 0xba00, ver: 0x3)
772 Seeing that "tap/device found" message, and no warnings, means
773 the JTAG communication is working. That's a key milestone, but
774 you'll probably need more project-specific setup.
776 @section What OpenOCD does as it starts
778 OpenOCD starts by processing the configuration commands provided
779 on the command line or, if there were no @option{-c command} or
780 @option{-f file.cfg} options given, in @file{openocd.cfg}.
781 @xref{configurationstage,,Configuration Stage}.
782 At the end of the configuration stage it verifies the JTAG scan
783 chain defined using those commands; your configuration should
784 ensure that this always succeeds.
785 Normally, OpenOCD then starts running as a server.
786 Alternatively, commands may be used to terminate the configuration
787 stage early, perform work (such as updating some flash memory),
788 and then shut down without acting as a server.
790 Once OpenOCD starts running as a server, it waits for connections from
791 clients (Telnet, GDB, RPC) and processes the commands issued through
794 If you are having problems, you can enable internal debug messages via
795 the @option{-d} option.
797 Also it is possible to interleave Jim-Tcl commands w/config scripts using the
798 @option{-c} command line switch.
800 To enable debug output (when reporting problems or working on OpenOCD
801 itself), use the @option{-d} command line switch. This sets the
802 @option{debug_level} to "3", outputting the most information,
803 including debug messages. The default setting is "2", outputting only
804 informational messages, warnings and errors. You can also change this
805 setting from within a telnet or gdb session using @command{debug_level<n>}
806 (@pxref{debuglevel,,debug_level}).
808 You can redirect all output from the server to a file using the
809 @option{-l <logfile>} switch.
811 Note! OpenOCD will launch the GDB & telnet server even if it can not
812 establish a connection with the target. In general, it is possible for
813 the JTAG controller to be unresponsive until the target is set up
814 correctly via e.g. GDB monitor commands in a GDB init script.
816 @node OpenOCD Project Setup
817 @chapter OpenOCD Project Setup
819 To use OpenOCD with your development projects, you need to do more than
820 just connect the JTAG adapter hardware (dongle) to your development board
821 and start the OpenOCD server.
822 You also need to configure your OpenOCD server so that it knows
823 about your adapter and board, and helps your work.
824 You may also want to connect OpenOCD to GDB, possibly
825 using Eclipse or some other GUI.
827 @section Hooking up the JTAG Adapter
829 Today's most common case is a dongle with a JTAG cable on one side
830 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
831 and a USB cable on the other.
832 Instead of USB, some dongles use Ethernet;
833 older ones may use a PC parallel port, or even a serial port.
836 @item @emph{Start with power to your target board turned off},
837 and nothing connected to your JTAG adapter.
838 If you're particularly paranoid, unplug power to the board.
839 It's important to have the ground signal properly set up,
840 unless you are using a JTAG adapter which provides
841 galvanic isolation between the target board and the
844 @item @emph{Be sure it's the right kind of JTAG connector.}
845 If your dongle has a 20-pin ARM connector, you need some kind
846 of adapter (or octopus, see below) to hook it up to
847 boards using 14-pin or 10-pin connectors ... or to 20-pin
848 connectors which don't use ARM's pinout.
850 In the same vein, make sure the voltage levels are compatible.
851 Not all JTAG adapters have the level shifters needed to work
852 with 1.2 Volt boards.
854 @item @emph{Be certain the cable is properly oriented} or you might
855 damage your board. In most cases there are only two possible
856 ways to connect the cable.
857 Connect the JTAG cable from your adapter to the board.
858 Be sure it's firmly connected.
860 In the best case, the connector is keyed to physically
861 prevent you from inserting it wrong.
862 This is most often done using a slot on the board's male connector
863 housing, which must match a key on the JTAG cable's female connector.
864 If there's no housing, then you must look carefully and
865 make sure pin 1 on the cable hooks up to pin 1 on the board.
866 Ribbon cables are frequently all grey except for a wire on one
867 edge, which is red. The red wire is pin 1.
869 Sometimes dongles provide cables where one end is an ``octopus'' of
870 color coded single-wire connectors, instead of a connector block.
871 These are great when converting from one JTAG pinout to another,
872 but are tedious to set up.
873 Use these with connector pinout diagrams to help you match up the
874 adapter signals to the right board pins.
876 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
877 A USB, parallel, or serial port connector will go to the host which
878 you are using to run OpenOCD.
879 For Ethernet, consult the documentation and your network administrator.
881 For USB-based JTAG adapters you have an easy sanity check at this point:
882 does the host operating system see the JTAG adapter? If you're running
883 Linux, try the @command{lsusb} command. If that host is an
884 MS-Windows host, you'll need to install a driver before OpenOCD works.
886 @item @emph{Connect the adapter's power supply, if needed.}
887 This step is primarily for non-USB adapters,
888 but sometimes USB adapters need extra power.
890 @item @emph{Power up the target board.}
891 Unless you just let the magic smoke escape,
892 you're now ready to set up the OpenOCD server
893 so you can use JTAG to work with that board.
897 Talk with the OpenOCD server using
898 telnet (@code{telnet localhost 4444} on many systems) or GDB.
899 @xref{GDB and OpenOCD}.
901 @section Project Directory
903 There are many ways you can configure OpenOCD and start it up.
905 A simple way to organize them all involves keeping a
906 single directory for your work with a given board.
907 When you start OpenOCD from that directory,
908 it searches there first for configuration files, scripts,
909 files accessed through semihosting,
910 and for code you upload to the target board.
911 It is also the natural place to write files,
912 such as log files and data you download from the board.
914 @section Configuration Basics
916 There are two basic ways of configuring OpenOCD, and
917 a variety of ways you can mix them.
918 Think of the difference as just being how you start the server:
921 @item Many @option{-f file} or @option{-c command} options on the command line
922 @item No options, but a @dfn{user config file}
923 in the current directory named @file{openocd.cfg}
926 Here is an example @file{openocd.cfg} file for a setup
927 using a Signalyzer FT2232-based JTAG adapter to talk to
928 a board with an Atmel AT91SAM7X256 microcontroller:
931 source [find interface/ftdi/signalyzer.cfg]
933 # GDB can also flash my flash!
934 gdb_memory_map enable
935 gdb_flash_program enable
937 source [find target/sam7x256.cfg]
940 Here is the command line equivalent of that configuration:
943 openocd -f interface/ftdi/signalyzer.cfg \
944 -c "gdb_memory_map enable" \
945 -c "gdb_flash_program enable" \
946 -f target/sam7x256.cfg
949 You could wrap such long command lines in shell scripts,
950 each supporting a different development task.
951 One might re-flash the board with a specific firmware version.
952 Another might set up a particular debugging or run-time environment.
955 At this writing (October 2009) the command line method has
956 problems with how it treats variables.
957 For example, after @option{-c "set VAR value"}, or doing the
958 same in a script, the variable @var{VAR} will have no value
959 that can be tested in a later script.
962 Here we will focus on the simpler solution: one user config
963 file, including basic configuration plus any TCL procedures
964 to simplify your work.
966 @section User Config Files
967 @cindex config file, user
968 @cindex user config file
969 @cindex config file, overview
971 A user configuration file ties together all the parts of a project
973 One of the following will match your situation best:
976 @item Ideally almost everything comes from configuration files
977 provided by someone else.
978 For example, OpenOCD distributes a @file{scripts} directory
979 (probably in @file{/usr/share/openocd/scripts} on Linux).
980 Board and tool vendors can provide these too, as can individual
981 user sites; the @option{-s} command line option lets you say
982 where to find these files. (@xref{Running}.)
983 The AT91SAM7X256 example above works this way.
985 Three main types of non-user configuration file each have their
986 own subdirectory in the @file{scripts} directory:
989 @item @b{interface} -- one for each different debug adapter;
990 @item @b{board} -- one for each different board
991 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
994 Best case: include just two files, and they handle everything else.
995 The first is an interface config file.
996 The second is board-specific, and it sets up the JTAG TAPs and
997 their GDB targets (by deferring to some @file{target.cfg} file),
998 declares all flash memory, and leaves you nothing to do except
1002 source [find interface/olimex-jtag-tiny.cfg]
1003 source [find board/csb337.cfg]
1006 Boards with a single microcontroller often won't need more
1007 than the target config file, as in the AT91SAM7X256 example.
1008 That's because there is no external memory (flash, DDR RAM), and
1009 the board differences are encapsulated by application code.
1011 @item Maybe you don't know yet what your board looks like to JTAG.
1012 Once you know the @file{interface.cfg} file to use, you may
1013 need help from OpenOCD to discover what's on the board.
1014 Once you find the JTAG TAPs, you can just search for appropriate
1016 configuration files ... or write your own, from the bottom up.
1017 @xref{autoprobing,,Autoprobing}.
1019 @item You can often reuse some standard config files but
1020 need to write a few new ones, probably a @file{board.cfg} file.
1021 You will be using commands described later in this User's Guide,
1022 and working with the guidelines in the next chapter.
1024 For example, there may be configuration files for your JTAG adapter
1025 and target chip, but you need a new board-specific config file
1026 giving access to your particular flash chips.
1027 Or you might need to write another target chip configuration file
1028 for a new chip built around the Cortex-M3 core.
1031 When you write new configuration files, please submit
1032 them for inclusion in the next OpenOCD release.
1033 For example, a @file{board/newboard.cfg} file will help the
1034 next users of that board, and a @file{target/newcpu.cfg}
1035 will help support users of any board using that chip.
1039 You may need to write some C code.
1040 It may be as simple as supporting a new FT2232 or parport
1041 based adapter; a bit more involved, like a NAND or NOR flash
1042 controller driver; or a big piece of work like supporting
1043 a new chip architecture.
1046 Reuse the existing config files when you can.
1047 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
1048 You may find a board configuration that's a good example to follow.
1050 When you write config files, separate the reusable parts
1051 (things every user of that interface, chip, or board needs)
1052 from ones specific to your environment and debugging approach.
1056 For example, a @code{gdb-attach} event handler that invokes
1057 the @command{reset init} command will interfere with debugging
1058 early boot code, which performs some of the same actions
1059 that the @code{reset-init} event handler does.
1062 Likewise, the @command{arm9 vector_catch} command (or
1063 @cindex vector_catch
1064 its siblings @command{xscale vector_catch}
1065 and @command{cortex_m vector_catch}) can be a time-saver
1066 during some debug sessions, but don't make everyone use that either.
1067 Keep those kinds of debugging aids in your user config file,
1068 along with messaging and tracing setup.
1069 (@xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.)
1072 You might need to override some defaults.
1073 For example, you might need to move, shrink, or back up the target's
1074 work area if your application needs much SRAM.
1077 TCP/IP port configuration is another example of something which
1078 is environment-specific, and should only appear in
1079 a user config file. @xref{tcpipports,,TCP/IP Ports}.
1082 @section Project-Specific Utilities
1084 A few project-specific utility
1085 routines may well speed up your work.
1086 Write them, and keep them in your project's user config file.
1088 For example, if you are making a boot loader work on a
1089 board, it's nice to be able to debug the ``after it's
1090 loaded to RAM'' parts separately from the finicky early
1091 code which sets up the DDR RAM controller and clocks.
1092 A script like this one, or a more GDB-aware sibling,
1096 proc ramboot @{ @} @{
1097 # Reset, running the target's "reset-init" scripts
1098 # to initialize clocks and the DDR RAM controller.
1099 # Leave the CPU halted.
1102 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
1103 load_image u-boot.bin 0x20000000
1110 Then once that code is working you will need to make it
1111 boot from NOR flash; a different utility would help.
1112 Alternatively, some developers write to flash using GDB.
1113 (You might use a similar script if you're working with a flash
1114 based microcontroller application instead of a boot loader.)
1117 proc newboot @{ @} @{
1118 # Reset, leaving the CPU halted. The "reset-init" event
1119 # proc gives faster access to the CPU and to NOR flash;
1120 # "reset halt" would be slower.
1123 # Write standard version of U-Boot into the first two
1124 # sectors of NOR flash ... the standard version should
1125 # do the same lowlevel init as "reset-init".
1126 flash protect 0 0 1 off
1127 flash erase_sector 0 0 1
1128 flash write_bank 0 u-boot.bin 0x0
1129 flash protect 0 0 1 on
1131 # Reboot from scratch using that new boot loader.
1136 You may need more complicated utility procedures when booting
1138 That often involves an extra bootloader stage,
1139 running from on-chip SRAM to perform DDR RAM setup so it can load
1140 the main bootloader code (which won't fit into that SRAM).
1142 Other helper scripts might be used to write production system images,
1143 involving considerably more than just a three stage bootloader.
1145 @section Target Software Changes
1147 Sometimes you may want to make some small changes to the software
1148 you're developing, to help make JTAG debugging work better.
1149 For example, in C or assembly language code you might
1150 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1151 handling issues like:
1155 @item @b{Watchdog Timers}...
1156 Watchdog timers are typically used to automatically reset systems if
1157 some application task doesn't periodically reset the timer. (The
1158 assumption is that the system has locked up if the task can't run.)
1159 When a JTAG debugger halts the system, that task won't be able to run
1160 and reset the timer ... potentially causing resets in the middle of
1161 your debug sessions.
1163 It's rarely a good idea to disable such watchdogs, since their usage
1164 needs to be debugged just like all other parts of your firmware.
1165 That might however be your only option.
1167 Look instead for chip-specific ways to stop the watchdog from counting
1168 while the system is in a debug halt state. It may be simplest to set
1169 that non-counting mode in your debugger startup scripts. You may however
1170 need a different approach when, for example, a motor could be physically
1171 damaged by firmware remaining inactive in a debug halt state. That might
1172 involve a type of firmware mode where that "non-counting" mode is disabled
1173 at the beginning then re-enabled at the end; a watchdog reset might fire
1174 and complicate the debug session, but hardware (or people) would be
1175 protected.@footnote{Note that many systems support a "monitor mode" debug
1176 that is a somewhat cleaner way to address such issues. You can think of
1177 it as only halting part of the system, maybe just one task,
1178 instead of the whole thing.
1179 At this writing, January 2010, OpenOCD based debugging does not support
1180 monitor mode debug, only "halt mode" debug.}
1182 @item @b{ARM Semihosting}...
1183 @cindex ARM semihosting
1184 When linked with a special runtime library provided with many
1185 toolchains@footnote{See chapter 8 "Semihosting" in
1186 @uref{http://infocenter.arm.com/help/topic/com.arm.doc.dui0203i/DUI0203I_rvct_developer_guide.pdf,
1187 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1188 The CodeSourcery EABI toolchain also includes a semihosting library.},
1189 your target code can use I/O facilities on the debug host. That library
1190 provides a small set of system calls which are handled by OpenOCD.
1191 It can let the debugger provide your system console and a file system,
1192 helping with early debugging or providing a more capable environment
1193 for sometimes-complex tasks like installing system firmware onto
1196 @item @b{ARM Wait-For-Interrupt}...
1197 Many ARM chips synchronize the JTAG clock using the core clock.
1198 Low power states which stop that core clock thus prevent JTAG access.
1199 Idle loops in tasking environments often enter those low power states
1200 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1202 You may want to @emph{disable that instruction} in source code,
1203 or otherwise prevent using that state,
1204 to ensure you can get JTAG access at any time.@footnote{As a more
1205 polite alternative, some processors have special debug-oriented
1206 registers which can be used to change various features including
1207 how the low power states are clocked while debugging.
1208 The STM32 DBGMCU_CR register is an example; at the cost of extra
1209 power consumption, JTAG can be used during low power states.}
1210 For example, the OpenOCD @command{halt} command may not
1211 work for an idle processor otherwise.
1213 @item @b{Delay after reset}...
1214 Not all chips have good support for debugger access
1215 right after reset; many LPC2xxx chips have issues here.
1216 Similarly, applications that reconfigure pins used for
1217 JTAG access as they start will also block debugger access.
1219 To work with boards like this, @emph{enable a short delay loop}
1220 the first thing after reset, before "real" startup activities.
1221 For example, one second's delay is usually more than enough
1222 time for a JTAG debugger to attach, so that
1223 early code execution can be debugged
1224 or firmware can be replaced.
1226 @item @b{Debug Communications Channel (DCC)}...
1227 Some processors include mechanisms to send messages over JTAG.
1228 Many ARM cores support these, as do some cores from other vendors.
1229 (OpenOCD may be able to use this DCC internally, speeding up some
1230 operations like writing to memory.)
1232 Your application may want to deliver various debugging messages
1233 over JTAG, by @emph{linking with a small library of code}
1234 provided with OpenOCD and using the utilities there to send
1235 various kinds of message.
1236 @xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.
1240 @section Target Hardware Setup
1242 Chip vendors often provide software development boards which
1243 are highly configurable, so that they can support all options
1244 that product boards may require. @emph{Make sure that any
1245 jumpers or switches match the system configuration you are
1248 Common issues include:
1252 @item @b{JTAG setup} ...
1253 Boards may support more than one JTAG configuration.
1254 Examples include jumpers controlling pullups versus pulldowns
1255 on the nTRST and/or nSRST signals, and choice of connectors
1256 (e.g. which of two headers on the base board,
1257 or one from a daughtercard).
1258 For some Texas Instruments boards, you may need to jumper the
1259 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1261 @item @b{Boot Modes} ...
1262 Complex chips often support multiple boot modes, controlled
1263 by external jumpers. Make sure this is set up correctly.
1264 For example many i.MX boards from NXP need to be jumpered
1265 to "ATX mode" to start booting using the on-chip ROM, when
1266 using second stage bootloader code stored in a NAND flash chip.
1268 Such explicit configuration is common, and not limited to
1269 booting from NAND. You might also need to set jumpers to
1270 start booting using code loaded from an MMC/SD card; external
1271 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1272 flash; some external host; or various other sources.
1275 @item @b{Memory Addressing} ...
1276 Boards which support multiple boot modes may also have jumpers
1277 to configure memory addressing. One board, for example, jumpers
1278 external chipselect 0 (used for booting) to address either
1279 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1280 or NAND flash. When it's jumpered to address NAND flash, that
1281 board must also be told to start booting from on-chip ROM.
1283 Your @file{board.cfg} file may also need to be told this jumper
1284 configuration, so that it can know whether to declare NOR flash
1285 using @command{flash bank} or instead declare NAND flash with
1286 @command{nand device}; and likewise which probe to perform in
1287 its @code{reset-init} handler.
1289 A closely related issue is bus width. Jumpers might need to
1290 distinguish between 8 bit or 16 bit bus access for the flash
1291 used to start booting.
1293 @item @b{Peripheral Access} ...
1294 Development boards generally provide access to every peripheral
1295 on the chip, sometimes in multiple modes (such as by providing
1296 multiple audio codec chips).
1297 This interacts with software
1298 configuration of pin multiplexing, where for example a
1299 given pin may be routed either to the MMC/SD controller
1300 or the GPIO controller. It also often interacts with
1301 configuration jumpers. One jumper may be used to route
1302 signals to an MMC/SD card slot or an expansion bus (which
1303 might in turn affect booting); others might control which
1304 audio or video codecs are used.
1308 Plus you should of course have @code{reset-init} event handlers
1309 which set up the hardware to match that jumper configuration.
1310 That includes in particular any oscillator or PLL used to clock
1311 the CPU, and any memory controllers needed to access external
1312 memory and peripherals. Without such handlers, you won't be
1313 able to access those resources without working target firmware
1314 which can do that setup ... this can be awkward when you're
1315 trying to debug that target firmware. Even if there's a ROM
1316 bootloader which handles a few issues, it rarely provides full
1317 access to all board-specific capabilities.
1320 @node Config File Guidelines
1321 @chapter Config File Guidelines
1323 This chapter is aimed at any user who needs to write a config file,
1324 including developers and integrators of OpenOCD and any user who
1325 needs to get a new board working smoothly.
1326 It provides guidelines for creating those files.
1328 You should find the following directories under
1329 @t{$(INSTALLDIR)/scripts}, with config files maintained upstream. Use
1330 them as-is where you can; or as models for new files.
1332 @item @file{interface} ...
1333 These are for debug adapters. Files that specify configuration to use
1334 specific JTAG, SWD and other adapters go here.
1335 @item @file{board} ...
1336 Think Circuit Board, PWA, PCB, they go by many names. Board files
1337 contain initialization items that are specific to a board.
1339 They reuse target configuration files, since the same
1340 microprocessor chips are used on many boards,
1341 but support for external parts varies widely. For
1342 example, the SDRAM initialization sequence for the board, or the type
1343 of external flash and what address it uses. Any initialization
1344 sequence to enable that external flash or SDRAM should be found in the
1345 board file. Boards may also contain multiple targets: two CPUs; or
1347 @item @file{target} ...
1348 Think chip. The ``target'' directory represents the JTAG TAPs
1350 which OpenOCD should control, not a board. Two common types of targets
1351 are ARM chips and FPGA or CPLD chips.
1352 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1353 the target config file defines all of them.
1354 @item @emph{more} ... browse for other library files which may be useful.
1355 For example, there are various generic and CPU-specific utilities.
1358 The @file{openocd.cfg} user config
1359 file may override features in any of the above files by
1360 setting variables before sourcing the target file, or by adding
1361 commands specific to their situation.
1363 @section Interface Config Files
1365 The user config file
1366 should be able to source one of these files with a command like this:
1369 source [find interface/FOOBAR.cfg]
1372 A preconfigured interface file should exist for every debug adapter
1373 in use today with OpenOCD.
1374 That said, perhaps some of these config files
1375 have only been used by the developer who created it.
1377 A separate chapter gives information about how to set these up.
1378 @xref{Debug Adapter Configuration}.
1379 Read the OpenOCD source code (and Developer's Guide)
1380 if you have a new kind of hardware interface
1381 and need to provide a driver for it.
1383 @deffn {Command} {find} 'filename'
1384 Prints full path to @var{filename} according to OpenOCD search rules.
1387 @deffn {Command} {ocd_find} 'filename'
1388 Prints full path to @var{filename} according to OpenOCD search rules. This
1389 is a low level function used by the @command{find}. Usually you want
1390 to use @command{find}, instead.
1393 @section Board Config Files
1394 @cindex config file, board
1395 @cindex board config file
1397 The user config file
1398 should be able to source one of these files with a command like this:
1401 source [find board/FOOBAR.cfg]
1404 The point of a board config file is to package everything
1405 about a given board that user config files need to know.
1406 In summary the board files should contain (if present)
1409 @item One or more @command{source [find target/...cfg]} statements
1410 @item NOR flash configuration (@pxref{norconfiguration,,NOR Configuration})
1411 @item NAND flash configuration (@pxref{nandconfiguration,,NAND Configuration})
1412 @item Target @code{reset} handlers for SDRAM and I/O configuration
1413 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1414 @item All things that are not ``inside a chip''
1417 Generic things inside target chips belong in target config files,
1418 not board config files. So for example a @code{reset-init} event
1419 handler should know board-specific oscillator and PLL parameters,
1420 which it passes to target-specific utility code.
1422 The most complex task of a board config file is creating such a
1423 @code{reset-init} event handler.
1424 Define those handlers last, after you verify the rest of the board
1425 configuration works.
1427 @subsection Communication Between Config files
1429 In addition to target-specific utility code, another way that
1430 board and target config files communicate is by following a
1431 convention on how to use certain variables.
1433 The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
1434 Thus the rule we follow in OpenOCD is this: Variables that begin with
1435 a leading underscore are temporary in nature, and can be modified and
1436 used at will within a target configuration file.
1438 Complex board config files can do the things like this,
1439 for a board with three chips:
1442 # Chip #1: PXA270 for network side, big endian
1443 set CHIPNAME network
1445 source [find target/pxa270.cfg]
1446 # on return: _TARGETNAME = network.cpu
1447 # other commands can refer to the "network.cpu" target.
1448 $_TARGETNAME configure .... events for this CPU..
1450 # Chip #2: PXA270 for video side, little endian
1453 source [find target/pxa270.cfg]
1454 # on return: _TARGETNAME = video.cpu
1455 # other commands can refer to the "video.cpu" target.
1456 $_TARGETNAME configure .... events for this CPU..
1458 # Chip #3: Xilinx FPGA for glue logic
1461 source [find target/spartan3.cfg]
1464 That example is oversimplified because it doesn't show any flash memory,
1465 or the @code{reset-init} event handlers to initialize external DRAM
1466 or (assuming it needs it) load a configuration into the FPGA.
1467 Such features are usually needed for low-level work with many boards,
1468 where ``low level'' implies that the board initialization software may
1469 not be working. (That's a common reason to need JTAG tools. Another
1470 is to enable working with microcontroller-based systems, which often
1471 have no debugging support except a JTAG connector.)
1473 Target config files may also export utility functions to board and user
1474 config files. Such functions should use name prefixes, to help avoid
1477 Board files could also accept input variables from user config files.
1478 For example, there might be a @code{J4_JUMPER} setting used to identify
1479 what kind of flash memory a development board is using, or how to set
1480 up other clocks and peripherals.
1482 @subsection Variable Naming Convention
1483 @cindex variable names
1485 Most boards have only one instance of a chip.
1486 However, it should be easy to create a board with more than
1487 one such chip (as shown above).
1488 Accordingly, we encourage these conventions for naming
1489 variables associated with different @file{target.cfg} files,
1490 to promote consistency and
1491 so that board files can override target defaults.
1493 Inputs to target config files include:
1496 @item @code{CHIPNAME} ...
1497 This gives a name to the overall chip, and is used as part of
1498 tap identifier dotted names.
1499 While the default is normally provided by the chip manufacturer,
1500 board files may need to distinguish between instances of a chip.
1501 @item @code{ENDIAN} ...
1502 By default @option{little} - although chips may hard-wire @option{big}.
1503 Chips that can't change endianness don't need to use this variable.
1504 @item @code{CPUTAPID} ...
1505 When OpenOCD examines the JTAG chain, it can be told verify the
1506 chips against the JTAG IDCODE register.
1507 The target file will hold one or more defaults, but sometimes the
1508 chip in a board will use a different ID (perhaps a newer revision).
1511 Outputs from target config files include:
1514 @item @code{_TARGETNAME} ...
1515 By convention, this variable is created by the target configuration
1516 script. The board configuration file may make use of this variable to
1517 configure things like a ``reset init'' script, or other things
1518 specific to that board and that target.
1519 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1520 @code{_TARGETNAME1}, ... etc.
1523 @subsection The reset-init Event Handler
1524 @cindex event, reset-init
1525 @cindex reset-init handler
1527 Board config files run in the OpenOCD configuration stage;
1528 they can't use TAPs or targets, since they haven't been
1530 This means you can't write memory or access chip registers;
1531 you can't even verify that a flash chip is present.
1532 That's done later in event handlers, of which the target @code{reset-init}
1533 handler is one of the most important.
1535 Except on microcontrollers, the basic job of @code{reset-init} event
1536 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1537 Microcontrollers rarely use boot loaders; they run right out of their
1538 on-chip flash and SRAM memory. But they may want to use one of these
1539 handlers too, if just for developer convenience.
1542 Because this is so very board-specific, and chip-specific, no examples
1544 Instead, look at the board config files distributed with OpenOCD.
1545 If you have a boot loader, its source code will help; so will
1546 configuration files for other JTAG tools
1547 (@pxref{translatingconfigurationfiles,,Translating Configuration Files}).
1550 Some of this code could probably be shared between different boards.
1551 For example, setting up a DRAM controller often doesn't differ by
1552 much except the bus width (16 bits or 32?) and memory timings, so a
1553 reusable TCL procedure loaded by the @file{target.cfg} file might take
1554 those as parameters.
1555 Similarly with oscillator, PLL, and clock setup;
1556 and disabling the watchdog.
1557 Structure the code cleanly, and provide comments to help
1558 the next developer doing such work.
1559 (@emph{You might be that next person} trying to reuse init code!)
1561 The last thing normally done in a @code{reset-init} handler is probing
1562 whatever flash memory was configured. For most chips that needs to be
1563 done while the associated target is halted, either because JTAG memory
1564 access uses the CPU or to prevent conflicting CPU access.
1566 @subsection JTAG Clock Rate
1568 Before your @code{reset-init} handler has set up
1569 the PLLs and clocking, you may need to run with
1570 a low JTAG clock rate.
1571 @xref{jtagspeed,,JTAG Speed}.
1572 Then you'd increase that rate after your handler has
1573 made it possible to use the faster JTAG clock.
1574 When the initial low speed is board-specific, for example
1575 because it depends on a board-specific oscillator speed, then
1576 you should probably set it up in the board config file;
1577 if it's target-specific, it belongs in the target config file.
1579 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1580 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1581 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1582 Consult chip documentation to determine the peak JTAG clock rate,
1583 which might be less than that.
1586 On most ARMs, JTAG clock detection is coupled to the core clock, so
1587 software using a @option{wait for interrupt} operation blocks JTAG access.
1588 Adaptive clocking provides a partial workaround, but a more complete
1589 solution just avoids using that instruction with JTAG debuggers.
1592 If both the chip and the board support adaptive clocking,
1593 use the @command{jtag_rclk}
1594 command, in case your board is used with JTAG adapter which
1595 also supports it. Otherwise use @command{adapter speed}.
1596 Set the slow rate at the beginning of the reset sequence,
1597 and the faster rate as soon as the clocks are at full speed.
1599 @anchor{theinitboardprocedure}
1600 @subsection The init_board procedure
1601 @cindex init_board procedure
1603 The concept of @code{init_board} procedure is very similar to @code{init_targets}
1604 (@xref{theinittargetsprocedure,,The init_targets procedure}.) - it's a replacement of ``linear''
1605 configuration scripts. This procedure is meant to be executed when OpenOCD enters run stage
1606 (@xref{enteringtherunstage,,Entering the Run Stage},) after @code{init_targets}. The idea to have
1607 separate @code{init_targets} and @code{init_board} procedures is to allow the first one to configure
1608 everything target specific (internal flash, internal RAM, etc.) and the second one to configure
1609 everything board specific (reset signals, chip frequency, reset-init event handler, external memory, etc.).
1610 Additionally ``linear'' board config file will most likely fail when target config file uses
1611 @code{init_targets} scheme (``linear'' script is executed before @code{init} and @code{init_targets} - after),
1612 so separating these two configuration stages is very convenient, as the easiest way to overcome this
1613 problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
1614 need to override @code{init_targets} defined in target config files when they only need to add some specifics.
1616 Just as @code{init_targets}, the @code{init_board} procedure can be overridden by ``next level'' script (which sources
1617 the original), allowing greater code reuse.
1620 ### board_file.cfg ###
1622 # source target file that does most of the config in init_targets
1623 source [find target/target.cfg]
1625 proc enable_fast_clock @{@} @{
1626 # enables fast on-board clock source
1627 # configures the chip to use it
1630 # initialize only board specifics - reset, clock, adapter frequency
1631 proc init_board @{@} @{
1632 reset_config trst_and_srst trst_pulls_srst
1634 $_TARGETNAME configure -event reset-start @{
1638 $_TARGETNAME configure -event reset-init @{
1645 @section Target Config Files
1646 @cindex config file, target
1647 @cindex target config file
1649 Board config files communicate with target config files using
1650 naming conventions as described above, and may source one or
1651 more target config files like this:
1654 source [find target/FOOBAR.cfg]
1657 The point of a target config file is to package everything
1658 about a given chip that board config files need to know.
1659 In summary the target files should contain
1663 @item Add TAPs to the scan chain
1664 @item Add CPU targets (includes GDB support)
1665 @item CPU/Chip/CPU-Core specific features
1669 As a rule of thumb, a target file sets up only one chip.
1670 For a microcontroller, that will often include a single TAP,
1671 which is a CPU needing a GDB target, and its on-chip flash.
1673 More complex chips may include multiple TAPs, and the target
1674 config file may need to define them all before OpenOCD
1675 can talk to the chip.
1676 For example, some phone chips have JTAG scan chains that include
1677 an ARM core for operating system use, a DSP,
1678 another ARM core embedded in an image processing engine,
1679 and other processing engines.
1681 @subsection Default Value Boiler Plate Code
1683 All target configuration files should start with code like this,
1684 letting board config files express environment-specific
1685 differences in how things should be set up.
1688 # Boards may override chip names, perhaps based on role,
1689 # but the default should match what the vendor uses
1690 if @{ [info exists CHIPNAME] @} @{
1691 set _CHIPNAME $CHIPNAME
1693 set _CHIPNAME sam7x256
1696 # ONLY use ENDIAN with targets that can change it.
1697 if @{ [info exists ENDIAN] @} @{
1703 # TAP identifiers may change as chips mature, for example with
1704 # new revision fields (the "3" here). Pick a good default; you
1705 # can pass several such identifiers to the "jtag newtap" command.
1706 if @{ [info exists CPUTAPID ] @} @{
1707 set _CPUTAPID $CPUTAPID
1709 set _CPUTAPID 0x3f0f0f0f
1712 @c but 0x3f0f0f0f is for an str73x part ...
1714 @emph{Remember:} Board config files may include multiple target
1715 config files, or the same target file multiple times
1716 (changing at least @code{CHIPNAME}).
1718 Likewise, the target configuration file should define
1719 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1720 use it later on when defining debug targets:
1723 set _TARGETNAME $_CHIPNAME.cpu
1724 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1727 @subsection Adding TAPs to the Scan Chain
1728 After the ``defaults'' are set up,
1729 add the TAPs on each chip to the JTAG scan chain.
1730 @xref{TAP Declaration}, and the naming convention
1733 In the simplest case the chip has only one TAP,
1734 probably for a CPU or FPGA.
1735 The config file for the Atmel AT91SAM7X256
1736 looks (in part) like this:
1739 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1742 A board with two such at91sam7 chips would be able
1743 to source such a config file twice, with different
1744 values for @code{CHIPNAME}, so
1745 it adds a different TAP each time.
1747 If there are nonzero @option{-expected-id} values,
1748 OpenOCD attempts to verify the actual tap id against those values.
1749 It will issue error messages if there is mismatch, which
1750 can help to pinpoint problems in OpenOCD configurations.
1753 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1754 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1755 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1756 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1757 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1760 There are more complex examples too, with chips that have
1761 multiple TAPs. Ones worth looking at include:
1764 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1765 plus a JRC to enable them
1766 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1767 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1768 is not currently used)
1771 @subsection Add CPU targets
1773 After adding a TAP for a CPU, you should set it up so that
1774 GDB and other commands can use it.
1775 @xref{CPU Configuration}.
1776 For the at91sam7 example above, the command can look like this;
1777 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1778 to little endian, and this chip doesn't support changing that.
1781 set _TARGETNAME $_CHIPNAME.cpu
1782 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1785 Work areas are small RAM areas associated with CPU targets.
1786 They are used by OpenOCD to speed up downloads,
1787 and to download small snippets of code to program flash chips.
1788 If the chip includes a form of ``on-chip-ram'' - and many do - define
1789 a work area if you can.
1790 Again using the at91sam7 as an example, this can look like:
1793 $_TARGETNAME configure -work-area-phys 0x00200000 \
1794 -work-area-size 0x4000 -work-area-backup 0
1797 @subsection Define CPU targets working in SMP
1799 After setting targets, you can define a list of targets working in SMP.
1802 set _TARGETNAME_1 $_CHIPNAME.cpu1
1803 set _TARGETNAME_2 $_CHIPNAME.cpu2
1804 target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap \
1805 -coreid 0 -dbgbase $_DAP_DBG1
1806 target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap \
1807 -coreid 1 -dbgbase $_DAP_DBG2
1808 #define 2 targets working in smp.
1809 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
1811 In the above example on cortex_a, 2 cpus are working in SMP.
1812 In SMP only one GDB instance is created and :
1814 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
1815 @item halt command triggers the halt of all targets in the list.
1816 @item resume command triggers the write context and the restart of all targets in the list.
1817 @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
1818 @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
1819 displayed by the GDB session @pxref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.
1822 The SMP behaviour can be disabled/enabled dynamically. On cortex_a following
1823 command have been implemented.
1825 @item cortex_a smp on : enable SMP mode, behaviour is as described above.
1826 @item cortex_a smp off : disable SMP mode, the current target is the one
1827 displayed in the GDB session, only this target is now controlled by GDB
1828 session. This behaviour is useful during system boot up.
1829 @item cortex_a smp : display current SMP mode.
1830 @item cortex_a smp_gdb : display/fix the core id displayed in GDB session see
1837 #0 : coreid 0 is displayed to GDB ,
1838 #-> -1 : next resume triggers a real resume
1839 > cortex_a smp_gdb 1
1841 #0 :coreid 0 is displayed to GDB ,
1842 #->1 : next resume displays coreid 1 to GDB
1846 #1 :coreid 1 is displayed to GDB ,
1847 #->1 : next resume displays coreid 1 to GDB
1848 > cortex_a smp_gdb -1
1850 #1 :coreid 1 is displayed to GDB,
1851 #->-1 : next resume triggers a real resume
1855 @subsection Chip Reset Setup
1857 As a rule, you should put the @command{reset_config} command
1858 into the board file. Most things you think you know about a
1859 chip can be tweaked by the board.
1861 Some chips have specific ways the TRST and SRST signals are
1862 managed. In the unusual case that these are @emph{chip specific}
1863 and can never be changed by board wiring, they could go here.
1864 For example, some chips can't support JTAG debugging without
1867 Provide a @code{reset-assert} event handler if you can.
1868 Such a handler uses JTAG operations to reset the target,
1869 letting this target config be used in systems which don't
1870 provide the optional SRST signal, or on systems where you
1871 don't want to reset all targets at once.
1872 Such a handler might write to chip registers to force a reset,
1873 use a JRC to do that (preferable -- the target may be wedged!),
1874 or force a watchdog timer to trigger.
1875 (For Cortex-M targets, this is not necessary. The target
1876 driver knows how to use trigger an NVIC reset when SRST is
1879 Some chips need special attention during reset handling if
1880 they're going to be used with JTAG.
1881 An example might be needing to send some commands right
1882 after the target's TAP has been reset, providing a
1883 @code{reset-deassert-post} event handler that writes a chip
1884 register to report that JTAG debugging is being done.
1885 Another would be reconfiguring the watchdog so that it stops
1886 counting while the core is halted in the debugger.
1888 JTAG clocking constraints often change during reset, and in
1889 some cases target config files (rather than board config files)
1890 are the right places to handle some of those issues.
1891 For example, immediately after reset most chips run using a
1892 slower clock than they will use later.
1893 That means that after reset (and potentially, as OpenOCD
1894 first starts up) they must use a slower JTAG clock rate
1895 than they will use later.
1896 @xref{jtagspeed,,JTAG Speed}.
1898 @quotation Important
1899 When you are debugging code that runs right after chip
1900 reset, getting these issues right is critical.
1901 In particular, if you see intermittent failures when
1902 OpenOCD verifies the scan chain after reset,
1903 look at how you are setting up JTAG clocking.
1906 @anchor{theinittargetsprocedure}
1907 @subsection The init_targets procedure
1908 @cindex init_targets procedure
1910 Target config files can either be ``linear'' (script executed line-by-line when parsed in
1911 configuration stage, @xref{configurationstage,,Configuration Stage},) or they can contain a special
1912 procedure called @code{init_targets}, which will be executed when entering run stage
1913 (after parsing all config files or after @code{init} command, @xref{enteringtherunstage,,Entering the Run Stage}.)
1914 Such procedure can be overridden by ``next level'' script (which sources the original).
1915 This concept facilitates code reuse when basic target config files provide generic configuration
1916 procedures and @code{init_targets} procedure, which can then be sourced and enhanced or changed in
1917 a ``more specific'' target config file. This is not possible with ``linear'' config scripts,
1918 because sourcing them executes every initialization commands they provide.
1921 ### generic_file.cfg ###
1923 proc setup_my_chip @{chip_name flash_size ram_size@} @{
1924 # basic initialization procedure ...
1927 proc init_targets @{@} @{
1928 # initializes generic chip with 4kB of flash and 1kB of RAM
1929 setup_my_chip MY_GENERIC_CHIP 4096 1024
1932 ### specific_file.cfg ###
1934 source [find target/generic_file.cfg]
1936 proc init_targets @{@} @{
1937 # initializes specific chip with 128kB of flash and 64kB of RAM
1938 setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
1942 The easiest way to convert ``linear'' config files to @code{init_targets} version is to
1943 enclose every line of ``code'' (i.e. not @code{source} commands, procedures, etc.) in this procedure.
1945 For an example of this scheme see LPC2000 target config files.
1947 The @code{init_boards} procedure is a similar concept concerning board config files
1948 (@xref{theinitboardprocedure,,The init_board procedure}.)
1950 @subsection The init_target_events procedure
1951 @cindex init_target_events procedure
1953 A special procedure called @code{init_target_events} is run just after
1954 @code{init_targets} (@xref{theinittargetsprocedure,,The init_targets
1955 procedure}.) and before @code{init_board}
1956 (@xref{theinitboardprocedure,,The init_board procedure}.) It is used
1957 to set up default target events for the targets that do not have those
1958 events already assigned.
1960 @subsection ARM Core Specific Hacks
1962 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1963 special high speed download features - enable it.
1965 If present, the MMU, the MPU and the CACHE should be disabled.
1967 Some ARM cores are equipped with trace support, which permits
1968 examination of the instruction and data bus activity. Trace
1969 activity is controlled through an ``Embedded Trace Module'' (ETM)
1970 on one of the core's scan chains. The ETM emits voluminous data
1971 through a ``trace port''. (@xref{armhardwaretracing,,ARM Hardware Tracing}.)
1972 If you are using an external trace port,
1973 configure it in your board config file.
1974 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
1975 configure it in your target config file.
1978 etm config $_TARGETNAME 16 normal full etb
1979 etb config $_TARGETNAME $_CHIPNAME.etb
1982 @subsection Internal Flash Configuration
1984 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1986 @b{Never ever} in the ``target configuration file'' define any type of
1987 flash that is external to the chip. (For example a BOOT flash on
1988 Chip Select 0.) Such flash information goes in a board file - not
1989 the TARGET (chip) file.
1993 @item at91sam7x256 - has 256K flash YES enable it.
1994 @item str912 - has flash internal YES enable it.
1995 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1996 @item pxa270 - again - CS0 flash - it goes in the board file.
1999 @anchor{translatingconfigurationfiles}
2000 @section Translating Configuration Files
2002 If you have a configuration file for another hardware debugger
2003 or toolset (Abatron, BDI2000, BDI3000, CCS,
2004 Lauterbach, SEGGER, Macraigor, etc.), translating
2005 it into OpenOCD syntax is often quite straightforward. The most tricky
2006 part of creating a configuration script is oftentimes the reset init
2007 sequence where e.g. PLLs, DRAM and the like is set up.
2009 One trick that you can use when translating is to write small
2010 Tcl procedures to translate the syntax into OpenOCD syntax. This
2011 can avoid manual translation errors and make it easier to
2012 convert other scripts later on.
2014 Example of transforming quirky arguments to a simple search and
2018 # Lauterbach syntax(?)
2020 # Data.Set c15:0x042f %long 0x40000015
2022 # OpenOCD syntax when using procedure below.
2024 # setc15 0x01 0x00050078
2026 proc setc15 @{regs value@} @{
2029 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
2031 arm mcr 15 [expr @{($regs >> 12) & 0x7@}] \
2032 [expr @{($regs >> 0) & 0xf@}] [expr @{($regs >> 4) & 0xf@}] \
2033 [expr @{($regs >> 8) & 0x7@}] $value
2039 @node Server Configuration
2040 @chapter Server Configuration
2041 @cindex initialization
2042 The commands here are commonly found in the openocd.cfg file and are
2043 used to specify what TCP/IP ports are used, and how GDB should be
2046 @anchor{configurationstage}
2047 @section Configuration Stage
2048 @cindex configuration stage
2049 @cindex config command
2051 When the OpenOCD server process starts up, it enters a
2052 @emph{configuration stage} which is the only time that
2053 certain commands, @emph{configuration commands}, may be issued.
2054 Normally, configuration commands are only available
2055 inside startup scripts.
2057 In this manual, the definition of a configuration command is
2058 presented as a @emph{Config Command}, not as a @emph{Command}
2059 which may be issued interactively.
2060 The runtime @command{help} command also highlights configuration
2061 commands, and those which may be issued at any time.
2063 Those configuration commands include declaration of TAPs,
2065 the interface used for JTAG communication,
2066 and other basic setup.
2067 The server must leave the configuration stage before it
2068 may access or activate TAPs.
2069 After it leaves this stage, configuration commands may no
2072 @deffn {Command} {command mode} [command_name]
2073 Returns the command modes allowed by a command: 'any', 'config', or
2074 'exec'. If no command is specified, returns the current command
2075 mode. Returns 'unknown' if an unknown command is given. Command can be
2076 multiple tokens. (command valid any time)
2078 In this document, the modes are described as stages, 'config' and
2079 'exec' mode correspond configuration stage and run stage. 'any' means
2080 the command can be executed in either
2081 stages. @xref{configurationstage,,Configuration Stage}, and
2082 @xref{enteringtherunstage,,Entering the Run Stage}.
2085 @anchor{enteringtherunstage}
2086 @section Entering the Run Stage
2088 The first thing OpenOCD does after leaving the configuration
2089 stage is to verify that it can talk to the scan chain
2090 (list of TAPs) which has been configured.
2091 It will warn if it doesn't find TAPs it expects to find,
2092 or finds TAPs that aren't supposed to be there.
2093 You should see no errors at this point.
2094 If you see errors, resolve them by correcting the
2095 commands you used to configure the server.
2096 Common errors include using an initial JTAG speed that's too
2097 fast, and not providing the right IDCODE values for the TAPs
2100 Once OpenOCD has entered the run stage, a number of commands
2102 A number of these relate to the debug targets you may have declared.
2103 For example, the @command{mww} command will not be available until
2104 a target has been successfully instantiated.
2105 If you want to use those commands, you may need to force
2106 entry to the run stage.
2108 @deffn {Config Command} {init}
2109 This command terminates the configuration stage and
2110 enters the run stage. This helps when you need to have
2111 the startup scripts manage tasks such as resetting the target,
2112 programming flash, etc. To reset the CPU upon startup, add "init" and
2113 "reset" at the end of the config script or at the end of the OpenOCD
2114 command line using the @option{-c} command line switch.
2116 If this command does not appear in any startup/configuration file
2117 OpenOCD executes the command for you after processing all
2118 configuration files and/or command line options.
2120 @b{NOTE:} This command normally occurs near the end of your
2121 openocd.cfg file to force OpenOCD to ``initialize'' and make the
2122 targets ready. For example: If your openocd.cfg file needs to
2123 read/write memory on your target, @command{init} must occur before
2124 the memory read/write commands. This includes @command{nand probe}.
2126 @command{init} calls the following internal OpenOCD commands to initialize
2127 corresponding subsystems:
2128 @deffn {Config Command} {target init}
2129 @deffnx {Command} {transport init}
2130 @deffnx {Command} {dap init}
2131 @deffnx {Config Command} {flash init}
2132 @deffnx {Config Command} {nand init}
2133 @deffnx {Config Command} {pld init}
2134 @deffnx {Command} {tpiu init}
2137 At last, @command{init} executes all the commands that are specified in
2138 the TCL list @var{post_init_commands}. The commands are executed in the
2139 same order they occupy in the list. If one of the commands fails, then
2140 the error is propagated and OpenOCD fails too.
2142 lappend post_init_commands @{echo "OpenOCD successfully initialized."@}
2143 lappend post_init_commands @{echo "Have fun with OpenOCD !"@}
2147 @deffn {Config Command} {noinit}
2148 Prevent OpenOCD from implicit @command{init} call at the end of startup.
2149 Allows issuing configuration commands over telnet or Tcl connection.
2150 When you are done with configuration use @command{init} to enter
2154 @deffn {Overridable Procedure} {jtag_init}
2155 This is invoked at server startup to verify that it can talk
2156 to the scan chain (list of TAPs) which has been configured.
2158 The default implementation first tries @command{jtag arp_init},
2159 which uses only a lightweight JTAG reset before examining the
2161 If that fails, it tries again, using a harder reset
2162 from the overridable procedure @command{init_reset}.
2164 Implementations must have verified the JTAG scan chain before
2166 This is done by calling @command{jtag arp_init}
2167 (or @command{jtag arp_init-reset}).
2171 @section TCP/IP Ports
2176 The OpenOCD server accepts remote commands in several syntaxes.
2177 Each syntax uses a different TCP/IP port, which you may specify
2178 only during configuration (before those ports are opened).
2180 For reasons including security, you may wish to prevent remote
2181 access using one or more of these ports.
2182 In such cases, just specify the relevant port number as "disabled".
2183 If you disable all access through TCP/IP, you will need to
2184 use the command line @option{-pipe} option.
2186 You can request the operating system to select one of the available
2187 ports for the server by specifying the relevant port number as "0".
2190 @deffn {Config Command} {gdb_port} [number]
2192 Normally gdb listens to a TCP/IP port, but GDB can also
2193 communicate via pipes(stdin/out or named pipes). The name
2194 "gdb_port" stuck because it covers probably more than 90% of
2195 the normal use cases.
2197 No arguments reports GDB port. "pipe" means listen to stdin
2198 output to stdout, an integer is base port number, "disabled"
2199 disables the gdb server.
2201 When using "pipe", also use log_output to redirect the log
2202 output to a file so as not to flood the stdin/out pipes.
2204 Any other string is interpreted as named pipe to listen to.
2205 Output pipe is the same name as input pipe, but with 'o' appended,
2206 e.g. /var/gdb, /var/gdbo.
2208 The GDB port for the first target will be the base port, the
2209 second target will listen on gdb_port + 1, and so on.
2210 When not specified during the configuration stage,
2211 the port @var{number} defaults to 3333.
2212 When @var{number} is not a numeric value, incrementing it to compute
2213 the next port number does not work. In this case, specify the proper
2214 @var{number} for each target by using the option @code{-gdb-port} of the
2215 commands @command{target create} or @command{$target_name configure}.
2216 @xref{gdbportoverride,,option -gdb-port}.
2218 Note: when using "gdb_port pipe", increasing the default remote timeout in
2219 gdb (with 'set remotetimeout') is recommended. An insufficient timeout may
2220 cause initialization to fail with "Unknown remote qXfer reply: OK".
2223 @deffn {Config Command} {tcl_port} [number]
2224 Specify or query the port used for a simplified RPC
2225 connection that can be used by clients to issue TCL commands and get the
2226 output from the Tcl engine.
2227 Intended as a machine interface.
2228 When not specified during the configuration stage,
2229 the port @var{number} defaults to 6666.
2230 When specified as "disabled", this service is not activated.
2233 @deffn {Config Command} {telnet_port} [number]
2234 Specify or query the
2235 port on which to listen for incoming telnet connections.
2236 This port is intended for interaction with one human through TCL commands.
2237 When not specified during the configuration stage,
2238 the port @var{number} defaults to 4444.
2239 When specified as "disabled", this service is not activated.
2242 @anchor{gdbconfiguration}
2243 @section GDB Configuration
2245 @cindex GDB configuration
2246 You can reconfigure some GDB behaviors if needed.
2247 The ones listed here are static and global.
2248 @xref{targetconfiguration,,Target Configuration}, about configuring individual targets.
2249 @xref{targetevents,,Target Events}, about configuring target-specific event handling.
2251 @anchor{gdbbreakpointoverride}
2252 @deffn {Command} {gdb_breakpoint_override} [@option{hard}|@option{soft}|@option{disable}]
2253 Force breakpoint type for gdb @command{break} commands.
2254 This option supports GDB GUIs which don't
2255 distinguish hard versus soft breakpoints, if the default OpenOCD and
2256 GDB behaviour is not sufficient. GDB normally uses hardware
2257 breakpoints if the memory map has been set up for flash regions.
2260 @anchor{gdbflashprogram}
2261 @deffn {Config Command} {gdb_flash_program} (@option{enable}|@option{disable})
2262 Set to @option{enable} to cause OpenOCD to program the flash memory when a
2263 vFlash packet is received.
2264 The default behaviour is @option{enable}.
2267 @deffn {Config Command} {gdb_memory_map} (@option{enable}|@option{disable})
2268 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
2269 requested. GDB will then know when to set hardware breakpoints, and program flash
2270 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
2271 for flash programming to work.
2272 Default behaviour is @option{enable}.
2273 @xref{gdbflashprogram,,gdb_flash_program}.
2276 @deffn {Config Command} {gdb_report_data_abort} (@option{enable}|@option{disable})
2277 Specifies whether data aborts cause an error to be reported
2278 by GDB memory read packets.
2279 The default behaviour is @option{disable};
2280 use @option{enable} see these errors reported.
2283 @deffn {Config Command} {gdb_report_register_access_error} (@option{enable}|@option{disable})
2284 Specifies whether register accesses requested by GDB register read/write
2285 packets report errors or not.
2286 The default behaviour is @option{disable};
2287 use @option{enable} see these errors reported.
2290 @deffn {Config Command} {gdb_target_description} (@option{enable}|@option{disable})
2291 Set to @option{enable} to cause OpenOCD to send the target descriptions to gdb via qXfer:features:read packet.
2292 The default behaviour is @option{enable}.
2295 @deffn {Command} {gdb_save_tdesc}
2296 Saves the target description file to the local file system.
2298 The file name is @i{target_name}.xml.
2301 @anchor{eventpolling}
2302 @section Event Polling
2304 Hardware debuggers are parts of asynchronous systems,
2305 where significant events can happen at any time.
2306 The OpenOCD server needs to detect some of these events,
2307 so it can report them to through TCL command line
2310 Examples of such events include:
2313 @item One of the targets can stop running ... maybe it triggers
2314 a code breakpoint or data watchpoint, or halts itself.
2315 @item Messages may be sent over ``debug message'' channels ... many
2316 targets support such messages sent over JTAG,
2317 for receipt by the person debugging or tools.
2318 @item Loss of power ... some adapters can detect these events.
2319 @item Resets not issued through JTAG ... such reset sources
2320 can include button presses or other system hardware, sometimes
2321 including the target itself (perhaps through a watchdog).
2322 @item Debug instrumentation sometimes supports event triggering
2323 such as ``trace buffer full'' (so it can quickly be emptied)
2324 or other signals (to correlate with code behavior).
2327 None of those events are signaled through standard JTAG signals.
2328 However, most conventions for JTAG connectors include voltage
2329 level and system reset (SRST) signal detection.
2330 Some connectors also include instrumentation signals, which
2331 can imply events when those signals are inputs.
2333 In general, OpenOCD needs to periodically check for those events,
2334 either by looking at the status of signals on the JTAG connector
2335 or by sending synchronous ``tell me your status'' JTAG requests
2336 to the various active targets.
2337 There is a command to manage and monitor that polling,
2338 which is normally done in the background.
2340 @deffn {Command} {poll} [@option{on}|@option{off}]
2341 Poll the current target for its current state.
2342 (Also, @pxref{targetcurstate,,target curstate}.)
2343 If that target is in debug mode, architecture
2344 specific information about the current state is printed.
2345 An optional parameter
2346 allows background polling to be enabled and disabled.
2348 You could use this from the TCL command shell, or
2349 from GDB using @command{monitor poll} command.
2350 Leave background polling enabled while you're using GDB.
2353 background polling: on
2354 target state: halted
2355 target halted in ARM state due to debug-request, \
2356 current mode: Supervisor
2357 cpsr: 0x800000d3 pc: 0x11081bfc
2358 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2363 @node Debug Adapter Configuration
2364 @chapter Debug Adapter Configuration
2365 @cindex config file, interface
2366 @cindex interface config file
2368 Correctly installing OpenOCD includes making your operating system give
2369 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2370 are used to select which one is used, and to configure how it is used.
2373 Because OpenOCD started out with a focus purely on JTAG, you may find
2374 places where it wrongly presumes JTAG is the only transport protocol
2375 in use. Be aware that recent versions of OpenOCD are removing that
2376 limitation. JTAG remains more functional than most other transports.
2377 Other transports do not support boundary scan operations, or may be
2378 specific to a given chip vendor. Some might be usable only for
2379 programming flash memory, instead of also for debugging.
2382 Debug Adapters/Interfaces/Dongles are normally configured
2383 through commands in an interface configuration
2384 file which is sourced by your @file{openocd.cfg} file, or
2385 through a command line @option{-f interface/....cfg} option.
2388 source [find interface/olimex-jtag-tiny.cfg]
2392 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2393 A few cases are so simple that you only need to say what driver to use:
2397 adapter driver jlink
2400 Most adapters need a bit more configuration than that.
2403 @section Adapter Configuration
2405 The @command{adapter driver} command tells OpenOCD what type of debug adapter you are
2406 using. Depending on the type of adapter, you may need to use one or
2407 more additional commands to further identify or configure the adapter.
2409 @deffn {Config Command} {adapter driver} name
2410 Use the adapter driver @var{name} to connect to the
2414 @deffn {Command} {adapter list}
2415 List the debug adapter drivers that have been built into
2416 the running copy of OpenOCD.
2418 @deffn {Config Command} {adapter transports} transport_name+
2419 Specifies the transports supported by this debug adapter.
2420 The adapter driver builds-in similar knowledge; use this only
2421 when external configuration (such as jumpering) changes what
2422 the hardware can support.
2425 @anchor{adapter gpio}
2426 @deffn {Config Command} {adapter gpio [ @
2427 @option{tdo} | @option{tdi} | @option{tms} | @option{tck} | @option{trst} | @
2428 @option{swdio} | @option{swdio_dir} | @option{swclk} | @option{srst} | @
2431 gpio_number | @option{-chip} chip_number | @
2432 @option{-active-high} | @option{-active-low} | @
2433 @option{-push-pull} | @option{-open-drain} | @option{-open-source} | @
2434 @option{-pull-none} | @option{-pull-up} | @option{-pull-down} | @
2435 @option{-init-inactive} | @option{-init-active} | @option{-init-input} @
2438 Define the GPIO mapping that the adapter will use. The following signals can be
2442 @item @option{tdo}, @option{tdi}, @option{tms}, @option{tck}, @option{trst}:
2443 JTAG transport signals
2444 @item @option{swdio}, @option{swclk}: SWD transport signals
2445 @item @option{swdio_dir}: optional swdio buffer control signal
2446 @item @option{srst}: system reset signal
2447 @item @option{led}: optional activity led
2451 Some adapters require that the GPIO chip number is set in addition to the GPIO
2452 number. The configuration options enable signals to be defined as active-high or
2453 active-low. The output drive mode can be set to push-pull, open-drain or
2454 open-source. Most adapters will have to emulate open-drain or open-source drive
2455 modes by switching between an input and output. Input and output signals can be
2456 instructed to use a pull-up or pull-down resistor, assuming it is supported by
2457 the adaptor driver and hardware. The initial state of outputs may also be set,
2458 "active" state means 1 for active-high outputs and 0 for active-low outputs.
2459 Bidirectional signals may also be initialized as an input. If the swdio signal
2460 is buffered the buffer direction can be controlled with the swdio_dir signal;
2461 the active state means that the buffer should be set as an output with respect
2462 to the adapter. The command options are cumulative with later commands able to
2463 override settings defined by earlier ones. The two commands @command{gpio led 7
2464 -active-high} and @command{gpio led -chip 1 -active-low} sent sequentially are
2465 equivalent to issuing the single command @command{gpio led 7 -chip 1
2466 -active-low}. It is not permissible to set the drive mode or initial state for
2467 signals which are inputs. The drive mode for the srst and trst signals must be
2468 set with the @command{adapter reset_config} command. It is not permissible to
2469 set the initial state of swdio_dir as it is derived from the initial state of
2470 swdio. The command @command{adapter gpio} prints the current configuration for
2471 all GPIOs while the command @command{adapter gpio gpio_name} prints the current
2472 configuration for gpio_name. Not all adapters support this generic GPIO mapping,
2473 some require their own commands to define the GPIOs used. Adapters that support
2474 the generic mapping may not support all of the listed options.
2477 @deffn {Command} {adapter name}
2478 Returns the name of the debug adapter driver being used.
2481 @deffn {Config Command} {adapter usb location} [<bus>-<port>[.<port>]...]
2482 Displays or specifies the physical USB port of the adapter to use. The path
2483 roots at @var{bus} and walks down the physical ports, with each
2484 @var{port} option specifying a deeper level in the bus topology, the last
2485 @var{port} denoting where the target adapter is actually plugged.
2486 The USB bus topology can be queried with the command @emph{lsusb -t} or @emph{dmesg}.
2488 This command is only available if your libusb1 is at least version 1.0.16.
2491 @deffn {Config Command} {adapter serial} serial_string
2492 Specifies the @var{serial_string} of the adapter to use.
2493 If this command is not specified, serial strings are not checked.
2494 Only the following adapter drivers use the serial string from this command:
2495 arm-jtag-ew, cmsis_dap, esp_usb_jtag, ft232r, ftdi, hla (stlink, ti-icdi), jlink, kitprog, opendus,
2496 openjtag, osbdm, presto, rlink, st-link, usb_blaster (ublast2), usbprog, vsllink, xds110.
2499 @section Interface Drivers
2501 Each of the interface drivers listed here must be explicitly
2502 enabled when OpenOCD is configured, in order to be made
2503 available at run time.
2505 @deffn {Interface Driver} {amt_jtagaccel}
2506 Amontec Chameleon in its JTAG Accelerator configuration,
2507 connected to a PC's EPP mode parallel port.
2508 This defines some driver-specific commands:
2510 @deffn {Config Command} {parport port} number
2511 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2512 the number of the @file{/dev/parport} device.
2515 @deffn {Config Command} {rtck} [@option{enable}|@option{disable}]
2516 Displays status of RTCK option.
2517 Optionally sets that option first.
2521 @deffn {Interface Driver} {angie}
2522 This is the NanoXplore's ANGIE USB-JTAG Adapter.
2525 @deffn {Interface Driver} {arm-jtag-ew}
2526 Olimex ARM-JTAG-EW USB adapter
2527 This has one driver-specific command:
2529 @deffn {Command} {armjtagew_info}
2534 @deffn {Interface Driver} {at91rm9200}
2535 Supports bitbanged JTAG from the local system,
2536 presuming that system is an Atmel AT91rm9200
2537 and a specific set of GPIOs is used.
2538 @c command: at91rm9200_device NAME
2539 @c chooses among list of bit configs ... only one option
2542 @deffn {Interface Driver} {cmsis-dap}
2543 ARM CMSIS-DAP compliant based adapter v1 (USB HID based)
2546 @deffn {Config Command} {cmsis-dap vid_pid} [vid pid]+
2547 The vendor ID and product ID of the CMSIS-DAP device. If not specified
2548 the driver will attempt to auto detect the CMSIS-DAP device.
2549 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2551 cmsis-dap vid_pid 0xc251 0xf001 0x0d28 0x0204
2555 @deffn {Config Command} {cmsis-dap backend} [@option{auto}|@option{usb_bulk}|@option{hid}]
2556 Specifies how to communicate with the adapter:
2559 @item @option{hid} Use HID generic reports - CMSIS-DAP v1
2560 @item @option{usb_bulk} Use USB bulk - CMSIS-DAP v2
2561 @item @option{auto} First try USB bulk CMSIS-DAP v2, if not found try HID CMSIS-DAP v1.
2562 This is the default if @command{cmsis-dap backend} is not specified.
2566 @deffn {Config Command} {cmsis-dap usb interface} [number]
2567 Specifies the @var{number} of the USB interface to use in v2 mode (USB bulk).
2568 In most cases need not to be specified and interfaces are searched by
2569 interface string or for user class interface.
2572 @deffn {Command} {cmsis-dap quirk} [@option{enable}|@option{disable}]
2573 Enables or disables the following workarounds of known CMSIS-DAP adapter
2576 @item disconnect and re-connect before sending a switch sequence
2577 @item packets pipelining is suppressed, only one packet at a time is
2578 submitted to the adapter
2580 The quirk workarounds are disabled by default.
2581 The command without a parameter displays current setting.
2584 @deffn {Command} {cmsis-dap info}
2585 Display various device information, like hardware version, firmware version, current bus status.
2588 @deffn {Command} {cmsis-dap cmd} number number ...
2589 Execute an arbitrary CMSIS-DAP command. Use for adapter testing or for handling
2590 of an adapter vendor specific command from a Tcl script.
2592 Take given numbers as bytes, assemble a CMSIS-DAP protocol command packet
2593 from them and send it to the adapter. The first 4 bytes of the adapter response
2595 See @url{https://arm-software.github.io/CMSIS_5/DAP/html/group__DAP__Commands__gr.html}
2599 @deffn {Interface Driver} {dummy}
2600 A dummy software-only driver for debugging.
2603 @deffn {Interface Driver} {ep93xx}
2604 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2607 @deffn {Interface Driver} {ftdi}
2608 This driver is for adapters using the MPSSE (Multi-Protocol Synchronous Serial
2609 Engine) mode built into many FTDI chips, such as the FT2232, FT4232 and FT232H.
2611 The driver is using libusb-1.0 in asynchronous mode to talk to the FTDI device,
2612 bypassing intermediate libraries like libftdi.
2614 Support for new FTDI based adapters can be added completely through
2615 configuration files, without the need to patch and rebuild OpenOCD.
2617 The driver uses a signal abstraction to enable Tcl configuration files to
2618 define outputs for one or several FTDI GPIO. These outputs can then be
2619 controlled using the @command{ftdi set_signal} command. Special signal names
2620 are reserved for nTRST, nSRST and LED (for blink) so that they, if defined,
2621 will be used for their customary purpose. Inputs can be read using the
2622 @command{ftdi get_signal} command.
2624 To support SWD, a signal named SWD_EN must be defined. It is set to 1 when the
2625 SWD protocol is selected. When set, the adapter should route the SWDIO pin to
2626 the data input. An SWDIO_OE signal, if defined, will be set to 1 or 0 as
2627 required by the protocol, to tell the adapter to drive the data output onto
2628 the SWDIO pin or keep the SWDIO pin Hi-Z, respectively.
2630 Depending on the type of buffer attached to the FTDI GPIO, the outputs have to
2631 be controlled differently. In order to support tristateable signals such as
2632 nSRST, both a data GPIO and an output-enable GPIO can be specified for each
2633 signal. The following output buffer configurations are supported:
2636 @item Push-pull with one FTDI output as (non-)inverted data line
2637 @item Open drain with one FTDI output as (non-)inverted output-enable
2638 @item Tristate with one FTDI output as (non-)inverted data line and another
2639 FTDI output as (non-)inverted output-enable
2640 @item Unbuffered, using the FTDI GPIO as a tristate output directly by
2641 switching data and direction as necessary
2644 These interfaces have several commands, used to configure the driver
2645 before initializing the JTAG scan chain:
2647 @deffn {Config Command} {ftdi vid_pid} [vid pid]+
2648 The vendor ID and product ID of the adapter. Up to eight
2649 [@var{vid}, @var{pid}] pairs may be given, e.g.
2651 ftdi vid_pid 0x0403 0xcff8 0x15ba 0x0003
2655 @deffn {Config Command} {ftdi device_desc} description
2656 Provides the USB device description (the @emph{iProduct string})
2657 of the adapter. If not specified, the device description is ignored
2658 during device selection.
2661 @deffn {Config Command} {ftdi channel} channel
2662 Selects the channel of the FTDI device to use for MPSSE operations. Most
2663 adapters use the default, channel 0, but there are exceptions.
2666 @deffn {Config Command} {ftdi layout_init} data direction
2667 Specifies the initial values of the FTDI GPIO data and direction registers.
2668 Each value is a 16-bit number corresponding to the concatenation of the high
2669 and low FTDI GPIO registers. The values should be selected based on the
2670 schematics of the adapter, such that all signals are set to safe levels with
2671 minimal impact on the target system. Avoid floating inputs, conflicting outputs
2672 and initially asserted reset signals.
2675 @deffn {Command} {ftdi layout_signal} name [@option{-data}|@option{-ndata} data_mask] [@option{-input}|@option{-ninput} input_mask] [@option{-oe}|@option{-noe} oe_mask] [@option{-alias}|@option{-nalias} name]
2676 Creates a signal with the specified @var{name}, controlled by one or more FTDI
2677 GPIO pins via a range of possible buffer connections. The masks are FTDI GPIO
2678 register bitmasks to tell the driver the connection and type of the output
2679 buffer driving the respective signal. @var{data_mask} is the bitmask for the
2680 pin(s) connected to the data input of the output buffer. @option{-ndata} is
2681 used with inverting data inputs and @option{-data} with non-inverting inputs.
2682 The @option{-oe} (or @option{-noe}) option tells where the output-enable (or
2683 not-output-enable) input to the output buffer is connected. The options
2684 @option{-input} and @option{-ninput} specify the bitmask for pins to be read
2685 with the method @command{ftdi get_signal}.
2687 Both @var{data_mask} and @var{oe_mask} need not be specified. For example, a
2688 simple open-collector transistor driver would be specified with @option{-oe}
2689 only. In that case the signal can only be set to drive low or to Hi-Z and the
2690 driver will complain if the signal is set to drive high. Which means that if
2691 it's a reset signal, @command{reset_config} must be specified as
2692 @option{srst_open_drain}, not @option{srst_push_pull}.
2694 A special case is provided when @option{-data} and @option{-oe} is set to the
2695 same bitmask. Then the FTDI pin is considered being connected straight to the
2696 target without any buffer. The FTDI pin is then switched between output and
2697 input as necessary to provide the full set of low, high and Hi-Z
2698 characteristics. In all other cases, the pins specified in a signal definition
2699 are always driven by the FTDI.
2701 If @option{-alias} or @option{-nalias} is used, the signal is created
2702 identical (or with data inverted) to an already specified signal
2706 @deffn {Command} {ftdi set_signal} name @option{0}|@option{1}|@option{z}
2707 Set a previously defined signal to the specified level.
2709 @item @option{0}, drive low
2710 @item @option{1}, drive high
2711 @item @option{z}, set to high-impedance
2715 @deffn {Command} {ftdi get_signal} name
2716 Get the value of a previously defined signal.
2719 @deffn {Command} {ftdi tdo_sample_edge} @option{rising}|@option{falling}
2720 Configure TCK edge at which the adapter samples the value of the TDO signal
2722 Due to signal propagation delays, sampling TDO on rising TCK can become quite
2723 peculiar at high JTAG clock speeds. However, FTDI chips offer a possibility to sample
2724 TDO on falling edge of TCK. With some board/adapter configurations, this may increase
2725 stability at higher JTAG clocks.
2727 @item @option{rising}, sample TDO on rising edge of TCK - this is the default
2728 @item @option{falling}, sample TDO on falling edge of TCK
2732 For example adapter definitions, see the configuration files shipped in the
2733 @file{interface/ftdi} directory.
2737 @deffn {Interface Driver} {ft232r}
2738 This driver is implementing synchronous bitbang mode of an FTDI FT232R,
2739 FT230X, FT231X and similar USB UART bridge ICs by reusing RS232 signals as GPIO.
2740 It currently doesn't support using CBUS pins as GPIO.
2742 List of connections (default physical pin numbers for FT232R in 28-pin SSOP package):
2749 @item DCD(10) - SRST
2752 User can change default pinout by supplying configuration
2753 commands with GPIO numbers or RS232 signal names.
2754 GPIO numbers correspond to bit numbers in FTDI GPIO register.
2755 They differ from physical pin numbers.
2756 For details see actual FTDI chip datasheets.
2757 Every JTAG line must be configured to unique GPIO number
2758 different than any other JTAG line, even those lines
2759 that are sometimes not used like TRST or SRST.
2773 These interfaces have several commands, used to configure the driver
2774 before initializing the JTAG scan chain:
2776 @deffn {Config Command} {ft232r vid_pid} @var{vid} @var{pid}
2777 The vendor ID and product ID of the adapter. If not specified, default
2778 0x0403:0x6001 is used.
2781 @deffn {Config Command} {ft232r jtag_nums} @var{tck} @var{tms} @var{tdi} @var{tdo}
2782 Set four JTAG GPIO numbers at once.
2783 If not specified, default 0 3 1 2 or TXD CTS RXD RTS is used.
2786 @deffn {Config Command} {ft232r tck_num} @var{tck}
2787 Set TCK GPIO number. If not specified, default 0 or TXD is used.
2790 @deffn {Config Command} {ft232r tms_num} @var{tms}
2791 Set TMS GPIO number. If not specified, default 3 or CTS is used.
2794 @deffn {Config Command} {ft232r tdi_num} @var{tdi}
2795 Set TDI GPIO number. If not specified, default 1 or RXD is used.
2798 @deffn {Config Command} {ft232r tdo_num} @var{tdo}
2799 Set TDO GPIO number. If not specified, default 2 or RTS is used.
2802 @deffn {Config Command} {ft232r trst_num} @var{trst}
2803 Set TRST GPIO number. If not specified, default 4 or DTR is used.
2806 @deffn {Config Command} {ft232r srst_num} @var{srst}
2807 Set SRST GPIO number. If not specified, default 6 or DCD is used.
2810 @deffn {Config Command} {ft232r restore_serial} @var{word}
2811 Restore serial port after JTAG. This USB bitmode control word
2812 (16-bit) will be sent before quit. Lower byte should
2813 set GPIO direction register to a "sane" state:
2814 0x15 for TXD RTS DTR as outputs (1), others as inputs (0). Higher
2815 byte is usually 0 to disable bitbang mode.
2816 When kernel driver reattaches, serial port should continue to work.
2817 Value 0xFFFF disables sending control word and serial port,
2818 then kernel driver will not reattach.
2819 If not specified, default 0xFFFF is used.
2824 @deffn {Interface Driver} {remote_bitbang}
2825 Drive JTAG and SWD from a remote process. This sets up a UNIX or TCP socket
2826 connection with a remote process and sends ASCII encoded bitbang requests to
2827 that process instead of directly driving JTAG and SWD.
2829 The remote_bitbang driver is useful for debugging software running on
2830 processors which are being simulated.
2832 @deffn {Config Command} {remote_bitbang port} number
2833 Specifies the TCP port of the remote process to connect to or 0 to use UNIX
2834 sockets instead of TCP.
2837 @deffn {Config Command} {remote_bitbang host} hostname
2838 Specifies the hostname of the remote process to connect to using TCP, or the
2839 name of the UNIX socket to use if remote_bitbang port is 0.
2842 @deffn {Config Command} {remote_bitbang use_remote_sleep} (on|off)
2843 If this option is enabled, delays will not be executed locally but instead
2844 forwarded to the remote host. This is useful if the remote host performs its
2845 own request queuing rather than executing requests immediately.
2847 This is disabled by default. This option must only be enabled if the given
2848 remote_bitbang host supports receiving the delay information.
2851 For example, to connect remotely via TCP to the host foobar you might have
2855 adapter driver remote_bitbang
2856 remote_bitbang port 3335
2857 remote_bitbang host foobar
2860 And if you also wished to enable remote sleeping:
2863 adapter driver remote_bitbang
2864 remote_bitbang port 3335
2865 remote_bitbang host foobar
2866 remote_bitbang use_remote_sleep on
2869 To connect to another process running locally via UNIX sockets with socket
2873 adapter driver remote_bitbang
2874 remote_bitbang port 0
2875 remote_bitbang host mysocket
2879 @deffn {Interface Driver} {usb_blaster}
2880 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2881 for FTDI chips. These interfaces have several commands, used to
2882 configure the driver before initializing the JTAG scan chain:
2884 @deffn {Config Command} {usb_blaster vid_pid} vid pid
2885 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2886 default values are used.
2887 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2888 Altera USB-Blaster (default):
2890 usb_blaster vid_pid 0x09FB 0x6001
2892 The following VID/PID is for Kolja Waschk's USB JTAG:
2894 usb_blaster vid_pid 0x16C0 0x06AD
2898 @deffn {Command} {usb_blaster pin} (@option{pin6}|@option{pin8}) (@option{0}|@option{1}|@option{s}|@option{t})
2899 Sets the state or function of the unused GPIO pins on USB-Blasters
2900 (pins 6 and 8 on the female JTAG header). These pins can be used as
2901 SRST and/or TRST provided the appropriate connections are made on the
2904 For example, to use pin 6 as SRST:
2906 usb_blaster pin pin6 s
2907 reset_config srst_only
2911 @deffn {Config Command} {usb_blaster lowlevel_driver} (@option{ftdi}|@option{ublast2})
2912 Chooses the low level access method for the adapter. If not specified,
2913 @option{ftdi} is selected unless it wasn't enabled during the
2914 configure stage. USB-Blaster II needs @option{ublast2}.
2917 @deffn {Config Command} {usb_blaster firmware} @var{path}
2918 This command specifies @var{path} to access USB-Blaster II firmware
2919 image. To be used with USB-Blaster II only.
2924 @deffn {Interface Driver} {gw16012}
2925 Gateworks GW16012 JTAG programmer.
2926 This has one driver-specific command:
2928 @deffn {Config Command} {parport port} [port_number]
2929 Display either the address of the I/O port
2930 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2931 If a parameter is provided, first switch to use that port.
2932 This is a write-once setting.
2936 @deffn {Interface Driver} {jlink}
2937 SEGGER J-Link family of USB adapters. It currently supports JTAG and SWD
2940 @quotation Compatibility Note
2941 SEGGER released many firmware versions for the many hardware versions they
2942 produced. OpenOCD was extensively tested and intended to run on all of them,
2943 but some combinations were reported as incompatible. As a general
2944 recommendation, it is advisable to use the latest firmware version
2945 available for each hardware version. However the current V8 is a moving
2946 target, and SEGGER firmware versions released after the OpenOCD was
2947 released may not be compatible. In such cases it is recommended to
2948 revert to the last known functional version. For 0.5.0, this is from
2949 "Feb 8 2012 14:30:39", packed with 4.42c. For 0.6.0, the last known
2950 version is from "May 3 2012 18:36:22", packed with 4.46f.
2953 @deffn {Command} {jlink hwstatus}
2954 Display various hardware related information, for example target voltage and pin
2957 @deffn {Command} {jlink freemem}
2958 Display free device internal memory.
2960 @deffn {Command} {jlink jtag} [@option{2}|@option{3}]
2961 Set the JTAG command version to be used. Without argument, show the actual JTAG
2964 @deffn {Command} {jlink config}
2965 Display the device configuration.
2967 @deffn {Command} {jlink config targetpower} [@option{on}|@option{off}]
2968 Set the target power state on JTAG-pin 19. Without argument, show the target
2971 @deffn {Command} {jlink config mac} [@option{ff:ff:ff:ff:ff:ff}]
2972 Set the MAC address of the device. Without argument, show the MAC address.
2974 @deffn {Command} {jlink config ip} [@option{A.B.C.D}(@option{/E}|@option{F.G.H.I})]
2975 Set the IP configuration of the device, where A.B.C.D is the IP address, E the
2976 bit of the subnet mask and F.G.H.I the subnet mask. Without arguments, show the
2979 @deffn {Command} {jlink config usb} [@option{0} to @option{3}]
2980 Set the USB address of the device. This will also change the USB Product ID
2981 (PID) of the device. Without argument, show the USB address.
2983 @deffn {Command} {jlink config reset}
2984 Reset the current configuration.
2986 @deffn {Command} {jlink config write}
2987 Write the current configuration to the internal persistent storage.
2989 @deffn {Command} {jlink emucom write} <channel> <data>
2990 Write data to an EMUCOM channel. The data needs to be encoded as hexadecimal
2993 The following example shows how to write the three bytes 0xaa, 0x0b and 0x23 to
2994 the EMUCOM channel 0x10:
2996 > jlink emucom write 0x10 aa0b23
2999 @deffn {Command} {jlink emucom read} <channel> <length>
3000 Read data from an EMUCOM channel. The read data is encoded as hexadecimal
3003 The following example shows how to read 4 bytes from the EMUCOM channel 0x0:
3005 > jlink emucom read 0x0 4
3009 @deffn {Config Command} {jlink usb} <@option{0} to @option{3}>
3010 Set the USB address of the interface, in case more than one adapter is connected
3011 to the host. If not specified, USB addresses are not considered. Device
3012 selection via USB address is not always unambiguous. It is recommended to use
3013 the serial number instead, if possible.
3015 As a configuration command, it can be used only before 'init'.
3019 @deffn {Interface Driver} {kitprog}
3020 This driver is for Cypress Semiconductor's KitProg adapters. The KitProg is an
3021 SWD-only adapter that is designed to be used with Cypress's PSoC and PRoC device
3022 families, but it is possible to use it with some other devices. If you are using
3023 this adapter with a PSoC or a PRoC, you may need to add
3024 @command{kitprog init_acquire_psoc} or @command{kitprog acquire_psoc} to your
3025 configuration script.
3027 Note that this driver is for the proprietary KitProg protocol, not the CMSIS-DAP
3028 mode introduced in firmware 2.14. If the KitProg is in CMSIS-DAP mode, it cannot
3029 be used with this driver, and must either be used with the cmsis-dap driver or
3030 switched back to KitProg mode. See the Cypress KitProg User Guide for
3031 instructions on how to switch KitProg modes.
3035 @item The frequency of SWCLK cannot be configured, and varies between 1.6 MHz
3037 @item For firmware versions below 2.14, "JTAG to SWD" sequences are replaced by
3038 "SWD line reset" in the driver. This is for two reasons. First, the KitProg does
3039 not support sending arbitrary SWD sequences, and only firmware 2.14 and later
3040 implement both "JTAG to SWD" and "SWD line reset" in firmware. Earlier firmware
3041 versions only implement "SWD line reset". Second, due to a firmware quirk, an
3042 SWD sequence must be sent after every target reset in order to re-establish
3043 communications with the target.
3044 @item Due in part to the limitation above, KitProg devices with firmware below
3045 version 2.14 will need to use @command{kitprog init_acquire_psoc} in order to
3046 communicate with PSoC 5LP devices. This is because, assuming debug is not
3047 disabled on the PSoC, the PSoC 5LP needs its JTAG interface switched to SWD
3048 mode before communication can begin, but prior to firmware 2.14, "JTAG to SWD"
3049 could only be sent with an acquisition sequence.
3052 @deffn {Config Command} {kitprog init_acquire_psoc}
3053 Indicate that a PSoC acquisition sequence needs to be run during adapter init.
3054 Please be aware that the acquisition sequence hard-resets the target.
3057 @deffn {Command} {kitprog acquire_psoc}
3058 Run a PSoC acquisition sequence immediately. Typically, this should not be used
3059 outside of the target-specific configuration scripts since it hard-resets the
3060 target as a side-effect.
3061 This is necessary for "reset halt" on some PSoC 4 series devices.
3064 @deffn {Command} {kitprog info}
3065 Display various adapter information, such as the hardware version, firmware
3066 version, and target voltage.
3070 @deffn {Interface Driver} {parport}
3071 Supports PC parallel port bit-banging cables:
3072 Wigglers, PLD download cable, and more.
3073 These interfaces have several commands, used to configure the driver
3074 before initializing the JTAG scan chain:
3076 @deffn {Config Command} {parport cable} name
3077 Set the layout of the parallel port cable used to connect to the target.
3078 This is a write-once setting.
3079 Currently valid cable @var{name} values include:
3082 @item @b{altium} Altium Universal JTAG cable.
3083 @item @b{arm-jtag} Same as original wiggler except SRST and
3084 TRST connections reversed and TRST is also inverted.
3085 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
3086 in configuration mode. This is only used to
3087 program the Chameleon itself, not a connected target.
3088 @item @b{dlc5} The Xilinx Parallel cable III.
3089 @item @b{flashlink} The ST Parallel cable.
3090 @item @b{lattice} Lattice ispDOWNLOAD Cable
3091 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
3093 Amontec's Chameleon Programmer. The new version available from
3094 the website uses the original Wiggler layout ('@var{wiggler}')
3095 @item @b{triton} The parallel port adapter found on the
3096 ``Karo Triton 1 Development Board''.
3097 This is also the layout used by the HollyGates design
3098 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
3099 @item @b{wiggler} The original Wiggler layout, also supported by
3100 several clones, such as the Olimex ARM-JTAG
3101 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
3102 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
3106 @deffn {Config Command} {parport port} [port_number]
3107 Display either the address of the I/O port
3108 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
3109 If a parameter is provided, first switch to use that port.
3110 This is a write-once setting.
3112 When using PPDEV to access the parallel port, use the number of the parallel port:
3113 @option{parport port 0} (the default). If @option{parport port 0x378} is specified
3114 you may encounter a problem.
3117 @deffn {Config Command} {parport toggling_time} [nanoseconds]
3118 Displays how many nanoseconds the hardware needs to toggle TCK;
3119 the parport driver uses this value to obey the
3120 @command{adapter speed} configuration.
3121 When the optional @var{nanoseconds} parameter is given,
3122 that setting is changed before displaying the current value.
3124 The default setting should work reasonably well on commodity PC hardware.
3125 However, you may want to calibrate for your specific hardware.
3127 To measure the toggling time with a logic analyzer or a digital storage
3128 oscilloscope, follow the procedure below:
3130 > parport toggling_time 1000
3133 This sets the maximum JTAG clock speed of the hardware, but
3134 the actual speed probably deviates from the requested 500 kHz.
3135 Now, measure the time between the two closest spaced TCK transitions.
3136 You can use @command{runtest 1000} or something similar to generate a
3137 large set of samples.
3138 Update the setting to match your measurement:
3140 > parport toggling_time <measured nanoseconds>
3142 Now the clock speed will be a better match for @command{adapter speed}
3143 command given in OpenOCD scripts and event handlers.
3145 You can do something similar with many digital multimeters, but note
3146 that you'll probably need to run the clock continuously for several
3147 seconds before it decides what clock rate to show. Adjust the
3148 toggling time up or down until the measured clock rate is a good
3149 match with the rate you specified in the @command{adapter speed} command;
3154 @deffn {Config Command} {parport write_on_exit} (@option{on}|@option{off})
3155 This will configure the parallel driver to write a known
3156 cable-specific value to the parallel interface on exiting OpenOCD.
3159 For example, the interface configuration file for a
3160 classic ``Wiggler'' cable on LPT2 might look something like this:
3163 adapter driver parport
3165 parport cable wiggler
3169 @deffn {Interface Driver} {presto}
3170 ASIX PRESTO USB JTAG programmer.
3173 @deffn {Interface Driver} {rlink}
3174 Raisonance RLink USB adapter
3177 @deffn {Interface Driver} {usbprog}
3178 usbprog is a freely programmable USB adapter.
3181 @deffn {Interface Driver} {vsllink}
3182 vsllink is part of Versaloon which is a versatile USB programmer.
3185 This defines quite a few driver-specific commands,
3186 which are not currently documented here.
3190 @anchor{hla_interface}
3191 @deffn {Interface Driver} {hla}
3192 This is a driver that supports multiple High Level Adapters.
3193 This type of adapter does not expose some of the lower level api's
3194 that OpenOCD would normally use to access the target.
3196 Currently supported adapters include the STMicroelectronics ST-LINK, TI ICDI
3197 and Nuvoton Nu-Link.
3198 ST-LINK firmware version >= V2.J21.S4 recommended due to issues with earlier
3199 versions of firmware where serial number is reset after first use. Suggest
3200 using ST firmware update utility to upgrade ST-LINK firmware even if current
3201 version reported is V2.J21.S4.
3203 @deffn {Config Command} {hla_device_desc} description
3204 Currently Not Supported.
3207 @deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi}|@option{nulink})
3208 Specifies the adapter layout to use.
3211 @deffn {Config Command} {hla_vid_pid} [vid pid]+
3212 Pairs of vendor IDs and product IDs of the device.
3215 @deffn {Config Command} {hla_stlink_backend} (usb | tcp [port])
3216 @emph{ST-Link only:} Choose between 'exclusive' USB communication (the default backend) or
3217 'shared' mode using ST-Link TCP server (the default port is 7184).
3219 @emph{Note:} ST-Link TCP server is a binary application provided by ST
3220 available from @url{https://www.st.com/en/development-tools/st-link-server.html,
3221 ST-LINK server software module}.
3224 @deffn {Command} {hla_command} command
3225 Execute a custom adapter-specific command. The @var{command} string is
3226 passed as is to the underlying adapter layout handler.
3230 @anchor{st_link_dap_interface}
3231 @deffn {Interface Driver} {st-link}
3232 This is a driver that supports STMicroelectronics adapters ST-LINK/V2
3233 (from firmware V2J24), STLINK-V3 and STLINK-V3PWR, thanks to a new API that provides
3234 directly access the arm ADIv5 DAP.
3236 The new API provide access to multiple AP on the same DAP, but the
3237 maximum number of the AP port is limited by the specific firmware version
3238 (e.g. firmware V2J29 has 3 as maximum AP number, while V2J32 has 8).
3239 An error is returned for any AP number above the maximum allowed value.
3241 @emph{Note:} Either these same adapters and their older versions are
3242 also supported by @ref{hla_interface, the hla interface driver}.
3244 @deffn {Config Command} {st-link backend} (usb | tcp [port])
3245 Choose between 'exclusive' USB communication (the default backend) or
3246 'shared' mode using ST-Link TCP server (the default port is 7184).
3248 @emph{Note:} ST-Link TCP server is a binary application provided by ST
3249 available from @url{https://www.st.com/en/development-tools/st-link-server.html,
3250 ST-LINK server software module}.
3252 @emph{Note:} ST-Link TCP server does not support the SWIM transport.
3255 @deffn {Config Command} {st-link vid_pid} [vid pid]+
3256 Pairs of vendor IDs and product IDs of the device.
3259 @deffn {Command} {st-link cmd} rx_n (tx_byte)+
3260 Sends an arbitrary command composed by the sequence of bytes @var{tx_byte}
3261 and receives @var{rx_n} bytes.
3263 For example, the command to read the target's supply voltage is one byte 0xf7 followed
3264 by 15 bytes zero. It returns 8 bytes, where the first 4 bytes represent the ADC sampling
3265 of the reference voltage 1.2V and the last 4 bytes represent the ADC sampling of half
3266 the target's supply voltage.
3268 > st-link cmd 8 0xf7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
3269 0xf1 0x05 0x00 0x00 0x0b 0x08 0x00 0x00
3271 The result can be converted to Volts (ignoring the most significant bytes, always zero)
3273 > set a [st-link cmd 8 0xf7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0]
3274 > set n [expr @{[lindex $a 4] + 256 * [lindex $a 5]@}]
3275 > set d [expr @{[lindex $a 0] + 256 * [lindex $a 1]@}]
3276 > echo [expr @{2 * 1.2 * $n / $d@}]
3282 @deffn {Interface Driver} {opendous}
3283 opendous-jtag is a freely programmable USB adapter.
3286 @deffn {Interface Driver} {ulink}
3287 This is the Keil ULINK v1 JTAG debugger.
3290 @deffn {Interface Driver} {xds110}
3291 The XDS110 is included as the embedded debug probe on many Texas Instruments
3292 LaunchPad evaluation boards. The XDS110 is also available as a stand-alone USB
3293 debug probe with the added capability to supply power to the target board. The
3294 following commands are supported by the XDS110 driver:
3296 @deffn {Config Command} {xds110 supply} voltage_in_millivolts
3297 Available only on the XDS110 stand-alone probe. Sets the voltage level of the
3298 XDS110 power supply. A value of 0 leaves the supply off. Otherwise, the supply
3299 can be set to any value in the range 1800 to 3600 millivolts.
3302 @deffn {Command} {xds110 info}
3303 Displays information about the connected XDS110 debug probe (e.g. firmware
3308 @deffn {Interface Driver} {xlnx_pcie_xvc}
3309 This driver supports the Xilinx Virtual Cable (XVC) over PCI Express.
3310 It is commonly found in Xilinx based PCI Express designs. It allows debugging
3311 fabric based JTAG/SWD devices such as Cortex-M1/M3 microcontrollers. Access to this is
3312 exposed via extended capability registers in the PCI Express configuration space.
3314 For more information see Xilinx PG245 (Section on From_PCIE_to_JTAG mode).
3316 @deffn {Config Command} {xlnx_pcie_xvc config} device
3317 Specifies the PCI Express device via parameter @var{device} to use.
3319 The correct value for @var{device} can be obtained by looking at the output
3320 of lscpi -D (first column) for the corresponding device.
3322 The string will be of the format "DDDD:BB:SS.F" such as "0000:65:00.1".
3327 @deffn {Interface Driver} {bcm2835gpio}
3328 This SoC is present in Raspberry Pi which is a cheap single-board computer
3329 exposing some GPIOs on its expansion header.
3331 The driver accesses memory-mapped GPIO peripheral registers directly
3332 for maximum performance, but the only possible race condition is for
3333 the pins' modes/muxing (which is highly unlikely), so it should be
3334 able to coexist nicely with both sysfs bitbanging and various
3335 peripherals' kernel drivers. The driver restores the previous
3336 configuration on exit.
3338 GPIO numbers >= 32 can't be used for performance reasons. GPIO configuration is
3339 handled by the generic command @ref{adapter gpio, @command{adapter gpio}}.
3341 See @file{interface/raspberrypi-native.cfg} for a sample config and
3342 @file{interface/raspberrypi-gpio-connector.cfg} for pinout.
3344 @deffn {Config Command} {bcm2835gpio speed_coeffs} @var{speed_coeff} @var{speed_offset}
3345 Set SPEED_COEFF and SPEED_OFFSET for delay calculations. If unspecified,
3346 speed_coeff defaults to 113714, and speed_offset defaults to 28.
3349 @deffn {Config Command} {bcm2835gpio peripheral_mem_dev} @var{device}
3350 Set the device path for access to the memory mapped GPIO control registers.
3351 Uses @file{/dev/gpiomem} by default, this is also the preferred option with
3352 respect to system security.
3353 If overridden to @file{/dev/mem}:
3355 @item OpenOCD needs @code{cap_sys_rawio} or run as root to open @file{/dev/mem}.
3356 Please be aware of security issues imposed by running OpenOCD with
3357 elevated user rights and by @file{/dev/mem} itself.
3358 @item correct @command{peripheral_base} must be configured.
3359 @item GPIO 0-27 pads are set to the limited slew rate
3360 and drive strength is reduced to 4 mA (2 mA on RPi 4).
3365 @deffn {Config Command} {bcm2835gpio peripheral_base} @var{base}
3366 Set the peripheral base register address to access GPIOs.
3367 Ignored if @file{/dev/gpiomem} is used. For the RPi1, use
3368 0x20000000. For RPi2 and RPi3, use 0x3F000000. For RPi4, use 0xFE000000. A full
3369 list can be found in the
3370 @uref{https://www.raspberrypi.org/documentation/hardware/raspberrypi/peripheral_addresses.md, official guide}.
3375 @deffn {Interface Driver} {imx_gpio}
3376 i.MX SoC is present in many community boards. Wandboard is an example
3377 of the one which is most popular.
3379 This driver is mostly the same as bcm2835gpio.
3381 See @file{interface/imx-native.cfg} for a sample config and
3387 @deffn {Interface Driver} {am335xgpio} The AM335x SoC is present in BeagleBone
3388 Black and BeagleBone Green single-board computers which expose some of the GPIOs
3389 on the two expansion headers.
3391 For maximum performance the driver accesses memory-mapped GPIO peripheral
3392 registers directly. The memory mapping requires read and write permission to
3393 kernel memory; if /dev/gpiomem exists it will be used, otherwise /dev/mem will
3394 be used. The driver restores the GPIO state on exit.
3396 All four GPIO ports are available. GPIO configuration is handled by the generic
3397 command @ref{adapter gpio, @command{adapter gpio}}.
3399 @deffn {Config Command} {am335xgpio speed_coeffs} @var{speed_coeff} @var{speed_offset}
3400 Set SPEED_COEFF and SPEED_OFFSET for delay calculations. If unspecified
3401 speed_coeff defaults to 600000 and speed_offset defaults to 575.
3404 See @file{interface/beaglebone-swd-native.cfg} for a sample configuration file.
3409 @deffn {Interface Driver} {linuxgpiod}
3410 Linux provides userspace access to GPIO through libgpiod since Linux kernel
3411 version v4.6. The driver emulates either JTAG or SWD transport through
3412 bitbanging. There are no driver-specific commands, all GPIO configuration is
3413 handled by the generic command @ref{adapter gpio, @command{adapter gpio}}. This
3414 driver supports the resistor pull options provided by the @command{adapter gpio}
3415 command but the underlying hardware may not be able to support them.
3417 See @file{interface/dln-2-gpiod.cfg} for a sample configuration file.
3421 @deffn {Interface Driver} {sysfsgpio}
3422 Linux legacy userspace access to GPIO through sysfs is deprecated from Linux kernel version v5.3.
3423 Prefer using @b{linuxgpiod}, instead.
3425 See @file{interface/sysfsgpio-raspberrypi.cfg} for a sample config.
3429 @deffn {Interface Driver} {openjtag}
3430 OpenJTAG compatible USB adapter.
3431 This defines some driver-specific commands:
3433 @deffn {Config Command} {openjtag variant} variant
3434 Specifies the variant of the OpenJTAG adapter (see @uref{http://www.openjtag.org/}).
3435 Currently valid @var{variant} values include:
3438 @item @b{standard} Standard variant (default).
3439 @item @b{cy7c65215} Cypress CY7C65215 Dual Channel USB-Serial Bridge Controller
3440 (see @uref{http://www.cypress.com/?rID=82870}).
3444 @deffn {Config Command} {openjtag device_desc} string
3445 The USB device description string of the adapter.
3446 This value is only used with the standard variant.
3449 @deffn {Config Command} {openjtag vid_pid} vid pid
3450 The USB vendor ID and product ID of the adapter. If not specified, default
3451 0x0403:0x6001 is used.
3452 This value is only used with the standard variant.
3454 openjtag vid_pid 0x403 0x6014
3460 @deffn {Interface Driver} {vdebug}
3461 Cadence Virtual Debug Interface driver.
3463 @deffn {Config Command} {vdebug server} host:port
3464 Specifies the host and TCP port number where the vdebug server runs.
3467 @deffn {Config Command} {vdebug batching} value
3468 Specifies the batching method for the vdebug request. Possible values are
3470 1 or wr to batch write transactions together (default)
3471 2 or rw to batch both read and write transactions
3474 @deffn {Config Command} {vdebug polling} min max
3475 Takes two values, representing the polling interval in ms. Lower values mean faster
3476 debugger responsiveness, but lower emulation performance. The minimum should be
3477 around 10, maximum should not exceed 1000, which is the default gdb and keepalive
3481 @deffn {Config Command} {vdebug bfm_path} path clk_period
3482 Specifies the hierarchical path and input clk period of the vdebug BFM in the design.
3483 The hierarchical path uses Verilog notation top.inst.inst
3484 The clock period must include the unit, for instance 40ns.
3487 @deffn {Config Command} {vdebug mem_path} path base size
3488 Specifies the hierarchical path to the design memory instance for backdoor access.
3489 Up to 4 memories can be specified. The hierarchical path uses Verilog notation.
3490 The base specifies start address in the design address space, size its size in bytes.
3491 Both values can use hexadecimal notation with prefix 0x.
3495 @deffn {Interface Driver} {jtag_dpi}
3496 SystemVerilog Direct Programming Interface (DPI) compatible driver for
3497 JTAG devices in emulation. The driver acts as a client for the SystemVerilog
3498 DPI server interface.
3500 @deffn {Config Command} {jtag_dpi set_port} port
3501 Specifies the TCP/IP port number of the SystemVerilog DPI server interface.
3504 @deffn {Config Command} {jtag_dpi set_address} address
3505 Specifies the TCP/IP address of the SystemVerilog DPI server interface.
3510 @deffn {Interface Driver} {buspirate}
3512 This driver is for the Bus Pirate (see @url{http://dangerousprototypes.com/docs/Bus_Pirate}) and compatible devices.
3513 It uses a simple data protocol over a serial port connection.
3515 Most hardware development boards have a UART, a real serial port, or a virtual USB serial device, so this driver
3516 allows you to start building your own JTAG adapter without the complexity of a custom USB connection.
3518 @deffn {Config Command} {buspirate port} serial_port
3519 Specify the serial port's filename. For example:
3521 buspirate port /dev/ttyUSB0
3525 @deffn {Config Command} {buspirate speed} (normal|fast)
3526 Set the communication speed to 115k (normal) or 1M (fast). For example:
3528 buspirate speed normal
3532 @deffn {Config Command} {buspirate mode} (normal|open-drain)
3533 Set the Bus Pirate output mode.
3535 @item In normal mode (push/pull), do not enable the pull-ups, and do not connect I/O header pin VPU to JTAG VREF.
3536 @item In open drain mode, you will then need to enable the pull-ups.
3540 buspirate mode normal
3544 @deffn {Config Command} {buspirate pullup} (0|1)
3545 Whether to connect (1) or not (0) the I/O header pin VPU (JTAG VREF)
3546 to the pull-up/pull-down resistors on MOSI (JTAG TDI), CLK (JTAG TCK), MISO (JTAG TDO) and CS (JTAG TMS).
3553 @deffn {Config Command} {buspirate vreg} (0|1)
3554 Whether to enable (1) or disable (0) the built-in voltage regulator,
3555 which can be used to supply power to a test circuit through
3556 I/O header pins +3V3 and +5V. For example:
3562 @deffn {Command} {buspirate led} (0|1)
3563 Turns the Bus Pirate's LED on (1) or off (0). For example:
3571 @deffn {Interface Driver} {esp_usb_jtag}
3572 Espressif JTAG driver to communicate with ESP32-C3, ESP32-S3 chips and ESP USB Bridge board using OpenOCD.
3573 These chips have built-in JTAG circuitry and can be debugged without any additional hardware.
3574 Only an USB cable connected to the D+/D- pins is necessary.
3576 @deffn {Command} {espusbjtag tdo}
3577 Returns the current state of the TDO line
3580 @deffn {Command} {espusbjtag setio} setio
3581 Manually set the status of the output lines with the order of (tdi tms tck trst srst)
3583 espusbjtag setio 0 1 0 1 0
3587 @deffn {Config Command} {espusbjtag vid_pid} vid_pid
3588 Set vendor ID and product ID for the ESP usb jtag driver
3590 espusbjtag vid_pid 0x303a 0x1001
3594 @deffn {Config Command} {espusbjtag caps_descriptor} caps_descriptor
3595 Set the jtag descriptor to read capabilities of ESP usb jtag driver
3597 espusbjtag caps_descriptor 0x2000
3601 @deffn {Config Command} {espusbjtag chip_id} chip_id
3602 Set chip id to transfer to the ESP USB bridge board
3604 espusbjtag chip_id 1
3610 @deffn {Interface Driver} {dmem} Direct Memory access debug interface
3612 The Texas Instruments K3 SoC family provides memory access to DAP
3613 and coresight control registers. This allows control over the
3614 microcontrollers directly from one of the processors on the SOC
3617 For maximum performance, the driver accesses the debug registers
3618 directly over the SoC memory map. The memory mapping requires read
3619 and write permission to kernel memory via "/dev/mem" and assumes that
3620 the system firewall configurations permit direct access to the debug
3625 | OpenOCD | SoC mem map (/dev/mem)
3626 | on +--------------+
3630 +-----------+ +-----v-----+
3631 |Cortex-M4F <--------+ |
3635 |Cortex-M4F <--------+ |
3636 +-----------+ +-----------+
3639 NOTE: Firewalls are configurable in K3 SoC and depending on various types of
3640 device configuration, this function may be blocked out. Typical behavior
3641 observed in such cases is a firewall exception report on the security
3642 controller and armv8 processor reporting a system error.
3644 See @file{tcl/interface/ti_k3_am625-swd-native.cfg} for a sample configuration
3647 @deffn {Command} {dmem info}
3648 Print the DAPBUS dmem configuration.
3651 @deffn {Config Command} {dmem device} device_path
3652 Set the DAPBUS memory access device (default: /dev/mem).
3655 @deffn {Config Command} {dmem base_address} base_address
3656 Set the DAPBUS base address which is used to access CoreSight
3657 compliant Access Ports (APs) directly.
3660 @deffn {Config Command} {dmem ap_address_offset} offset_address
3661 Set the address offset between Access Ports (APs).
3664 @deffn {Config Command} {dmem max_aps} n
3665 Set the maximum number of valid access ports on the SoC.
3668 @deffn {Config Command} {dmem emu_ap_list} n
3669 Set the list of Access Ports (APs) that need to be emulated. This
3670 emulation mode supports software translation of an AP request into an
3671 address mapped transaction that does not rely on physical AP hardware.
3672 This maybe needed if the AP is either denied access via memory map or
3673 protected using other SoC mechanisms.
3676 @deffn {Config Command} {dmem emu_base_address_range} base_address address_window_size
3677 Set the emulated address and address window size. Both of these
3678 parameters must be aligned to page size.
3683 @section Transport Configuration
3685 As noted earlier, depending on the version of OpenOCD you use,
3686 and the debug adapter you are using,
3687 several transports may be available to
3688 communicate with debug targets (or perhaps to program flash memory).
3689 @deffn {Command} {transport list}
3690 displays the names of the transports supported by this
3694 @deffn {Command} {transport select} @option{transport_name}
3695 Select which of the supported transports to use in this OpenOCD session.
3697 When invoked with @option{transport_name}, attempts to select the named
3698 transport. The transport must be supported by the debug adapter
3699 hardware and by the version of OpenOCD you are using (including the
3702 If no transport has been selected and no @option{transport_name} is
3703 provided, @command{transport select} auto-selects the first transport
3704 supported by the debug adapter.
3706 @command{transport select} always returns the name of the session's selected
3710 @subsection JTAG Transport
3712 JTAG is the original transport supported by OpenOCD, and most
3713 of the OpenOCD commands support it.
3714 JTAG transports expose a chain of one or more Test Access Points (TAPs),
3715 each of which must be explicitly declared.
3716 JTAG supports both debugging and boundary scan testing.
3717 Flash programming support is built on top of debug support.
3719 JTAG transport is selected with the command @command{transport select
3720 jtag}. Unless your adapter uses either @ref{hla_interface,the hla interface
3721 driver} (in which case the command is @command{transport select hla_jtag})
3722 or @ref{st_link_dap_interface,the st-link interface driver} (in which case
3723 the command is @command{transport select dapdirect_jtag}).
3725 @subsection SWD Transport
3727 @cindex Serial Wire Debug
3728 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
3729 Debug Access Point (DAP, which must be explicitly declared.
3730 (SWD uses fewer signal wires than JTAG.)
3731 SWD is debug-oriented, and does not support boundary scan testing.
3732 Flash programming support is built on top of debug support.
3733 (Some processors support both JTAG and SWD.)
3735 SWD transport is selected with the command @command{transport select
3736 swd}. Unless your adapter uses either @ref{hla_interface,the hla interface
3737 driver} (in which case the command is @command{transport select hla_swd})
3738 or @ref{st_link_dap_interface,the st-link interface driver} (in which case
3739 the command is @command{transport select dapdirect_swd}).
3741 @deffn {Config Command} {swd newdap} ...
3742 Declares a single DAP which uses SWD transport.
3743 Parameters are currently the same as "jtag newtap" but this is
3747 @cindex SWD multi-drop
3748 The newer SWD devices (SW-DP v2 or SWJ-DP v2) support the multi-drop extension
3749 of SWD protocol: two or more devices can be connected to one SWD adapter.
3750 SWD transport works in multi-drop mode if @ref{dap_create,DAP} is configured
3751 with both @code{-dp-id} and @code{-instance-id} parameters regardless how many
3754 Not all adapters and adapter drivers support SWD multi-drop. Only the following
3755 adapter drivers are SWD multi-drop capable:
3756 cmsis_dap (use an adapter with CMSIS-DAP version 2.0), ftdi, all bitbang based.
3758 @subsection SPI Transport
3760 @cindex Serial Peripheral Interface
3761 The Serial Peripheral Interface (SPI) is a general purpose transport
3762 which uses four wire signaling. Some processors use it as part of a
3763 solution for flash programming.
3765 @anchor{swimtransport}
3766 @subsection SWIM Transport
3768 @cindex Single Wire Interface Module
3769 The Single Wire Interface Module (SWIM) is a low-pin-count debug protocol used
3770 by the STMicroelectronics MCU family STM8 and documented in the
3771 @uref{https://www.st.com/resource/en/user_manual/cd00173911.pdf, User Manual UM470}.
3773 SWIM does not support boundary scan testing nor multiple cores.
3775 The SWIM transport is selected with the command @command{transport select swim}.
3777 The concept of TAPs does not fit in the protocol since SWIM does not implement
3778 a scan chain. Nevertheless, the current SW model of OpenOCD requires defining a
3779 virtual SWIM TAP through the command @command{swim newtap basename tap_type}.
3780 The TAP definition must precede the target definition command
3781 @command{target create target_name stm8 -chain-position basename.tap_type}.
3785 JTAG clock setup is part of system setup.
3786 It @emph{does not belong with interface setup} since any interface
3787 only knows a few of the constraints for the JTAG clock speed.
3788 Sometimes the JTAG speed is
3789 changed during the target initialization process: (1) slow at
3790 reset, (2) program the CPU clocks, (3) run fast.
3791 Both the "slow" and "fast" clock rates are functions of the
3792 oscillators used, the chip, the board design, and sometimes
3793 power management software that may be active.
3795 The speed used during reset, and the scan chain verification which
3796 follows reset, can be adjusted using a @code{reset-start}
3797 target event handler.
3798 It can then be reconfigured to a faster speed by a
3799 @code{reset-init} target event handler after it reprograms those
3800 CPU clocks, or manually (if something else, such as a boot loader,
3801 sets up those clocks).
3802 @xref{targetevents,,Target Events}.
3803 When the initial low JTAG speed is a chip characteristic, perhaps
3804 because of a required oscillator speed, provide such a handler
3805 in the target config file.
3806 When that speed is a function of a board-specific characteristic
3807 such as which speed oscillator is used, it belongs in the board
3808 config file instead.
3809 In both cases it's safest to also set the initial JTAG clock rate
3810 to that same slow speed, so that OpenOCD never starts up using a
3811 clock speed that's faster than the scan chain can support.
3815 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
3818 If your system supports adaptive clocking (RTCK), configuring
3819 JTAG to use that is probably the most robust approach.
3820 However, it introduces delays to synchronize clocks; so it
3821 may not be the fastest solution.
3823 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
3824 instead of @command{adapter speed}, but only for (ARM) cores and boards
3825 which support adaptive clocking.
3827 @deffn {Command} {adapter speed} max_speed_kHz
3828 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
3829 JTAG interfaces usually support a limited number of
3830 speeds. The speed actually used won't be faster
3831 than the speed specified.
3833 Chip data sheets generally include a top JTAG clock rate.
3834 The actual rate is often a function of a CPU core clock,
3835 and is normally less than that peak rate.
3836 For example, most ARM cores accept at most one sixth of the CPU clock.
3838 Speed 0 (khz) selects RTCK method.
3839 @xref{faqrtck,,FAQ RTCK}.
3840 If your system uses RTCK, you won't need to change the
3841 JTAG clocking after setup.
3842 Not all interfaces, boards, or targets support ``rtck''.
3843 If the interface device can not
3844 support it, an error is returned when you try to use RTCK.
3847 @defun jtag_rclk fallback_speed_kHz
3848 @cindex adaptive clocking
3850 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
3851 If that fails (maybe the interface, board, or target doesn't
3852 support it), falls back to the specified frequency.
3854 # Fall back to 3mhz if RTCK is not supported
3859 @node Reset Configuration
3860 @chapter Reset Configuration
3861 @cindex Reset Configuration
3863 Every system configuration may require a different reset
3864 configuration. This can also be quite confusing.
3865 Resets also interact with @var{reset-init} event handlers,
3866 which do things like setting up clocks and DRAM, and
3867 JTAG clock rates. (@xref{jtagspeed,,JTAG Speed}.)
3868 They can also interact with JTAG routers.
3869 Please see the various board files for examples.
3872 To maintainers and integrators:
3873 Reset configuration touches several things at once.
3874 Normally the board configuration file
3875 should define it and assume that the JTAG adapter supports
3876 everything that's wired up to the board's JTAG connector.
3878 However, the target configuration file could also make note
3879 of something the silicon vendor has done inside the chip,
3880 which will be true for most (or all) boards using that chip.
3881 And when the JTAG adapter doesn't support everything, the
3882 user configuration file will need to override parts of
3883 the reset configuration provided by other files.
3886 @section Types of Reset
3888 There are many kinds of reset possible through JTAG, but
3889 they may not all work with a given board and adapter.
3890 That's part of why reset configuration can be error prone.
3894 @emph{System Reset} ... the @emph{SRST} hardware signal
3895 resets all chips connected to the JTAG adapter, such as processors,
3896 power management chips, and I/O controllers. Normally resets triggered
3897 with this signal behave exactly like pressing a RESET button.
3899 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
3900 just the TAP controllers connected to the JTAG adapter.
3901 Such resets should not be visible to the rest of the system; resetting a
3902 device's TAP controller just puts that controller into a known state.
3904 @emph{Emulation Reset} ... many devices can be reset through JTAG
3905 commands. These resets are often distinguishable from system
3906 resets, either explicitly (a "reset reason" register says so)
3907 or implicitly (not all parts of the chip get reset).
3909 @emph{Other Resets} ... system-on-chip devices often support
3910 several other types of reset.
3911 You may need to arrange that a watchdog timer stops
3912 while debugging, preventing a watchdog reset.
3913 There may be individual module resets.
3916 In the best case, OpenOCD can hold SRST, then reset
3917 the TAPs via TRST and send commands through JTAG to halt the
3918 CPU at the reset vector before the 1st instruction is executed.
3919 Then when it finally releases the SRST signal, the system is
3920 halted under debugger control before any code has executed.
3921 This is the behavior required to support the @command{reset halt}
3922 and @command{reset init} commands; after @command{reset init} a
3923 board-specific script might do things like setting up DRAM.
3924 (@xref{resetcommand,,Reset Command}.)
3926 @anchor{srstandtrstissues}
3927 @section SRST and TRST Issues
3929 Because SRST and TRST are hardware signals, they can have a
3930 variety of system-specific constraints. Some of the most
3935 @item @emph{Signal not available} ... Some boards don't wire
3936 SRST or TRST to the JTAG connector. Some JTAG adapters don't
3937 support such signals even if they are wired up.
3938 Use the @command{reset_config} @var{signals} options to say
3939 when either of those signals is not connected.
3940 When SRST is not available, your code might not be able to rely
3941 on controllers having been fully reset during code startup.
3942 Missing TRST is not a problem, since JTAG-level resets can
3943 be triggered using with TMS signaling.
3945 @item @emph{Signals shorted} ... Sometimes a chip, board, or
3946 adapter will connect SRST to TRST, instead of keeping them separate.
3947 Use the @command{reset_config} @var{combination} options to say
3948 when those signals aren't properly independent.
3950 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
3951 delay circuit, reset supervisor, or on-chip features can extend
3952 the effect of a JTAG adapter's reset for some time after the adapter
3953 stops issuing the reset. For example, there may be chip or board
3954 requirements that all reset pulses last for at least a
3955 certain amount of time; and reset buttons commonly have
3956 hardware debouncing.
3957 Use the @command{adapter srst delay} and @command{jtag_ntrst_delay}
3958 commands to say when extra delays are needed.
3960 @item @emph{Drive type} ... Reset lines often have a pullup
3961 resistor, letting the JTAG interface treat them as open-drain
3962 signals. But that's not a requirement, so the adapter may need
3963 to use push/pull output drivers.
3964 Also, with weak pullups it may be advisable to drive
3965 signals to both levels (push/pull) to minimize rise times.
3966 Use the @command{reset_config} @var{trst_type} and
3967 @var{srst_type} parameters to say how to drive reset signals.
3969 @item @emph{Special initialization} ... Targets sometimes need
3970 special JTAG initialization sequences to handle chip-specific
3971 issues (not limited to errata).
3972 For example, certain JTAG commands might need to be issued while
3973 the system as a whole is in a reset state (SRST active)
3974 but the JTAG scan chain is usable (TRST inactive).
3975 Many systems treat combined assertion of SRST and TRST as a
3976 trigger for a harder reset than SRST alone.
3977 Such custom reset handling is discussed later in this chapter.
3980 There can also be other issues.
3981 Some devices don't fully conform to the JTAG specifications.
3982 Trivial system-specific differences are common, such as
3983 SRST and TRST using slightly different names.
3984 There are also vendors who distribute key JTAG documentation for
3985 their chips only to developers who have signed a Non-Disclosure
3988 Sometimes there are chip-specific extensions like a requirement to use
3989 the normally-optional TRST signal (precluding use of JTAG adapters which
3990 don't pass TRST through), or needing extra steps to complete a TAP reset.
3992 In short, SRST and especially TRST handling may be very finicky,
3993 needing to cope with both architecture and board specific constraints.
3995 @section Commands for Handling Resets
3997 @deffn {Command} {adapter srst pulse_width} milliseconds
3998 Minimum amount of time (in milliseconds) OpenOCD should wait
3999 after asserting nSRST (active-low system reset) before
4000 allowing it to be deasserted.
4003 @deffn {Command} {adapter srst delay} milliseconds
4004 How long (in milliseconds) OpenOCD should wait after deasserting
4005 nSRST (active-low system reset) before starting new JTAG operations.
4006 When a board has a reset button connected to SRST line it will
4007 probably have hardware debouncing, implying you should use this.
4010 @deffn {Command} {jtag_ntrst_assert_width} milliseconds
4011 Minimum amount of time (in milliseconds) OpenOCD should wait
4012 after asserting nTRST (active-low JTAG TAP reset) before
4013 allowing it to be deasserted.
4016 @deffn {Command} {jtag_ntrst_delay} milliseconds
4017 How long (in milliseconds) OpenOCD should wait after deasserting
4018 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
4021 @anchor{reset_config}
4022 @deffn {Command} {reset_config} mode_flag ...
4023 This command displays or modifies the reset configuration
4024 of your combination of JTAG board and target in target
4025 configuration scripts.
4027 Information earlier in this section describes the kind of problems
4028 the command is intended to address (@pxref{srstandtrstissues,,SRST and TRST Issues}).
4029 As a rule this command belongs only in board config files,
4030 describing issues like @emph{board doesn't connect TRST};
4031 or in user config files, addressing limitations derived
4032 from a particular combination of interface and board.
4033 (An unlikely example would be using a TRST-only adapter
4034 with a board that only wires up SRST.)
4036 The @var{mode_flag} options can be specified in any order, but only one
4037 of each type -- @var{signals}, @var{combination}, @var{gates},
4038 @var{trst_type}, @var{srst_type} and @var{connect_type}
4039 -- may be specified at a time.
4040 If you don't provide a new value for a given type, its previous
4041 value (perhaps the default) is unchanged.
4042 For example, this means that you don't need to say anything at all about
4043 TRST just to declare that if the JTAG adapter should want to drive SRST,
4044 it must explicitly be driven high (@option{srst_push_pull}).
4048 @var{signals} can specify which of the reset signals are connected.
4049 For example, If the JTAG interface provides SRST, but the board doesn't
4050 connect that signal properly, then OpenOCD can't use it.
4051 Possible values are @option{none} (the default), @option{trst_only},
4052 @option{srst_only} and @option{trst_and_srst}.
4055 If your board provides SRST and/or TRST through the JTAG connector,
4056 you must declare that so those signals can be used.
4060 The @var{combination} is an optional value specifying broken reset
4061 signal implementations.
4062 The default behaviour if no option given is @option{separate},
4063 indicating everything behaves normally.
4064 @option{srst_pulls_trst} states that the
4065 test logic is reset together with the reset of the system (e.g. NXP
4066 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
4067 the system is reset together with the test logic (only hypothetical, I
4068 haven't seen hardware with such a bug, and can be worked around).
4069 @option{combined} implies both @option{srst_pulls_trst} and
4070 @option{trst_pulls_srst}.
4073 The @var{gates} tokens control flags that describe some cases where
4074 JTAG may be unavailable during reset.
4075 @option{srst_gates_jtag} (default)
4076 indicates that asserting SRST gates the
4077 JTAG clock. This means that no communication can happen on JTAG
4078 while SRST is asserted.
4079 Its converse is @option{srst_nogate}, indicating that JTAG commands
4080 can safely be issued while SRST is active.
4083 The @var{connect_type} tokens control flags that describe some cases where
4084 SRST is asserted while connecting to the target. @option{srst_nogate}
4085 is required to use this option.
4086 @option{connect_deassert_srst} (default)
4087 indicates that SRST will not be asserted while connecting to the target.
4088 Its converse is @option{connect_assert_srst}, indicating that SRST will
4089 be asserted before any target connection.
4090 Only some targets support this feature, STM32 and STR9 are examples.
4091 This feature is useful if you are unable to connect to your target due
4092 to incorrect options byte config or illegal program execution.
4095 The optional @var{trst_type} and @var{srst_type} parameters allow the
4096 driver mode of each reset line to be specified. These values only affect
4097 JTAG interfaces with support for different driver modes, like the Amontec
4098 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
4099 relevant signal (TRST or SRST) is not connected.
4103 Possible @var{trst_type} driver modes for the test reset signal (TRST)
4104 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
4105 Most boards connect this signal to a pulldown, so the JTAG TAPs
4106 never leave reset unless they are hooked up to a JTAG adapter.
4109 Possible @var{srst_type} driver modes for the system reset signal (SRST)
4110 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
4111 Most boards connect this signal to a pullup, and allow the
4112 signal to be pulled low by various events including system
4113 power-up and pressing a reset button.
4117 @section Custom Reset Handling
4120 OpenOCD has several ways to help support the various reset
4121 mechanisms provided by chip and board vendors.
4122 The commands shown in the previous section give standard parameters.
4123 There are also @emph{event handlers} associated with TAPs or Targets.
4124 Those handlers are Tcl procedures you can provide, which are invoked
4125 at particular points in the reset sequence.
4127 @emph{When SRST is not an option} you must set
4128 up a @code{reset-assert} event handler for your target.
4129 For example, some JTAG adapters don't include the SRST signal;
4130 and some boards have multiple targets, and you won't always
4131 want to reset everything at once.
4133 After configuring those mechanisms, you might still
4134 find your board doesn't start up or reset correctly.
4135 For example, maybe it needs a slightly different sequence
4136 of SRST and/or TRST manipulations, because of quirks that
4137 the @command{reset_config} mechanism doesn't address;
4138 or asserting both might trigger a stronger reset, which
4139 needs special attention.
4141 Experiment with lower level operations, such as
4142 @command{adapter assert}, @command{adapter deassert}
4143 and the @command{jtag arp_*} operations shown here,
4144 to find a sequence of operations that works.
4145 @xref{JTAG Commands}.
4146 When you find a working sequence, it can be used to override
4147 @command{jtag_init}, which fires during OpenOCD startup
4148 (@pxref{configurationstage,,Configuration Stage});
4149 or @command{init_reset}, which fires during reset processing.
4151 You might also want to provide some project-specific reset
4152 schemes. For example, on a multi-target board the standard
4153 @command{reset} command would reset all targets, but you
4154 may need the ability to reset only one target at time and
4155 thus want to avoid using the board-wide SRST signal.
4157 @deffn {Overridable Procedure} {init_reset} mode
4158 This is invoked near the beginning of the @command{reset} command,
4159 usually to provide as much of a cold (power-up) reset as practical.
4160 By default it is also invoked from @command{jtag_init} if
4161 the scan chain does not respond to pure JTAG operations.
4162 The @var{mode} parameter is the parameter given to the
4163 low level reset command (@option{halt},
4164 @option{init}, or @option{run}), @option{setup},
4165 or potentially some other value.
4167 The default implementation just invokes @command{jtag arp_init-reset}.
4168 Replacements will normally build on low level JTAG
4169 operations such as @command{adapter assert} and @command{adapter deassert}.
4170 Operations here must not address individual TAPs
4171 (or their associated targets)
4172 until the JTAG scan chain has first been verified to work.
4174 Implementations must have verified the JTAG scan chain before
4176 This is done by calling @command{jtag arp_init}
4177 (or @command{jtag arp_init-reset}).
4180 @deffn {Command} {jtag arp_init}
4181 This validates the scan chain using just the four
4182 standard JTAG signals (TMS, TCK, TDI, TDO).
4183 It starts by issuing a JTAG-only reset.
4184 Then it performs checks to verify that the scan chain configuration
4185 matches the TAPs it can observe.
4186 Those checks include checking IDCODE values for each active TAP,
4187 and verifying the length of their instruction registers using
4188 TAP @code{-ircapture} and @code{-irmask} values.
4189 If these tests all pass, TAP @code{setup} events are
4190 issued to all TAPs with handlers for that event.
4193 @deffn {Command} {jtag arp_init-reset}
4194 This uses TRST and SRST to try resetting
4195 everything on the JTAG scan chain
4196 (and anything else connected to SRST).
4197 It then invokes the logic of @command{jtag arp_init}.
4201 @node TAP Declaration
4202 @chapter TAP Declaration
4203 @cindex TAP declaration
4204 @cindex TAP configuration
4206 @emph{Test Access Ports} (TAPs) are the core of JTAG.
4207 TAPs serve many roles, including:
4210 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target.
4211 @item @b{Flash Programming} Some chips program the flash directly via JTAG.
4212 Others do it indirectly, making a CPU do it.
4213 @item @b{Program Download} Using the same CPU support GDB uses,
4214 you can initialize a DRAM controller, download code to DRAM, and then
4215 start running that code.
4216 @item @b{Boundary Scan} Most chips support boundary scan, which
4217 helps test for board assembly problems like solder bridges
4218 and missing connections.
4221 OpenOCD must know about the active TAPs on your board(s).
4222 Setting up the TAPs is the core task of your configuration files.
4223 Once those TAPs are set up, you can pass their names to code
4224 which sets up CPUs and exports them as GDB targets,
4225 probes flash memory, performs low-level JTAG operations, and more.
4227 @section Scan Chains
4230 TAPs are part of a hardware @dfn{scan chain},
4231 which is a daisy chain of TAPs.
4232 They also need to be added to
4233 OpenOCD's software mirror of that hardware list,
4234 giving each member a name and associating other data with it.
4235 Simple scan chains, with a single TAP, are common in
4236 systems with a single microcontroller or microprocessor.
4237 More complex chips may have several TAPs internally.
4238 Very complex scan chains might have a dozen or more TAPs:
4239 several in one chip, more in the next, and connecting
4240 to other boards with their own chips and TAPs.
4242 You can display the list with the @command{scan_chain} command.
4243 (Don't confuse this with the list displayed by the @command{targets}
4244 command, presented in the next chapter.
4245 That only displays TAPs for CPUs which are configured as
4247 Here's what the scan chain might look like for a chip more than one TAP:
4250 TapName Enabled IdCode Expected IrLen IrCap IrMask
4251 -- ------------------ ------- ---------- ---------- ----- ----- ------
4252 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
4253 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
4254 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
4257 OpenOCD can detect some of that information, but not all
4258 of it. @xref{autoprobing,,Autoprobing}.
4259 Unfortunately, those TAPs can't always be autoconfigured,
4260 because not all devices provide good support for that.
4261 JTAG doesn't require supporting IDCODE instructions, and
4262 chips with JTAG routers may not link TAPs into the chain
4263 until they are told to do so.
4265 The configuration mechanism currently supported by OpenOCD
4266 requires explicit configuration of all TAP devices using
4267 @command{jtag newtap} commands, as detailed later in this chapter.
4268 A command like this would declare one tap and name it @code{chip1.cpu}:
4271 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
4274 Each target configuration file lists the TAPs provided
4276 Board configuration files combine all the targets on a board,
4278 Note that @emph{the order in which TAPs are declared is very important.}
4279 That declaration order must match the order in the JTAG scan chain,
4280 both inside a single chip and between them.
4281 @xref{faqtaporder,,FAQ TAP Order}.
4283 For example, the STMicroelectronics STR912 chip has
4284 three separate TAPs@footnote{See the ST
4285 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
4286 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
4287 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
4288 To configure those taps, @file{target/str912.cfg}
4289 includes commands something like this:
4292 jtag newtap str912 flash ... params ...
4293 jtag newtap str912 cpu ... params ...
4294 jtag newtap str912 bs ... params ...
4297 Actual config files typically use a variable such as @code{$_CHIPNAME}
4298 instead of literals like @option{str912}, to support more than one chip
4299 of each type. @xref{Config File Guidelines}.
4301 @deffn {Command} {jtag names}
4302 Returns the names of all current TAPs in the scan chain.
4303 Use @command{jtag cget} or @command{jtag tapisenabled}
4304 to examine attributes and state of each TAP.
4306 foreach t [jtag names] @{
4307 puts [format "TAP: %s\n" $t]
4312 @deffn {Command} {scan_chain}
4313 Displays the TAPs in the scan chain configuration,
4315 The set of TAPs listed by this command is fixed by
4316 exiting the OpenOCD configuration stage,
4317 but systems with a JTAG router can
4318 enable or disable TAPs dynamically.
4321 @c FIXME! "jtag cget" should be able to return all TAP
4322 @c attributes, like "$target_name cget" does for targets.
4324 @c Probably want "jtag eventlist", and a "tap-reset" event
4325 @c (on entry to RESET state).
4330 When TAP objects are declared with @command{jtag newtap},
4331 a @dfn{dotted.name} is created for the TAP, combining the
4332 name of a module (usually a chip) and a label for the TAP.
4333 For example: @code{xilinx.tap}, @code{str912.flash},
4334 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
4335 Many other commands use that dotted.name to manipulate or
4336 refer to the TAP. For example, CPU configuration uses the
4337 name, as does declaration of NAND or NOR flash banks.
4339 The components of a dotted name should follow ``C'' symbol
4340 name rules: start with an alphabetic character, then numbers
4341 and underscores are OK; while others (including dots!) are not.
4343 @section TAP Declaration Commands
4345 @deffn {Config Command} {jtag newtap} chipname tapname configparams...
4346 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
4347 and configured according to the various @var{configparams}.
4349 The @var{chipname} is a symbolic name for the chip.
4350 Conventionally target config files use @code{$_CHIPNAME},
4351 defaulting to the model name given by the chip vendor but
4354 @cindex TAP naming convention
4355 The @var{tapname} reflects the role of that TAP,
4356 and should follow this convention:
4359 @item @code{bs} -- For boundary scan if this is a separate TAP;
4360 @item @code{cpu} -- The main CPU of the chip, alternatively
4361 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
4362 @code{arm1} and @code{arm2} on chips with two ARMs, and so forth;
4363 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
4364 @item @code{flash} -- If the chip has a flash TAP, like the str912;
4365 @item @code{jrc} -- For JTAG route controller (example: the ICEPick modules
4366 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
4367 @item @code{tap} -- Should be used only for FPGA- or CPLD-like devices
4369 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
4370 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
4371 For example, the Freescale i.MX31 has a SDMA (Smart DMA) with
4372 a JTAG TAP; that TAP should be named @code{sdma}.
4375 Every TAP requires at least the following @var{configparams}:
4378 @item @code{-irlen} @var{NUMBER}
4379 @*The length in bits of the
4380 instruction register, such as 4 or 5 bits.
4383 A TAP may also provide optional @var{configparams}:
4386 @item @code{-disable} (or @code{-enable})
4387 @*Use the @code{-disable} parameter to flag a TAP which is not
4388 linked into the scan chain after a reset using either TRST
4389 or the JTAG state machine's @sc{reset} state.
4390 You may use @code{-enable} to highlight the default state
4391 (the TAP is linked in).
4392 @xref{enablinganddisablingtaps,,Enabling and Disabling TAPs}.
4393 @item @code{-expected-id} @var{NUMBER}
4394 @*A non-zero @var{number} represents a 32-bit IDCODE
4395 which you expect to find when the scan chain is examined.
4396 These codes are not required by all JTAG devices.
4397 @emph{Repeat the option} as many times as required if more than one
4398 ID code could appear (for example, multiple versions).
4399 Specify @var{number} as zero to suppress warnings about IDCODE
4400 values that were found but not included in the list.
4402 Provide this value if at all possible, since it lets OpenOCD
4403 tell when the scan chain it sees isn't right. These values
4404 are provided in vendors' chip documentation, usually a technical
4405 reference manual. Sometimes you may need to probe the JTAG
4406 hardware to find these values.
4407 @xref{autoprobing,,Autoprobing}.
4408 @item @code{-ignore-version}
4409 @*Specify this to ignore the JTAG version field in the @code{-expected-id}
4410 option. When vendors put out multiple versions of a chip, or use the same
4411 JTAG-level ID for several largely-compatible chips, it may be more practical
4412 to ignore the version field than to update config files to handle all of
4413 the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
4414 @item @code{-ignore-bypass}
4415 @*Specify this to ignore the 'bypass' bit of the idcode. Some vendor put
4416 an invalid idcode regarding this bit. Specify this to ignore this bit and
4417 to not consider this tap in bypass mode.
4418 @item @code{-ircapture} @var{NUMBER}
4419 @*The bit pattern loaded by the TAP into the JTAG shift register
4420 on entry to the @sc{ircapture} state, such as 0x01.
4421 JTAG requires the two LSBs of this value to be 01.
4422 By default, @code{-ircapture} and @code{-irmask} are set
4423 up to verify that two-bit value. You may provide
4424 additional bits if you know them, or indicate that
4425 a TAP doesn't conform to the JTAG specification.
4426 @item @code{-irmask} @var{NUMBER}
4427 @*A mask used with @code{-ircapture}
4428 to verify that instruction scans work correctly.
4429 Such scans are not used by OpenOCD except to verify that
4430 there seems to be no problems with JTAG scan chain operations.
4431 @item @code{-ignore-syspwrupack}
4432 @*Specify this to ignore the CSYSPWRUPACK bit in the ARM DAP DP CTRL/STAT
4433 register during initial examination and when checking the sticky error bit.
4434 This bit is normally checked after setting the CSYSPWRUPREQ bit, but some
4435 devices do not set the ack bit until sometime later.
4436 @item @code{-ir-bypass} @var{NUMBER}
4437 @*Vendor specific bypass instruction, required by some hierarchical JTAG
4438 routers where the normal BYPASS instruction bypasses the whole router and
4439 a vendor specific bypass instruction is required to access child nodes.
4443 @section Other TAP commands
4445 @deffn {Command} {jtag cget} dotted.name @option{-idcode}
4446 Get the value of the IDCODE found in hardware.
4449 @deffn {Command} {jtag cget} dotted.name @option{-event} event_name
4450 @deffnx {Command} {jtag configure} dotted.name @option{-event} event_name handler
4451 At this writing this TAP attribute
4452 mechanism is limited and used mostly for event handling.
4453 (It is not a direct analogue of the @code{cget}/@code{configure}
4454 mechanism for debugger targets.)
4455 See the next section for information about the available events.
4457 The @code{configure} subcommand assigns an event handler,
4458 a TCL string which is evaluated when the event is triggered.
4459 The @code{cget} subcommand returns that handler.
4466 OpenOCD includes two event mechanisms.
4467 The one presented here applies to all JTAG TAPs.
4468 The other applies to debugger targets,
4469 which are associated with certain TAPs.
4471 The TAP events currently defined are:
4474 @item @b{post-reset}
4475 @* The TAP has just completed a JTAG reset.
4476 The tap may still be in the JTAG @sc{reset} state.
4477 Handlers for these events might perform initialization sequences
4478 such as issuing TCK cycles, TMS sequences to ensure
4479 exit from the ARM SWD mode, and more.
4481 Because the scan chain has not yet been verified, handlers for these events
4482 @emph{should not issue commands which scan the JTAG IR or DR registers}
4483 of any particular target.
4484 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
4486 @* The scan chain has been reset and verified.
4487 This handler may enable TAPs as needed.
4488 @item @b{tap-disable}
4489 @* The TAP needs to be disabled. This handler should
4490 implement @command{jtag tapdisable}
4491 by issuing the relevant JTAG commands.
4492 @item @b{tap-enable}
4493 @* The TAP needs to be enabled. This handler should
4494 implement @command{jtag tapenable}
4495 by issuing the relevant JTAG commands.
4498 If you need some action after each JTAG reset which isn't actually
4499 specific to any TAP (since you can't yet trust the scan chain's
4500 contents to be accurate), you might:
4503 jtag configure CHIP.jrc -event post-reset @{
4504 echo "JTAG Reset done"
4505 ... non-scan jtag operations to be done after reset
4510 @anchor{enablinganddisablingtaps}
4511 @section Enabling and Disabling TAPs
4512 @cindex JTAG Route Controller
4515 In some systems, a @dfn{JTAG Route Controller} (JRC)
4516 is used to enable and/or disable specific JTAG TAPs.
4517 Many ARM-based chips from Texas Instruments include
4518 an ``ICEPick'' module, which is a JRC.
4519 Such chips include DaVinci and OMAP3 processors.
4521 A given TAP may not be visible until the JRC has been
4522 told to link it into the scan chain; and if the JRC
4523 has been told to unlink that TAP, it will no longer
4525 Such routers address problems that JTAG ``bypass mode''
4529 @item The scan chain can only go as fast as its slowest TAP.
4530 @item Having many TAPs slows instruction scans, since all
4531 TAPs receive new instructions.
4532 @item TAPs in the scan chain must be powered up, which wastes
4533 power and prevents debugging some power management mechanisms.
4536 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
4537 as implied by the existence of JTAG routers.
4538 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
4539 does include a kind of JTAG router functionality.
4541 @c (a) currently the event handlers don't seem to be able to
4542 @c fail in a way that could lead to no-change-of-state.
4544 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
4545 shown below, and is implemented using TAP event handlers.
4546 So for example, when defining a TAP for a CPU connected to
4547 a JTAG router, your @file{target.cfg} file
4548 should define TAP event handlers using
4549 code that looks something like this:
4552 jtag configure CHIP.cpu -event tap-enable @{
4553 ... jtag operations using CHIP.jrc
4555 jtag configure CHIP.cpu -event tap-disable @{
4556 ... jtag operations using CHIP.jrc
4560 Then you might want that CPU's TAP enabled almost all the time:
4563 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
4566 Note how that particular setup event handler declaration
4567 uses quotes to evaluate @code{$CHIP} when the event is configured.
4568 Using brackets @{ @} would cause it to be evaluated later,
4569 at runtime, when it might have a different value.
4571 @deffn {Command} {jtag tapdisable} dotted.name
4572 If necessary, disables the tap
4573 by sending it a @option{tap-disable} event.
4574 Returns the string "1" if the tap
4575 specified by @var{dotted.name} is enabled,
4576 and "0" if it is disabled.
4579 @deffn {Command} {jtag tapenable} dotted.name
4580 If necessary, enables the tap
4581 by sending it a @option{tap-enable} event.
4582 Returns the string "1" if the tap
4583 specified by @var{dotted.name} is enabled,
4584 and "0" if it is disabled.
4587 @deffn {Command} {jtag tapisenabled} dotted.name
4588 Returns the string "1" if the tap
4589 specified by @var{dotted.name} is enabled,
4590 and "0" if it is disabled.
4593 Humans will find the @command{scan_chain} command more helpful
4594 for querying the state of the JTAG taps.
4598 @anchor{autoprobing}
4599 @section Autoprobing
4601 @cindex JTAG autoprobe
4603 TAP configuration is the first thing that needs to be done
4604 after interface and reset configuration. Sometimes it's
4605 hard finding out what TAPs exist, or how they are identified.
4606 Vendor documentation is not always easy to find and use.
4608 To help you get past such problems, OpenOCD has a limited
4609 @emph{autoprobing} ability to look at the scan chain, doing
4610 a @dfn{blind interrogation} and then reporting the TAPs it finds.
4611 To use this mechanism, start the OpenOCD server with only data
4612 that configures your JTAG interface, and arranges to come up
4613 with a slow clock (many devices don't support fast JTAG clocks
4614 right when they come out of reset).
4616 For example, your @file{openocd.cfg} file might have:
4619 source [find interface/olimex-arm-usb-tiny-h.cfg]
4620 reset_config trst_and_srst
4624 When you start the server without any TAPs configured, it will
4625 attempt to autoconfigure the TAPs. There are two parts to this:
4628 @item @emph{TAP discovery} ...
4629 After a JTAG reset (sometimes a system reset may be needed too),
4630 each TAP's data registers will hold the contents of either the
4631 IDCODE or BYPASS register.
4632 If JTAG communication is working, OpenOCD will see each TAP,
4633 and report what @option{-expected-id} to use with it.
4634 @item @emph{IR Length discovery} ...
4635 Unfortunately JTAG does not provide a reliable way to find out
4636 the value of the @option{-irlen} parameter to use with a TAP
4638 If OpenOCD can discover the length of a TAP's instruction
4639 register, it will report it.
4640 Otherwise you may need to consult vendor documentation, such
4641 as chip data sheets or BSDL files.
4644 In many cases your board will have a simple scan chain with just
4645 a single device. Here's what OpenOCD reported with one board
4646 that's a bit more complex:
4650 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
4651 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
4652 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
4653 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
4654 AUTO auto0.tap - use "... -irlen 4"
4655 AUTO auto1.tap - use "... -irlen 4"
4656 AUTO auto2.tap - use "... -irlen 6"
4657 no gdb ports allocated as no target has been specified
4660 Given that information, you should be able to either find some existing
4661 config files to use, or create your own. If you create your own, you
4662 would configure from the bottom up: first a @file{target.cfg} file
4663 with these TAPs, any targets associated with them, and any on-chip
4664 resources; then a @file{board.cfg} with off-chip resources, clocking,
4667 @anchor{dapdeclaration}
4668 @section DAP declaration (ARMv6-M, ARMv7 and ARMv8 targets)
4669 @cindex DAP declaration
4671 Since OpenOCD version 0.11.0, the Debug Access Port (DAP) is
4672 no longer implicitly created together with the target. It must be
4673 explicitly declared using the @command{dap create} command. For all ARMv6-M, ARMv7
4674 and ARMv8 targets, the option "@option{-dap} @var{dap_name}" has to be used
4675 instead of "@option{-chain-position} @var{dotted.name}" when the target is created.
4677 The @command{dap} command group supports the following sub-commands:
4680 @deffn {Command} {dap create} dap_name @option{-chain-position} dotted.name configparams...
4681 Declare a DAP instance named @var{dap_name} linked to the JTAG tap
4682 @var{dotted.name}. This also creates a new command (@command{dap_name})
4683 which is used for various purposes including additional configuration.
4684 There can only be one DAP for each JTAG tap in the system.
4686 A DAP may also provide optional @var{configparams}:
4690 Specify that it's an ADIv5 DAP. This is the default if not specified.
4692 Specify that it's an ADIv6 DAP.
4693 @item @code{-ignore-syspwrupack}
4694 Specify this to ignore the CSYSPWRUPACK bit in the ARM DAP DP CTRL/STAT
4695 register during initial examination and when checking the sticky error bit.
4696 This bit is normally checked after setting the CSYSPWRUPREQ bit, but some
4697 devices do not set the ack bit until sometime later.
4699 @item @code{-dp-id} @var{number}
4700 @*Debug port identification number for SWD DPv2 multidrop.
4701 The @var{number} is written to bits 0..27 of DP TARGETSEL during DP selection.
4702 To find the id number of a single connected device read DP TARGETID:
4703 @code{device.dap dpreg 0x24}
4704 Use bits 0..27 of TARGETID.
4706 @item @code{-instance-id} @var{number}
4707 @*Instance identification number for SWD DPv2 multidrop.
4708 The @var{number} is written to bits 28..31 of DP TARGETSEL during DP selection.
4709 To find the instance number of a single connected device read DP DLPIDR:
4710 @code{device.dap dpreg 0x34}
4711 The instance number is in bits 28..31 of DLPIDR value.
4715 @deffn {Command} {dap names}
4716 This command returns a list of all registered DAP objects. It it useful mainly
4720 @deffn {Command} {dap info} [@var{num}|@option{root}]
4721 Displays the ROM table for MEM-AP @var{num},
4722 defaulting to the currently selected AP of the currently selected target.
4723 On ADIv5 DAP @var{num} is the numeric index of the AP.
4724 On ADIv6 DAP @var{num} is the base address of the AP.
4725 With ADIv6 only, @option{root} specifies the root ROM table.
4728 @deffn {Command} {dap init}
4729 Initialize all registered DAPs. This command is used internally
4730 during initialization. It can be issued at any time after the
4731 initialization, too.
4734 The following commands exist as subcommands of DAP instances:
4736 @deffn {Command} {$dap_name info} [@var{num}|@option{root}]
4737 Displays the ROM table for MEM-AP @var{num},
4738 defaulting to the currently selected AP.
4739 On ADIv5 DAP @var{num} is the numeric index of the AP.
4740 On ADIv6 DAP @var{num} is the base address of the AP.
4741 With ADIv6 only, @option{root} specifies the root ROM table.
4744 @deffn {Command} {$dap_name apid} [num]
4745 Displays ID register from AP @var{num}, defaulting to the currently selected AP.
4746 On ADIv5 DAP @var{num} is the numeric index of the AP.
4747 On ADIv6 DAP @var{num} is the base address of the AP.
4750 @anchor{DAP subcommand apreg}
4751 @deffn {Command} {$dap_name apreg} ap_num reg [value]
4752 Displays content of a register @var{reg} from AP @var{ap_num}
4753 or set a new value @var{value}.
4754 On ADIv5 DAP @var{ap_num} is the numeric index of the AP.
4755 On ADIv6 DAP @var{ap_num} is the base address of the AP.
4756 @var{reg} is byte address of a word register, 0, 4, 8 ... 0xfc.
4759 @deffn {Command} {$dap_name apsel} [num]
4760 Select AP @var{num}, defaulting to 0.
4761 On ADIv5 DAP @var{num} is the numeric index of the AP.
4762 On ADIv6 DAP @var{num} is the base address of the AP.
4765 @deffn {Command} {$dap_name dpreg} reg [value]
4766 Displays the content of DP register at address @var{reg}, or set it to a new
4769 In case of SWD, @var{reg} is a value in packed format
4770 @math{dpbanksel << 4 | addr} and assumes values 0, 4, 8 ... 0xfc.
4771 In case of JTAG it only assumes values 0, 4, 8 and 0xc.
4773 @emph{Note:} Consider using @command{poll off} to avoid any disturbing
4774 background activity by OpenOCD while you are operating at such low-level.
4777 @deffn {Command} {$dap_name baseaddr} [num]
4778 Displays debug base address from MEM-AP @var{num},
4779 defaulting to the currently selected AP.
4780 On ADIv5 DAP @var{num} is the numeric index of the AP.
4781 On ADIv6 DAP @var{num} is the base address of the AP.
4784 @deffn {Command} {$dap_name memaccess} [value]
4785 Displays the number of extra tck cycles in the JTAG idle to use for MEM-AP
4786 memory bus access [0-255], giving additional time to respond to reads.
4787 If @var{value} is defined, first assigns that.
4790 @deffn {Command} {$dap_name apcsw} [value [mask]]
4791 Displays or changes CSW bit pattern for MEM-AP transfers.
4793 At the begin of each memory access the CSW pattern is extended (bitwise or-ed)
4794 by @dfn{Size} and @dfn{AddrInc} bit-fields according to transfer requirements
4795 and the result is written to the real CSW register. All bits except dynamically
4796 updated fields @dfn{Size} and @dfn{AddrInc} can be changed by changing
4797 the CSW pattern. Refer to ARM ADI v5 manual chapter 7.6.4 and appendix A
4800 Use @var{value} only syntax if you want to set the new CSW pattern as a whole.
4801 The example sets HPROT1 bit (required by Cortex-M) and clears the rest of
4804 kx.dap apcsw 0x2000000
4807 If @var{mask} is also used, the CSW pattern is changed only on bit positions
4808 where the mask bit is 1. The following example sets HPROT3 (cacheable)
4809 and leaves the rest of the pattern intact. It configures memory access through
4810 DCache on Cortex-M7.
4812 set CSW_HPROT3_CACHEABLE [expr @{1 << 27@}]
4813 samv.dap apcsw $CSW_HPROT3_CACHEABLE $CSW_HPROT3_CACHEABLE
4816 Another example clears SPROT bit and leaves the rest of pattern intact:
4818 set CSW_SPROT [expr @{1 << 30@}]
4819 samv.dap apcsw 0 $CSW_SPROT
4822 @emph{Note:} If you want to check the real value of CSW, not CSW pattern, use
4823 @code{xxx.dap apreg 0}. @xref{DAP subcommand apreg,,}.
4825 @emph{Warning:} Some of the CSW bits are vital for working memory transfer.
4826 If you set a wrong CSW pattern and MEM-AP stopped working, use the following
4827 example with a proper dap name:
4829 xxx.dap apcsw default
4833 @deffn {Config Command} {$dap_name ti_be_32_quirks} [@option{enable}]
4834 Set/get quirks mode for TI TMS450/TMS570 processors
4838 @deffn {Config Command} {$dap_name nu_npcx_quirks} [@option{enable}]
4839 Set/get quirks mode for Nuvoton NPCX/NPCD MCU families
4843 @node CPU Configuration
4844 @chapter CPU Configuration
4847 This chapter discusses how to set up GDB debug targets for CPUs.
4848 You can also access these targets without GDB
4849 (@pxref{Architecture and Core Commands},
4850 and @ref{targetstatehandling,,Target State handling}) and
4851 through various kinds of NAND and NOR flash commands.
4852 If you have multiple CPUs you can have multiple such targets.
4854 We'll start by looking at how to examine the targets you have,
4855 then look at how to add one more target and how to configure it.
4857 @section Target List
4858 @cindex target, current
4859 @cindex target, list
4861 All targets that have been set up are part of a list,
4862 where each member has a name.
4863 That name should normally be the same as the TAP name.
4864 You can display the list with the @command{targets}
4866 This display often has only one CPU; here's what it might
4867 look like with more than one:
4869 TargetName Type Endian TapName State
4870 -- ------------------ ---------- ------ ------------------ ------------
4871 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
4872 1 MyTarget cortex_m little mychip.foo tap-disabled
4875 One member of that list is the @dfn{current target}, which
4876 is implicitly referenced by many commands.
4877 It's the one marked with a @code{*} near the target name.
4878 In particular, memory addresses often refer to the address
4879 space seen by that current target.
4880 Commands like @command{mdw} (memory display words)
4881 and @command{flash erase_address} (erase NOR flash blocks)
4882 are examples; and there are many more.
4884 Several commands let you examine the list of targets:
4886 @deffn {Command} {target current}
4887 Returns the name of the current target.
4890 @deffn {Command} {target names}
4891 Lists the names of all current targets in the list.
4893 foreach t [target names] @{
4894 puts [format "Target: %s\n" $t]
4899 @c yep, "target list" would have been better.
4900 @c plus maybe "target setdefault".
4902 @deffn {Command} {targets} [name]
4903 @emph{Note: the name of this command is plural. Other target
4904 command names are singular.}
4906 With no parameter, this command displays a table of all known
4907 targets in a user friendly form.
4909 With a parameter, this command sets the current target to
4910 the given target with the given @var{name}; this is
4911 only relevant on boards which have more than one target.
4914 @section Target CPU Types
4918 Each target has a @dfn{CPU type}, as shown in the output of
4919 the @command{targets} command. You need to specify that type
4920 when calling @command{target create}.
4921 The CPU type indicates more than just the instruction set.
4922 It also indicates how that instruction set is implemented,
4923 what kind of debug support it integrates,
4924 whether it has an MMU (and if so, what kind),
4925 what core-specific commands may be available
4926 (@pxref{Architecture and Core Commands}),
4929 It's easy to see what target types are supported,
4930 since there's a command to list them.
4932 @anchor{targettypes}
4933 @deffn {Command} {target types}
4934 Lists all supported target types.
4935 At this writing, the supported CPU types are:
4938 @item @code{aarch64} -- this is an ARMv8-A core with an MMU.
4939 @item @code{arm11} -- this is a generation of ARMv6 cores.
4940 @item @code{arm720t} -- this is an ARMv4 core with an MMU.
4941 @item @code{arm7tdmi} -- this is an ARMv4 core.
4942 @item @code{arm920t} -- this is an ARMv4 core with an MMU.
4943 @item @code{arm926ejs} -- this is an ARMv5 core with an MMU.
4944 @item @code{arm946e} -- this is an ARMv5 core with an MMU.
4945 @item @code{arm966e} -- this is an ARMv5 core.
4946 @item @code{arm9tdmi} -- this is an ARMv4 core.
4947 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
4948 (Support for this is preliminary and incomplete.)
4949 @item @code{avr32_ap7k} -- this an AVR32 core.
4950 @item @code{cortex_a} -- this is an ARMv7-A core with an MMU.
4951 @item @code{cortex_m} -- this is an ARMv7-M core, supporting only the
4952 compact Thumb2 instruction set. Supports also ARMv6-M and ARMv8-M cores
4953 @item @code{cortex_r4} -- this is an ARMv7-R core.
4954 @item @code{dragonite} -- resembles arm966e.
4955 @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
4956 (Support for this is still incomplete.)
4957 @item @code{dsp5680xx} -- implements Freescale's 5680x DSP.
4958 @item @code{esirisc} -- this is an EnSilica eSi-RISC core.
4959 The current implementation supports eSi-32xx cores.
4960 @item @code{esp32} -- this is an Espressif SoC with dual Xtensa cores.
4961 @item @code{esp32s2} -- this is an Espressif SoC with single Xtensa core.
4962 @item @code{esp32s3} -- this is an Espressif SoC with dual Xtensa cores.
4963 @item @code{fa526} -- resembles arm920 (w/o Thumb).
4964 @item @code{feroceon} -- resembles arm926.
4965 @item @code{hla_target} -- a Cortex-M alternative to work with HL adapters like ST-Link.
4966 @item @code{ls1_sap} -- this is the SAP on NXP LS102x CPUs,
4967 allowing access to physical memory addresses independently of CPU cores.
4968 @item @code{mem_ap} -- this is an ARM debug infrastructure Access Port without
4969 a CPU, through which bus read and write cycles can be generated; it may be
4970 useful for working with non-CPU hardware behind an AP or during development of
4971 support for new CPUs.
4972 It's possible to connect a GDB client to this target (the GDB port has to be
4973 specified, @xref{gdbportoverride,,option -gdb-port}.), and a fake ARM core will
4974 be emulated to comply to GDB remote protocol.
4975 @item @code{mips_m4k} -- a MIPS core.
4976 @item @code{mips_mips64} -- a MIPS64 core.
4977 @item @code{or1k} -- this is an OpenRISC 1000 core.
4978 The current implementation supports three JTAG TAP cores:
4980 @item @code{OpenCores TAP} (See: @url{http://opencores.org/project@comma{}jtag})
4981 @item @code{Altera Virtual JTAG TAP} (See: @url{http://www.altera.com/literature/ug/ug_virtualjtag.pdf})
4982 @item @code{Xilinx BSCAN_* virtual JTAG interface} (See: @url{http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/spartan6_hdl.pdf})
4984 And two debug interfaces cores:
4986 @item @code{Advanced debug interface}
4987 @*(See: @url{http://opencores.org/project@comma{}adv_debug_sys})
4988 @item @code{SoC Debug Interface}
4989 @*(See: @url{http://opencores.org/project@comma{}dbg_interface})
4991 @item @code{quark_d20xx} -- an Intel Quark D20xx core.
4992 @item @code{quark_x10xx} -- an Intel Quark X10xx core.
4993 @item @code{riscv} -- a RISC-V core.
4994 @item @code{stm8} -- implements an STM8 core.
4995 @item @code{testee} -- a dummy target for cases without a real CPU, e.g. CPLD.
4996 @item @code{xscale} -- this is actually an architecture,
4997 not a CPU type. It is based on the ARMv5 architecture.
4998 @item @code{xtensa} -- this is a generic Cadence/Tensilica Xtensa core.
5002 To avoid being confused by the variety of ARM based cores, remember
5003 this key point: @emph{ARM is a technology licencing company}.
5004 (See: @url{http://www.arm.com}.)
5005 The CPU name used by OpenOCD will reflect the CPU design that was
5006 licensed, not a vendor brand which incorporates that design.
5007 Name prefixes like arm7, arm9, arm11, and cortex
5008 reflect design generations;
5009 while names like ARMv4, ARMv5, ARMv6, ARMv7 and ARMv8
5010 reflect an architecture version implemented by a CPU design.
5012 @anchor{targetconfiguration}
5013 @section Target Configuration
5015 Before creating a ``target'', you must have added its TAP to the scan chain.
5016 When you've added that TAP, you will have a @code{dotted.name}
5017 which is used to set up the CPU support.
5018 The chip-specific configuration file will normally configure its CPU(s)
5019 right after it adds all of the chip's TAPs to the scan chain.
5021 Although you can set up a target in one step, it's often clearer if you
5022 use shorter commands and do it in two steps: create it, then configure
5024 All operations on the target after it's created will use a new
5025 command, created as part of target creation.
5027 The two main things to configure after target creation are
5028 a work area, which usually has target-specific defaults even
5029 if the board setup code overrides them later;
5030 and event handlers (@pxref{targetevents,,Target Events}), which tend
5031 to be much more board-specific.
5032 The key steps you use might look something like this
5035 dap create mychip.dap -chain-position mychip.cpu
5036 target create MyTarget cortex_m -dap mychip.dap
5037 MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
5038 MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
5039 MyTarget configure -event reset-init @{ myboard_reinit @}
5042 You should specify a working area if you can; typically it uses some
5044 Such a working area can speed up many things, including bulk
5045 writes to target memory;
5046 flash operations like checking to see if memory needs to be erased;
5047 GDB memory checksumming;
5051 On more complex chips, the work area can become
5052 inaccessible when application code
5053 (such as an operating system)
5054 enables or disables the MMU.
5055 For example, the particular MMU context used to access the virtual
5056 address will probably matter ... and that context might not have
5057 easy access to other addresses needed.
5058 At this writing, OpenOCD doesn't have much MMU intelligence.
5061 It's often very useful to define a @code{reset-init} event handler.
5062 For systems that are normally used with a boot loader,
5063 common tasks include updating clocks and initializing memory
5065 That may be needed to let you write the boot loader into flash,
5066 in order to ``de-brick'' your board; or to load programs into
5067 external DDR memory without having run the boot loader.
5069 @deffn {Config Command} {target create} target_name type configparams...
5070 This command creates a GDB debug target that refers to a specific JTAG tap.
5071 It enters that target into a list, and creates a new
5072 command (@command{@var{target_name}}) which is used for various
5073 purposes including additional configuration.
5076 @item @var{target_name} ... is the name of the debug target.
5077 By convention this should be the same as the @emph{dotted.name}
5078 of the TAP associated with this target, which must be specified here
5079 using the @code{-chain-position @var{dotted.name}} configparam.
5081 This name is also used to create the target object command,
5082 referred to here as @command{$target_name},
5083 and in other places the target needs to be identified.
5084 @item @var{type} ... specifies the target type. @xref{targettypes,,target types}.
5085 @item @var{configparams} ... all parameters accepted by
5086 @command{$target_name configure} are permitted.
5087 If the target is big-endian, set it here with @code{-endian big}.
5089 You @emph{must} set the @code{-chain-position @var{dotted.name}} or
5090 @code{-dap @var{dap_name}} here.
5094 @deffn {Command} {$target_name configure} configparams...
5095 The options accepted by this command may also be
5096 specified as parameters to @command{target create}.
5097 Their values can later be queried one at a time by
5098 using the @command{$target_name cget} command.
5100 @emph{Warning:} changing some of these after setup is dangerous.
5101 For example, moving a target from one TAP to another;
5102 and changing its endianness.
5106 @item @code{-chain-position} @var{dotted.name} -- names the TAP
5107 used to access this target.
5109 @item @code{-dap} @var{dap_name} -- names the DAP used to access
5110 this target. @xref{dapdeclaration,,DAP declaration}, on how to
5111 create and manage DAP instances.
5113 @item @code{-endian} (@option{big}|@option{little}) -- specifies
5114 whether the CPU uses big or little endian conventions
5116 @item @code{-event} @var{event_name} @var{event_body} --
5117 @xref{targetevents,,Target Events}.
5118 Note that this updates a list of named event handlers.
5119 Calling this twice with two different event names assigns
5120 two different handlers, but calling it twice with the
5121 same event name assigns only one handler.
5123 Current target is temporarily overridden to the event issuing target
5124 before handler code starts and switched back after handler is done.
5126 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
5127 whether the work area gets backed up; by default,
5128 @emph{it is not backed up.}
5129 When possible, use a working_area that doesn't need to be backed up,
5130 since performing a backup slows down operations.
5131 For example, the beginning of an SRAM block is likely to
5132 be used by most build systems, but the end is often unused.
5134 @item @code{-work-area-size} @var{size} -- specify work are size,
5135 in bytes. The same size applies regardless of whether its physical
5136 or virtual address is being used.
5138 @item @code{-work-area-phys} @var{address} -- set the work area
5139 base @var{address} to be used when no MMU is active.
5141 @item @code{-work-area-virt} @var{address} -- set the work area
5142 base @var{address} to be used when an MMU is active.
5143 @emph{Do not specify a value for this except on targets with an MMU.}
5144 The value should normally correspond to a static mapping for the
5145 @code{-work-area-phys} address, set up by the current operating system.
5148 @item @code{-rtos} @var{rtos_type} -- enable rtos support for target,
5149 @var{rtos_type} can be one of @option{auto}, @option{none}, @option{eCos},
5150 @option{ThreadX}, @option{FreeRTOS}, @option{linux}, @option{ChibiOS},
5151 @option{embKernel}, @option{mqx}, @option{uCOS-III}, @option{nuttx},
5152 @option{RIOT}, @option{Zephyr}, @option{rtkernel}
5153 @xref{gdbrtossupport,,RTOS Support}.
5155 @item @code{-defer-examine} -- skip target examination at initial JTAG chain
5156 scan and after a reset. A manual call to arp_examine is required to
5157 access the target for debugging.
5159 @item @code{-ap-num} @var{ap_number} -- set DAP access port for target.
5160 On ADIv5 DAP @var{ap_number} is the numeric index of the DAP AP the target is connected to.
5161 On ADIv6 DAP @var{ap_number} is the base address of the DAP AP the target is connected to.
5162 Use this option with systems where multiple, independent cores are connected
5163 to separate access ports of the same DAP.
5165 @item @code{-cti} @var{cti_name} -- set Cross-Trigger Interface (CTI) connected
5166 to the target. Currently, only the @code{aarch64} target makes use of this option,
5167 where it is a mandatory configuration for the target run control.
5168 @xref{armcrosstrigger,,ARM Cross-Trigger Interface},
5169 for instruction on how to declare and control a CTI instance.
5171 @anchor{gdbportoverride}
5172 @item @code{-gdb-port} @var{number} -- see command @command{gdb_port} for the
5173 possible values of the parameter @var{number}, which are not only numeric values.
5174 Use this option to override, for this target only, the global parameter set with
5175 command @command{gdb_port}.
5176 @xref{gdb_port,,command gdb_port}.
5178 @item @code{-gdb-max-connections} @var{number} -- EXPERIMENTAL: set the maximum
5179 number of GDB connections that are allowed for the target. Default is 1.
5180 A negative value for @var{number} means unlimited connections.
5181 See @xref{gdbmeminspect,,Using GDB as a non-intrusive memory inspector}.
5185 @section Other $target_name Commands
5186 @cindex object command
5188 The Tcl/Tk language has the concept of object commands,
5189 and OpenOCD adopts that same model for targets.
5191 A good Tk example is a on screen button.
5192 Once a button is created a button
5193 has a name (a path in Tk terms) and that name is useable as a first
5194 class command. For example in Tk, one can create a button and later
5195 configure it like this:
5199 button .foobar -background red -command @{ foo @}
5201 .foobar configure -foreground blue
5203 set x [.foobar cget -background]
5205 puts [format "The button is %s" $x]
5208 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
5209 button, and its object commands are invoked the same way.
5212 str912.cpu mww 0x1234 0x42
5213 omap3530.cpu mww 0x5555 123
5216 The commands supported by OpenOCD target objects are:
5218 @deffn {Command} {$target_name arp_examine} @option{allow-defer}
5219 @deffnx {Command} {$target_name arp_halt}
5220 @deffnx {Command} {$target_name arp_poll}
5221 @deffnx {Command} {$target_name arp_reset}
5222 @deffnx {Command} {$target_name arp_waitstate}
5223 Internal OpenOCD scripts (most notably @file{startup.tcl})
5224 use these to deal with specific reset cases.
5225 They are not otherwise documented here.
5228 @deffn {Command} {$target_name set_reg} dict
5229 Set register values of the target.
5232 @item @var{dict} ... Tcl dictionary with pairs of register names and values.
5235 For example, the following command sets the value 0 to the program counter (pc)
5236 register and 0x1000 to the stack pointer (sp) register:
5239 set_reg @{pc 0 sp 0x1000@}
5243 @deffn {Command} {$target_name get_reg} [-force] list
5244 Get register values from the target and return them as Tcl dictionary with pairs
5245 of register names and values.
5246 If option "-force" is set, the register values are read directly from the
5247 target, bypassing any caching.
5250 @item @var{list} ... List of register names
5253 For example, the following command retrieves the values from the program
5254 counter (pc) and stack pointer (sp) register:
5261 @deffn {Command} {$target_name write_memory} address width data ['phys']
5262 This function provides an efficient way to write to the target memory from a Tcl
5266 @item @var{address} ... target memory address
5267 @item @var{width} ... memory access bit size, can be 8, 16, 32 or 64
5268 @item @var{data} ... Tcl list with the elements to write
5269 @item ['phys'] ... treat the memory address as physical instead of virtual address
5272 For example, the following command writes two 32 bit words into the target
5273 memory at address 0x20000000:
5276 write_memory 0x20000000 32 @{0xdeadbeef 0x00230500@}
5280 @deffn {Command} {$target_name read_memory} address width count ['phys']
5281 This function provides an efficient way to read the target memory from a Tcl
5283 A Tcl list containing the requested memory elements is returned by this function.
5286 @item @var{address} ... target memory address
5287 @item @var{width} ... memory access bit size, can be 8, 16, 32 or 64
5288 @item @var{count} ... number of elements to read
5289 @item ['phys'] ... treat the memory address as physical instead of virtual address
5292 For example, the following command reads two 32 bit words from the target
5293 memory at address 0x20000000:
5296 read_memory 0x20000000 32 2
5300 @deffn {Command} {$target_name cget} queryparm
5301 Each configuration parameter accepted by
5302 @command{$target_name configure}
5303 can be individually queried, to return its current value.
5304 The @var{queryparm} is a parameter name
5305 accepted by that command, such as @code{-work-area-phys}.
5306 There are a few special cases:
5309 @item @code{-event} @var{event_name} -- returns the handler for the
5310 event named @var{event_name}.
5311 This is a special case because setting a handler requires
5313 @item @code{-type} -- returns the target type.
5314 This is a special case because this is set using
5315 @command{target create} and can't be changed
5316 using @command{$target_name configure}.
5319 For example, if you wanted to summarize information about
5320 all the targets you might use something like this:
5323 foreach name [target names] @{
5324 set y [$name cget -endian]
5325 set z [$name cget -type]
5326 puts [format "Chip %d is %s, Endian: %s, type: %s" \
5332 @anchor{targetcurstate}
5333 @deffn {Command} {$target_name curstate}
5334 Displays the current target state:
5335 @code{debug-running},
5338 @code{running}, or @code{unknown}.
5339 (Also, @pxref{eventpolling,,Event Polling}.)
5342 @deffn {Command} {$target_name debug_reason}
5343 Displays the current debug reason:
5344 @code{debug-request},
5347 @code{watchpoint-and-breakpoint},
5349 @code{target-not-halted},
5350 @code{program-exit},
5351 @code{exception-catch} or @code{undefined}.
5354 @deffn {Command} {$target_name eventlist}
5355 Displays a table listing all event handlers
5356 currently associated with this target.
5357 @xref{targetevents,,Target Events}.
5360 @deffn {Command} {$target_name invoke-event} event_name
5361 Invokes the handler for the event named @var{event_name}.
5362 (This is primarily intended for use by OpenOCD framework
5363 code, for example by the reset code in @file{startup.tcl}.)
5366 @deffn {Command} {$target_name mdd} [phys] addr [count]
5367 @deffnx {Command} {$target_name mdw} [phys] addr [count]
5368 @deffnx {Command} {$target_name mdh} [phys] addr [count]
5369 @deffnx {Command} {$target_name mdb} [phys] addr [count]
5370 Display contents of address @var{addr}, as
5371 64-bit doublewords (@command{mdd}),
5372 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
5373 or 8-bit bytes (@command{mdb}).
5374 When the current target has an MMU which is present and active,
5375 @var{addr} is interpreted as a virtual address.
5376 Otherwise, or if the optional @var{phys} flag is specified,
5377 @var{addr} is interpreted as a physical address.
5378 If @var{count} is specified, displays that many units.
5379 (If you want to process the data instead of displaying it,
5380 see the @code{read_memory} primitives.)
5383 @deffn {Command} {$target_name mwd} [phys] addr doubleword [count]
5384 @deffnx {Command} {$target_name mww} [phys] addr word [count]
5385 @deffnx {Command} {$target_name mwh} [phys] addr halfword [count]
5386 @deffnx {Command} {$target_name mwb} [phys] addr byte [count]
5387 Writes the specified @var{doubleword} (64 bits), @var{word} (32 bits),
5388 @var{halfword} (16 bits), or @var{byte} (8-bit) value,
5389 at the specified address @var{addr}.
5390 When the current target has an MMU which is present and active,
5391 @var{addr} is interpreted as a virtual address.
5392 Otherwise, or if the optional @var{phys} flag is specified,
5393 @var{addr} is interpreted as a physical address.
5394 If @var{count} is specified, fills that many units of consecutive address.
5397 @anchor{targetevents}
5398 @section Target Events
5399 @cindex target events
5401 At various times, certain things can happen, or you want them to happen.
5404 @item What should happen when GDB connects? Should your target reset?
5405 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
5406 @item Is using SRST appropriate (and possible) on your system?
5407 Or instead of that, do you need to issue JTAG commands to trigger reset?
5408 SRST usually resets everything on the scan chain, which can be inappropriate.
5409 @item During reset, do you need to write to certain memory locations
5410 to set up system clocks or
5411 to reconfigure the SDRAM?
5412 How about configuring the watchdog timer, or other peripherals,
5413 to stop running while you hold the core stopped for debugging?
5416 All of the above items can be addressed by target event handlers.
5417 These are set up by @command{$target_name configure -event} or
5418 @command{target create ... -event}.
5420 The programmer's model matches the @code{-command} option used in Tcl/Tk
5421 buttons and events. The two examples below act the same, but one creates
5422 and invokes a small procedure while the other inlines it.
5425 proc my_init_proc @{ @} @{
5426 echo "Disabling watchdog..."
5427 mww 0xfffffd44 0x00008000
5429 mychip.cpu configure -event reset-init my_init_proc
5430 mychip.cpu configure -event reset-init @{
5431 echo "Disabling watchdog..."
5432 mww 0xfffffd44 0x00008000
5436 The following target events are defined:
5439 @item @b{debug-halted}
5440 @* The target has halted for debug reasons (i.e.: breakpoint)
5441 @item @b{debug-resumed}
5442 @* The target has resumed (i.e.: GDB said run)
5443 @item @b{early-halted}
5444 @* Occurs early in the halt process
5445 @item @b{examine-start}
5446 @* Before target examine is called.
5447 @item @b{examine-end}
5448 @* After target examine is called with no errors.
5449 @item @b{examine-fail}
5450 @* After target examine fails.
5451 @item @b{gdb-attach}
5452 @* When GDB connects. Issued before any GDB communication with the target
5453 starts. GDB expects the target is halted during attachment.
5454 @xref{gdbmeminspect,,GDB as a non-intrusive memory inspector}, how to
5455 connect GDB to running target.
5456 The event can be also used to set up the target so it is possible to probe flash.
5457 Probing flash is necessary during GDB connect if you want to use
5458 @pxref{programmingusinggdb,,programming using GDB}.
5459 Another use of the flash memory map is for GDB to automatically choose
5460 hardware or software breakpoints depending on whether the breakpoint
5461 is in RAM or read only memory.
5462 Default is @code{halt}
5463 @item @b{gdb-detach}
5464 @* When GDB disconnects
5466 @* When the target has halted and GDB is not doing anything (see early halt)
5467 @item @b{gdb-flash-erase-start}
5468 @* Before the GDB flash process tries to erase the flash (default is
5470 @item @b{gdb-flash-erase-end}
5471 @* After the GDB flash process has finished erasing the flash
5472 @item @b{gdb-flash-write-start}
5473 @* Before GDB writes to the flash
5474 @item @b{gdb-flash-write-end}
5475 @* After GDB writes to the flash (default is @code{reset halt})
5477 @* Before the target steps, GDB is trying to start/resume the target
5479 @* The target has halted
5480 @item @b{reset-assert-pre}
5481 @* Issued as part of @command{reset} processing
5482 after @command{reset-start} was triggered
5483 but before either SRST alone is asserted on the scan chain,
5484 or @code{reset-assert} is triggered.
5485 @item @b{reset-assert}
5486 @* Issued as part of @command{reset} processing
5487 after @command{reset-assert-pre} was triggered.
5488 When such a handler is present, cores which support this event will use
5489 it instead of asserting SRST.
5490 This support is essential for debugging with JTAG interfaces which
5491 don't include an SRST line (JTAG doesn't require SRST), and for
5492 selective reset on scan chains that have multiple targets.
5493 @item @b{reset-assert-post}
5494 @* Issued as part of @command{reset} processing
5495 after @code{reset-assert} has been triggered.
5496 or the target asserted SRST on the entire scan chain.
5497 @item @b{reset-deassert-pre}
5498 @* Issued as part of @command{reset} processing
5499 after @code{reset-assert-post} has been triggered.
5500 @item @b{reset-deassert-post}
5501 @* Issued as part of @command{reset} processing
5502 after @code{reset-deassert-pre} has been triggered
5503 and (if the target is using it) after SRST has been
5504 released on the scan chain.
5506 @* Issued as the final step in @command{reset} processing.
5507 @item @b{reset-init}
5508 @* Used by @b{reset init} command for board-specific initialization.
5509 This event fires after @emph{reset-deassert-post}.
5511 This is where you would configure PLLs and clocking, set up DRAM so
5512 you can download programs that don't fit in on-chip SRAM, set up pin
5513 multiplexing, and so on.
5514 (You may be able to switch to a fast JTAG clock rate here, after
5515 the target clocks are fully set up.)
5516 @item @b{reset-start}
5517 @* Issued as the first step in @command{reset} processing
5518 before @command{reset-assert-pre} is called.
5520 This is the most robust place to use @command{jtag_rclk}
5521 or @command{adapter speed} to switch to a low JTAG clock rate,
5522 when reset disables PLLs needed to use a fast clock.
5523 @item @b{resume-start}
5524 @* Before any target is resumed
5525 @item @b{resume-end}
5526 @* After all targets have resumed
5528 @* Target has resumed
5529 @item @b{step-start}
5530 @* Before a target is single-stepped
5532 @* After single-step has completed
5533 @item @b{trace-config}
5534 @* After target hardware trace configuration was changed
5535 @item @b{semihosting-user-cmd-0x100}
5536 @* The target made a semihosting call with user-defined operation number 0x100
5537 @item @b{semihosting-user-cmd-0x101}
5538 @* The target made a semihosting call with user-defined operation number 0x101
5539 @item @b{semihosting-user-cmd-0x102}
5540 @* The target made a semihosting call with user-defined operation number 0x102
5541 @item @b{semihosting-user-cmd-0x103}
5542 @* The target made a semihosting call with user-defined operation number 0x103
5543 @item @b{semihosting-user-cmd-0x104}
5544 @* The target made a semihosting call with user-defined operation number 0x104
5545 @item @b{semihosting-user-cmd-0x105}
5546 @* The target made a semihosting call with user-defined operation number 0x105
5547 @item @b{semihosting-user-cmd-0x106}
5548 @* The target made a semihosting call with user-defined operation number 0x106
5549 @item @b{semihosting-user-cmd-0x107}
5550 @* The target made a semihosting call with user-defined operation number 0x107
5554 OpenOCD events are not supposed to be preempt by another event, but this
5555 is not enforced in current code. Only the target event @b{resumed} is
5556 executed with polling disabled; this avoids polling to trigger the event
5557 @b{halted}, reversing the logical order of execution of their handlers.
5558 Future versions of OpenOCD will prevent the event preemption and will
5559 disable the schedule of polling during the event execution. Do not rely
5560 on polling in any event handler; this means, don't expect the status of
5561 a core to change during the execution of the handler. The event handler
5562 will have to enable polling or use @command{$target_name arp_poll} to
5563 check if the core has changed status.
5566 @node Flash Commands
5567 @chapter Flash Commands
5569 OpenOCD has different commands for NOR and NAND flash;
5570 the ``flash'' command works with NOR flash, while
5571 the ``nand'' command works with NAND flash.
5572 This partially reflects different hardware technologies:
5573 NOR flash usually supports direct CPU instruction and data bus access,
5574 while data from a NAND flash must be copied to memory before it can be
5575 used. (SPI flash must also be copied to memory before use.)
5576 However, the documentation also uses ``flash'' as a generic term;
5577 for example, ``Put flash configuration in board-specific files''.
5581 @item Configure via the command @command{flash bank}
5582 @* Do this in a board-specific configuration file,
5583 passing parameters as needed by the driver.
5584 @item Operate on the flash via @command{flash subcommand}
5585 @* Often commands to manipulate the flash are typed by a human, or run
5586 via a script in some automated way. Common tasks include writing a
5587 boot loader, operating system, or other data.
5589 @* Flashing via GDB requires the flash be configured via ``flash
5590 bank'', and the GDB flash features be enabled.
5591 @xref{gdbconfiguration,,GDB Configuration}.
5594 Many CPUs have the ability to ``boot'' from the first flash bank.
5595 This means that misprogramming that bank can ``brick'' a system,
5596 so that it can't boot.
5597 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
5598 board by (re)installing working boot firmware.
5600 @anchor{norconfiguration}
5601 @section Flash Configuration Commands
5602 @cindex flash configuration
5604 @deffn {Config Command} {flash bank} name driver base size chip_width bus_width target [driver_options]
5605 Configures a flash bank which provides persistent storage
5606 for addresses from @math{base} to @math{base + size - 1}.
5607 These banks will often be visible to GDB through the target's memory map.
5608 In some cases, configuring a flash bank will activate extra commands;
5609 see the driver-specific documentation.
5612 @item @var{name} ... may be used to reference the flash bank
5613 in other flash commands. A number is also available.
5614 @item @var{driver} ... identifies the controller driver
5615 associated with the flash bank being declared.
5616 This is usually @code{cfi} for external flash, or else
5617 the name of a microcontroller with embedded flash memory.
5618 @xref{flashdriverlist,,Flash Driver List}.
5619 @item @var{base} ... Base address of the flash chip.
5620 @item @var{size} ... Size of the chip, in bytes.
5621 For some drivers, this value is detected from the hardware.
5622 @item @var{chip_width} ... Width of the flash chip, in bytes;
5623 ignored for most microcontroller drivers.
5624 @item @var{bus_width} ... Width of the data bus used to access the
5625 chip, in bytes; ignored for most microcontroller drivers.
5626 @item @var{target} ... Names the target used to issue
5627 commands to the flash controller.
5628 @comment Actually, it's currently a controller-specific parameter...
5629 @item @var{driver_options} ... drivers may support, or require,
5630 additional parameters. See the driver-specific documentation
5631 for more information.
5634 This command is not available after OpenOCD initialization has completed.
5635 Use it in board specific configuration files, not interactively.
5639 @comment less confusing would be: "flash list" (like "nand list")
5640 @deffn {Command} {flash banks}
5641 Prints a one-line summary of each device that was
5642 declared using @command{flash bank}, numbered from zero.
5643 Note that this is the @emph{plural} form;
5644 the @emph{singular} form is a very different command.
5647 @deffn {Command} {flash list}
5648 Retrieves a list of associative arrays for each device that was
5649 declared using @command{flash bank}, numbered from zero.
5650 This returned list can be manipulated easily from within scripts.
5653 @deffn {Command} {flash probe} num
5654 Identify the flash, or validate the parameters of the configured flash. Operation
5655 depends on the flash type.
5656 The @var{num} parameter is a value shown by @command{flash banks}.
5657 Most flash commands will implicitly @emph{autoprobe} the bank;
5658 flash drivers can distinguish between probing and autoprobing,
5659 but most don't bother.
5662 @section Preparing a Target before Flash Programming
5664 The target device should be in well defined state before the flash programming
5667 @emph{Always issue} @command{reset init} before @ref{flashprogrammingcommands,,Flash Programming Commands}.
5668 Do not issue another @command{reset} or @command{reset halt} or @command{resume}
5669 until the programming session is finished.
5671 If you use @ref{programmingusinggdb,,Programming using GDB},
5672 the target is prepared automatically in the event gdb-flash-erase-start
5674 The jimtcl script @command{program} calls @command{reset init} explicitly.
5676 @section Erasing, Reading, Writing to Flash
5677 @cindex flash erasing
5678 @cindex flash reading
5679 @cindex flash writing
5680 @cindex flash programming
5681 @anchor{flashprogrammingcommands}
5683 One feature distinguishing NOR flash from NAND or serial flash technologies
5684 is that for read access, it acts exactly like any other addressable memory.
5685 This means you can use normal memory read commands like @command{mdw} or
5686 @command{dump_image} with it, with no special @command{flash} subcommands.
5687 @xref{memoryaccess,,Memory access}, and @ref{imageaccess,,Image access}.
5689 Write access works differently. Flash memory normally needs to be erased
5690 before it's written. Erasing a sector turns all of its bits to ones, and
5691 writing can turn ones into zeroes. This is why there are special commands
5692 for interactive erasing and writing, and why GDB needs to know which parts
5693 of the address space hold NOR flash memory.
5696 Most of these erase and write commands leverage the fact that NOR flash
5697 chips consume target address space. They implicitly refer to the current
5698 JTAG target, and map from an address in that target's address space
5699 back to a flash bank.
5700 @comment In May 2009, those mappings may fail if any bank associated
5701 @comment with that target doesn't successfully autoprobe ... bug worth fixing?
5702 A few commands use abstract addressing based on bank and sector numbers,
5703 and don't depend on searching the current target and its address space.
5704 Avoid confusing the two command models.
5707 Some flash chips implement software protection against accidental writes,
5708 since such buggy writes could in some cases ``brick'' a system.
5709 For such systems, erasing and writing may require sector protection to be
5711 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
5712 and AT91SAM7 on-chip flash.
5713 @xref{flashprotect,,flash protect}.
5715 @deffn {Command} {flash erase_sector} num first last
5716 Erase sectors in bank @var{num}, starting at sector @var{first}
5717 up to and including @var{last}.
5718 Sector numbering starts at 0.
5719 Providing a @var{last} sector of @option{last}
5720 specifies "to the end of the flash bank".
5721 The @var{num} parameter is a value shown by @command{flash banks}.
5724 @deffn {Command} {flash erase_address} [@option{pad}] [@option{unlock}] address length
5725 Erase sectors starting at @var{address} for @var{length} bytes.
5726 Unless @option{pad} is specified, @math{address} must begin a
5727 flash sector, and @math{address + length - 1} must end a sector.
5728 Specifying @option{pad} erases extra data at the beginning and/or
5729 end of the specified region, as needed to erase only full sectors.
5730 The flash bank to use is inferred from the @var{address}, and
5731 the specified length must stay within that bank.
5732 As a special case, when @var{length} is zero and @var{address} is
5733 the start of the bank, the whole flash is erased.
5734 If @option{unlock} is specified, then the flash is unprotected
5735 before erase starts.
5738 @deffn {Command} {flash filld} address double-word length
5739 @deffnx {Command} {flash fillw} address word length
5740 @deffnx {Command} {flash fillh} address halfword length
5741 @deffnx {Command} {flash fillb} address byte length
5742 Fills flash memory with the specified @var{double-word} (64 bits), @var{word} (32 bits),
5743 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
5744 starting at @var{address} and continuing
5745 for @var{length} units (word/halfword/byte).
5746 No erasure is done before writing; when needed, that must be done
5747 before issuing this command.
5748 Writes are done in blocks of up to 1024 bytes, and each write is
5749 verified by reading back the data and comparing it to what was written.
5750 The flash bank to use is inferred from the @var{address} of
5751 each block, and the specified length must stay within that bank.
5753 @comment no current checks for errors if fill blocks touch multiple banks!
5755 @deffn {Command} {flash mdw} addr [count]
5756 @deffnx {Command} {flash mdh} addr [count]
5757 @deffnx {Command} {flash mdb} addr [count]
5758 Display contents of address @var{addr}, as
5759 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
5760 or 8-bit bytes (@command{mdb}).
5761 If @var{count} is specified, displays that many units.
5762 Reads from flash using the flash driver, therefore it enables reading
5763 from a bank not mapped in target address space.
5764 The flash bank to use is inferred from the @var{address} of
5765 each block, and the specified length must stay within that bank.
5768 @deffn {Command} {flash write_bank} num filename [offset]
5769 Write the binary @file{filename} to flash bank @var{num},
5770 starting at @var{offset} bytes from the beginning of the bank. If @var{offset}
5771 is omitted, start at the beginning of the flash bank.
5772 The @var{num} parameter is a value shown by @command{flash banks}.
5775 @deffn {Command} {flash read_bank} num filename [offset [length]]
5776 Read @var{length} bytes from the flash bank @var{num} starting at @var{offset}
5777 and write the contents to the binary @file{filename}. If @var{offset} is
5778 omitted, start at the beginning of the flash bank. If @var{length} is omitted,
5779 read the remaining bytes from the flash bank.
5780 The @var{num} parameter is a value shown by @command{flash banks}.
5783 @deffn {Command} {flash verify_bank} num filename [offset]
5784 Compare the contents of the binary file @var{filename} with the contents of the
5785 flash bank @var{num} starting at @var{offset}. If @var{offset} is omitted,
5786 start at the beginning of the flash bank. Fail if the contents do not match.
5787 The @var{num} parameter is a value shown by @command{flash banks}.
5790 @deffn {Command} {flash write_image} [erase] [unlock] filename [offset] [type]
5791 Write the image @file{filename} to the current target's flash bank(s).
5792 Only loadable sections from the image are written.
5793 A relocation @var{offset} may be specified, in which case it is added
5794 to the base address for each section in the image.
5795 The file [@var{type}] can be specified
5796 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
5797 @option{elf} (ELF file), @option{s19} (Motorola s19).
5798 @option{mem}, or @option{builder}.
5799 The relevant flash sectors will be erased prior to programming
5800 if the @option{erase} parameter is given. If @option{unlock} is
5801 provided, then the flash banks are unlocked before erase and
5802 program. The flash bank to use is inferred from the address of
5806 Be careful using the @option{erase} flag when the flash is holding
5807 data you want to preserve.
5808 Portions of the flash outside those described in the image's
5809 sections might be erased with no notice.
5812 When a section of the image being written does not fill out all the
5813 sectors it uses, the unwritten parts of those sectors are necessarily
5814 also erased, because sectors can't be partially erased.
5816 Data stored in sector "holes" between image sections are also affected.
5817 For example, "@command{flash write_image erase ...}" of an image with
5818 one byte at the beginning of a flash bank and one byte at the end
5819 erases the entire bank -- not just the two sectors being written.
5821 Also, when flash protection is important, you must re-apply it after
5822 it has been removed by the @option{unlock} flag.
5827 @deffn {Command} {flash verify_image} filename [offset] [type]
5828 Verify the image @file{filename} to the current target's flash bank(s).
5829 Parameters follow the description of 'flash write_image'.
5830 In contrast to the 'verify_image' command, for banks with specific
5831 verify method, that one is used instead of the usual target's read
5832 memory methods. This is necessary for flash banks not readable by
5833 ordinary memory reads.
5834 This command gives only an overall good/bad result for each bank, not
5835 addresses of individual failed bytes as it's intended only as quick
5836 check for successful programming.
5839 @section Other Flash commands
5840 @cindex flash protection
5842 @deffn {Command} {flash erase_check} num
5843 Check erase state of sectors in flash bank @var{num},
5844 and display that status.
5845 The @var{num} parameter is a value shown by @command{flash banks}.
5848 @deffn {Command} {flash info} num [sectors]
5849 Print info about flash bank @var{num}, a list of protection blocks
5850 and their status. Use @option{sectors} to show a list of sectors instead.
5852 The @var{num} parameter is a value shown by @command{flash banks}.
5853 This command will first query the hardware, it does not print cached
5854 and possibly stale information.
5857 @anchor{flashprotect}
5858 @deffn {Command} {flash protect} num first last (@option{on}|@option{off})
5859 Enable (@option{on}) or disable (@option{off}) protection of flash blocks
5860 in flash bank @var{num}, starting at protection block @var{first}
5861 and continuing up to and including @var{last}.
5862 Providing a @var{last} block of @option{last}
5863 specifies "to the end of the flash bank".
5864 The @var{num} parameter is a value shown by @command{flash banks}.
5865 The protection block is usually identical to a flash sector.
5866 Some devices may utilize a protection block distinct from flash sector.
5867 See @command{flash info} for a list of protection blocks.
5870 @deffn {Command} {flash padded_value} num value
5871 Sets the default value used for padding any image sections, This should
5872 normally match the flash bank erased value. If not specified by this
5873 command or the flash driver then it defaults to 0xff.
5877 @deffn {Command} {program} filename [preverify] [verify] [reset] [exit] [offset]
5878 This is a helper script that simplifies using OpenOCD as a standalone
5879 programmer. The only required parameter is @option{filename}, the others are optional.
5880 @xref{Flash Programming}.
5883 @anchor{flashdriverlist}
5884 @section Flash Driver List
5885 As noted above, the @command{flash bank} command requires a driver name,
5886 and allows driver-specific options and behaviors.
5887 Some drivers also activate driver-specific commands.
5889 @deffn {Flash Driver} {virtual}
5890 This is a special driver that maps a previously defined bank to another
5891 address. All bank settings will be copied from the master physical bank.
5893 The @var{virtual} driver defines one mandatory parameters,
5896 @item @var{master_bank} The bank that this virtual address refers to.
5899 So in the following example addresses 0xbfc00000 and 0x9fc00000 refer to
5900 the flash bank defined at address 0x1fc00000. Any command executed on
5901 the virtual banks is actually performed on the physical banks.
5903 flash bank $_FLASHNAME pic32mx 0x1fc00000 0 0 0 $_TARGETNAME
5904 flash bank vbank0 virtual 0xbfc00000 0 0 0 \
5905 $_TARGETNAME $_FLASHNAME
5906 flash bank vbank1 virtual 0x9fc00000 0 0 0 \
5907 $_TARGETNAME $_FLASHNAME
5911 @subsection External Flash
5913 @deffn {Flash Driver} {cfi}
5914 @cindex Common Flash Interface
5916 The ``Common Flash Interface'' (CFI) is the main standard for
5917 external NOR flash chips, each of which connects to a
5918 specific external chip select on the CPU.
5919 Frequently the first such chip is used to boot the system.
5920 Your board's @code{reset-init} handler might need to
5921 configure additional chip selects using other commands (like: @command{mww} to
5922 configure a bus and its timings), or
5923 perhaps configure a GPIO pin that controls the ``write protect'' pin
5925 The CFI driver can use a target-specific working area to significantly
5928 The CFI driver can accept the following optional parameters, in any order:
5931 @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
5932 like AM29LV010 and similar types.
5933 @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
5934 @item @var{bus_swap} ... when data bytes in a 16-bit flash needs to be swapped.
5935 @item @var{data_swap} ... when data bytes in a 16-bit flash needs to be
5936 swapped when writing data values (i.e. not CFI commands).
5939 To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
5940 wide on a sixteen bit bus:
5943 flash bank $_FLASHNAME cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
5944 flash bank $_FLASHNAME cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
5947 To configure one bank of 32 MBytes
5948 built from two sixteen bit (two byte) wide parts wired in parallel
5949 to create a thirty-two bit (four byte) bus with doubled throughput:
5952 flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
5955 @c "cfi part_id" disabled
5959 @deffn {Flash Driver} {jtagspi}
5960 @cindex Generic JTAG2SPI driver
5964 Several FPGAs and CPLDs can retrieve their configuration (bitstream) from a
5965 SPI flash connected to them. To access this flash from the host, some FPGA
5966 device provides dedicated JTAG instructions, while other FPGA devices should
5967 be programmed with a special proxy bitstream that exposes the SPI flash on
5968 the device's JTAG interface. The flash can then be accessed through JTAG.
5970 Since signalling between JTAG and SPI is compatible, all that is required for
5971 a proxy bitstream is to connect TDI-MOSI, TDO-MISO, TCK-CLK and activate
5972 the flash chip select when the JTAG state machine is in SHIFT-DR.
5974 Such a bitstream for several Xilinx FPGAs can be found in
5975 @file{contrib/loaders/flash/fpga/xilinx_bscan_spi.py}. It requires
5976 @uref{https://github.com/m-labs/migen, migen} and a Xilinx toolchain to build.
5978 This mechanism with a proxy bitstream can also be used for FPGAs from Intel and
5979 Efinix. FPGAs from Lattice and Cologne Chip have dedicated JTAG instructions
5980 and procedure to connect the JTAG to the SPI signals and don't need a proxy
5981 bitstream. Support for these devices with dedicated procedure is provided by
5982 the pld drivers. For convenience the PLD drivers will provide the USERx code
5983 for FPGAs with a proxy bitstream. Currently the following PLD drivers are able
5986 @item Efinix: proxy-bitstream
5987 @item Gatemate: dedicated procedure
5988 @item Intel/Altera: proxy-bitstream
5989 @item Lattice: dedicated procedure supporting ECP2, ECP3, ECP5, Certus and Certus Pro devices
5990 @item AMD/Xilinx: proxy-bitstream
5994 This flash bank driver requires a target on a JTAG tap and will access that
5995 tap directly. Since no support from the target is needed, the target can be a
5996 "testee" dummy. Since the target does not expose the flash memory
5997 mapping, target commands that would otherwise be expected to access the flash
5998 will not work. These include all @command{*_image} and
5999 @command{$target_name m*} commands as well as @command{program}. Equivalent
6000 functionality is available through the @command{flash write_bank},
6001 @command{flash read_bank}, and @command{flash verify_bank} commands.
6003 According to device size, 1- to 4-byte addresses are sent. However, some
6004 flash chips additionally have to be switched to 4-byte addresses by an extra
6008 @item @var{ir} ... is loaded into the JTAG IR to map the flash as the JTAG DR.
6009 For the bitstreams generated from @file{xilinx_bscan_spi.py} this is the
6010 @var{USER1} instruction.
6012 target create $_TARGETNAME testee -chain-position $_CHIPNAME.tap
6013 set _USER1_INSTR_CODE 0x02
6014 flash bank $_FLASHNAME jtagspi 0x0 0 0 0 \
6015 $_TARGETNAME $_USER1_INSTR_CODE
6018 @item The option @option{-pld} @var{name} is used to have support from the
6019 PLD driver of pld device @var{name}. The name is the name of the pld device
6020 given during creation of the pld device.
6021 Pld device names are shown by the @command{pld devices} command.
6024 target create $_TARGETNAME testee -chain-position $_CHIPNAME.tap
6025 set _JTAGSPI_CHAIN_ID $_CHIPNAME.pld
6026 flash bank $_FLASHNAME jtagspi 0x0 0 0 0 \
6027 $_TARGETNAME -pld $_JTAGSPI_CHAIN_ID
6031 @deffn Command {jtagspi set} bank_id name total_size page_size read_cmd unused pprg_cmd mass_erase_cmd sector_size sector_erase_cmd
6032 Sets flash parameters: @var{name} human readable string, @var{total_size}
6033 size in bytes, @var{page_size} is write page size. @var{read_cmd} and @var{pprg_cmd}
6034 are commands for read and page program, respectively. @var{mass_erase_cmd},
6035 @var{sector_size} and @var{sector_erase_cmd} are optional.
6037 jtagspi set 0 w25q128 0x1000000 0x100 0x03 0 0x02 0xC7 0x10000 0xD8
6041 @deffn Command {jtagspi cmd} bank_id resp_num cmd_byte ...
6042 Sends command @var{cmd_byte} and at most 20 following bytes and reads
6043 @var{resp_num} bytes afterwards. E.g. for 'Enter 4-byte address mode'
6045 jtagspi cmd 0 0 0xB7
6049 @deffn Command {jtagspi always_4byte} bank_id [ on | off ]
6050 Some devices use 4-byte addresses for all commands except the legacy 0x03 read
6051 regardless of device size. This command controls the corresponding hack.
6055 @deffn {Flash Driver} {xcf}
6056 @cindex Xilinx Platform flash driver
6058 Xilinx FPGAs can be configured from specialized flash ICs named Platform Flash.
6059 It is (almost) regular NOR flash with erase sectors, program pages, etc. The
6060 only difference is special registers controlling its FPGA specific behavior.
6061 They must be properly configured for successful FPGA loading using
6062 additional @var{xcf} driver command:
6064 @deffn {Command} {xcf ccb} <bank_id>
6065 command accepts additional parameters:
6067 @item @var{external|internal} ... selects clock source.
6068 @item @var{serial|parallel} ... selects serial or parallel data bus mode.
6069 @item @var{slave|master} ... selects slave of master mode for flash device.
6070 @item @var{40|20} ... selects clock frequency in MHz for internal clock
6074 xcf ccb 0 external parallel slave 40
6076 All of them must be specified even if clock frequency is pointless
6077 in slave mode. If only bank id specified than command prints current
6078 CCB register value. Note: there is no need to write this register
6079 every time you erase/program data sectors because it stores in
6083 @deffn {Command} {xcf configure} <bank_id>
6084 Initiates FPGA loading procedure. Useful if your board has no "configure"
6091 Additional driver notes:
6093 @item Only single revision supported.
6094 @item Driver automatically detects need of bit reverse, but
6095 only "bin" (raw binary, do not confuse it with "bit") and "mcs"
6096 (Intel hex) file types supported.
6097 @item For additional info check xapp972.pdf and ug380.pdf.
6101 @deffn {Flash Driver} {lpcspifi}
6102 @cindex NXP SPI Flash Interface
6105 NXP's LPC43xx and LPC18xx families include a proprietary SPI
6106 Flash Interface (SPIFI) peripheral that can drive and provide
6107 memory mapped access to external SPI flash devices.
6109 The lpcspifi driver initializes this interface and provides
6110 program and erase functionality for these serial flash devices.
6111 Use of this driver @b{requires} a working area of at least 1kB
6112 to be configured on the target device; more than this will
6113 significantly reduce flash programming times.
6115 The setup command only requires the @var{base} parameter. All
6116 other parameters are ignored, and the flash size and layout
6117 are configured by the driver.
6120 flash bank $_FLASHNAME lpcspifi 0x14000000 0 0 0 $_TARGETNAME
6125 @deffn {Flash Driver} {stmsmi}
6126 @cindex STMicroelectronics Serial Memory Interface
6129 Some devices from STMicroelectronics (e.g. STR75x MCU family,
6130 SPEAr MPU family) include a proprietary
6131 ``Serial Memory Interface'' (SMI) controller able to drive external
6133 Depending on specific device and board configuration, up to 4 external
6134 flash devices can be connected.
6136 SMI makes the flash content directly accessible in the CPU address
6137 space; each external device is mapped in a memory bank.
6138 CPU can directly read data, execute code and boot from SMI banks.
6139 Normal OpenOCD commands like @command{mdw} can be used to display
6142 The setup command only requires the @var{base} parameter in order
6143 to identify the memory bank.
6144 All other parameters are ignored. Additional information, like
6145 flash size, are detected automatically.
6148 flash bank $_FLASHNAME stmsmi 0xf8000000 0 0 0 $_TARGETNAME
6153 @deffn {Flash Driver} {stmqspi}
6154 @cindex STMicroelectronics QuadSPI/OctoSPI Interface
6158 Some devices from STMicroelectronics include a proprietary ``QuadSPI Interface''
6159 (e.g. STM32F4, STM32F7, STM32L4) or ``OctoSPI Interface'' (e.g. STM32L4+)
6160 controller able to drive one or even two (dual mode) external SPI flash devices.
6161 The OctoSPI is a superset of QuadSPI, its presence is detected automatically.
6162 Currently only the regular command mode is supported, whereas the HyperFlash
6165 QuadSPI/OctoSPI makes the flash contents directly accessible in the CPU address
6166 space; in case of dual mode both devices must be of the same type and are
6167 mapped in the same memory bank (even and odd addresses interleaved).
6168 CPU can directly read data, execute code (but not boot) from QuadSPI bank.
6170 The 'flash bank' command only requires the @var{base} parameter and the extra
6171 parameter @var{io_base} in order to identify the memory bank. Both are fixed
6172 by hardware, see datasheet or RM. All other parameters are ignored.
6174 The controller must be initialized after each reset and properly configured
6175 for memory-mapped read operation for the particular flash chip(s), for the full
6176 list of available register settings cf. the controller's RM. This setup is quite
6177 board specific (that's why booting from this memory is not possible). The
6178 flash driver infers all parameters from current controller register values when
6179 'flash probe @var{bank_id}' is executed.
6181 Normal OpenOCD commands like @command{mdw} can be used to display the flash content,
6182 but only after proper controller initialization as described above. However,
6183 due to a silicon bug in some devices, attempting to access the very last word
6186 It is possible to use two (even different) flash chips alternatingly, if individual
6187 bank chip selects are available. For some package variants, this is not the case
6188 due to limited pin count. To switch from one to another, adjust FSEL bit accordingly
6189 and re-issue 'flash probe bank_id'. Note that the bank base address will @emph{not}
6190 change, so the address spaces of both devices will overlap. In dual flash mode
6191 both chips must be identical regarding size and most other properties.
6193 Block or sector protection internal to the flash chip is not handled by this
6194 driver at all, but can be dealt with manually by the 'cmd' command, see below.
6195 The sector protection via 'flash protect' command etc. is completely internal to
6196 openocd, intended only to prevent accidental erase or overwrite and it does not
6197 persist across openocd invocations.
6199 OpenOCD contains a hardcoded list of flash devices with their properties,
6200 these are auto-detected. If a device is not included in this list, SFDP discovery
6201 is attempted. If this fails or gives inappropriate results, manual setting is
6202 required (see 'set' command).
6205 flash bank $_FLASHNAME stmqspi 0x90000000 0 0 0 \
6206 $_TARGETNAME 0xA0001000
6207 flash bank $_FLASHNAME stmqspi 0x70000000 0 0 0 \
6208 $_TARGETNAME 0xA0001400
6211 There are three specific commands
6212 @deffn {Command} {stmqspi mass_erase} bank_id
6213 Clears sector protections and performs a mass erase. Works only if there is no
6214 chip specific write protection engaged.
6217 @deffn {Command} {stmqspi set} bank_id name total_size page_size read_cmd fread_cmd pprg_cmd mass_erase_cmd sector_size sector_erase_cmd
6218 Set flash parameters: @var{name} human readable string, @var{total_size} size
6219 in bytes, @var{page_size} is write page size. @var{read_cmd}, @var{fread_cmd} and @var{pprg_cmd}
6220 are commands for reading and page programming. @var{fread_cmd} is used in DPI and QPI modes,
6221 @var{read_cmd} in normal SPI (single line) mode. @var{mass_erase_cmd}, @var{sector_size}
6222 and @var{sector_erase_cmd} are optional.
6224 This command is required if chip id is not hardcoded yet and e.g. for EEPROMs or FRAMs
6225 which don't support an id command.
6227 In dual mode parameters of both chips are set identically. The parameters refer to
6228 a single chip, so the whole bank gets twice the specified capacity etc.
6231 @deffn {Command} {stmqspi cmd} bank_id resp_num cmd_byte ...
6232 If @var{resp_num} is zero, sends command @var{cmd_byte} and following data
6233 bytes. In dual mode command byte is sent to @emph{both} chips but data bytes are
6234 sent @emph{alternatingly} to chip 1 and 2, first to flash 1, second to flash 2, etc.,
6235 i.e. the total number of bytes (including cmd_byte) must be odd.
6237 If @var{resp_num} is not zero, cmd and at most four following data bytes are
6238 sent, in dual mode @emph{simultaneously} to both chips. Then @var{resp_num} bytes
6239 are read interleaved from both chips starting with chip 1. In this case
6240 @var{resp_num} must be even.
6242 Note the hardware dictated subtle difference of those two cases in dual-flash mode.
6244 To check basic communication settings, issue
6246 stmqspi cmd bank_id 0 0x04; stmqspi cmd bank_id 1 0x05
6247 stmqspi cmd bank_id 0 0x06; stmqspi cmd bank_id 1 0x05
6249 for single flash mode or
6251 stmqspi cmd bank_id 0 0x04; stmqspi cmd bank_id 2 0x05
6252 stmqspi cmd bank_id 0 0x06; stmqspi cmd bank_id 2 0x05
6254 for dual flash mode. This should return the status register contents.
6256 In 8-line mode, @var{cmd_byte} is sent twice - first time as given, second time
6257 complemented. Additionally, in 8-line mode only, some commands (e.g. Read Status)
6258 need a dummy address, e.g.
6260 stmqspi cmd bank_id 1 0x05 0x00 0x00 0x00 0x00
6262 should return the status register contents.
6268 @deffn {Flash Driver} {mrvlqspi}
6269 This driver supports QSPI flash controller of Marvell's Wireless
6270 Microcontroller platform.
6272 The flash size is autodetected based on the table of known JEDEC IDs
6273 hardcoded in the OpenOCD sources.
6276 flash bank $_FLASHNAME mrvlqspi 0x0 0 0 0 $_TARGETNAME 0x46010000
6281 @deffn {Flash Driver} {ath79}
6282 @cindex Atheros ath79 SPI driver
6284 Members of ATH79 SoC family from Atheros include a SPI interface with 3
6286 On reset a SPI flash connected to the first chip select (CS0) is made
6287 directly read-accessible in the CPU address space (up to 16MBytes)
6288 and is usually used to store the bootloader and operating system.
6289 Normal OpenOCD commands like @command{mdw} can be used to display
6290 the flash content while it is in memory-mapped mode (only the first
6291 4MBytes are accessible without additional configuration on reset).
6293 The setup command only requires the @var{base} parameter in order
6294 to identify the memory bank. The actual value for the base address
6295 is not otherwise used by the driver. However the mapping is passed
6296 to gdb. Thus for the memory mapped flash (chipselect CS0) the base
6297 address should be the actual memory mapped base address. For unmapped
6298 chipselects (CS1 and CS2) care should be taken to use a base address
6299 that does not overlap with real memory regions.
6300 Additional information, like flash size, are detected automatically.
6301 An optional additional parameter sets the chipselect for the bank,
6302 with the default CS0.
6303 CS1 and CS2 require additional GPIO setup before they can be used
6304 since the alternate function must be enabled on the GPIO pin
6305 CS1/CS2 is routed to on the given SoC.
6308 flash bank $_FLASHNAME ath79 0xbf000000 0 0 0 $_TARGETNAME
6310 # When using multiple chipselects the base should be different
6311 # for each, otherwise the write_image command is not able to
6312 # distinguish the banks.
6313 flash bank flash0 ath79 0xbf000000 0 0 0 $_TARGETNAME cs0
6314 flash bank flash1 ath79 0x10000000 0 0 0 $_TARGETNAME cs1
6315 flash bank flash2 ath79 0x20000000 0 0 0 $_TARGETNAME cs2
6320 @deffn {Flash Driver} {fespi}
6321 @cindex Freedom E SPI
6324 SiFive's Freedom E SPI controller, used in HiFive and other boards.
6327 flash bank $_FLASHNAME fespi 0x20000000 0 0 0 $_TARGETNAME
6331 @subsection Internal Flash (Microcontrollers)
6333 @deffn {Flash Driver} {aduc702x}
6334 The ADUC702x analog microcontrollers from Analog Devices
6335 include internal flash and use ARM7TDMI cores.
6336 The aduc702x flash driver works with models ADUC7019 through ADUC7028.
6337 The setup command only requires the @var{target} argument
6338 since all devices in this family have the same memory layout.
6341 flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME
6345 @deffn {Flash Driver} {ambiqmicro}
6348 All members of the Apollo microcontroller family from
6349 Ambiq Micro include internal flash and use ARM's Cortex-M4 core.
6350 The host connects over USB to an FTDI interface that communicates
6351 with the target using SWD.
6353 The @var{ambiqmicro} driver reads the Chip Information Register detect
6354 the device class of the MCU.
6355 The Flash and SRAM sizes directly follow device class, and are used
6356 to set up the flash banks.
6357 If this fails, the driver will use default values set to the minimum
6358 sizes of an Apollo chip.
6360 All Apollo chips have two flash banks of the same size.
6361 In all cases the first flash bank starts at location 0,
6362 and the second bank starts after the first.
6366 flash bank $_FLASHNAME ambiqmicro 0 0x00040000 0 0 $_TARGETNAME
6367 # Flash bank 1 - same size as bank0, starts after bank 0.
6368 flash bank $_FLASHNAME ambiqmicro 0x00040000 0x00040000 0 0 \
6372 Flash is programmed using custom entry points into the bootloader.
6373 This is the only way to program the flash as no flash control registers
6374 are available to the user.
6376 The @var{ambiqmicro} driver adds some additional commands:
6378 @deffn {Command} {ambiqmicro mass_erase} <bank>
6381 @deffn {Command} {ambiqmicro page_erase} <bank> <first> <last>
6384 @deffn {Command} {ambiqmicro program_otp} <bank> <offset> <count>
6385 Program OTP is a one time operation to create write protected flash.
6386 The user writes sectors to SRAM starting at 0x10000010.
6387 Program OTP will write these sectors from SRAM to flash, and write protect
6392 @deffn {Flash Driver} {at91samd}
6394 All members of the ATSAM D2x, D1x, D0x, ATSAMR, ATSAML and ATSAMC microcontroller
6395 families from Atmel include internal flash and use ARM's Cortex-M0+ core.
6397 Do not use for ATSAM D51 and E5x: use @xref{atsame5}.
6399 The devices have one flash bank:
6402 flash bank $_FLASHNAME at91samd 0x00000000 0 1 1 $_TARGETNAME
6405 @deffn {Command} {at91samd chip-erase}
6406 Issues a complete Flash erase via the Device Service Unit (DSU). This can be
6407 used to erase a chip back to its factory state and does not require the
6408 processor to be halted.
6411 @deffn {Command} {at91samd set-security}
6412 Secures the Flash via the Set Security Bit (SSB) command. This prevents access
6413 to the Flash and can only be undone by using the chip-erase command which
6414 erases the Flash contents and turns off the security bit. Warning: at this
6415 time, openocd will not be able to communicate with a secured chip and it is
6416 therefore not possible to chip-erase it without using another tool.
6419 at91samd set-security enable
6423 @deffn {Command} {at91samd eeprom}
6424 Shows or sets the EEPROM emulation size configuration, stored in the User Row
6425 of the Flash. When setting, the EEPROM size must be specified in bytes and it
6426 must be one of the permitted sizes according to the datasheet. Settings are
6427 written immediately but only take effect on MCU reset. EEPROM emulation
6428 requires additional firmware support and the minimum EEPROM size may not be
6429 the same as the minimum that the hardware supports. Set the EEPROM size to 0
6430 in order to disable this feature.
6434 at91samd eeprom 1024
6438 @deffn {Command} {at91samd bootloader}
6439 Shows or sets the bootloader size configuration, stored in the User Row of the
6440 Flash. This is called the BOOTPROT region. When setting, the bootloader size
6441 must be specified in bytes and it must be one of the permitted sizes according
6442 to the datasheet. Settings are written immediately but only take effect on
6443 MCU reset. Setting the bootloader size to 0 disables bootloader protection.
6447 at91samd bootloader 16384
6451 @deffn {Command} {at91samd dsu_reset_deassert}
6452 This command releases internal reset held by DSU
6453 and prepares reset vector catch in case of reset halt.
6454 Command is used internally in event reset-deassert-post.
6457 @deffn {Command} {at91samd nvmuserrow}
6458 Writes or reads the entire 64 bit wide NVM user row register which is located at
6459 0x804000. This register includes various fuses lock-bits and factory calibration
6460 data. Reading the register is done by invoking this command without any
6461 arguments. Writing is possible by giving 1 or 2 hex values. The first argument
6462 is the register value to be written and the second one is an optional changemask.
6463 Every bit which value in changemask is 0 will stay unchanged. The lock- and
6464 reserved-bits are masked out and cannot be changed.
6468 >at91samd nvmuserrow
6469 NVMUSERROW: 0xFFFFFC5DD8E0C788
6470 # Write 0xFFFFFC5DD8E0C788 to user row
6471 >at91samd nvmuserrow 0xFFFFFC5DD8E0C788
6472 # Write 0x12300 to user row but leave other bits and low
6474 >at91samd nvmuserrow 0x12345 0xFFF00
6481 @deffn {Flash Driver} {at91sam3}
6483 All members of the AT91SAM3 microcontroller family from
6484 Atmel include internal flash and use ARM's Cortex-M3 core. The driver
6485 currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
6486 that the driver was orginaly developed and tested using the
6487 AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in
6488 the family was cribbed from the data sheet. @emph{Note to future
6489 readers/updaters: Please remove this worrisome comment after other
6490 chips are confirmed.}
6492 The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
6493 have one flash bank. In all cases the flash banks are at
6494 the following fixed locations:
6497 # Flash bank 0 - all chips
6498 flash bank $_FLASHNAME at91sam3 0x00080000 0 1 1 $_TARGETNAME
6499 # Flash bank 1 - only 256K chips
6500 flash bank $_FLASHNAME at91sam3 0x00100000 0 1 1 $_TARGETNAME
6503 Internally, the AT91SAM3 flash memory is organized as follows.
6504 Unlike the AT91SAM7 chips, these are not used as parameters
6505 to the @command{flash bank} command:
6508 @item @emph{N-Banks:} 256K chips have 2 banks, others have 1 bank.
6509 @item @emph{Bank Size:} 128K/64K Per flash bank
6510 @item @emph{Sectors:} 16 or 8 per bank
6511 @item @emph{SectorSize:} 8K Per Sector
6512 @item @emph{PageSize:} 256 bytes per page. Note that OpenOCD operates on 'sector' sizes, not page sizes.
6515 The AT91SAM3 driver adds some additional commands:
6517 @deffn {Command} {at91sam3 gpnvm}
6518 @deffnx {Command} {at91sam3 gpnvm clear} number
6519 @deffnx {Command} {at91sam3 gpnvm set} number
6520 @deffnx {Command} {at91sam3 gpnvm show} [@option{all}|number]
6521 With no parameters, @command{show} or @command{show all},
6522 shows the status of all GPNVM bits.
6523 With @command{show} @var{number}, displays that bit.
6525 With @command{set} @var{number} or @command{clear} @var{number},
6526 modifies that GPNVM bit.
6529 @deffn {Command} {at91sam3 info}
6530 This command attempts to display information about the AT91SAM3
6531 chip. @emph{First} it read the @code{CHIPID_CIDR} [address 0x400e0740, see
6532 Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
6533 document id: doc6430A] and decodes the values. @emph{Second} it reads the
6534 various clock configuration registers and attempts to display how it
6535 believes the chip is configured. By default, the SLOWCLK is assumed to
6536 be 32768 Hz, see the command @command{at91sam3 slowclk}.
6539 @deffn {Command} {at91sam3 slowclk} [value]
6540 This command shows/sets the slow clock frequency used in the
6541 @command{at91sam3 info} command calculations above.
6545 @deffn {Flash Driver} {at91sam4}
6547 All members of the AT91SAM4 microcontroller family from
6548 Atmel include internal flash and use ARM's Cortex-M4 core.
6549 This driver uses the same command names/syntax as @xref{at91sam3}.
6552 @deffn {Flash Driver} {at91sam4l}
6554 All members of the AT91SAM4L microcontroller family from
6555 Atmel include internal flash and use ARM's Cortex-M4 core.
6556 This driver uses the same command names/syntax as @xref{at91sam3}.
6558 The AT91SAM4L driver adds some additional commands:
6559 @deffn {Command} {at91sam4l smap_reset_deassert}
6560 This command releases internal reset held by SMAP
6561 and prepares reset vector catch in case of reset halt.
6562 Command is used internally in event reset-deassert-post.
6567 @deffn {Flash Driver} {atsame5}
6569 All members of the SAM E54, E53, E51 and D51 microcontroller
6570 families from Microchip (former Atmel) include internal flash
6571 and use ARM's Cortex-M4 core.
6573 The devices have two ECC flash banks with a swapping feature.
6574 This driver handles both banks together as it were one.
6575 Bank swapping is not supported yet.
6578 flash bank $_FLASHNAME atsame5 0x00000000 0 1 1 $_TARGETNAME
6581 @deffn {Command} {atsame5 bootloader}
6582 Shows or sets the bootloader size configuration, stored in the User Page of the
6583 Flash. This is called the BOOTPROT region. When setting, the bootloader size
6584 must be specified in bytes. The nearest bigger protection size is used.
6585 Settings are written immediately but only take effect on MCU reset.
6586 Setting the bootloader size to 0 disables bootloader protection.
6590 atsame5 bootloader 16384
6594 @deffn {Command} {atsame5 chip-erase}
6595 Issues a complete Flash erase via the Device Service Unit (DSU). This can be
6596 used to erase a chip back to its factory state and does not require the
6597 processor to be halted.
6600 @deffn {Command} {atsame5 dsu_reset_deassert}
6601 This command releases internal reset held by DSU
6602 and prepares reset vector catch in case of reset halt.
6603 Command is used internally in event reset-deassert-post.
6606 @deffn {Command} {atsame5 userpage}
6607 Writes or reads the first 64 bits of NVM User Page which is located at
6608 0x804000. This field includes various fuses.
6609 Reading is done by invoking this command without any arguments.
6610 Writing is possible by giving 1 or 2 hex values. The first argument
6611 is the value to be written and the second one is an optional bit mask
6612 (a zero bit in the mask means the bit stays unchanged).
6613 The reserved fields are always masked out and cannot be changed.
6618 USER PAGE: 0xAEECFF80FE9A9239
6620 >atsame5 userpage 0xAEECFF80FE9A9239
6621 # Write 2 to SEESBLK and 4 to SEEPSZ fields but leave other
6622 # bits unchanged (setup SmartEEPROM of virtual size 8192
6624 >atsame5 userpage 0x4200000000 0x7f00000000
6630 @deffn {Flash Driver} {atsamv}
6632 All members of the ATSAMV7x, ATSAMS70, and ATSAME70 families from
6633 Atmel include internal flash and use ARM's Cortex-M7 core.
6634 This driver uses the same command names/syntax as @xref{at91sam3}.
6637 flash bank $_FLASHNAME atsamv 0x00400000 0 0 0 $_TARGETNAME
6640 @deffn {Command} {atsamv gpnvm} [@option{show} [@option{all}|number]]
6641 @deffnx {Command} {atsamv gpnvm} (@option{clr}|@option{set}) number
6642 With no parameters, @option{show} or @option{show all},
6643 shows the status of all GPNVM bits.
6644 With @option{show} @var{number}, displays that bit.
6646 With @option{set} @var{number} or @option{clear} @var{number},
6647 modifies that GPNVM bit.
6652 @deffn {Flash Driver} {at91sam7}
6653 All members of the AT91SAM7 microcontroller family from Atmel include
6654 internal flash and use ARM7TDMI cores. The driver automatically
6655 recognizes a number of these chips using the chip identification
6656 register, and autoconfigures itself.
6659 flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME
6662 For chips which are not recognized by the controller driver, you must
6663 provide additional parameters in the following order:
6666 @item @var{chip_model} ... label used with @command{flash info}
6668 @item @var{sectors_per_bank}
6669 @item @var{pages_per_sector}
6670 @item @var{pages_size}
6671 @item @var{num_nvm_bits}
6672 @item @var{freq_khz} ... required if an external clock is provided,
6673 optional (but recommended) when the oscillator frequency is known
6676 It is recommended that you provide zeroes for all of those values
6677 except the clock frequency, so that everything except that frequency
6678 will be autoconfigured.
6679 Knowing the frequency helps ensure correct timings for flash access.
6681 The flash controller handles erases automatically on a page (128/256 byte)
6682 basis, so explicit erase commands are not necessary for flash programming.
6683 However, there is an ``EraseAll`` command that can erase an entire flash
6684 plane (of up to 256KB), and it will be used automatically when you issue
6685 @command{flash erase_sector} or @command{flash erase_address} commands.
6687 @deffn {Command} {at91sam7 gpnvm} bitnum (@option{set}|@option{clear})
6688 Set or clear a ``General Purpose Non-Volatile Memory'' (GPNVM)
6689 bit for the processor. Each processor has a number of such bits,
6690 used for controlling features such as brownout detection (so they
6691 are not truly general purpose).
6693 This assumes that the first flash bank (number 0) is associated with
6694 the appropriate at91sam7 target.
6699 @deffn {Flash Driver} {avr}
6700 The AVR 8-bit microcontrollers from Atmel integrate flash memory.
6701 @emph{The current implementation is incomplete.}
6702 @comment - defines mass_erase ... pointless given flash_erase_address
6705 @deffn {Flash Driver} {bluenrg-x}
6706 STMicroelectronics BlueNRG-1, BlueNRG-2 and BlueNRG-LP/LPS Bluetooth low energy wireless system-on-chip. They include ARM Cortex-M0/M0+ core and internal flash memory.
6707 The driver automatically recognizes these chips using
6708 the chip identification registers, and autoconfigures itself.
6711 flash bank $_FLASHNAME bluenrg-x 0 0 0 0 $_TARGETNAME
6714 Note that when users ask to erase all the sectors of the flash, a mass erase command is used which is faster than erasing
6715 each single sector one by one.
6718 flash erase_sector 0 0 last # It will perform a mass erase
6721 Triggering a mass erase is also useful when users want to disable readout protection.
6724 @deffn {Flash Driver} {cc26xx}
6725 All versions of the SimpleLink CC13xx and CC26xx microcontrollers from Texas
6726 Instruments include internal flash. The cc26xx flash driver supports both the
6727 CC13xx and CC26xx family of devices. The driver automatically recognizes the
6728 specific version's flash parameters and autoconfigures itself. The flash bank
6729 starts at address 0.
6732 flash bank $_FLASHNAME cc26xx 0 0 0 0 $_TARGETNAME
6736 @deffn {Flash Driver} {cc3220sf}
6737 The CC3220SF version of the SimpleLink CC32xx microcontrollers from Texas
6738 Instruments includes 1MB of internal flash. The cc3220sf flash driver only
6739 supports the internal flash. The serial flash on SimpleLink boards is
6740 programmed via the bootloader over a UART connection. Security features of
6741 the CC3220SF may erase the internal flash during power on reset. Refer to
6742 documentation at @url{www.ti.com/cc3220sf} for details on security features
6743 and programming the serial flash.
6746 flash bank $_FLASHNAME cc3220sf 0 0 0 0 $_TARGETNAME
6750 @deffn {Flash Driver} {efm32}
6751 All members of the EFM32/EFR32 microcontroller family from Energy Micro (now Silicon Labs)
6752 include internal flash and use Arm Cortex-M3 or Cortex-M4 cores. The driver automatically
6753 recognizes a number of these chips using the chip identification register, and
6754 autoconfigures itself.
6756 flash bank $_FLASHNAME efm32 0 0 0 0 $_TARGETNAME
6758 It supports writing to the user data page, as well as the portion of the lockbits page
6759 past 512 bytes on chips with larger page sizes. The latter is used by the SiLabs
6760 bootloader/AppLoader system for encryption keys. Setting protection on these pages is
6761 currently not supported.
6763 flash bank userdata.flash efm32 0x0FE00000 0 0 0 $_TARGETNAME
6764 flash bank lockbits.flash efm32 0x0FE04000 0 0 0 $_TARGETNAME
6767 A special feature of efm32 controllers is that it is possible to completely disable the
6768 debug interface by writing the correct values to the 'Debug Lock Word'. OpenOCD supports
6769 this via the following command:
6773 The @var{num} parameter is a value shown by @command{flash banks}.
6774 Note that in order for this command to take effect, the target needs to be reset.
6775 @emph{The current implementation is incomplete. Unprotecting flash pages is not
6779 @deffn {Flash Driver} {esirisc}
6780 Members of the eSi-RISC family may optionally include internal flash programmed
6781 via the eSi-TSMC Flash interface. Additional parameters are required to
6782 configure the driver: @option{cfg_address} is the base address of the
6783 configuration register interface, @option{clock_hz} is the expected clock
6784 frequency, and @option{wait_states} is the number of configured read wait states.
6787 flash bank $_FLASHNAME esirisc base_address size_bytes 0 0 \
6788 $_TARGETNAME cfg_address clock_hz wait_states
6791 @deffn {Command} {esirisc flash mass_erase} bank_id
6792 Erase all pages in data memory for the bank identified by @option{bank_id}.
6795 @deffn {Command} {esirisc flash ref_erase} bank_id
6796 Erase the reference cell for the bank identified by @option{bank_id}. @emph{This
6797 is an uncommon operation.}
6801 @deffn {Flash Driver} {fm3}
6802 All members of the FM3 microcontroller family from Fujitsu
6803 include internal flash and use ARM Cortex-M3 cores.
6804 The @var{fm3} driver uses the @var{target} parameter to select the
6805 correct bank config, it can currently be one of the following:
6806 @code{mb9bfxx1.cpu}, @code{mb9bfxx2.cpu}, @code{mb9bfxx3.cpu},
6807 @code{mb9bfxx4.cpu}, @code{mb9bfxx5.cpu} or @code{mb9bfxx6.cpu}.
6810 flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME
6814 @deffn {Flash Driver} {fm4}
6815 All members of the FM4 microcontroller family from Spansion (formerly Fujitsu)
6816 include internal flash and use ARM Cortex-M4 cores.
6817 The @var{fm4} driver uses a @var{family} parameter to select the
6818 correct bank config, it can currently be one of the following:
6819 @code{MB9BFx64}, @code{MB9BFx65}, @code{MB9BFx66}, @code{MB9BFx67}, @code{MB9BFx68},
6820 @code{S6E2Cx8}, @code{S6E2Cx9}, @code{S6E2CxA} or @code{S6E2Dx},
6821 with @code{x} treated as wildcard and otherwise case (and any trailing
6822 characters) ignored.
6825 flash bank $@{_FLASHNAME@}0 fm4 0x00000000 0 0 0 \
6826 $_TARGETNAME S6E2CCAJ0A
6827 flash bank $@{_FLASHNAME@}1 fm4 0x00100000 0 0 0 \
6828 $_TARGETNAME S6E2CCAJ0A
6830 @emph{The current implementation is incomplete. Protection is not supported,
6831 nor is Chip Erase (only Sector Erase is implemented).}
6834 @deffn {Flash Driver} {kinetis}
6836 Several microcontrollers from NXP (former Freescale), including
6837 Kx, KLx, KVx and KE1x members of the Kinetis family,
6838 and S32K11x/S32K14x microcontrollers, include
6839 internal flash and use ARM Cortex-M0+ or M4 cores.
6840 Kinetis and S32K1 families use incompatible
6841 identification registers, so the driver assumes Kinetis and requires
6842 a driver option to indicate S32K1 is to be used.
6843 Within the familiy, the driver automatically
6844 recognizes flash size and a number of flash banks (1-4) using the chip
6845 identification register, and autoconfigures itself.
6846 Use kinetis_ke driver for KE0x and KEAx devices.
6848 The @var{kinetis} driver defines option:
6850 @item -s32k select S32K11x/S32K14x microcontroller flash support.
6852 @item -sim-base @var{addr} ... base of System Integration Module where chip identification resides. Driver tries known locations if option is omitted.
6856 flash bank $_FLASHNAME kinetis 0 0 0 0 $_TARGETNAME
6859 @deffn {Config Command} {kinetis create_banks}
6860 Configuration command enables automatic creation of additional flash banks
6861 based on real flash layout of device. Banks are created during device probe.
6862 Use 'flash probe 0' to force probe.
6865 @deffn {Command} {kinetis fcf_source} [protection|write]
6866 Select what source is used when writing to a Flash Configuration Field.
6867 @option{protection} mode builds FCF content from protection bits previously
6868 set by 'flash protect' command.
6869 This mode is default. MCU is protected from unwanted locking by immediate
6870 writing FCF after erase of relevant sector.
6871 @option{write} mode enables direct write to FCF.
6872 Protection cannot be set by 'flash protect' command. FCF is written along
6873 with the rest of a flash image.
6874 @emph{BEWARE: Incorrect flash configuration may permanently lock the device!}
6877 @deffn {Command} {kinetis fopt} [num]
6878 Set value to write to FOPT byte of Flash Configuration Field.
6879 Used in kinetis 'fcf_source protection' mode only.
6882 @deffn {Command} {kinetis mdm check_security}
6883 Checks status of device security lock. Used internally in examine-end
6884 and examine-fail event.
6887 @deffn {Command} {kinetis mdm halt}
6888 Issues a halt via the MDM-AP. This command can be used to break a watchdog reset
6889 loop when connecting to an unsecured target.
6892 @deffn {Command} {kinetis mdm mass_erase}
6893 Issues a complete flash erase via the MDM-AP. This can be used to erase a chip
6894 back to its factory state, removing security. It does not require the processor
6895 to be halted, however the target will remain in a halted state after this
6899 @deffn {Command} {kinetis nvm_partition}
6900 For FlexNVM devices only (KxxDX and KxxFX).
6901 Not supported (yet) on S32K1 devices.
6902 Command shows or sets data flash or EEPROM backup size in kilobytes,
6903 sets two EEPROM blocks sizes in bytes and enables/disables loading
6904 of EEPROM contents to FlexRAM during reset.
6906 For details see device reference manual, Flash Memory Module,
6907 Program Partition command.
6909 Setting is possible only once after mass_erase.
6910 Reset the device after partition setting.
6912 Show partition size:
6914 kinetis nvm_partition info
6917 Set 32 KB data flash, rest of FlexNVM is EEPROM backup. EEPROM has two blocks
6918 of 512 and 1536 bytes and its contents is loaded to FlexRAM during reset:
6920 kinetis nvm_partition dataflash 32 512 1536 on
6923 Set 16 KB EEPROM backup, rest of FlexNVM is a data flash. EEPROM has two blocks
6924 of 1024 bytes and its contents is not loaded to FlexRAM during reset:
6926 kinetis nvm_partition eebkp 16 1024 1024 off
6930 @deffn {Command} {kinetis mdm reset}
6931 Issues a reset via the MDM-AP. This causes the MCU to output a low pulse on the
6932 RESET pin, which can be used to reset other hardware on board.
6935 @deffn {Command} {kinetis disable_wdog}
6936 For Kx devices only (KLx has different COP watchdog, it is not supported).
6937 Command disables watchdog timer.
6941 @deffn {Flash Driver} {kinetis_ke}
6943 KE0x and KEAx members of the Kinetis microcontroller family from NXP include
6944 internal flash and use ARM Cortex-M0+. The driver automatically recognizes
6945 the KE0x sub-family using the chip identification register, and
6946 autoconfigures itself.
6947 Use kinetis (not kinetis_ke) driver for KE1x devices.
6950 flash bank $_FLASHNAME kinetis_ke 0 0 0 0 $_TARGETNAME
6953 @deffn {Command} {kinetis_ke mdm check_security}
6954 Checks status of device security lock. Used internally in examine-end event.
6957 @deffn {Command} {kinetis_ke mdm mass_erase}
6958 Issues a complete Flash erase via the MDM-AP.
6959 This can be used to erase a chip back to its factory state.
6960 Command removes security lock from a device (use of SRST highly recommended).
6961 It does not require the processor to be halted.
6964 @deffn {Command} {kinetis_ke disable_wdog}
6965 Command disables watchdog timer.
6969 @deffn {Flash Driver} {lpc2000}
6970 This is the driver to support internal flash of all members of the
6971 LPC11(x)00 and LPC1300 microcontroller families and most members of
6972 the LPC800, LPC1500, LPC1700, LPC1800, LPC2000, LPC4000, LPC54100,
6973 LPC8Nxx and NHS31xx microcontroller families from NXP.
6976 There are LPC2000 devices which are not supported by the @var{lpc2000}
6978 The LPC2888 is supported by the @var{lpc288x} driver.
6979 The LPC29xx family is supported by the @var{lpc2900} driver.
6982 The @var{lpc2000} driver defines two mandatory and two optional parameters,
6983 which must appear in the following order:
6986 @item @var{variant} ... required, may be
6987 @option{lpc2000_v1} (older LPC21xx and LPC22xx)
6988 @option{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
6989 @option{lpc1700} (LPC175x and LPC176x and LPC177x/8x)
6990 @option{lpc4300} - available also as @option{lpc1800} alias (LPC18x[2357] and
6992 @option{lpc800} (LPC8xx)
6993 @option{lpc1100} (LPC11(x)xx and LPC13xx)
6994 @option{lpc1500} (LPC15xx)
6995 @option{lpc54100} (LPC541xx)
6996 @option{lpc4000} (LPC40xx)
6997 or @option{auto} - automatically detects flash variant and size for LPC11(x)00,
6998 LPC8xx, LPC13xx, LPC17xx, LPC40xx, LPC8Nxx and NHS31xx
6999 @item @var{clock_kHz} ... the frequency, in kiloHertz,
7000 at which the core is running
7001 @item @option{calc_checksum} ... optional (but you probably want to provide this!),
7002 telling the driver to calculate a valid checksum for the exception vector table.
7004 If you don't provide @option{calc_checksum} when you're writing the vector
7005 table, the boot ROM will almost certainly ignore your flash image.
7006 However, if you do provide it,
7007 with most tool chains @command{verify_image} will fail.
7009 @item @option{iap_entry} ... optional telling the driver to use a different
7010 ROM IAP entry point.
7013 LPC flashes don't require the chip and bus width to be specified.
7016 flash bank $_FLASHNAME lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
7017 lpc2000_v2 14765 calc_checksum
7020 @deffn {Command} {lpc2000 part_id} bank
7021 Displays the four byte part identifier associated with
7022 the specified flash @var{bank}.
7026 @deffn {Flash Driver} {lpc288x}
7027 The LPC2888 microcontroller from NXP needs slightly different flash
7028 support from its lpc2000 siblings.
7029 The @var{lpc288x} driver defines one mandatory parameter,
7030 the programming clock rate in Hz.
7031 LPC flashes don't require the chip and bus width to be specified.
7034 flash bank $_FLASHNAME lpc288x 0 0 0 0 $_TARGETNAME 12000000
7038 @deffn {Flash Driver} {lpc2900}
7039 This driver supports the LPC29xx ARM968E based microcontroller family
7042 The predefined parameters @var{base}, @var{size}, @var{chip_width} and
7043 @var{bus_width} of the @code{flash bank} command are ignored. Flash size and
7044 sector layout are auto-configured by the driver.
7045 The driver has one additional mandatory parameter: The CPU clock rate
7046 (in kHz) at the time the flash operations will take place. Most of the time this
7047 will not be the crystal frequency, but a higher PLL frequency. The
7048 @code{reset-init} event handler in the board script is usually the place where
7051 The driver rejects flashless devices (currently the LPC2930).
7053 The EEPROM in LPC2900 devices is not mapped directly into the address space.
7054 It must be handled much more like NAND flash memory, and will therefore be
7055 handled by a separate @code{lpc2900_eeprom} driver (not yet available).
7057 Sector protection in terms of the LPC2900 is handled transparently. Every time a
7058 sector needs to be erased or programmed, it is automatically unprotected.
7059 What is shown as protection status in the @code{flash info} command, is
7060 actually the LPC2900 @emph{sector security}. This is a mechanism to prevent a
7061 sector from ever being erased or programmed again. As this is an irreversible
7062 mechanism, it is handled by a special command (@code{lpc2900 secure_sector}),
7063 and not by the standard @code{flash protect} command.
7065 Example for a 125 MHz clock frequency:
7067 flash bank $_FLASHNAME lpc2900 0 0 0 0 $_TARGETNAME 125000
7070 Some @code{lpc2900}-specific commands are defined. In the following command list,
7071 the @var{bank} parameter is the bank number as obtained by the
7072 @code{flash banks} command.
7074 @deffn {Command} {lpc2900 signature} bank
7075 Calculates a 128-bit hash value, the @emph{signature}, from the whole flash
7076 content. This is a hardware feature of the flash block, hence the calculation is
7077 very fast. You may use this to verify the content of a programmed device against
7082 signature: 0x5f40cdc8:0xc64e592e:0x10490f89:0x32a0f317
7086 @deffn {Command} {lpc2900 read_custom} bank filename
7087 Reads the 912 bytes of customer information from the flash index sector, and
7088 saves it to a file in binary format.
7091 lpc2900 read_custom 0 /path_to/customer_info.bin
7095 The index sector of the flash is a @emph{write-only} sector. It cannot be
7096 erased! In order to guard against unintentional write access, all following
7097 commands need to be preceded by a successful call to the @code{password}
7100 @deffn {Command} {lpc2900 password} bank password
7101 You need to use this command right before each of the following commands:
7102 @code{lpc2900 write_custom}, @code{lpc2900 secure_sector},
7103 @code{lpc2900 secure_jtag}.
7105 The password string is fixed to "I_know_what_I_am_doing".
7108 lpc2900 password 0 I_know_what_I_am_doing
7109 Potentially dangerous operation allowed in next command!
7113 @deffn {Command} {lpc2900 write_custom} bank filename type
7114 Writes the content of the file into the customer info space of the flash index
7115 sector. The filetype can be specified with the @var{type} field. Possible values
7116 for @var{type} are: @var{bin} (binary), @var{ihex} (Intel hex format),
7117 @var{elf} (ELF binary) or @var{s19} (Motorola S-records). The file must
7118 contain a single section, and the contained data length must be exactly
7120 @quotation Attention
7121 This cannot be reverted! Be careful!
7125 lpc2900 write_custom 0 /path_to/customer_info.bin bin
7129 @deffn {Command} {lpc2900 secure_sector} bank first last
7130 Secures the sector range from @var{first} to @var{last} (including) against
7131 further program and erase operations. The sector security will be effective
7132 after the next power cycle.
7133 @quotation Attention
7134 This cannot be reverted! Be careful!
7136 Secured sectors appear as @emph{protected} in the @code{flash info} command.
7139 lpc2900 secure_sector 0 1 1
7141 #0 : lpc2900 at 0x20000000, size 0x000c0000, (...)
7142 # 0: 0x00000000 (0x2000 8kB) not protected
7143 # 1: 0x00002000 (0x2000 8kB) protected
7144 # 2: 0x00004000 (0x2000 8kB) not protected
7148 @deffn {Command} {lpc2900 secure_jtag} bank
7149 Irreversibly disable the JTAG port. The new JTAG security setting will be
7150 effective after the next power cycle.
7151 @quotation Attention
7152 This cannot be reverted! Be careful!
7156 lpc2900 secure_jtag 0
7161 @deffn {Flash Driver} {mdr}
7162 This drivers handles the integrated NOR flash on Milandr Cortex-M
7163 based controllers. A known limitation is that the Info memory can't be
7164 read or verified as it's not memory mapped.
7167 flash bank <name> mdr <base> <size> \
7168 0 0 <target#> @var{type} @var{page_count} @var{sec_count}
7172 @item @var{type} - 0 for main memory, 1 for info memory
7173 @item @var{page_count} - total number of pages
7174 @item @var{sec_count} - number of sector per page count
7179 if @{ [info exists IMEMORY] && [string equal $IMEMORY true] @} @{
7180 flash bank $@{_CHIPNAME@}_info.flash mdr 0x00000000 0x01000 \
7181 0 0 $_TARGETNAME 1 1 4
7183 flash bank $_CHIPNAME.flash mdr 0x00000000 0x20000 \
7184 0 0 $_TARGETNAME 0 32 4
7189 @deffn {Flash Driver} {msp432}
7190 All versions of the SimpleLink MSP432 microcontrollers from Texas
7191 Instruments include internal flash. The msp432 flash driver automatically
7192 recognizes the specific version's flash parameters and autoconfigures itself.
7193 Main program flash starts at address 0. The information flash region on
7194 MSP432P4 versions starts at address 0x200000.
7197 flash bank $_FLASHNAME msp432 0 0 0 0 $_TARGETNAME
7200 @deffn {Command} {msp432 mass_erase} bank_id [main|all]
7201 Performs a complete erase of flash. By default, @command{mass_erase} will erase
7202 only the main program flash.
7204 On MSP432P4 versions, using @command{mass_erase all} will erase both the
7205 main program and information flash regions. To also erase the BSL in information
7206 flash, the user must first use the @command{bsl} command.
7209 @deffn {Command} {msp432 bsl} bank_id [unlock|lock]
7210 On MSP432P4 versions, @command{bsl} unlocks and locks the bootstrap loader (BSL)
7211 region in information flash so that flash commands can erase or write the BSL.
7212 Leave the BSL locked to prevent accidentally corrupting the bootstrap loader.
7214 To erase and program the BSL:
7217 flash erase_address 0x202000 0x2000
7218 flash write_image bsl.bin 0x202000
7224 @deffn {Flash Driver} {niietcm4}
7225 This drivers handles the integrated NOR flash on NIIET Cortex-M4
7226 based controllers. Flash size and sector layout are auto-configured by the driver.
7227 Main flash memory is called "Bootflash" and has main region and info region.
7228 Info region is NOT memory mapped by default,
7229 but it can replace first part of main region if needed.
7230 Full erase, single and block writes are supported for both main and info regions.
7231 There is additional not memory mapped flash called "Userflash", which
7232 also have division into regions: main and info.
7233 Purpose of userflash - to store system and user settings.
7234 Driver has special commands to perform operations with this memory.
7237 flash bank $_FLASHNAME niietcm4 0 0 0 0 $_TARGETNAME
7240 Some niietcm4-specific commands are defined:
7242 @deffn {Command} {niietcm4 uflash_read_byte} bank ('main'|'info') address
7243 Read byte from main or info userflash region.
7246 @deffn {Command} {niietcm4 uflash_write_byte} bank ('main'|'info') address value
7247 Write byte to main or info userflash region.
7250 @deffn {Command} {niietcm4 uflash_full_erase} bank
7251 Erase all userflash including info region.
7254 @deffn {Command} {niietcm4 uflash_erase} bank ('main'|'info') first_sector last_sector
7255 Erase sectors of main or info userflash region, starting at sector first up to and including last.
7258 @deffn {Command} {niietcm4 uflash_protect_check} bank ('main'|'info')
7259 Check sectors protect.
7262 @deffn {Command} {niietcm4 uflash_protect} bank ('main'|'info') first_sector last_sector ('on'|'off')
7263 Protect sectors of main or info userflash region, starting at sector first up to and including last.
7266 @deffn {Command} {niietcm4 bflash_info_remap} bank ('on'|'off')
7267 Enable remapping bootflash info region to 0x00000000 (or 0x40000000 if external memory boot used).
7270 @deffn {Command} {niietcm4 extmem_cfg} bank ('gpioa'|'gpiob'|'gpioc'|'gpiod'|'gpioe'|'gpiof'|'gpiog'|'gpioh') pin_num ('func1'|'func3')
7271 Configure external memory interface for boot.
7274 @deffn {Command} {niietcm4 service_mode_erase} bank
7275 Perform emergency erase of all flash (bootflash and userflash).
7278 @deffn {Command} {niietcm4 driver_info} bank
7279 Show information about flash driver.
7284 @deffn {Flash Driver} {npcx}
7285 All versions of the NPCX microcontroller families from Nuvoton include internal
7286 flash. The NPCX flash driver supports the NPCX family of devices. The driver
7287 automatically recognizes the specific version's flash parameters and
7288 autoconfigures itself. The flash bank starts at address 0x64000000. An optional additional
7289 parameter sets the FIU version for the bank, with the default FIU is @var{npcx.fiu}.
7293 flash bank $_FLASHNAME npcx 0x64000000 0 0 0 $_TARGETNAME npcx_v2.fiu
7295 # FIU defaults to npcx.fiu
7296 flash bank $_FLASHNAME npcx 0x64000000 0 0 0 $_TARGETNAME
7301 @deffn {Flash Driver} {nrf5}
7302 All members of the nRF51 microcontroller families from Nordic Semiconductor
7303 include internal flash and use ARM Cortex-M0 core. nRF52 family powered
7304 by ARM Cortex-M4 or M4F core is supported too. nRF52832 is fully supported
7305 including BPROT flash protection scheme. nRF52833 and nRF52840 devices are
7306 supported with the exception of security extensions (flash access control list
7310 flash bank $_FLASHNAME nrf5 0 0x00000000 0 0 $_TARGETNAME
7313 Some nrf5-specific commands are defined:
7315 @deffn {Command} {nrf5 mass_erase}
7316 Erases the contents of the code memory and user information
7317 configuration registers as well. It must be noted that this command
7318 works only for chips that do not have factory pre-programmed region 0
7322 @deffn {Command} {nrf5 info}
7323 Decodes and shows information from FICR and UICR registers.
7328 @deffn {Flash Driver} {ocl}
7329 This driver is an implementation of the ``on chip flash loader''
7330 protocol proposed by Pavel Chromy.
7332 It is a minimalistic command-response protocol intended to be used
7333 over a DCC when communicating with an internal or external flash
7334 loader running from RAM. An example implementation for AT91SAM7x is
7335 available in @file{contrib/loaders/flash/at91sam7x/}.
7338 flash bank $_FLASHNAME ocl 0 0 0 0 $_TARGETNAME
7342 @deffn {Flash Driver} {pic32mx}
7343 The PIC32MX microcontrollers are based on the MIPS 4K cores,
7344 and integrate flash memory.
7347 flash bank $_FLASHNAME pix32mx 0x1fc00000 0 0 0 $_TARGETNAME
7348 flash bank $_FLASHNAME pix32mx 0x1d000000 0 0 0 $_TARGETNAME
7351 @comment numerous *disabled* commands are defined:
7352 @comment - chip_erase ... pointless given flash_erase_address
7353 @comment - lock, unlock ... pointless given protect on/off (yes?)
7354 @comment - pgm_word ... shouldn't bank be deduced from address??
7355 Some pic32mx-specific commands are defined:
7356 @deffn {Command} {pic32mx pgm_word} address value bank
7357 Programs the specified 32-bit @var{value} at the given @var{address}
7358 in the specified chip @var{bank}.
7360 @deffn {Command} {pic32mx unlock} bank
7361 Unlock and erase specified chip @var{bank}.
7362 This will remove any Code Protection.
7366 @deffn {Flash Driver} {psoc4}
7367 All members of the PSoC 41xx/42xx microcontroller family from Cypress
7368 include internal flash and use ARM Cortex-M0 cores.
7369 The driver automatically recognizes a number of these chips using
7370 the chip identification register, and autoconfigures itself.
7372 Note: Erased internal flash reads as 00.
7373 System ROM of PSoC 4 does not implement erase of a flash sector.
7376 flash bank $_FLASHNAME psoc4 0 0 0 0 $_TARGETNAME
7379 psoc4-specific commands
7380 @deffn {Command} {psoc4 flash_autoerase} num (on|off)
7381 Enables or disables autoerase mode for a flash bank.
7383 If flash_autoerase is off, use mass_erase before flash programming.
7384 Flash erase command fails if region to erase is not whole flash memory.
7386 If flash_autoerase is on, a sector is both erased and programmed in one
7387 system ROM call. Flash erase command is ignored.
7388 This mode is suitable for gdb load.
7390 The @var{num} parameter is a value shown by @command{flash banks}.
7393 @deffn {Command} {psoc4 mass_erase} num
7394 Erases the contents of the flash memory, protection and security lock.
7396 The @var{num} parameter is a value shown by @command{flash banks}.
7400 @deffn {Flash Driver} {psoc5lp}
7401 All members of the PSoC 5LP microcontroller family from Cypress
7402 include internal program flash and use ARM Cortex-M3 cores.
7403 The driver probes for a number of these chips and autoconfigures itself,
7404 apart from the base address.
7407 flash bank $_FLASHNAME psoc5lp 0x00000000 0 0 0 $_TARGETNAME
7410 @b{Note:} PSoC 5LP chips can be configured to have ECC enabled or disabled.
7411 @quotation Attention
7412 If flash operations are performed in ECC-disabled mode, they will also affect
7413 the ECC flash region. Erasing a 16k flash sector in the 0x00000000 area will
7414 then also erase the corresponding 2k data bytes in the 0x48000000 area.
7415 Writing to the ECC data bytes in ECC-disabled mode is not implemented.
7418 Commands defined in the @var{psoc5lp} driver:
7420 @deffn {Command} {psoc5lp mass_erase}
7421 Erases all flash data and ECC/configuration bytes, all flash protection rows,
7422 and all row latches in all flash arrays on the device.
7426 @deffn {Flash Driver} {psoc5lp_eeprom}
7427 All members of the PSoC 5LP microcontroller family from Cypress
7428 include internal EEPROM and use ARM Cortex-M3 cores.
7429 The driver probes for a number of these chips and autoconfigures itself,
7430 apart from the base address.
7433 flash bank $_CHIPNAME.eeprom psoc5lp_eeprom 0x40008000 0 0 0 \
7438 @deffn {Flash Driver} {psoc5lp_nvl}
7439 All members of the PSoC 5LP microcontroller family from Cypress
7440 include internal Nonvolatile Latches and use ARM Cortex-M3 cores.
7441 The driver probes for a number of these chips and autoconfigures itself.
7444 flash bank $_CHIPNAME.nvl psoc5lp_nvl 0 0 0 0 $_TARGETNAME
7447 PSoC 5LP chips have multiple NV Latches:
7450 @item Device Configuration NV Latch - 4 bytes
7451 @item Write Once (WO) NV Latch - 4 bytes
7454 @b{Note:} This driver only implements the Device Configuration NVL.
7456 The @var{psoc5lp} driver reads the ECC mode from Device Configuration NVL.
7457 @quotation Attention
7458 Switching ECC mode via write to Device Configuration NVL will require a reset
7459 after successful write.
7463 @deffn {Flash Driver} {psoc6}
7464 Supports PSoC6 (CY8C6xxx) family of Cypress microcontrollers.
7465 PSoC6 is a dual-core device with CM0+ and CM4 cores. Both cores share
7466 the same Flash/RAM/MMIO address space.
7468 Flash in PSoC6 is split into three regions:
7470 @item Main Flash - this is the main storage for user application.
7471 Total size varies among devices, sector size: 256 kBytes, row size:
7472 512 bytes. Supports erase operation on individual rows.
7473 @item Work Flash - intended to be used as storage for user data
7474 (e.g. EEPROM emulation). Total size: 32 KBytes, sector size: 32 KBytes,
7475 row size: 512 bytes.
7476 @item Supervisory Flash - special region which contains device-specific
7477 service data. This region does not support erase operation. Only few rows can
7478 be programmed by the user, most of the rows are read only. Programming
7479 operation will erase row automatically.
7482 All three flash regions are supported by the driver. Flash geometry is detected
7483 automatically by parsing data in SPCIF_GEOMETRY register.
7485 PSoC6 is equipped with NOR Flash so erased Flash reads as 0x00.
7488 flash bank main_flash_cm0 psoc6 0x10000000 0 0 0 \
7490 flash bank work_flash_cm0 psoc6 0x14000000 0 0 0 \
7492 flash bank super_flash_user_cm0 psoc6 0x16000800 0 0 0 \
7494 flash bank super_flash_nar_cm0 psoc6 0x16001A00 0 0 0 \
7496 flash bank super_flash_key_cm0 psoc6 0x16005A00 0 0 0 \
7498 flash bank super_flash_toc2_cm0 psoc6 0x16007C00 0 0 0 \
7501 flash bank main_flash_cm4 psoc6 0x10000000 0 0 0 \
7503 flash bank work_flash_cm4 psoc6 0x14000000 0 0 0 \
7505 flash bank super_flash_user_cm4 psoc6 0x16000800 0 0 0 \
7507 flash bank super_flash_nar_cm4 psoc6 0x16001A00 0 0 0 \
7509 flash bank super_flash_key_cm4 psoc6 0x16005A00 0 0 0 \
7511 flash bank super_flash_toc2_cm4 psoc6 0x16007C00 0 0 0 \
7515 psoc6-specific commands
7516 @deffn {Command} {psoc6 reset_halt}
7517 Command can be used to simulate broken Vector Catch from gdbinit or tcl scripts.
7518 When invoked for CM0+ target, it will set break point at application entry point
7519 and issue SYSRESETREQ. This will reset both cores and all peripherals. CM0+ will
7520 reset CM4 during boot anyway so this is safe. On CM4 target, VECTRESET is used
7521 instead of SYSRESETREQ to avoid unwanted reset of CM0+;
7524 @deffn {Command} {psoc6 mass_erase} num
7525 Erases the contents given flash bank. The @var{num} parameter is a value shown
7526 by @command{flash banks}.
7527 Note: only Main and Work flash regions support Erase operation.
7531 @deffn {Flash Driver} {qn908x}
7532 The NXP QN908x microcontrollers feature a Cortex-M4F with integrated Bluetooth
7533 LE 5 support and an internal flash of up to 512 KiB. These chips only support
7536 The @var{qn908x} driver uses the internal "Flash Memory Controller" block via
7537 SWD to erase, program and read the internal flash. This driver does not
7538 support the ISP (In-System Programming) mode which is an alternate way to
7539 program the flash via UART, SPI or USB.
7541 The internal flash is 512 KiB in size in all released chips and it starts at
7542 the address 0x01000000, although it can be mapped to address 0 and it is
7543 aliased to other addresses. This driver only recognizes the bank starting at
7546 The internal bootloader stored in ROM is in charge of loading and verifying
7547 the image from flash, or enter ISP mode. The programmed image must start at
7548 the beginning of the flash and contain a valid header and a matching CRC32
7549 checksum. Additionally, the image header contains a "Code Read Protection"
7550 (CRP) word which indicates whether SWD access is enabled, as well as whether
7551 ISP mode is enabled. Therefore, it is possible to program an image that
7552 disables SWD and ISP making it impossible to program another image in the
7553 future through these interfaces, or even debug the current image. While this is
7554 a valid use case for production deployments where the chips are locked down, by
7555 default this driver doesn't allow such images that disable the SWD interface.
7556 To program such images see the @command{qn908x allow_brick} command.
7558 Apart from the CRP field which is located in the image header, the last page
7559 of the flash memory contains a "Flash lock and protect" descriptor which allows
7560 to individually protect each 2 KiB page, as well as disabling SWD access to the
7561 flash and RAM. If this access is disabled it is not possible to read, erase or
7562 program individual pages from the SWD interface or even access the read-only
7563 "Flash information page" with information about the bootloader version and
7564 flash size. However when this protection is in place, it is still possible to
7565 mass erase the whole chip and then program a new image, for which you can use
7566 the @command{qn908x mass_erase}.
7570 flash bank $FLASHNAME qn908x 0x01000000 0 0 0 $TARGETNAME calc_checksum
7575 @item @option{calc_checksum} optional parameter to compute the required
7576 checksum of the first bytes in the vector table.
7578 If the checksum in the header of your image is invalid and you don't provide the
7579 @option{calc_checksum} option the boot ROM will not boot your image and it may
7580 render the flash inaccessible. On the other hand, if you use this option to
7581 compute the checksum keep in mind that @command{verify_image} will fail on
7582 those four bytes of the checksum since those bytes in the flash will have the
7587 @deffn {Command} {qn908x allow_brick}
7588 Allow the qn908x driver to program images with a "Code Read Protection" byte
7589 that disables the SWD access. Programming such image will cause OpenOCD to
7590 not be able to reach the target over SWD anymore after the new image is
7591 programmed and its configuration takes effect, e.g. after a reboot. After
7592 executing @command{qn908x allow_brick} these images will be allowed to be
7593 programmed when writing to the flash.
7596 @deffn {Command} {qn908x disable_wdog}
7597 Disable the watchdog timer (WDT) by resetting its CTRL field. The WDT starts
7598 enabled after a @command{reset halt} and it doesn't run while the target is
7599 halted. However, the verification process in this driver uses the generic
7600 Cortex-M verification process which executes a payload in RAM and thus
7601 requires the watchdog to be disabled before running @command{verify_image}
7602 after a reset halt or any other condition where the watchdog is running.
7603 Note that this is not done automatically and you must run this command in
7607 @deffn {Command} {qn908x mass_erase}
7608 Erases the complete flash using the mass_erase method. Mass erase is only
7609 allowed if enabled in the Lock Status Register 8 (LOCK_STAT_8) which is read
7610 from the last sector of the flash on boot. However, this mass_erase lock
7611 protection can be bypassed and this command does so automatically.
7613 In the same LOCK_STAT_8 the flash and RAM access from SWD can be disabled by
7614 setting two bits in this register. After a mass_erase, all the bits of the
7615 flash would be set, making it the default to restrict SWD access to the flash
7616 and RAM regions. This new after erase LOCK_STAT_8 value only takes effect after
7617 being read from flash on the next reboot for example. After a mass_erase the
7618 LOCK_STAT_8 register is changed by the hardware to allow access to flash and
7619 RAM regardless of the value on flash, but only right after a mass_erase and
7620 until the next boot. Therefore it is possible to perform a mass_erase, program
7621 a new image, verify it and then reboot to a valid image that's locked from the
7624 The @command{qn908x mass_erase} command clears the bits that would be loaded
7625 from the flash into LOCK_STAT_8 after erasing the whole chip to allow SWD
7626 access for debugging or re-flashing an image without a mass_erase by default.
7627 If the image being programmed also programs the last page of the flash with its
7628 own settings, this mass_erase behavior will interfere with that write since a
7629 new erase of at least the last page would need to be performed before writing
7630 to it again. For this reason the optional @option{keep_lock} argument can be
7631 used to leave the flash and RAM lock set. For development environments, the
7632 default behavior is desired.
7634 The mass erase locking mechanism is independent from the individual page
7635 locking bits, so it is possible that you can't erase a given page that is
7636 locked and you can't unprotect that page because the locking bits are also
7637 locked, but can still mass erase the whole flash.
7641 @deffn {Flash Driver} {rp2040}
7642 Supports RP2040 "Raspberry Pi Pico" microcontroller.
7643 RP2040 is a dual-core device with two CM0+ cores. Both cores share the same
7644 Flash/RAM/MMIO address space. Non-volatile storage is achieved with an
7645 external QSPI flash; a Boot ROM provides helper functions.
7648 flash bank $_FLASHNAME rp2040_flash $_FLASHBASE $_FLASHSIZE 1 32 $_TARGETNAME
7652 @deffn {Flash Driver} {rsl10}
7653 Supports Onsemi RSL10 microcontroller flash memory. Uses functions
7654 stored in ROM to control flash memory interface.
7657 flash bank $_FLASHNAME rsl10 $_FLASHBASE $_FLASHSIZE 0 0 $_TARGETNAME
7660 @deffn {Command} {rsl10 lock} key1 key2 key3 key4
7661 Writes @var{key1 key2 key3 key4} words to @var{0x81044 0x81048 0x8104c
7662 0x8050}. Locks debug port by writing @var{0x4C6F634B} to @var{0x81040}.
7664 To unlock use the @command{rsl10 unlock key1 key2 key3 key4} command.
7667 @deffn {Command} {rsl10 unlock} key1 key2 key3 key4
7668 Unlocks debug port, by writing @var{key1 key2 key3 key4} words to
7669 registers through DAP, and clears @var{0x81040} address in flash to 0x1.
7672 @deffn {Command} {rsl10 mass_erase}
7673 Erases all unprotected flash sectors.
7677 @deffn {Flash Driver} {sim3x}
7678 All members of the SiM3 microcontroller family from Silicon Laboratories
7679 include internal flash and use ARM Cortex-M3 cores. It supports both JTAG
7681 The @var{sim3x} driver tries to probe the device to auto detect the MCU.
7682 If this fails, it will use the @var{size} parameter as the size of flash bank.
7685 flash bank $_FLASHNAME sim3x 0 $_CPUROMSIZE 0 0 $_TARGETNAME
7688 There are 2 commands defined in the @var{sim3x} driver:
7690 @deffn {Command} {sim3x mass_erase}
7691 Erases the complete flash. This is used to unlock the flash.
7692 And this command is only possible when using the SWD interface.
7695 @deffn {Command} {sim3x lock}
7696 Lock the flash. To unlock use the @command{sim3x mass_erase} command.
7700 @deffn {Flash Driver} {stellaris}
7701 All members of the Stellaris LM3Sxxx, LM4x and Tiva C microcontroller
7702 families from Texas Instruments include internal flash. The driver
7703 automatically recognizes a number of these chips using the chip
7704 identification register, and autoconfigures itself.
7707 flash bank $_FLASHNAME stellaris 0 0 0 0 $_TARGETNAME
7710 @deffn {Command} {stellaris recover}
7711 Performs the @emph{Recovering a "Locked" Device} procedure to restore
7712 the flash and its associated nonvolatile registers to their factory
7713 default values (erased). This is the only way to remove flash
7714 protection or re-enable debugging if that capability has been
7717 Note that the final "power cycle the chip" step in this procedure
7718 must be performed by hand, since OpenOCD can't do it.
7720 if more than one Stellaris chip is connected, the procedure is
7721 applied to all of them.
7726 @deffn {Flash Driver} {stm32f1x}
7727 This driver supports the STM32F0, STM32F1 and STM32F3 microcontroller series from STMicroelectronics.
7728 The driver is also compatible with the GD32F1, GD32VF103 (RISC-V core), GD32F3 and GD32E23 microcontroller series from GigaDevice.
7729 The driver also supports the APM32F0 and APM32F1 series from Geehy Semiconductor.
7730 The driver automatically recognizes a number of these chips using the chip identification register, and autoconfigures itself.
7733 flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
7736 Note that some devices have been found that have a flash size register that contains
7737 an invalid value, to workaround this issue you can override the probed value used by
7741 flash bank $_FLASHNAME stm32f1x 0 0x20000 0 0 $_TARGETNAME
7744 If you have a target with dual flash banks then define the second bank
7745 as per the following example.
7747 flash bank $_FLASHNAME stm32f1x 0x08080000 0 0 0 $_TARGETNAME
7750 Some stm32f1x-specific commands are defined:
7752 @deffn {Command} {stm32f1x lock} num
7753 Locks the entire stm32 device against reading.
7754 The @var{num} parameter is a value shown by @command{flash banks}.
7757 @deffn {Command} {stm32f1x unlock} num
7758 Unlocks the entire stm32 device for reading. This command will cause
7759 a mass erase of the entire stm32 device if previously locked.
7760 The @var{num} parameter is a value shown by @command{flash banks}.
7763 @deffn {Command} {stm32f1x mass_erase} num
7764 Mass erases the entire stm32 device.
7765 The @var{num} parameter is a value shown by @command{flash banks}.
7768 @deffn {Command} {stm32f1x options_read} num
7769 Reads and displays active stm32 option bytes loaded during POR
7770 or upon executing the @command{stm32f1x options_load} command.
7771 The @var{num} parameter is a value shown by @command{flash banks}.
7774 @deffn {Command} {stm32f1x options_write} num (@option{SWWDG}|@option{HWWDG}) (@option{RSTSTNDBY}|@option{NORSTSTNDBY}) (@option{RSTSTOP}|@option{NORSTSTOP}) (@option{USEROPT} user_data)
7775 Writes the stm32 option byte with the specified values.
7776 The @var{num} parameter is a value shown by @command{flash banks}.
7777 The @var{user_data} parameter is content of higher 16 bits of the option byte register (Data0 and Data1 as one 16bit number).
7780 @deffn {Command} {stm32f1x options_load} num
7781 Generates a special kind of reset to re-load the stm32 option bytes written
7782 by the @command{stm32f1x options_write} or @command{flash protect} commands
7783 without having to power cycle the target. Not applicable to stm32f1x devices.
7784 The @var{num} parameter is a value shown by @command{flash banks}.
7788 @deffn {Flash Driver} {stm32f2x}
7789 All members of the STM32F2, STM32F4 and STM32F7 microcontroller families from STMicroelectronics
7790 include internal flash and use ARM Cortex-M3/M4/M7 cores.
7791 The driver also works for the APM32F4 series from Geehy Semiconductor.
7792 The driver automatically recognizes a number of these chips using
7793 the chip identification register, and autoconfigures itself.
7796 flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
7799 If you use OTP (One-Time Programmable) memory define it as a second bank
7800 as per the following example.
7802 flash bank $_FLASHNAME stm32f2x 0x1FFF7800 0 0 0 $_TARGETNAME
7805 @deffn {Command} {stm32f2x otp} num (@option{enable}|@option{disable}|@option{show})
7806 Enables or disables OTP write commands for bank @var{num}.
7807 The @var{num} parameter is a value shown by @command{flash banks}.
7810 Note that some devices have been found that have a flash size register that contains
7811 an invalid value, to workaround this issue you can override the probed value used by
7815 flash bank $_FLASHNAME stm32f2x 0 0x20000 0 0 $_TARGETNAME
7818 Some stm32f2x-specific commands are defined:
7820 @deffn {Command} {stm32f2x lock} num
7821 Locks the entire stm32 device.
7822 The @var{num} parameter is a value shown by @command{flash banks}.
7825 @deffn {Command} {stm32f2x unlock} num
7826 Unlocks the entire stm32 device.
7827 The @var{num} parameter is a value shown by @command{flash banks}.
7830 @deffn {Command} {stm32f2x mass_erase} num
7831 Mass erases the entire stm32f2x device.
7832 The @var{num} parameter is a value shown by @command{flash banks}.
7835 @deffn {Command} {stm32f2x options_read} num
7836 Reads and displays user options and (where implemented) boot_addr0, boot_addr1, optcr2.
7837 The @var{num} parameter is a value shown by @command{flash banks}.
7840 @deffn {Command} {stm32f2x options_write} num user_options boot_addr0 boot_addr1
7841 Writes user options and (where implemented) boot_addr0 and boot_addr1 in raw format.
7842 Warning: The meaning of the various bits depends on the device, always check datasheet!
7843 The @var{num} parameter is a value shown by @command{flash banks}, @var{user_options} a
7844 12 bit value, consisting of bits 31-28 and 7-0 of FLASH_OPTCR, @var{boot_addr0} and
7845 @var{boot_addr1} two halfwords (of FLASH_OPTCR1).
7848 @deffn {Command} {stm32f2x optcr2_write} num optcr2
7849 Writes FLASH_OPTCR2 options. Warning: Clearing PCROPi bits requires a full mass erase!
7850 The @var{num} parameter is a value shown by @command{flash banks}, @var{optcr2} a 32-bit word.
7854 @deffn {Flash Driver} {stm32h7x}
7855 All members of the STM32H7 microcontroller families from STMicroelectronics
7856 include internal flash and use ARM Cortex-M7 core.
7857 The driver automatically recognizes a number of these chips using
7858 the chip identification register, and autoconfigures itself.
7861 flash bank $_FLASHNAME stm32h7x 0 0 0 0 $_TARGETNAME
7864 Note that some devices have been found that have a flash size register that contains
7865 an invalid value, to workaround this issue you can override the probed value used by
7869 flash bank $_FLASHNAME stm32h7x 0 0x20000 0 0 $_TARGETNAME
7872 Some stm32h7x-specific commands are defined:
7874 @deffn {Command} {stm32h7x lock} num
7875 Locks the entire stm32 device.
7876 The @var{num} parameter is a value shown by @command{flash banks}.
7879 @deffn {Command} {stm32h7x unlock} num
7880 Unlocks the entire stm32 device.
7881 The @var{num} parameter is a value shown by @command{flash banks}.
7884 @deffn {Command} {stm32h7x mass_erase} num
7885 Mass erases the entire stm32h7x device.
7886 The @var{num} parameter is a value shown by @command{flash banks}.
7889 @deffn {Command} {stm32h7x option_read} num reg_offset
7890 Reads an option byte register from the stm32h7x device.
7891 The @var{num} parameter is a value shown by @command{flash banks}, @var{reg_offset}
7892 is the register offset of the option byte to read from the used bank registers' base.
7893 For example: in STM32H74x/H75x the bank 1 registers' base is 0x52002000 and 0x52002100 for bank 2.
7898 stm32h7x option_read 0 0x1c
7900 stm32h7x option_read 0 0x38
7902 stm32h7x option_read 1 0x38
7906 @deffn {Command} {stm32h7x option_write} num reg_offset value [reg_mask]
7907 Writes an option byte register of the stm32h7x device.
7908 The @var{num} parameter is a value shown by @command{flash banks}, @var{reg_offset}
7909 is the register offset of the option byte to write from the used bank register base,
7910 and @var{reg_mask} is the mask to apply when writing the register (only bits with a '1'
7915 # swap bank 1 and bank 2 in dual bank devices
7916 # by setting SWAP_BANK_OPT bit in OPTSR_PRG
7917 stm32h7x option_write 0 0x20 0x8000000 0x8000000
7922 @deffn {Flash Driver} {stm32lx}
7923 All members of the STM32L0 and STM32L1 microcontroller families from STMicroelectronics
7924 include internal flash and use ARM Cortex-M3 and Cortex-M0+ cores.
7925 The driver automatically recognizes a number of these chips using
7926 the chip identification register, and autoconfigures itself.
7929 flash bank $_FLASHNAME stm32lx 0 0 0 0 $_TARGETNAME
7932 Note that some devices have been found that have a flash size register that contains
7933 an invalid value, to workaround this issue you can override the probed value used by
7934 the flash driver. If you use 0 as the bank base address, it tells the
7935 driver to autodetect the bank location assuming you're configuring the
7939 flash bank $_FLASHNAME stm32lx 0x08000000 0x20000 0 0 $_TARGETNAME
7942 Some stm32lx-specific commands are defined:
7944 @deffn {Command} {stm32lx lock} num
7945 Locks the entire stm32 device.
7946 The @var{num} parameter is a value shown by @command{flash banks}.
7949 @deffn {Command} {stm32lx unlock} num
7950 Unlocks the entire stm32 device.
7951 The @var{num} parameter is a value shown by @command{flash banks}.
7954 @deffn {Command} {stm32lx mass_erase} num
7955 Mass erases the entire stm32lx device (all flash banks and EEPROM
7956 data). This is the only way to unlock a protected flash (unless RDP
7957 Level is 2 which can't be unlocked at all).
7958 The @var{num} parameter is a value shown by @command{flash banks}.
7962 @deffn {Flash Driver} {stm32l4x}
7963 All members of the STM32 G0, G4, L4, L4+, L5, U5, WB and WL
7964 microcontroller families from STMicroelectronics include internal flash
7965 and use ARM Cortex-M0+, M4 and M33 cores.
7966 The driver automatically recognizes a number of these chips using
7967 the chip identification register, and autoconfigures itself.
7970 flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME
7973 If you use OTP (One-Time Programmable) memory define it as a second bank
7974 as per the following example.
7976 flash bank $_FLASHNAME stm32l4x 0x1FFF7000 0 0 0 $_TARGETNAME
7979 @deffn {Command} {stm32l4x otp} num (@option{enable}|@option{disable}|@option{show})
7980 Enables or disables OTP write commands for bank @var{num}.
7981 The @var{num} parameter is a value shown by @command{flash banks}.
7984 Note that some devices have been found that have a flash size register that contains
7985 an invalid value, to workaround this issue you can override the probed value used by
7986 the flash driver. However, specifying a wrong value might lead to a completely
7987 wrong flash layout, so this feature must be used carefully.
7990 flash bank $_FLASHNAME stm32l4x 0x08000000 0x40000 0 0 $_TARGETNAME
7993 Some stm32l4x-specific commands are defined:
7995 @deffn {Command} {stm32l4x lock} num
7996 Locks the entire stm32 device.
7997 The @var{num} parameter is a value shown by @command{flash banks}.
7999 @emph{Note:} To apply the protection change immediately, use @command{stm32l4x option_load}.
8002 @deffn {Command} {stm32l4x unlock} num
8003 Unlocks the entire stm32 device.
8004 The @var{num} parameter is a value shown by @command{flash banks}.
8006 @emph{Note:} To apply the protection change immediately, use @command{stm32l4x option_load}.
8009 @deffn {Command} {stm32l4x mass_erase} num
8010 Mass erases the entire stm32l4x device.
8011 The @var{num} parameter is a value shown by @command{flash banks}.
8014 @deffn {Command} {stm32l4x option_read} num reg_offset
8015 Reads an option byte register from the stm32l4x device.
8016 The @var{num} parameter is a value shown by @command{flash banks}, @var{reg_offset}
8017 is the register offset of the Option byte to read.
8019 For example to read the FLASH_OPTR register:
8021 stm32l4x option_read 0 0x20
8022 # Option Register (for STM32L4x): <0x40022020> = 0xffeff8aa
8023 # Option Register (for STM32WBx): <0x58004020> = ...
8024 # The correct flash base address will be used automatically
8027 The above example will read out the FLASH_OPTR register which contains the RDP
8028 option byte, Watchdog configuration, BOR level etc.
8031 @deffn {Command} {stm32l4x option_write} num reg_offset reg_mask
8032 Write an option byte register of the stm32l4x device.
8033 The @var{num} parameter is a value shown by @command{flash banks}, @var{reg_offset}
8034 is the register offset of the Option byte to write, and @var{reg_mask} is the mask
8035 to apply when writing the register (only bits with a '1' will be touched).
8037 @emph{Note:} To apply the option bytes change immediately, use @command{stm32l4x option_load}.
8039 For example to write the WRP1AR option bytes:
8041 stm32l4x option_write 0 0x28 0x00FF0000 0x00FF00FF
8044 The above example will write the WRP1AR option register configuring the Write protection
8045 Area A for bank 1. The above example set WRP1AR_END=255, WRP1AR_START=0.
8046 This will effectively write protect all sectors in flash bank 1.
8049 @deffn {Command} {stm32l4x wrp_info} num [device_bank]
8050 List the protected areas using WRP.
8051 The @var{num} parameter is a value shown by @command{flash banks}.
8052 @var{device_bank} parameter is optional, possible values 'bank1' or 'bank2',
8053 if not specified, the command will display the whole flash protected areas.
8055 @b{Note:} @var{device_bank} is different from banks created using @code{flash bank}.
8056 Devices supported in this flash driver, can have main flash memory organized
8057 in single or dual-banks mode.
8058 Thus the usage of @var{device_bank} is meaningful only in dual-bank mode, to get
8059 write protected areas in a specific @var{device_bank}
8063 @deffn {Command} {stm32l4x option_load} num
8064 Forces a re-load of the option byte registers. Will cause a system reset of the device.
8065 The @var{num} parameter is a value shown by @command{flash banks}.
8068 @deffn Command {stm32l4x trustzone} num [@option{enable} | @option{disable}]
8069 Enables or disables Global TrustZone Security, using the TZEN option bit.
8070 If neither @option{enabled} nor @option{disable} are specified, the command will display
8071 the TrustZone status.
8072 @emph{Note:} This command works only with devices with TrustZone, eg. STM32L5.
8073 @emph{Note:} This command will perform an OBL_Launch after modifying the TZEN.
8077 @deffn {Flash Driver} {str7x}
8078 All members of the STR7 microcontroller family from STMicroelectronics
8079 include internal flash and use ARM7TDMI cores.
8080 The @var{str7x} driver defines one mandatory parameter, @var{variant},
8081 which is either @code{STR71x}, @code{STR73x} or @code{STR75x}.
8084 flash bank $_FLASHNAME str7x \
8085 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
8088 @deffn {Command} {str7x disable_jtag} bank
8089 Activate the Debug/Readout protection mechanism
8090 for the specified flash bank.
8094 @deffn {Flash Driver} {str9x}
8095 Most members of the STR9 microcontroller family from STMicroelectronics
8096 include internal flash and use ARM966E cores.
8097 The str9 needs the flash controller to be configured using
8098 the @command{str9x flash_config} command prior to Flash programming.
8101 flash bank $_FLASHNAME str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
8102 str9x flash_config 0 4 2 0 0x80000
8105 @deffn {Command} {str9x flash_config} num bbsr nbbsr bbadr nbbadr
8106 Configures the str9 flash controller.
8107 The @var{num} parameter is a value shown by @command{flash banks}.
8110 @item @var{bbsr} - Boot Bank Size register
8111 @item @var{nbbsr} - Non Boot Bank Size register
8112 @item @var{bbadr} - Boot Bank Start Address register
8113 @item @var{nbbadr} - Boot Bank Start Address register
8119 @deffn {Flash Driver} {str9xpec}
8122 Only use this driver for locking/unlocking the device or configuring the option bytes.
8123 Use the standard str9 driver for programming.
8124 Before using the flash commands the turbo mode must be enabled using the
8125 @command{str9xpec enable_turbo} command.
8127 Here is some background info to help
8128 you better understand how this driver works. OpenOCD has two flash drivers for
8132 Standard driver @option{str9x} programmed via the str9 core. Normally used for
8133 flash programming as it is faster than the @option{str9xpec} driver.
8135 Direct programming @option{str9xpec} using the flash controller. This is an
8136 ISC compliant (IEEE 1532) tap connected in series with the str9 core. The str9
8137 core does not need to be running to program using this flash driver. Typical use
8138 for this driver is locking/unlocking the target and programming the option bytes.
8141 Before we run any commands using the @option{str9xpec} driver we must first disable
8142 the str9 core. This example assumes the @option{str9xpec} driver has been
8143 configured for flash bank 0.
8145 # assert srst, we do not want core running
8146 # while accessing str9xpec flash driver
8148 # turn off target polling
8151 str9xpec enable_turbo 0
8153 str9xpec options_read 0
8154 # re-enable str9 core
8155 str9xpec disable_turbo 0
8159 The above example will read the str9 option bytes.
8160 When performing a unlock remember that you will not be able to halt the str9 - it
8161 has been locked. Halting the core is not required for the @option{str9xpec} driver
8162 as mentioned above, just issue the commands above manually or from a telnet prompt.
8164 Several str9xpec-specific commands are defined:
8166 @deffn {Command} {str9xpec disable_turbo} num
8167 Restore the str9 into JTAG chain.
8170 @deffn {Command} {str9xpec enable_turbo} num
8171 Enable turbo mode, will simply remove the str9 from the chain and talk
8172 directly to the embedded flash controller.
8175 @deffn {Command} {str9xpec lock} num
8176 Lock str9 device. The str9 will only respond to an unlock command that will
8180 @deffn {Command} {str9xpec part_id} num
8181 Prints the part identifier for bank @var{num}.
8184 @deffn {Command} {str9xpec options_cmap} num (@option{bank0}|@option{bank1})
8185 Configure str9 boot bank.
8188 @deffn {Command} {str9xpec options_lvdsel} num (@option{vdd}|@option{vdd_vddq})
8189 Configure str9 lvd source.
8192 @deffn {Command} {str9xpec options_lvdthd} num (@option{2.4v}|@option{2.7v})
8193 Configure str9 lvd threshold.
8196 @deffn {Command} {str9xpec options_lvdwarn} bank (@option{vdd}|@option{vdd_vddq})
8197 Configure str9 lvd reset warning source.
8200 @deffn {Command} {str9xpec options_read} num
8201 Read str9 option bytes.
8204 @deffn {Command} {str9xpec options_write} num
8205 Write str9 option bytes.
8208 @deffn {Command} {str9xpec unlock} num
8214 @deffn {Flash Driver} {swm050}
8216 All members of the swm050 microcontroller family from Foshan Synwit Tech.
8219 flash bank $_FLASHNAME swm050 0x0 0x2000 0 0 $_TARGETNAME
8222 One swm050-specific command is defined:
8224 @deffn {Command} {swm050 mass_erase} bank_id
8225 Erases the entire flash bank.
8231 @deffn {Flash Driver} {tms470}
8232 Most members of the TMS470 microcontroller family from Texas Instruments
8233 include internal flash and use ARM7TDMI cores.
8234 This driver doesn't require the chip and bus width to be specified.
8236 Some tms470-specific commands are defined:
8238 @deffn {Command} {tms470 flash_keyset} key0 key1 key2 key3
8239 Saves programming keys in a register, to enable flash erase and write commands.
8242 @deffn {Command} {tms470 osc_megahertz} clock_mhz
8243 Reports the clock speed, which is used to calculate timings.
8246 @deffn {Command} {tms470 plldis} (0|1)
8247 Disables (@var{1}) or enables (@var{0}) use of the PLL to speed up
8252 @deffn {Flash Driver} {w600}
8253 W60x series Wi-Fi SoC from WinnerMicro
8254 are designed with ARM Cortex-M3 and have 1M Byte QFLASH inside.
8255 The @var{w600} driver uses the @var{target} parameter to select the
8256 correct bank config.
8259 flash bank $_FLASHNAME w600 0x08000000 0 0 0 $_TARGETNAMEs
8263 @deffn {Flash Driver} {xmc1xxx}
8264 All members of the XMC1xxx microcontroller family from Infineon.
8265 This driver does not require the chip and bus width to be specified.
8268 @deffn {Flash Driver} {xmc4xxx}
8269 All members of the XMC4xxx microcontroller family from Infineon.
8270 This driver does not require the chip and bus width to be specified.
8272 Some xmc4xxx-specific commands are defined:
8274 @deffn {Command} {xmc4xxx flash_password} bank_id passwd1 passwd2
8275 Saves flash protection passwords which are used to lock the user flash
8278 @deffn {Command} {xmc4xxx flash_unprotect} bank_id user_level[0-1]
8279 Removes Flash write protection from the selected user bank
8284 @section NAND Flash Commands
8287 Compared to NOR or SPI flash, NAND devices are inexpensive
8288 and high density. Today's NAND chips, and multi-chip modules,
8289 commonly hold multiple GigaBytes of data.
8291 NAND chips consist of a number of ``erase blocks'' of a given
8292 size (such as 128 KBytes), each of which is divided into a
8293 number of pages (of perhaps 512 or 2048 bytes each). Each
8294 page of a NAND flash has an ``out of band'' (OOB) area to hold
8295 Error Correcting Code (ECC) and other metadata, usually 16 bytes
8296 of OOB for every 512 bytes of page data.
8298 One key characteristic of NAND flash is that its error rate
8299 is higher than that of NOR flash. In normal operation, that
8300 ECC is used to correct and detect errors. However, NAND
8301 blocks can also wear out and become unusable; those blocks
8302 are then marked "bad". NAND chips are even shipped from the
8303 manufacturer with a few bad blocks. The highest density chips
8304 use a technology (MLC) that wears out more quickly, so ECC
8305 support is increasingly important as a way to detect blocks
8306 that have begun to fail, and help to preserve data integrity
8307 with techniques such as wear leveling.
8309 Software is used to manage the ECC. Some controllers don't
8310 support ECC directly; in those cases, software ECC is used.
8311 Other controllers speed up the ECC calculations with hardware.
8312 Single-bit error correction hardware is routine. Controllers
8313 geared for newer MLC chips may correct 4 or more errors for
8314 every 512 bytes of data.
8316 You will need to make sure that any data you write using
8317 OpenOCD includes the appropriate kind of ECC. For example,
8318 that may mean passing the @code{oob_softecc} flag when
8319 writing NAND data, or ensuring that the correct hardware
8322 The basic steps for using NAND devices include:
8324 @item Declare via the command @command{nand device}
8325 @* Do this in a board-specific configuration file,
8326 passing parameters as needed by the controller.
8327 @item Configure each device using @command{nand probe}.
8328 @* Do this only after the associated target is set up,
8329 such as in its reset-init script or in procures defined
8330 to access that device.
8331 @item Operate on the flash via @command{nand subcommand}
8332 @* Often commands to manipulate the flash are typed by a human, or run
8333 via a script in some automated way. Common task include writing a
8334 boot loader, operating system, or other data needed to initialize or
8338 @b{NOTE:} At the time this text was written, the largest NAND
8339 flash fully supported by OpenOCD is 2 GiBytes (16 GiBits).
8340 This is because the variables used to hold offsets and lengths
8341 are only 32 bits wide.
8342 (Larger chips may work in some cases, unless an offset or length
8343 is larger than 0xffffffff, the largest 32-bit unsigned integer.)
8344 Some larger devices will work, since they are actually multi-chip
8345 modules with two smaller chips and individual chipselect lines.
8347 @anchor{nandconfiguration}
8348 @subsection NAND Configuration Commands
8349 @cindex NAND configuration
8351 NAND chips must be declared in configuration scripts,
8352 plus some additional configuration that's done after
8353 OpenOCD has initialized.
8355 @deffn {Config Command} {nand device} name driver target [configparams...]
8356 Declares a NAND device, which can be read and written to
8357 after it has been configured through @command{nand probe}.
8358 In OpenOCD, devices are single chips; this is unlike some
8359 operating systems, which may manage multiple chips as if
8360 they were a single (larger) device.
8361 In some cases, configuring a device will activate extra
8362 commands; see the controller-specific documentation.
8364 @b{NOTE:} This command is not available after OpenOCD
8365 initialization has completed. Use it in board specific
8366 configuration files, not interactively.
8369 @item @var{name} ... may be used to reference the NAND bank
8370 in most other NAND commands. A number is also available.
8371 @item @var{driver} ... identifies the NAND controller driver
8372 associated with the NAND device being declared.
8373 @xref{nanddriverlist,,NAND Driver List}.
8374 @item @var{target} ... names the target used when issuing
8375 commands to the NAND controller.
8376 @comment Actually, it's currently a controller-specific parameter...
8377 @item @var{configparams} ... controllers may support, or require,
8378 additional parameters. See the controller-specific documentation
8379 for more information.
8383 @deffn {Command} {nand list}
8384 Prints a summary of each device declared
8385 using @command{nand device}, numbered from zero.
8386 Note that un-probed devices show no details.
8389 #0: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
8390 blocksize: 131072, blocks: 8192
8391 #1: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
8392 blocksize: 131072, blocks: 8192
8397 @deffn {Command} {nand probe} num
8398 Probes the specified device to determine key characteristics
8399 like its page and block sizes, and how many blocks it has.
8400 The @var{num} parameter is the value shown by @command{nand list}.
8401 You must (successfully) probe a device before you can use
8402 it with most other NAND commands.
8405 @subsection Erasing, Reading, Writing to NAND Flash
8407 @deffn {Command} {nand dump} num filename offset length [oob_option]
8408 @cindex NAND reading
8409 Reads binary data from the NAND device and writes it to the file,
8410 starting at the specified offset.
8411 The @var{num} parameter is the value shown by @command{nand list}.
8413 Use a complete path name for @var{filename}, so you don't depend
8414 on the directory used to start the OpenOCD server.
8416 The @var{offset} and @var{length} must be exact multiples of the
8417 device's page size. They describe a data region; the OOB data
8418 associated with each such page may also be accessed.
8420 @b{NOTE:} At the time this text was written, no error correction
8421 was done on the data that's read, unless raw access was disabled
8422 and the underlying NAND controller driver had a @code{read_page}
8423 method which handled that error correction.
8425 By default, only page data is saved to the specified file.
8426 Use an @var{oob_option} parameter to save OOB data:
8428 @item no oob_* parameter
8429 @*Output file holds only page data; OOB is discarded.
8430 @item @code{oob_raw}
8431 @*Output file interleaves page data and OOB data;
8432 the file will be longer than "length" by the size of the
8433 spare areas associated with each data page.
8434 Note that this kind of "raw" access is different from
8435 what's implied by @command{nand raw_access}, which just
8436 controls whether a hardware-aware access method is used.
8437 @item @code{oob_only}
8438 @*Output file has only raw OOB data, and will
8439 be smaller than "length" since it will contain only the
8440 spare areas associated with each data page.
8444 @deffn {Command} {nand erase} num [offset length]
8445 @cindex NAND erasing
8446 @cindex NAND programming
8447 Erases blocks on the specified NAND device, starting at the
8448 specified @var{offset} and continuing for @var{length} bytes.
8449 Both of those values must be exact multiples of the device's
8450 block size, and the region they specify must fit entirely in the chip.
8451 If those parameters are not specified,
8452 the whole NAND chip will be erased.
8453 The @var{num} parameter is the value shown by @command{nand list}.
8455 @b{NOTE:} This command will try to erase bad blocks, when told
8456 to do so, which will probably invalidate the manufacturer's bad
8458 For the remainder of the current server session, @command{nand info}
8459 will still report that the block ``is'' bad.
8462 @deffn {Command} {nand write} num filename offset [option...]
8463 @cindex NAND writing
8464 @cindex NAND programming
8465 Writes binary data from the file into the specified NAND device,
8466 starting at the specified offset. Those pages should already
8467 have been erased; you can't change zero bits to one bits.
8468 The @var{num} parameter is the value shown by @command{nand list}.
8470 Use a complete path name for @var{filename}, so you don't depend
8471 on the directory used to start the OpenOCD server.
8473 The @var{offset} must be an exact multiple of the device's page size.
8474 All data in the file will be written, assuming it doesn't run
8475 past the end of the device.
8476 Only full pages are written, and any extra space in the last
8477 page will be filled with 0xff bytes. (That includes OOB data,
8478 if that's being written.)
8480 @b{NOTE:} At the time this text was written, bad blocks are
8481 ignored. That is, this routine will not skip bad blocks,
8482 but will instead try to write them. This can cause problems.
8484 Provide at most one @var{option} parameter. With some
8485 NAND drivers, the meanings of these parameters may change
8486 if @command{nand raw_access} was used to disable hardware ECC.
8488 @item no oob_* parameter
8489 @*File has only page data, which is written.
8490 If raw access is in use, the OOB area will not be written.
8491 Otherwise, if the underlying NAND controller driver has
8492 a @code{write_page} routine, that routine may write the OOB
8493 with hardware-computed ECC data.
8494 @item @code{oob_only}
8495 @*File has only raw OOB data, which is written to the OOB area.
8496 Each page's data area stays untouched. @i{This can be a dangerous
8497 option}, since it can invalidate the ECC data.
8498 You may need to force raw access to use this mode.
8499 @item @code{oob_raw}
8500 @*File interleaves data and OOB data, both of which are written
8501 If raw access is enabled, the data is written first, then the
8503 Otherwise, if the underlying NAND controller driver has
8504 a @code{write_page} routine, that routine may modify the OOB
8505 before it's written, to include hardware-computed ECC data.
8506 @item @code{oob_softecc}
8507 @*File has only page data, which is written.
8508 The OOB area is filled with 0xff, except for a standard 1-bit
8509 software ECC code stored in conventional locations.
8510 You might need to force raw access to use this mode, to prevent
8511 the underlying driver from applying hardware ECC.
8512 @item @code{oob_softecc_kw}
8513 @*File has only page data, which is written.
8514 The OOB area is filled with 0xff, except for a 4-bit software ECC
8515 specific to the boot ROM in Marvell Kirkwood SoCs.
8516 You might need to force raw access to use this mode, to prevent
8517 the underlying driver from applying hardware ECC.
8521 @deffn {Command} {nand verify} num filename offset [option...]
8522 @cindex NAND verification
8523 @cindex NAND programming
8524 Verify the binary data in the file has been programmed to the
8525 specified NAND device, starting at the specified offset.
8526 The @var{num} parameter is the value shown by @command{nand list}.
8528 Use a complete path name for @var{filename}, so you don't depend
8529 on the directory used to start the OpenOCD server.
8531 The @var{offset} must be an exact multiple of the device's page size.
8532 All data in the file will be read and compared to the contents of the
8533 flash, assuming it doesn't run past the end of the device.
8534 As with @command{nand write}, only full pages are verified, so any extra
8535 space in the last page will be filled with 0xff bytes.
8537 The same @var{options} accepted by @command{nand write},
8538 and the file will be processed similarly to produce the buffers that
8539 can be compared against the contents produced from @command{nand dump}.
8541 @b{NOTE:} This will not work when the underlying NAND controller
8542 driver's @code{write_page} routine must update the OOB with a
8543 hardware-computed ECC before the data is written. This limitation may
8544 be removed in a future release.
8547 @subsection Other NAND commands
8548 @cindex NAND other commands
8550 @deffn {Command} {nand check_bad_blocks} num [offset length]
8551 Checks for manufacturer bad block markers on the specified NAND
8552 device. If no parameters are provided, checks the whole
8553 device; otherwise, starts at the specified @var{offset} and
8554 continues for @var{length} bytes.
8555 Both of those values must be exact multiples of the device's
8556 block size, and the region they specify must fit entirely in the chip.
8557 The @var{num} parameter is the value shown by @command{nand list}.
8559 @b{NOTE:} Before using this command you should force raw access
8560 with @command{nand raw_access enable} to ensure that the underlying
8561 driver will not try to apply hardware ECC.
8564 @deffn {Command} {nand info} num
8565 The @var{num} parameter is the value shown by @command{nand list}.
8566 This prints the one-line summary from "nand list", plus for
8567 devices which have been probed this also prints any known
8568 status for each block.
8571 @deffn {Command} {nand raw_access} num (@option{enable}|@option{disable})
8572 Sets or clears an flag affecting how page I/O is done.
8573 The @var{num} parameter is the value shown by @command{nand list}.
8575 This flag is cleared (disabled) by default, but changing that
8576 value won't affect all NAND devices. The key factor is whether
8577 the underlying driver provides @code{read_page} or @code{write_page}
8578 methods. If it doesn't provide those methods, the setting of
8579 this flag is irrelevant; all access is effectively ``raw''.
8581 When those methods exist, they are normally used when reading
8582 data (@command{nand dump} or reading bad block markers) or
8583 writing it (@command{nand write}). However, enabling
8584 raw access (setting the flag) prevents use of those methods,
8585 bypassing hardware ECC logic.
8586 @i{This can be a dangerous option}, since writing blocks
8587 with the wrong ECC data can cause them to be marked as bad.
8590 @anchor{nanddriverlist}
8591 @subsection NAND Driver List
8592 As noted above, the @command{nand device} command allows
8593 driver-specific options and behaviors.
8594 Some controllers also activate controller-specific commands.
8596 @deffn {NAND Driver} {at91sam9}
8597 This driver handles the NAND controllers found on AT91SAM9 family chips from
8598 Atmel. It takes two extra parameters: address of the NAND chip;
8599 address of the ECC controller.
8601 nand device $NANDFLASH at91sam9 $CHIPNAME 0x40000000 0xfffffe800
8603 AT91SAM9 chips support single-bit ECC hardware. The @code{write_page} and
8604 @code{read_page} methods are used to utilize the ECC hardware unless they are
8605 disabled by using the @command{nand raw_access} command. There are four
8606 additional commands that are needed to fully configure the AT91SAM9 NAND
8607 controller. Two are optional; most boards use the same wiring for ALE/CLE:
8608 @deffn {Config Command} {at91sam9 cle} num addr_line
8609 Configure the address line used for latching commands. The @var{num}
8610 parameter is the value shown by @command{nand list}.
8612 @deffn {Config Command} {at91sam9 ale} num addr_line
8613 Configure the address line used for latching addresses. The @var{num}
8614 parameter is the value shown by @command{nand list}.
8617 For the next two commands, it is assumed that the pins have already been
8618 properly configured for input or output.
8619 @deffn {Config Command} {at91sam9 rdy_busy} num pio_base_addr pin
8620 Configure the RDY/nBUSY input from the NAND device. The @var{num}
8621 parameter is the value shown by @command{nand list}. @var{pio_base_addr}
8622 is the base address of the PIO controller and @var{pin} is the pin number.
8624 @deffn {Config Command} {at91sam9 ce} num pio_base_addr pin
8625 Configure the chip enable input to the NAND device. The @var{num}
8626 parameter is the value shown by @command{nand list}. @var{pio_base_addr}
8627 is the base address of the PIO controller and @var{pin} is the pin number.
8631 @deffn {NAND Driver} {davinci}
8632 This driver handles the NAND controllers found on DaVinci family
8633 chips from Texas Instruments.
8634 It takes three extra parameters:
8635 address of the NAND chip;
8636 hardware ECC mode to use (@option{hwecc1},
8637 @option{hwecc4}, @option{hwecc4_infix});
8638 address of the AEMIF controller on this processor.
8640 nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000
8642 All DaVinci processors support the single-bit ECC hardware,
8643 and newer ones also support the four-bit ECC hardware.
8644 The @code{write_page} and @code{read_page} methods are used
8645 to implement those ECC modes, unless they are disabled using
8646 the @command{nand raw_access} command.
8649 @deffn {NAND Driver} {lpc3180}
8650 These controllers require an extra @command{nand device}
8651 parameter: the clock rate used by the controller.
8652 @deffn {Command} {lpc3180 select} num [mlc|slc]
8653 Configures use of the MLC or SLC controller mode.
8654 MLC implies use of hardware ECC.
8655 The @var{num} parameter is the value shown by @command{nand list}.
8658 At this writing, this driver includes @code{write_page}
8659 and @code{read_page} methods. Using @command{nand raw_access}
8660 to disable those methods will prevent use of hardware ECC
8661 in the MLC controller mode, but won't change SLC behavior.
8663 @comment current lpc3180 code won't issue 5-byte address cycles
8665 @deffn {NAND Driver} {mx3}
8666 This driver handles the NAND controller in i.MX31. The mxc driver
8667 should work for this chip as well.
8670 @deffn {NAND Driver} {mxc}
8671 This driver handles the NAND controller found in Freescale i.MX
8672 chips. It has support for v1 (i.MX27 and i.MX31) and v2 (i.MX35).
8673 The driver takes 3 extra arguments, chip (@option{mx27},
8674 @option{mx31}, @option{mx35}), ecc (@option{noecc}, @option{hwecc})
8675 and optionally if bad block information should be swapped between
8676 main area and spare area (@option{biswap}), defaults to off.
8678 nand device mx35.nand mxc imx35.cpu mx35 hwecc biswap
8680 @deffn {Command} {mxc biswap} bank_num [enable|disable]
8681 Turns on/off bad block information swapping from main area,
8682 without parameter query status.
8686 @deffn {NAND Driver} {orion}
8687 These controllers require an extra @command{nand device}
8688 parameter: the address of the controller.
8690 nand device orion 0xd8000000
8692 These controllers don't define any specialized commands.
8693 At this writing, their drivers don't include @code{write_page}
8694 or @code{read_page} methods, so @command{nand raw_access} won't
8695 change any behavior.
8698 @deffn {NAND Driver} {s3c2410}
8699 @deffnx {NAND Driver} {s3c2412}
8700 @deffnx {NAND Driver} {s3c2440}
8701 @deffnx {NAND Driver} {s3c2443}
8702 @deffnx {NAND Driver} {s3c6400}
8703 These S3C family controllers don't have any special
8704 @command{nand device} options, and don't define any
8705 specialized commands.
8706 At this writing, their drivers don't include @code{write_page}
8707 or @code{read_page} methods, so @command{nand raw_access} won't
8708 change any behavior.
8711 @node Flash Programming
8712 @chapter Flash Programming
8714 OpenOCD implements numerous ways to program the target flash, whether internal or external.
8715 Programming can be achieved by either using @ref{programmingusinggdb,,Programming using GDB},
8716 or using the commands given in @ref{flashprogrammingcommands,,Flash Programming Commands}.
8718 @*To simplify using the flash commands directly a jimtcl script is available that handles the programming and verify stage.
8719 OpenOCD will program/verify/reset the target and optionally shutdown.
8721 The script is executed as follows and by default the following actions will be performed.
8723 @item 'init' is executed.
8724 @item 'reset init' is called to reset and halt the target, any 'reset init' scripts are executed.
8725 @item @code{flash write_image} is called to erase and write any flash using the filename given.
8726 @item If the @option{preverify} parameter is given, the target is "verified" first and only flashed if this fails.
8727 @item @code{verify_image} is called if @option{verify} parameter is given.
8728 @item @code{reset run} is called if @option{reset} parameter is given.
8729 @item OpenOCD is shutdown if @option{exit} parameter is given.
8732 An example of usage is given below. @xref{program}.
8735 # program and verify using elf/hex/s19. verify and reset
8736 # are optional parameters
8737 openocd -f board/stm32f3discovery.cfg \
8738 -c "program filename.elf verify reset exit"
8740 # binary files need the flash address passing
8741 openocd -f board/stm32f3discovery.cfg \
8742 -c "program filename.bin exit 0x08000000"
8745 @node PLD/FPGA Commands
8746 @chapter PLD/FPGA Commands
8750 Programmable Logic Devices (PLDs) and the more flexible
8751 Field Programmable Gate Arrays (FPGAs) are both types of programmable hardware.
8752 OpenOCD can support programming them.
8753 Although PLDs are generally restrictive (cells are less functional, and
8754 there are no special purpose cells for memory or computational tasks),
8755 they share the same OpenOCD infrastructure.
8756 Accordingly, both are called PLDs here.
8758 @section PLD/FPGA Configuration and Commands
8760 As it does for JTAG TAPs, debug targets, and flash chips (both NOR and NAND),
8761 OpenOCD maintains a list of PLDs available for use in various commands.
8762 Also, each such PLD requires a driver. PLD drivers may also be needed to program
8763 SPI flash connected to the FPGA to store the bitstream (@xref{jtagspi} for details).
8765 They are referenced by the name which was given when the pld was created or
8766 the number shown by the @command{pld devices} command.
8767 New PLDs are defined by @command{pld create pld_name driver_name -chain-position tap_name [driver_options]}.
8769 @deffn {Config Command} {pld create} pld_name driver_name -chain-position tap_name [driver_options]
8770 Creates a new PLD device, supported by driver @var{driver_name},
8771 assigning @var{pld_name} for further reference.
8772 @code{-chain-position} @var{tap_name} names the TAP
8773 used to access this target.
8774 The driver may make use of any @var{driver_options} to configure its behavior.
8777 @deffn {Command} {pld devices}
8778 List the known PLDs with their name.
8781 @deffn {Command} {pld load} pld_name filename
8782 Loads the file @file{filename} into the PLD identified by @var{pld_name}.
8783 The file format must be inferred by the driver.
8786 @section PLD/FPGA Drivers, Options, and Commands
8788 Drivers may support PLD-specific options to the @command{pld device}
8789 definition command, and may also define commands usable only with
8790 that particular type of PLD.
8792 @deffn {FPGA Driver} {virtex2} [@option{-no_jstart}]
8793 Virtex-II is a family of FPGAs sold by Xilinx.
8794 This driver can also be used to load Series3, Series6, Series7 and Zynq 7000 devices.
8795 It supports the IEEE 1532 standard for In-System Configuration (ISC).
8797 If @var{-no_jstart} is given, the JSTART instruction is not used after
8798 loading the bitstream. While required for Series2, Series3, and Series6, it
8799 breaks bitstream loading on Series7.
8802 openocd -f board/digilent_zedboard.cfg -c "init" \
8803 -c "pld load 0 zedboard_bitstream.bit"
8807 @deffn {Command} {virtex2 read_stat} pld_name
8808 Reads and displays the Virtex-II status register (STAT)
8809 for FPGA @var{pld_name}.
8812 @deffn {Command} {virtex2 set_instr_codes} pld_name cfg_out cfg_in jprogb jstart jshutdown [user1 [user2 [user3 [user4]]]]
8813 Change values for boundary scan instructions. Default are values for Virtex 2, devices Virtex 4/5/6 and
8814 SSI devices are using different values.
8815 @var{pld_name} is the name of the pld device.
8816 @var{cfg_out} is the value used to select CFG_OUT instruction.
8817 @var{cfg_in} is the value used to select CFG_IN instruction.
8818 @var{jprogb} is the value used to select JPROGRAM instruction.
8819 @var{jstart} is the value used to select JSTART instruction.
8820 @var{jshutdown} is the value used to select JSHUTDOWN instruction.
8821 @var{user1} to @var{user4} are the intruction used to select the user registers USER1 to USER4.
8824 @deffn {Command} {virtex2 set_user_codes} pld_name user1 [user2 [user3 [user4]]]
8825 Change values for boundary scan instructions selecting the registers USER1 to USER4.
8826 Description of the arguments can be found at command @command{virtex2 set_instr_codes}.
8829 @deffn {Command} {virtex2 refresh} pld_name
8830 Load the bitstream from external memory for FPGA @var{pld_name}. A.k.a. program.
8836 @deffn {FPGA Driver} {lattice} [@option{-family} <name>]
8837 The FGPA families ECP2, ECP3, ECP5, Certus and CertusPro by Lattice are supported.
8838 This driver can be used to load the bitstream into the FPGA or read the status register and read/write the usercode register.
8840 For the option @option{-family} @var{name} is one of @var{ecp2 ecp3 ecp5 certus}. This is needed when the JTAG ID of the device is not known by openocd (newer NX devices).
8842 @deffn {Command} {lattice read_status} pld_name
8843 Reads and displays the status register
8844 for FPGA @var{pld_name}.
8847 @deffn {Command} {lattice read_user} pld_name
8848 Reads and displays the user register
8849 for FPGA @var{pld_name}.
8852 @deffn {Command} {lattice write_user} pld_name val
8853 Writes the user register.
8854 for FPGA @var{pld_name} with value @var{val}.
8857 @deffn {Command} {lattice set_preload} pld_name length
8858 Set the length of the register for the preload. This is needed when the JTAG ID of the device is not known by openocd (newer NX devices).
8859 The load command for the FPGA @var{pld_name} will use a length for the preload of @var{length}.
8862 @deffn {Command} {lattice refresh} pld_name
8863 Load the bitstream from external memory for FPGA @var{pld_name}. A.k.a program.
8868 @deffn {FPGA Driver} {efinix} [@option{-family} <name>]
8869 Both families (Trion and Titanium) sold by Efinix are supported as both use the same protocol for In-System Configuration.
8870 This driver can be used to load the bitstream into the FPGA.
8871 For the option @option{-family} @var{name} is one of @var{trion|titanium}.
8875 @deffn {FPGA Driver} {intel} [@option{-family} <name>]
8876 This driver can be used to load the bitstream into Intel (former Altera) FPGAs.
8877 The families Cyclone III, Cyclone IV, Cyclone V, Cyclone 10, Arria II are supported.
8878 @c Arria V and Arria 10, MAX II, MAX V, MAX10)
8880 For the option @option{-family} @var{name} is one of @var{cycloneiii cycloneiv cyclonev cyclone10 arriaii}.
8881 This is needed when the JTAG ID of the device is ambiguous (same ID is used for chips in different families).
8883 As input file format the driver supports a '.rbf' (raw bitstream file) file. The '.rbf' file can be generated
8884 from a '.sof' file with @verb{|quartus_cpf -c blinker.sof blinker.rbf|}
8886 Creates a new PLD device, an FPGA of the Cyclone III family, using the TAP named @verb{|cycloneiii.tap|}:
8888 pld create cycloneiii.pld intel -chain-position cycloneiii.tap -family cycloneiii
8891 @deffn {Command} {intel set_bscan} pld_name len
8892 Set boundary scan register length of FPGA @var{pld_name} to @var{len}. This is needed because the
8893 length can vary between chips with the same JTAG ID.
8896 @deffn {Command} {intel set_check_pos} pld_name pos
8897 Selects the position @var{pos} in the boundary-scan register. The bit at this
8898 position is checked after loading the bitstream and must be '1', which is the case when no error occurred.
8899 With a value of -1 for @var{pos} the check will be omitted.
8904 @deffn {FPGA Driver} {gowin}
8905 This driver can be used to load the bitstream into FPGAs from Gowin.
8906 It is possible to program the SRAM. Programming the flash is not supported.
8907 The files @verb{|.fs|} and @verb{|.bin|} generated by Gowin FPGA Designer are supported.
8909 @deffn {Command} {gowin read_status} pld_name
8910 Reads and displays the status register
8911 for FPGA @var{pld_name}.
8914 @deffn {Command} {gowin read_user} pld_name
8915 Reads and displays the user register
8916 for FPGA @var{pld_name}.
8919 @deffn {Command} {gowin refresh} pld_name
8920 Load the bitstream from external memory for
8921 FPGA @var{pld_name}. A.k.a. reload.
8926 @deffn {FPGA Driver} {gatemate}
8927 This driver can be used to load the bitstream into GateMate FPGAs form CologneChip.
8928 The files @verb{|.bit|} and @verb{|.cfg|} both generated by p_r tool from CologneChip are supported.
8932 @node General Commands
8933 @chapter General Commands
8936 The commands documented in this chapter here are common commands that
8937 you, as a human, may want to type and see the output of. Configuration type
8938 commands are documented elsewhere.
8942 @item @b{Source Of Commands}
8943 @* OpenOCD commands can occur in a configuration script (discussed
8944 elsewhere) or typed manually by a human or supplied programmatically,
8945 or via one of several TCP/IP Ports.
8947 @item @b{From the human}
8948 @* A human should interact with the telnet interface (default port: 4444)
8949 or via GDB (default port 3333).
8951 To issue commands from within a GDB session, use the @option{monitor}
8952 command, e.g. use @option{monitor poll} to issue the @option{poll}
8953 command. All output is relayed through the GDB session.
8955 @item @b{Machine Interface}
8956 The Tcl interface's intent is to be a machine interface. The default Tcl
8961 @section Server Commands
8963 @deffn {Command} {exit}
8964 Exits the current telnet session.
8967 @deffn {Command} {help} [string]
8968 With no parameters, prints help text for all commands.
8969 Otherwise, prints each helptext containing @var{string}.
8970 Not every command provides helptext.
8972 Configuration commands, and commands valid at any time, are
8973 explicitly noted in parenthesis.
8974 In most cases, no such restriction is listed; this indicates commands
8975 which are only available after the configuration stage has completed.
8978 @deffn {Command} {usage} [string]
8979 With no parameters, prints usage text for all commands. Otherwise,
8980 prints all usage text of which command, help text, and usage text
8981 containing @var{string}.
8982 Not every command provides helptext.
8985 @deffn {Command} {sleep} msec [@option{busy}]
8986 Wait for at least @var{msec} milliseconds before resuming.
8987 If @option{busy} is passed, busy-wait instead of sleeping.
8988 (This option is strongly discouraged.)
8989 Useful in connection with script files
8990 (@command{script} command and @command{target_name} configuration).
8993 @deffn {Command} {shutdown} [@option{error}]
8994 Close the OpenOCD server, disconnecting all clients (GDB, telnet,
8995 other). If option @option{error} is used, OpenOCD will return a
8996 non-zero exit code to the parent process.
8998 If user types CTRL-C or kills OpenOCD, the command @command{shutdown}
8999 will be automatically executed to cause OpenOCD to exit.
9001 It is possible to specify, in the TCL list @var{pre_shutdown_commands} , a
9002 set of commands to be automatically executed before @command{shutdown} , e.g.:
9004 lappend pre_shutdown_commands @{echo "Goodbye, my friend ..."@}
9005 lappend pre_shutdown_commands @{echo "see you soon !"@}
9007 The commands in the list will be executed (in the same order they occupy
9008 in the list) before OpenOCD exits. If one of the commands in the list
9009 fails, then the remaining commands are not executed anymore while OpenOCD
9010 will proceed to quit.
9014 @deffn {Command} {debug_level} [n]
9015 @cindex message level
9016 Display debug level.
9017 If @var{n} (from 0..4) is provided, then set it to that level.
9018 This affects the kind of messages sent to the server log.
9019 Level 0 is error messages only;
9020 level 1 adds warnings;
9021 level 2 adds informational messages;
9022 level 3 adds debugging messages;
9023 and level 4 adds verbose low-level debug messages.
9024 The default is level 2, but that can be overridden on
9025 the command line along with the location of that log
9026 file (which is normally the server's standard output).
9030 @deffn {Command} {echo} [-n] message
9031 Logs a message at "user" priority.
9032 Option "-n" suppresses trailing newline.
9034 echo "Downloading kernel -- please wait"
9038 @deffn {Command} {log_output} [filename | "default"]
9039 Redirect logging to @var{filename} or set it back to default output;
9040 the default log output channel is stderr.
9043 @deffn {Command} {add_script_search_dir} [directory]
9044 Add @var{directory} to the file/script search path.
9047 @deffn {Config Command} {bindto} [@var{name}]
9048 Specify hostname or IPv4 address on which to listen for incoming
9049 TCP/IP connections. By default, OpenOCD will listen on the loopback
9050 interface only. If your network environment is safe, @code{bindto
9051 0.0.0.0} can be used to cover all available interfaces.
9054 @anchor{targetstatehandling}
9055 @section Target State handling
9058 @cindex target initialization
9060 In this section ``target'' refers to a CPU configured as
9061 shown earlier (@pxref{CPU Configuration}).
9062 These commands, like many, implicitly refer to
9063 a current target which is used to perform the
9064 various operations. The current target may be changed
9065 by using @command{targets} command with the name of the
9066 target which should become current.
9068 @deffn {Command} {reg} [(number|name) [(value|'force')]]
9069 Access a single register by @var{number} or by its @var{name}.
9070 The target must generally be halted before access to CPU core
9071 registers is allowed. Depending on the hardware, some other
9072 registers may be accessible while the target is running.
9074 @emph{With no arguments}:
9075 list all available registers for the current target,
9076 showing number, name, size, value, and cache status.
9077 For valid entries, a value is shown; valid entries
9078 which are also dirty (and will be written back later)
9079 are flagged as such.
9081 @emph{With number/name}: display that register's value.
9082 Use @var{force} argument to read directly from the target,
9083 bypassing any internal cache.
9085 @emph{With both number/name and value}: set register's value.
9086 Writes may be held in a writeback cache internal to OpenOCD,
9087 so that setting the value marks the register as dirty instead
9088 of immediately flushing that value. Resuming CPU execution
9089 (including by single stepping) or otherwise activating the
9090 relevant module will flush such values.
9092 Cores may have surprisingly many registers in their
9093 Debug and trace infrastructure:
9098 (0) r0 (/32): 0x0000D3C2 (dirty)
9099 (1) r1 (/32): 0xFD61F31C
9102 (164) ETM_contextid_comparator_mask (/32)
9107 @deffn {Command} {set_reg} dict
9108 Set register values of the target.
9111 @item @var{dict} ... Tcl dictionary with pairs of register names and values.
9114 For example, the following command sets the value 0 to the program counter (pc)
9115 register and 0x1000 to the stack pointer (sp) register:
9118 set_reg @{pc 0 sp 0x1000@}
9122 @deffn {Command} {get_reg} [-force] list
9123 Get register values from the target and return them as Tcl dictionary with pairs
9124 of register names and values.
9125 If option "-force" is set, the register values are read directly from the
9126 target, bypassing any caching.
9129 @item @var{list} ... List of register names
9132 For example, the following command retrieves the values from the program
9133 counter (pc) and stack pointer (sp) register:
9140 @deffn {Command} {write_memory} address width data ['phys']
9141 This function provides an efficient way to write to the target memory from a Tcl
9145 @item @var{address} ... target memory address
9146 @item @var{width} ... memory access bit size, can be 8, 16, 32 or 64
9147 @item @var{data} ... Tcl list with the elements to write
9148 @item ['phys'] ... treat the memory address as physical instead of virtual address
9151 For example, the following command writes two 32 bit words into the target
9152 memory at address 0x20000000:
9155 write_memory 0x20000000 32 @{0xdeadbeef 0x00230500@}
9159 @deffn {Command} {read_memory} address width count ['phys']
9160 This function provides an efficient way to read the target memory from a Tcl
9162 A Tcl list containing the requested memory elements is returned by this function.
9165 @item @var{address} ... target memory address
9166 @item @var{width} ... memory access bit size, can be 8, 16, 32 or 64
9167 @item @var{count} ... number of elements to read
9168 @item ['phys'] ... treat the memory address as physical instead of virtual address
9171 For example, the following command reads two 32 bit words from the target
9172 memory at address 0x20000000:
9175 read_memory 0x20000000 32 2
9179 @deffn {Command} {halt} [ms]
9180 @deffnx {Command} {wait_halt} [ms]
9181 The @command{halt} command first sends a halt request to the target,
9182 which @command{wait_halt} doesn't.
9183 Otherwise these behave the same: wait up to @var{ms} milliseconds,
9184 or 5 seconds if there is no parameter, for the target to halt
9185 (and enter debug mode).
9186 Using 0 as the @var{ms} parameter prevents OpenOCD from waiting.
9189 On ARM cores, software using the @emph{wait for interrupt} operation
9190 often blocks the JTAG access needed by a @command{halt} command.
9191 This is because that operation also puts the core into a low
9192 power mode by gating the core clock;
9193 but the core clock is needed to detect JTAG clock transitions.
9195 One partial workaround uses adaptive clocking: when the core is
9196 interrupted the operation completes, then JTAG clocks are accepted
9197 at least until the interrupt handler completes.
9198 However, this workaround is often unusable since the processor, board,
9199 and JTAG adapter must all support adaptive JTAG clocking.
9200 Also, it can't work until an interrupt is issued.
9202 A more complete workaround is to not use that operation while you
9203 work with a JTAG debugger.
9204 Tasking environments generally have idle loops where the body is the
9205 @emph{wait for interrupt} operation.
9206 (On older cores, it is a coprocessor action;
9207 newer cores have a @option{wfi} instruction.)
9208 Such loops can just remove that operation, at the cost of higher
9209 power consumption (because the CPU is needlessly clocked).
9214 @deffn {Command} {resume} [address]
9215 Resume the target at its current code position,
9216 or the optional @var{address} if it is provided.
9219 @deffn {Command} {step} [address]
9220 Single-step the target at its current code position,
9221 or the optional @var{address} if it is provided.
9224 @anchor{resetcommand}
9225 @deffn {Command} {reset}
9226 @deffnx {Command} {reset run}
9227 @deffnx {Command} {reset halt}
9228 @deffnx {Command} {reset init}
9229 Perform as hard a reset as possible, using SRST if possible.
9230 @emph{All defined targets will be reset, and target
9231 events will fire during the reset sequence.}
9233 The optional parameter specifies what should
9234 happen after the reset.
9235 If there is no parameter, a @command{reset run} is executed.
9236 The other options will not work on all systems.
9237 @xref{Reset Configuration}.
9240 @item @b{run} Let the target run
9241 @item @b{halt} Immediately halt the target
9242 @item @b{init} Immediately halt the target, and execute the reset-init script
9246 @deffn {Command} {soft_reset_halt}
9247 Requesting target halt and executing a soft reset. This is often used
9248 when a target cannot be reset and halted. The target, after reset is
9249 released begins to execute code. OpenOCD attempts to stop the CPU and
9250 then sets the program counter back to the reset vector. Unfortunately
9251 the code that was executed may have left the hardware in an unknown
9255 @deffn {Command} {adapter assert} [signal [assert|deassert signal]]
9256 @deffnx {Command} {adapter deassert} [signal [assert|deassert signal]]
9257 Set values of reset signals.
9258 Without parameters returns current status of the signals.
9259 The @var{signal} parameter values may be
9260 @option{srst}, indicating that srst signal is to be asserted or deasserted,
9261 @option{trst}, indicating that trst signal is to be asserted or deasserted.
9263 The @command{reset_config} command should already have been used
9264 to configure how the board and the adapter treat these two
9265 signals, and to say if either signal is even present.
9266 @xref{Reset Configuration}.
9267 Trying to assert a signal that is not present triggers an error.
9268 If a signal is present on the adapter and not specified in the command,
9269 the signal will not be modified.
9272 TRST is specially handled.
9273 It actually signifies JTAG's @sc{reset} state.
9274 So if the board doesn't support the optional TRST signal,
9275 or it doesn't support it along with the specified SRST value,
9276 JTAG reset is triggered with TMS and TCK signals
9277 instead of the TRST signal.
9278 And no matter how that JTAG reset is triggered, once
9279 the scan chain enters @sc{reset} with TRST inactive,
9280 TAP @code{post-reset} events are delivered to all TAPs
9281 with handlers for that event.
9285 @anchor{memoryaccess}
9286 @section Memory access commands
9287 @cindex memory access
9289 These commands allow accesses of a specific size to the memory
9290 system. Often these are used to configure the current target in some
9291 special way. For example - one may need to write certain values to the
9292 SDRAM controller to enable SDRAM.
9295 @item Use the @command{targets} (plural) command
9296 to change the current target.
9297 @item In system level scripts these commands are deprecated.
9298 Please use their TARGET object siblings to avoid making assumptions
9299 about what TAP is the current target, or about MMU configuration.
9302 @deffn {Command} {mdd} [phys] addr [count]
9303 @deffnx {Command} {mdw} [phys] addr [count]
9304 @deffnx {Command} {mdh} [phys] addr [count]
9305 @deffnx {Command} {mdb} [phys] addr [count]
9306 Display contents of address @var{addr}, as
9307 64-bit doublewords (@command{mdd}),
9308 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
9309 or 8-bit bytes (@command{mdb}).
9310 When the current target has an MMU which is present and active,
9311 @var{addr} is interpreted as a virtual address.
9312 Otherwise, or if the optional @var{phys} flag is specified,
9313 @var{addr} is interpreted as a physical address.
9314 If @var{count} is specified, displays that many units.
9315 (If you want to process the data instead of displaying it,
9316 see the @code{read_memory} primitives.)
9319 @deffn {Command} {mwd} [phys] addr doubleword [count]
9320 @deffnx {Command} {mww} [phys] addr word [count]
9321 @deffnx {Command} {mwh} [phys] addr halfword [count]
9322 @deffnx {Command} {mwb} [phys] addr byte [count]
9323 Writes the specified @var{doubleword} (64 bits), @var{word} (32 bits),
9324 @var{halfword} (16 bits), or @var{byte} (8-bit) value,
9325 at the specified address @var{addr}.
9326 When the current target has an MMU which is present and active,
9327 @var{addr} is interpreted as a virtual address.
9328 Otherwise, or if the optional @var{phys} flag is specified,
9329 @var{addr} is interpreted as a physical address.
9330 If @var{count} is specified, fills that many units of consecutive address.
9333 @anchor{imageaccess}
9334 @section Image loading commands
9335 @cindex image loading
9336 @cindex image dumping
9338 @deffn {Command} {dump_image} filename address size
9339 Dump @var{size} bytes of target memory starting at @var{address} to the
9340 binary file named @var{filename}.
9343 @deffn {Command} {fast_load}
9344 Loads an image stored in memory by @command{fast_load_image} to the
9345 current target. Must be preceded by fast_load_image.
9348 @deffn {Command} {fast_load_image} filename [address [@option{bin}|@option{ihex}|@option{elf}|@option{s19} [@option{min_addr} [@option{max_length}]]]]]]
9349 Normally you should be using @command{load_image} or GDB load. However, for
9350 testing purposes or when I/O overhead is significant(OpenOCD running on an embedded
9351 host), storing the image in memory and uploading the image to the target
9352 can be a way to upload e.g. multiple debug sessions when the binary does not change.
9353 Arguments are the same as @command{load_image}, but the image is stored in OpenOCD host
9354 memory, i.e. does not affect target. This approach is also useful when profiling
9355 target programming performance as I/O and target programming can easily be profiled
9359 @deffn {Command} {load_image} filename [address [@option{bin}|@option{ihex}|@option{elf}|@option{s19} [@option{min_addr} [@option{max_length}]]]]
9360 Load image from file @var{filename} to target memory.
9361 If an @var{address} is specified, it is used as an offset to the file format
9362 defined addressing (e.g. @option{bin} file is loaded at that address).
9363 The file format may optionally be specified
9364 (@option{bin}, @option{ihex}, @option{elf}, or @option{s19}).
9365 In addition the following arguments may be specified:
9366 @var{min_addr} - ignore data below @var{min_addr} (this is w.r.t. to the target's load address + @var{address})
9367 @var{max_length} - maximum number of bytes to load.
9369 proc load_image_bin @{fname foffset address length @} @{
9370 # Load data from fname filename at foffset offset to
9371 # target at address. Load at most length bytes.
9372 load_image $fname [expr @{$address - $foffset@}] bin \
9378 @deffn {Command} {test_image} filename [address [@option{bin}|@option{ihex}|@option{elf}]]
9379 Displays image section sizes and addresses
9380 as if @var{filename} were loaded into target memory
9381 starting at @var{address} (defaults to zero).
9382 The file format may optionally be specified
9383 (@option{bin}, @option{ihex}, or @option{elf})
9386 @deffn {Command} {verify_image} filename [address [@option{bin}|@option{ihex}|@option{elf}]]
9387 Verify @var{filename} against target memory.
9388 If an @var{address} is specified, it is used as an offset to the file format
9389 defined addressing (e.g. @option{bin} file is compared against memory starting
9391 The file format may optionally be specified
9392 (@option{bin}, @option{ihex}, or @option{elf})
9393 This will first attempt a comparison using a CRC checksum, if this fails it will try a binary compare.
9396 @deffn {Command} {verify_image_checksum} filename [address [@option{bin}|@option{ihex}|@option{elf}]]
9397 Verify @var{filename} against target memory.
9398 If an @var{address} is specified, it is used as an offset to the file format
9399 defined addressing (e.g. @option{bin} file is compared against memory starting
9401 The file format may optionally be specified
9402 (@option{bin}, @option{ihex}, or @option{elf})
9403 This perform a comparison using a CRC checksum only
9407 @section Breakpoint and Watchpoint commands
9411 CPUs often make debug modules accessible through JTAG, with
9412 hardware support for a handful of code breakpoints and data
9414 In addition, CPUs almost always support software breakpoints.
9416 @deffn {Command} {bp} [address len [@option{hw}]]
9417 With no parameters, lists all active breakpoints.
9418 Else sets a breakpoint on code execution starting
9419 at @var{address} for @var{length} bytes.
9420 This is a software breakpoint, unless @option{hw} is specified
9421 in which case it will be a hardware breakpoint.
9423 (@xref{arm9vectorcatch,,arm9 vector_catch}, or @pxref{xscalevectorcatch,,xscale vector_catch},
9424 for similar mechanisms that do not consume hardware breakpoints.)
9427 @deffn {Command} {rbp} @option{all} | address
9428 Remove the breakpoint at @var{address} or all breakpoints.
9431 @deffn {Command} {rwp} @option{all} | address
9432 Remove data watchpoint on @var{address} or all watchpoints.
9435 @deffn {Command} {wp} [address length [(@option{r}|@option{w}|@option{a}) [value [mask]]]]
9436 With no parameters, lists all active watchpoints.
9437 Else sets a data watchpoint on data from @var{address} for @var{length} bytes.
9438 The watch point is an "access" watchpoint unless
9439 the @option{r} or @option{w} parameter is provided,
9440 defining it as respectively a read or write watchpoint.
9441 If a @var{value} is provided, that value is used when determining if
9442 the watchpoint should trigger. The value may be first be masked
9443 using @var{mask} to mark ``don't care'' fields.
9447 @section Real Time Transfer (RTT)
9449 Real Time Transfer (RTT) is an interface specified by SEGGER based on basic
9450 memory reads and writes to transfer data bidirectionally between target and host.
9451 The specification is independent of the target architecture.
9452 Every target that supports so called "background memory access", which means
9453 that the target memory can be accessed by the debugger while the target is
9454 running, can be used.
9455 This interface is especially of interest for targets without
9456 Serial Wire Output (SWO), such as ARM Cortex-M0, or where semihosting is not
9457 applicable because of real-time constraints.
9460 The current implementation supports only single target devices.
9463 The data transfer between host and target device is organized through
9464 unidirectional up/down-channels for target-to-host and host-to-target
9465 communication, respectively.
9468 The current implementation does not respect channel buffer flags.
9469 They are used to determine what happens when writing to a full buffer, for
9473 Channels are exposed via raw TCP/IP connections. One or more RTT servers can be
9474 assigned to each channel to make them accessible to an unlimited number
9475 of TCP/IP connections.
9477 @deffn {Command} {rtt setup} address size ID
9478 Configure RTT for the currently selected target.
9479 Once RTT is started, OpenOCD searches for a control block with the
9480 identifier @var{ID} starting at the memory address @var{address} within the next
9484 @deffn {Command} {rtt start}
9486 If the control block location is not known, OpenOCD starts searching for it.
9489 @deffn {Command} {rtt stop}
9493 @deffn {Command} {rtt polling_interval} [interval]
9494 Display the polling interval.
9495 If @var{interval} is provided, set the polling interval.
9496 The polling interval determines (in milliseconds) how often the up-channels are
9497 checked for new data.
9500 @deffn {Command} {rtt channels}
9501 Display a list of all channels and their properties.
9504 @deffn {Command} {rtt channellist}
9505 Return a list of all channels and their properties as Tcl list.
9506 The list can be manipulated easily from within scripts.
9509 @deffn {Command} {rtt server start} port channel [message]
9510 Start a TCP server on @var{port} for the channel @var{channel}. When
9511 @var{message} is not empty, it will be sent to a client when it connects.
9514 @deffn {Command} {rtt server stop} port
9515 Stop the TCP sever with port @var{port}.
9518 The following example shows how to setup RTT using the SEGGER RTT implementation
9519 on the target device.
9524 rtt setup 0x20000000 2048 "SEGGER RTT"
9527 rtt server start 9090 0
9530 In this example, OpenOCD searches the control block with the ID "SEGGER RTT"
9531 starting at 0x20000000 for 2048 bytes. The RTT channel 0 is exposed through the
9535 @section Misc Commands
9538 @deffn {Command} {profile} seconds filename [start end]
9539 Profiling samples the CPU's program counter as quickly as possible,
9540 which is useful for non-intrusive stochastic profiling.
9541 Saves up to 1000000 samples in @file{filename} using ``gmon.out''
9542 format. Optional @option{start} and @option{end} parameters allow to
9543 limit the address range.
9546 @deffn {Command} {version} [git]
9547 Returns a string identifying the version of this OpenOCD server.
9548 With option @option{git}, it returns the git version obtained at compile time
9549 through ``git describe''.
9552 @deffn {Command} {virt2phys} virtual_address
9553 Requests the current target to map the specified @var{virtual_address}
9554 to its corresponding physical address, and displays the result.
9557 @deffn {Command} {add_help_text} 'command_name' 'help-string'
9558 Add or replace help text on the given @var{command_name}.
9561 @deffn {Command} {add_usage_text} 'command_name' 'help-string'
9562 Add or replace usage text on the given @var{command_name}.
9565 @node Architecture and Core Commands
9566 @chapter Architecture and Core Commands
9567 @cindex Architecture Specific Commands
9568 @cindex Core Specific Commands
9570 Most CPUs have specialized JTAG operations to support debugging.
9571 OpenOCD packages most such operations in its standard command framework.
9572 Some of those operations don't fit well in that framework, so they are
9573 exposed here as architecture or implementation (core) specific commands.
9575 @anchor{armhardwaretracing}
9576 @section ARM Hardware Tracing
9581 CPUs based on ARM cores may include standard tracing interfaces,
9582 based on an ``Embedded Trace Module'' (ETM) which sends voluminous
9583 address and data bus trace records to a ``Trace Port''.
9587 Development-oriented boards will sometimes provide a high speed
9588 trace connector for collecting that data, when the particular CPU
9589 supports such an interface.
9590 (The standard connector is a 38-pin Mictor, with both JTAG
9591 and trace port support.)
9592 Those trace connectors are supported by higher end JTAG adapters
9593 and some logic analyzer modules; frequently those modules can
9594 buffer several megabytes of trace data.
9595 Configuring an ETM coupled to such an external trace port belongs
9596 in the board-specific configuration file.
9598 If the CPU doesn't provide an external interface, it probably
9599 has an ``Embedded Trace Buffer'' (ETB) on the chip, which is a
9600 dedicated SRAM. 4KBytes is one common ETB size.
9601 Configuring an ETM coupled only to an ETB belongs in the CPU-specific
9602 (target) configuration file, since it works the same on all boards.
9605 ETM support in OpenOCD doesn't seem to be widely used yet.
9608 ETM support may be buggy, and at least some @command{etm config}
9609 parameters should be detected by asking the ETM for them.
9611 ETM trigger events could also implement a kind of complex
9612 hardware breakpoint, much more powerful than the simple
9613 watchpoint hardware exported by EmbeddedICE modules.
9614 @emph{Such breakpoints can be triggered even when using the
9615 dummy trace port driver}.
9617 It seems like a GDB hookup should be possible,
9618 as well as tracing only during specific states
9619 (perhaps @emph{handling IRQ 23} or @emph{calls foo()}).
9621 There should be GUI tools to manipulate saved trace data and help
9622 analyse it in conjunction with the source code.
9623 It's unclear how much of a common interface is shared
9624 with the current XScale trace support, or should be
9625 shared with eventual Nexus-style trace module support.
9627 At this writing (November 2009) only ARM7, ARM9, and ARM11 support
9628 for ETM modules is available. The code should be able to
9629 work with some newer cores; but not all of them support
9630 this original style of JTAG access.
9633 @subsection ETM Configuration
9634 ETM setup is coupled with the trace port driver configuration.
9636 @deffn {Config Command} {etm config} target width mode clocking driver
9637 Declares the ETM associated with @var{target}, and associates it
9638 with a given trace port @var{driver}. @xref{traceportdrivers,,Trace Port Drivers}.
9640 Several of the parameters must reflect the trace port capabilities,
9641 which are a function of silicon capabilities (exposed later
9642 using @command{etm info}) and of what hardware is connected to
9643 that port (such as an external pod, or ETB).
9644 The @var{width} must be either 4, 8, or 16,
9645 except with ETMv3.0 and newer modules which may also
9646 support 1, 2, 24, 32, 48, and 64 bit widths.
9647 (With those versions, @command{etm info} also shows whether
9648 the selected port width and mode are supported.)
9650 The @var{mode} must be @option{normal}, @option{multiplexed},
9651 or @option{demultiplexed}.
9652 The @var{clocking} must be @option{half} or @option{full}.
9655 With ETMv3.0 and newer, the bits set with the @var{mode} and
9656 @var{clocking} parameters both control the mode.
9657 This modified mode does not map to the values supported by
9658 previous ETM modules, so this syntax is subject to change.
9662 You can see the ETM registers using the @command{reg} command.
9663 Not all possible registers are present in every ETM.
9664 Most of the registers are write-only, and are used to configure
9665 what CPU activities are traced.
9669 @deffn {Command} {etm info}
9670 Displays information about the current target's ETM.
9671 This includes resource counts from the @code{ETM_CONFIG} register,
9672 as well as silicon capabilities (except on rather old modules).
9673 from the @code{ETM_SYS_CONFIG} register.
9676 @deffn {Command} {etm status}
9677 Displays status of the current target's ETM and trace port driver:
9678 is the ETM idle, or is it collecting data?
9679 Did trace data overflow?
9683 @deffn {Command} {etm tracemode} [type context_id_bits cycle_accurate branch_output]
9684 Displays what data that ETM will collect.
9685 If arguments are provided, first configures that data.
9686 When the configuration changes, tracing is stopped
9687 and any buffered trace data is invalidated.
9690 @item @var{type} ... describing how data accesses are traced,
9691 when they pass any ViewData filtering that was set up.
9693 @option{none} (save nothing),
9694 @option{data} (save data),
9695 @option{address} (save addresses),
9696 @option{all} (save data and addresses)
9697 @item @var{context_id_bits} ... 0, 8, 16, or 32
9698 @item @var{cycle_accurate} ... @option{enable} or @option{disable}
9699 cycle-accurate instruction tracing.
9700 Before ETMv3, enabling this causes much extra data to be recorded.
9701 @item @var{branch_output} ... @option{enable} or @option{disable}.
9702 Disable this unless you need to try reconstructing the instruction
9703 trace stream without an image of the code.
9707 @deffn {Command} {etm trigger_debug} (@option{enable}|@option{disable})
9708 Displays whether ETM triggering debug entry (like a breakpoint) is
9709 enabled or disabled, after optionally modifying that configuration.
9710 The default behaviour is @option{disable}.
9711 Any change takes effect after the next @command{etm start}.
9713 By using script commands to configure ETM registers, you can make the
9714 processor enter debug state automatically when certain conditions,
9715 more complex than supported by the breakpoint hardware, happen.
9718 @subsection ETM Trace Operation
9720 After setting up the ETM, you can use it to collect data.
9721 That data can be exported to files for later analysis.
9722 It can also be parsed with OpenOCD, for basic sanity checking.
9724 To configure what is being traced, you will need to write
9725 various trace registers using @command{reg ETM_*} commands.
9726 For the definitions of these registers, read ARM publication
9727 @emph{IHI 0014, ``Embedded Trace Macrocell, Architecture Specification''}.
9728 Be aware that most of the relevant registers are write-only,
9729 and that ETM resources are limited. There are only a handful
9730 of address comparators, data comparators, counters, and so on.
9732 Examples of scenarios you might arrange to trace include:
9735 @item Code flow within a function, @emph{excluding} subroutines
9736 it calls. Use address range comparators to enable tracing
9737 for instruction access within that function's body.
9738 @item Code flow within a function, @emph{including} subroutines
9739 it calls. Use the sequencer and address comparators to activate
9740 tracing on an ``entered function'' state, then deactivate it by
9741 exiting that state when the function's exit code is invoked.
9742 @item Code flow starting at the fifth invocation of a function,
9743 combining one of the above models with a counter.
9744 @item CPU data accesses to the registers for a particular device,
9745 using address range comparators and the ViewData logic.
9746 @item Such data accesses only during IRQ handling, combining the above
9747 model with sequencer triggers which on entry and exit to the IRQ handler.
9748 @item @emph{... more}
9751 At this writing, September 2009, there are no Tcl utility
9752 procedures to help set up any common tracing scenarios.
9754 @deffn {Command} {etm analyze}
9755 Reads trace data into memory, if it wasn't already present.
9756 Decodes and prints the data that was collected.
9759 @deffn {Command} {etm dump} filename
9760 Stores the captured trace data in @file{filename}.
9763 @deffn {Command} {etm image} filename [base_address] [type]
9764 Opens an image file.
9767 @deffn {Command} {etm load} filename
9768 Loads captured trace data from @file{filename}.
9771 @deffn {Command} {etm start}
9772 Starts trace data collection.
9775 @deffn {Command} {etm stop}
9776 Stops trace data collection.
9779 @anchor{traceportdrivers}
9780 @subsection Trace Port Drivers
9782 To use an ETM trace port it must be associated with a driver.
9784 @deffn {Trace Port Driver} {dummy}
9785 Use the @option{dummy} driver if you are configuring an ETM that's
9786 not connected to anything (on-chip ETB or off-chip trace connector).
9787 @emph{This driver lets OpenOCD talk to the ETM, but it does not expose
9788 any trace data collection.}
9789 @deffn {Config Command} {etm_dummy config} target
9790 Associates the ETM for @var{target} with a dummy driver.
9794 @deffn {Trace Port Driver} {etb}
9795 Use the @option{etb} driver if you are configuring an ETM
9796 to use on-chip ETB memory.
9797 @deffn {Config Command} {etb config} target etb_tap
9798 Associates the ETM for @var{target} with the ETB at @var{etb_tap}.
9799 You can see the ETB registers using the @command{reg} command.
9801 @deffn {Command} {etb trigger_percent} [percent]
9802 This displays, or optionally changes, ETB behavior after the
9803 ETM's configured @emph{trigger} event fires.
9804 It controls how much more trace data is saved after the (single)
9805 trace trigger becomes active.
9808 @item The default corresponds to @emph{trace around} usage,
9809 recording 50 percent data before the event and the rest
9811 @item The minimum value of @var{percent} is 2 percent,
9812 recording almost exclusively data before the trigger.
9813 Such extreme @emph{trace before} usage can help figure out
9814 what caused that event to happen.
9815 @item The maximum value of @var{percent} is 100 percent,
9816 recording data almost exclusively after the event.
9817 This extreme @emph{trace after} usage might help sort out
9818 how the event caused trouble.
9820 @c REVISIT allow "break" too -- enter debug mode.
9825 @anchor{armcrosstrigger}
9826 @section ARM Cross-Trigger Interface
9829 The ARM Cross-Trigger Interface (CTI) is a generic CoreSight component
9830 that connects event sources like tracing components or CPU cores with each
9831 other through a common trigger matrix (CTM). For ARMv8 architecture, a
9832 CTI is mandatory for core run control and each core has an individual
9833 CTI instance attached to it. OpenOCD has limited support for CTI using
9834 the @emph{cti} group of commands.
9836 @deffn {Command} {cti create} cti_name @option{-dap} dap_name @option{-ap-num} apn @option{-baseaddr} base_address
9837 Creates a CTI instance @var{cti_name} on the DAP instance @var{dap_name} on MEM-AP
9839 On ADIv5 DAP @var{apn} is the numeric index of the DAP AP the CTI is connected to.
9840 On ADIv6 DAP @var{apn} is the base address of the DAP AP the CTI is connected to.
9841 The @var{base_address} must match the base address of the CTI
9842 on the respective MEM-AP. All arguments are mandatory. This creates a
9843 new command @command{$cti_name} which is used for various purposes
9844 including additional configuration.
9847 @deffn {Command} {$cti_name enable} @option{on|off}
9848 Enable (@option{on}) or disable (@option{off}) the CTI.
9851 @deffn {Command} {$cti_name dump}
9852 Displays a register dump of the CTI.
9855 @deffn {Command} {$cti_name write} @var{reg_name} @var{value}
9856 Write @var{value} to the CTI register with the symbolic name @var{reg_name}.
9859 @deffn {Command} {$cti_name read} @var{reg_name}
9860 Print the value read from the CTI register with the symbolic name @var{reg_name}.
9863 @deffn {Command} {$cti_name ack} @var{event}
9864 Acknowledge a CTI @var{event}.
9867 @deffn {Command} {$cti_name channel} @var{channel_number} @var{operation}
9868 Perform a specific channel operation, the possible operations are:
9869 gate, ungate, set, clear and pulse
9872 @deffn {Command} {$cti_name testmode} @option{on|off}
9873 Enable (@option{on}) or disable (@option{off}) the integration test mode
9877 @deffn {Command} {cti names}
9878 Prints a list of names of all CTI objects created. This command is mainly
9879 useful in TCL scripting.
9882 @section Generic ARM
9885 These commands should be available on all ARM processors.
9886 They are available in addition to other core-specific
9887 commands that may be available.
9889 @deffn {Command} {arm core_state} [@option{arm}|@option{thumb}]
9890 Displays the core_state, optionally changing it to process
9891 either @option{arm} or @option{thumb} instructions.
9892 The target may later be resumed in the currently set core_state.
9893 (Processors may also support the Jazelle state, but
9894 that is not currently supported in OpenOCD.)
9897 @deffn {Command} {arm disassemble} address [count [@option{thumb}]]
9899 Disassembles @var{count} instructions starting at @var{address}.
9900 If @var{count} is not specified, a single instruction is disassembled.
9901 If @option{thumb} is specified, or the low bit of the address is set,
9902 Thumb2 (mixed 16/32-bit) instructions are used;
9903 else ARM (32-bit) instructions are used.
9904 (Processors may also support the Jazelle state, but
9905 those instructions are not currently understood by OpenOCD.)
9907 Note that all Thumb instructions are Thumb2 instructions,
9908 so older processors (without Thumb2 support) will still
9909 see correct disassembly of Thumb code.
9910 Also, ThumbEE opcodes are the same as Thumb2,
9911 with a handful of exceptions.
9912 ThumbEE disassembly currently has no explicit support.
9915 @deffn {Command} {arm mcr} pX op1 CRn CRm op2 value
9916 Write @var{value} to a coprocessor @var{pX} register
9917 passing parameters @var{CRn},
9918 @var{CRm}, opcodes @var{opc1} and @var{opc2},
9919 and using the MCR instruction.
9920 (Parameter sequence matches the ARM instruction, but omits
9924 @deffn {Command} {arm mrc} pX coproc op1 CRn CRm op2
9925 Read a coprocessor @var{pX} register passing parameters @var{CRn},
9926 @var{CRm}, opcodes @var{opc1} and @var{opc2},
9927 and the MRC instruction.
9928 Returns the result so it can be manipulated by Jim scripts.
9929 (Parameter sequence matches the ARM instruction, but omits
9933 @deffn {Command} {arm reg}
9934 Display a table of all banked core registers, fetching the current value from every
9935 core mode if necessary.
9938 @deffn {Command} {arm semihosting} [@option{enable}|@option{disable}]
9939 @cindex ARM semihosting
9940 Display status of semihosting, after optionally changing that status.
9942 Semihosting allows for code executing on an ARM target to use the
9943 I/O facilities on the host computer i.e. the system where OpenOCD
9944 is running. The target application must be linked against a library
9945 implementing the ARM semihosting convention that forwards operation
9946 requests by using a special SVC instruction that is trapped at the
9947 Supervisor Call vector by OpenOCD.
9950 @deffn {Command} {arm semihosting_redirect} (@option{disable} | @option{tcp} <port> [@option{debug}|@option{stdio}|@option{all}])
9951 @cindex ARM semihosting
9952 Redirect semihosting messages to a specified TCP port.
9954 This command redirects debug (READC, WRITEC and WRITE0) and stdio (READ, WRITE)
9955 semihosting operations to the specified TCP port.
9956 The command allows to select which type of operations to redirect (debug, stdio, all (default)).
9958 Note: for stdio operations, only I/O from/to ':tt' file descriptors are redirected.
9961 @deffn {Command} {arm semihosting_cmdline} [@option{enable}|@option{disable}]
9962 @cindex ARM semihosting
9963 Set the command line to be passed to the debugger.
9966 arm semihosting_cmdline argv0 argv1 argv2 ...
9969 This option lets one set the command line arguments to be passed to
9970 the program. The first argument (argv0) is the program name in a
9971 standard C environment (argv[0]). Depending on the program (not much
9972 programs look at argv[0]), argv0 is ignored and can be any string.
9975 @deffn {Command} {arm semihosting_fileio} [@option{enable}|@option{disable}]
9976 @cindex ARM semihosting
9977 Display status of semihosting fileio, after optionally changing that
9980 Enabling this option forwards semihosting I/O to GDB process using the
9981 File-I/O remote protocol extension. This is especially useful for
9982 interacting with remote files or displaying console messages in the
9986 @deffn {Command} {arm semihosting_resexit} [@option{enable}|@option{disable}]
9987 @cindex ARM semihosting
9988 Enable resumable SEMIHOSTING_SYS_EXIT.
9990 When SEMIHOSTING_SYS_EXIT is called outside a debug session,
9991 things are simple, the openocd process calls exit() and passes
9992 the value returned by the target.
9994 When SEMIHOSTING_SYS_EXIT is called during a debug session,
9995 by default execution returns to the debugger, leaving the
9996 debugger in a HALT state, similar to the state entered when
9997 encountering a break.
9999 In some use cases, it is useful to have SEMIHOSTING_SYS_EXIT
10000 return normally, as any semihosting call, and do not break
10002 The standard allows this to happen, but the condition
10003 to trigger it is a bit obscure ("by performing an RDI_Execute
10004 request or equivalent").
10006 To make the SEMIHOSTING_SYS_EXIT call return normally, enable
10007 this option (default: disabled).
10010 @deffn {Command} {arm semihosting_read_user_param}
10011 @cindex ARM semihosting
10012 Read parameter of the semihosting call from the target. Usable in
10013 semihosting-user-cmd-0x10* event handlers, returning a string.
10015 When the target makes semihosting call with operation number from range 0x100-
10016 0x107, an optional string parameter can be passed to the server. This parameter
10017 is valid during the run of the event handlers and is accessible with this
10021 @deffn {Command} {arm semihosting_basedir} [dir]
10022 @cindex ARM semihosting
10023 Set the base directory for semihosting I/O, either an absolute path or a path relative to OpenOCD working directory.
10024 Use "." for the current directory.
10027 @section ARMv4 and ARMv5 Architecture
10031 The ARMv4 and ARMv5 architectures are widely used in embedded systems,
10032 and introduced core parts of the instruction set in use today.
10033 That includes the Thumb instruction set, introduced in the ARMv4T
10036 @subsection ARM7 and ARM9 specific commands
10040 These commands are specific to ARM7 and ARM9 cores, like ARM7TDMI, ARM720T,
10041 ARM9TDMI, ARM920T or ARM926EJ-S.
10042 They are available in addition to the ARM commands,
10043 and any other core-specific commands that may be available.
10045 @deffn {Command} {arm7_9 dbgrq} [@option{enable}|@option{disable}]
10046 Displays the value of the flag controlling use of the
10047 EmbeddedIce DBGRQ signal to force entry into debug mode,
10048 instead of breakpoints.
10049 If a boolean parameter is provided, first assigns that flag.
10052 safe for all but ARM7TDMI-S cores (like NXP LPC).
10053 This feature is enabled by default on most ARM9 cores,
10054 including ARM9TDMI, ARM920T, and ARM926EJ-S.
10057 @deffn {Command} {arm7_9 dcc_downloads} [@option{enable}|@option{disable}]
10059 Displays the value of the flag controlling use of the debug communications
10060 channel (DCC) to write larger (>128 byte) amounts of memory.
10061 If a boolean parameter is provided, first assigns that flag.
10063 DCC downloads offer a huge speed increase, but might be
10064 unsafe, especially with targets running at very low speeds. This command was introduced
10065 with OpenOCD rev. 60, and requires a few bytes of working area.
10068 @deffn {Command} {arm7_9 fast_memory_access} [@option{enable}|@option{disable}]
10069 Displays the value of the flag controlling use of memory writes and reads
10070 that don't check completion of the operation.
10071 If a boolean parameter is provided, first assigns that flag.
10073 This provides a huge speed increase, especially with USB JTAG
10074 cables (FT2232), but might be unsafe if used with targets running at very low
10075 speeds, like the 32kHz startup clock of an AT91RM9200.
10078 @subsection ARM9 specific commands
10081 ARM9-family cores are built around ARM9TDMI or ARM9E (including ARM9EJS)
10082 integer processors.
10083 Such cores include the ARM920T, ARM926EJ-S, and ARM966.
10085 @c 9-june-2009: tried this on arm920t, it didn't work.
10086 @c no-params always lists nothing caught, and that's how it acts.
10087 @c 23-oct-2009: doesn't work _consistently_ ... as if the ICE
10088 @c versions have different rules about when they commit writes.
10090 @anchor{arm9vectorcatch}
10091 @deffn {Command} {arm9 vector_catch} [@option{all}|@option{none}|list]
10092 @cindex vector_catch
10093 Vector Catch hardware provides a sort of dedicated breakpoint
10094 for hardware events such as reset, interrupt, and abort.
10095 You can use this to conserve normal breakpoint resources,
10096 so long as you're not concerned with code that branches directly
10097 to those hardware vectors.
10099 This always finishes by listing the current configuration.
10100 If parameters are provided, it first reconfigures the
10101 vector catch hardware to intercept
10102 @option{all} of the hardware vectors,
10103 @option{none} of them,
10104 or a list with one or more of the following:
10105 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt}
10106 @option{irq} @option{fiq}.
10109 @subsection ARM920T specific commands
10112 These commands are available to ARM920T based CPUs,
10113 which are implementations of the ARMv4T architecture
10114 built using the ARM9TDMI integer core.
10115 They are available in addition to the ARM, ARM7/ARM9,
10118 @deffn {Command} {arm920t cache_info}
10119 Print information about the caches found. This allows to see whether your target
10120 is an ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
10123 @deffn {Command} {arm920t cp15} regnum [value]
10124 Display cp15 register @var{regnum};
10125 else if a @var{value} is provided, that value is written to that register.
10126 This uses "physical access" and the register number is as
10127 shown in bits 38..33 of table 9-9 in the ARM920T TRM.
10128 (Not all registers can be written.)
10131 @deffn {Command} {arm920t read_cache} filename
10132 Dump the content of ICache and DCache to a file named @file{filename}.
10135 @deffn {Command} {arm920t read_mmu} filename
10136 Dump the content of the ITLB and DTLB to a file named @file{filename}.
10139 @subsection ARM926ej-s specific commands
10142 These commands are available to ARM926ej-s based CPUs,
10143 which are implementations of the ARMv5TEJ architecture
10144 based on the ARM9EJ-S integer core.
10145 They are available in addition to the ARM, ARM7/ARM9,
10148 The Feroceon cores also support these commands, although
10149 they are not built from ARM926ej-s designs.
10151 @deffn {Command} {arm926ejs cache_info}
10152 Print information about the caches found.
10155 @subsection ARM966E specific commands
10158 These commands are available to ARM966 based CPUs,
10159 which are implementations of the ARMv5TE architecture.
10160 They are available in addition to the ARM, ARM7/ARM9,
10163 @deffn {Command} {arm966e cp15} regnum [value]
10164 Display cp15 register @var{regnum};
10165 else if a @var{value} is provided, that value is written to that register.
10166 The six bit @var{regnum} values are bits 37..32 from table 7-2 of the
10168 There is no current control over bits 31..30 from that table,
10169 as required for BIST support.
10172 @subsection XScale specific commands
10175 Some notes about the debug implementation on the XScale CPUs:
10177 The XScale CPU provides a special debug-only mini-instruction cache
10178 (mini-IC) in which exception vectors and target-resident debug handler
10179 code are placed by OpenOCD. In order to get access to the CPU, OpenOCD
10180 must point vector 0 (the reset vector) to the entry of the debug
10181 handler. However, this means that the complete first cacheline in the
10182 mini-IC is marked valid, which makes the CPU fetch all exception
10183 handlers from the mini-IC, ignoring the code in RAM.
10185 To address this situation, OpenOCD provides the @code{xscale
10186 vector_table} command, which allows the user to explicitly write
10187 individual entries to either the high or low vector table stored in
10190 It is recommended to place a pc-relative indirect branch in the vector
10191 table, and put the branch destination somewhere in memory. Doing so
10192 makes sure the code in the vector table stays constant regardless of
10193 code layout in memory:
10196 ldr pc,[pc,#0x100-8]
10197 ldr pc,[pc,#0x100-8]
10198 ldr pc,[pc,#0x100-8]
10199 ldr pc,[pc,#0x100-8]
10200 ldr pc,[pc,#0x100-8]
10201 ldr pc,[pc,#0x100-8]
10202 ldr pc,[pc,#0x100-8]
10203 ldr pc,[pc,#0x100-8]
10205 .long real_reset_vector
10206 .long real_ui_handler
10207 .long real_swi_handler
10208 .long real_pf_abort
10209 .long real_data_abort
10210 .long 0 /* unused */
10211 .long real_irq_handler
10212 .long real_fiq_handler
10215 Alternatively, you may choose to keep some or all of the mini-IC
10216 vector table entries synced with those written to memory by your
10217 system software. The mini-IC can not be modified while the processor
10218 is executing, but for each vector table entry not previously defined
10219 using the @code{xscale vector_table} command, OpenOCD will copy the
10220 value from memory to the mini-IC every time execution resumes from a
10221 halt. This is done for both high and low vector tables (although the
10222 table not in use may not be mapped to valid memory, and in this case
10223 that copy operation will silently fail). This means that you will
10224 need to briefly halt execution at some strategic point during system
10225 start-up; e.g., after the software has initialized the vector table,
10226 but before exceptions are enabled. A breakpoint can be used to
10227 accomplish this once the appropriate location in the start-up code has
10228 been identified. A watchpoint over the vector table region is helpful
10229 in finding the location if you're not sure. Note that the same
10230 situation exists any time the vector table is modified by the system
10233 The debug handler must be placed somewhere in the address space using
10234 the @code{xscale debug_handler} command. The allowed locations for the
10235 debug handler are either (0x800 - 0x1fef800) or (0xfe000800 -
10236 0xfffff800). The default value is 0xfe000800.
10238 XScale has resources to support two hardware breakpoints and two
10239 watchpoints. However, the following restrictions on watchpoint
10240 functionality apply: (1) the value and mask arguments to the @code{wp}
10241 command are not supported, (2) the watchpoint length must be a
10242 power of two and not less than four, and can not be greater than the
10243 watchpoint address, and (3) a watchpoint with a length greater than
10244 four consumes all the watchpoint hardware resources. This means that
10245 at any one time, you can have enabled either two watchpoints with a
10246 length of four, or one watchpoint with a length greater than four.
10248 These commands are available to XScale based CPUs,
10249 which are implementations of the ARMv5TE architecture.
10251 @deffn {Command} {xscale analyze_trace}
10252 Displays the contents of the trace buffer.
10255 @deffn {Command} {xscale cache_clean_address} address
10256 Changes the address used when cleaning the data cache.
10259 @deffn {Command} {xscale cache_info}
10260 Displays information about the CPU caches.
10263 @deffn {Command} {xscale cp15} regnum [value]
10264 Display cp15 register @var{regnum};
10265 else if a @var{value} is provided, that value is written to that register.
10268 @deffn {Command} {xscale debug_handler} target address
10269 Changes the address used for the specified target's debug handler.
10272 @deffn {Command} {xscale dcache} [@option{enable}|@option{disable}]
10273 Enables or disable the CPU's data cache.
10276 @deffn {Command} {xscale dump_trace} filename
10277 Dumps the raw contents of the trace buffer to @file{filename}.
10280 @deffn {Command} {xscale icache} [@option{enable}|@option{disable}]
10281 Enables or disable the CPU's instruction cache.
10284 @deffn {Command} {xscale mmu} [@option{enable}|@option{disable}]
10285 Enables or disable the CPU's memory management unit.
10288 @deffn {Command} {xscale trace_buffer} [@option{enable}|@option{disable} [@option{fill} [n] | @option{wrap}]]
10289 Displays the trace buffer status, after optionally
10290 enabling or disabling the trace buffer
10291 and modifying how it is emptied.
10294 @deffn {Command} {xscale trace_image} filename [offset [type]]
10295 Opens a trace image from @file{filename}, optionally rebasing
10296 its segment addresses by @var{offset}.
10297 The image @var{type} may be one of
10298 @option{bin} (binary), @option{ihex} (Intel hex),
10299 @option{elf} (ELF file), @option{s19} (Motorola s19),
10300 @option{mem}, or @option{builder}.
10303 @anchor{xscalevectorcatch}
10304 @deffn {Command} {xscale vector_catch} [mask]
10305 @cindex vector_catch
10306 Display a bitmask showing the hardware vectors to catch.
10307 If the optional parameter is provided, first set the bitmask to that value.
10309 The mask bits correspond with bit 16..23 in the DCSR:
10312 0x02 Trap Undefined Instructions
10313 0x04 Trap Software Interrupt
10314 0x08 Trap Prefetch Abort
10315 0x10 Trap Data Abort
10322 @deffn {Command} {xscale vector_table} [(@option{low}|@option{high}) index value]
10323 @cindex vector_table
10325 Set an entry in the mini-IC vector table. There are two tables: one for
10326 low vectors (at 0x00000000), and one for high vectors (0xFFFF0000), each
10327 holding the 8 exception vectors. @var{index} can be 1-7, because vector 0
10328 points to the debug handler entry and can not be overwritten.
10329 @var{value} holds the 32-bit opcode that is placed in the mini-IC.
10331 Without arguments, the current settings are displayed.
10335 @section ARMv6 Architecture
10338 @subsection ARM11 specific commands
10341 @deffn {Command} {arm11 memwrite burst} [@option{enable}|@option{disable}]
10342 Displays the value of the memwrite burst-enable flag,
10343 which is enabled by default.
10344 If a boolean parameter is provided, first assigns that flag.
10345 Burst writes are only used for memory writes larger than 1 word.
10346 They improve performance by assuming that the CPU has read each data
10347 word over JTAG and completed its write before the next word arrives,
10348 instead of polling for a status flag to verify that completion.
10349 This is usually safe, because JTAG runs much slower than the CPU.
10352 @deffn {Command} {arm11 memwrite error_fatal} [@option{enable}|@option{disable}]
10353 Displays the value of the memwrite error_fatal flag,
10354 which is enabled by default.
10355 If a boolean parameter is provided, first assigns that flag.
10356 When set, certain memory write errors cause earlier transfer termination.
10359 @deffn {Command} {arm11 step_irq_enable} [@option{enable}|@option{disable}]
10360 Displays the value of the flag controlling whether
10361 IRQs are enabled during single stepping;
10362 they are disabled by default.
10363 If a boolean parameter is provided, first assigns that.
10366 @deffn {Command} {arm11 vcr} [value]
10367 @cindex vector_catch
10368 Displays the value of the @emph{Vector Catch Register (VCR)},
10369 coprocessor 14 register 7.
10370 If @var{value} is defined, first assigns that.
10372 Vector Catch hardware provides dedicated breakpoints
10373 for certain hardware events.
10374 The specific bit values are core-specific (as in fact is using
10375 coprocessor 14 register 7 itself) but all current ARM11
10376 cores @emph{except the ARM1176} use the same six bits.
10379 @section ARMv7 and ARMv8 Architecture
10383 @subsection ARMv7-A specific commands
10386 @deffn {Command} {cortex_a cache_info}
10387 display information about target caches
10390 @deffn {Command} {cortex_a dacrfixup} [@option{on}|@option{off}]
10391 Work around issues with software breakpoints when the program text is
10392 mapped read-only by the operating system. This option sets the CP15 DACR
10393 to "all-manager" to bypass MMU permission checks on memory access.
10397 @deffn {Command} {cortex_a dbginit}
10398 Initialize core debug
10399 Enables debug by unlocking the Software Lock and clearing sticky powerdown indications
10402 @deffn {Command} {cortex_a smp} [on|off]
10403 Display/set the current SMP mode
10406 @deffn {Command} {cortex_a smp_gdb} [core_id]
10407 Display/set the current core displayed in GDB
10410 @deffn {Command} {cortex_a maskisr} [@option{on}|@option{off}]
10411 Selects whether interrupts will be processed when single stepping
10414 @deffn {Command} {cache_config l2x} [base way]
10415 configure l2x cache
10418 @deffn {Command} {cortex_a mmu dump} [@option{0}|@option{1}|@option{addr} address [@option{num_entries}]]
10419 Dump the MMU translation table from TTB0 or TTB1 register, or from physical
10420 memory location @var{address}. When dumping the table from @var{address}, print at most
10421 @var{num_entries} page table entries. @var{num_entries} is optional, if omitted, the maximum
10422 possible (4096) entries are printed.
10425 @subsection ARMv7-R specific commands
10428 @deffn {Command} {cortex_r4 dbginit}
10429 Initialize core debug
10430 Enables debug by unlocking the Software Lock and clearing sticky powerdown indications
10433 @deffn {Command} {cortex_r4 maskisr} [@option{on}|@option{off}]
10434 Selects whether interrupts will be processed when single stepping
10438 @subsection ARM CoreSight TPIU and SWO specific commands
10444 ARM CoreSight provides several modules to generate debugging
10445 information internally (ITM, DWT and ETM). Their output is directed
10446 through TPIU or SWO modules to be captured externally either on an SWO pin (this
10447 configuration is called SWV) or on a synchronous parallel trace port.
10449 ARM CoreSight provides independent HW blocks named TPIU and SWO each with its
10450 own functionality. Embedded in Cortex-M3 and M4, ARM provides an optional HW
10451 block that includes both TPIU and SWO functionalities and is again named TPIU,
10452 which causes quite some confusion.
10453 The registers map of all the TPIU and SWO implementations allows using a single
10454 driver that detects at runtime the features available.
10456 The @command{tpiu} is used for either TPIU or SWO.
10457 A convenient alias @command{swo} is available to help distinguish, in scripts,
10458 the commands for SWO from the commands for TPIU.
10460 @deffn {Command} {swo} ...
10461 Alias of @command{tpiu ...}. Can be used in scripts to distinguish the commands
10462 for SWO from the commands for TPIU.
10465 @deffn {Command} {tpiu create} tpiu_name configparams...
10466 Creates a TPIU or a SWO object. The two commands are equivalent.
10467 Add the object in a list and add new commands (@command{@var{tpiu_name}})
10468 which are used for various purposes including additional configuration.
10471 @item @var{tpiu_name} -- the name of the TPIU or SWO object.
10472 This name is also used to create the object's command, referred to here
10473 as @command{$tpiu_name}, and in other places where the TPIU or SWO needs to be identified.
10474 @item @var{configparams} -- all parameters accepted by @command{$tpiu_name configure} are permitted.
10476 You @emph{must} set here the AP and MEM_AP base_address through @code{-dap @var{dap_name}},
10477 @code{-ap-num @var{ap_number}} and @code{-baseaddr @var{base_address}}.
10481 @deffn {Command} {tpiu names}
10482 Lists all the TPIU or SWO objects created so far. The two commands are equivalent.
10485 @deffn {Command} {tpiu init}
10486 Initialize all registered TPIU and SWO. The two commands are equivalent.
10487 These commands are used internally during initialization. They can be issued
10488 at any time after the initialization, too.
10491 @deffn {Command} {$tpiu_name cget} queryparm
10492 Each configuration parameter accepted by @command{$tpiu_name configure} can be
10493 individually queried, to return its current value.
10494 The @var{queryparm} is a parameter name accepted by that command, such as @code{-dap}.
10497 @deffn {Command} {$tpiu_name configure} configparams...
10498 The options accepted by this command may also be specified as parameters
10499 to @command{tpiu create}. Their values can later be queried one at a time by
10500 using the @command{$tpiu_name cget} command.
10503 @item @code{-dap} @var{dap_name} -- names the DAP used to access this
10504 TPIU. @xref{dapdeclaration,,DAP declaration}, on how to create and manage DAP instances.
10506 @item @code{-ap-num} @var{ap_number} -- sets DAP access port for TPIU.
10507 On ADIv5 DAP @var{ap_number} is the numeric index of the DAP AP the TPIU is connected to.
10508 On ADIv6 DAP @var{ap_number} is the base address of the DAP AP the TPIU is connected to.
10510 @item @code{-baseaddr} @var{base_address} -- sets the TPIU @var{base_address} where
10511 to access the TPIU in the DAP AP memory space.
10513 @item @code{-protocol} (@option{sync}|@option{uart}|@option{manchester}) -- sets the
10514 protocol used for trace data:
10516 @item @option{sync} -- synchronous parallel trace output mode, using @var{port_width}
10517 data bits (default);
10518 @item @option{uart} -- use asynchronous SWO mode with NRZ (same as regular UART 8N1) coding;
10519 @item @option{manchester} -- use asynchronous SWO mode with Manchester coding.
10522 @item @code{-event} @var{event_name} @var{event_body} -- assigns an event handler,
10523 a TCL string which is evaluated when the event is triggered. The events
10524 @code{pre-enable}, @code{post-enable}, @code{pre-disable} and @code{post-disable}
10525 are defined for TPIU/SWO.
10526 A typical use case for the event @code{pre-enable} is to enable the trace clock
10529 @item @code{-output} (@option{external}|@option{:}@var{port}|@var{filename}|@option{-}) -- specifies
10530 the destination of the trace data:
10532 @item @option{external} -- configure TPIU/SWO to let user capture trace
10533 output externally, either with an additional UART or with a logic analyzer (default);
10534 @item @option{-} -- configure TPIU/SWO and debug adapter to gather trace data
10535 and forward it to @command{tcl_trace} command;
10536 @item @option{:}@var{port} -- configure TPIU/SWO and debug adapter to gather
10537 trace data, open a TCP server at port @var{port} and send the trace data to
10538 each connected client;
10539 @item @var{filename} -- configure TPIU/SWO and debug adapter to
10540 gather trace data and append it to @var{filename}, which can be
10541 either a regular file or a named pipe.
10544 @item @code{-traceclk} @var{TRACECLKIN_freq} -- mandatory parameter.
10545 Specifies the frequency in Hz of the trace clock. For the TPIU embedded in
10546 Cortex-M3 or M4, this is usually the same frequency as HCLK. For protocol
10547 @option{sync} this is twice the frequency of the pin data rate.
10549 @item @code{-pin-freq} @var{trace_freq} -- specifies the expected data rate
10550 in Hz of the SWO pin. Parameter used only on protocols @option{uart} and
10551 @option{manchester}. Can be omitted to let the adapter driver select the
10552 maximum supported rate automatically.
10554 @item @code{-port-width} @var{port_width} -- sets to @var{port_width} the width
10555 of the synchronous parallel port used for trace output. Parameter used only on
10556 protocol @option{sync}. If not specified, default value is @var{1}.
10558 @item @code{-formatter} (@option{0}|@option{1}) -- specifies if the formatter
10559 should be enabled. Parameter used only on protocol @option{sync}. If not specified,
10560 default value is @var{0}.
10564 @deffn {Command} {$tpiu_name enable}
10565 Uses the parameters specified by the previous @command{$tpiu_name configure}
10566 to configure and enable the TPIU or the SWO.
10567 If required, the adapter is also configured and enabled to receive the trace
10569 This command can be used before @command{init}, but it will take effect only
10570 after the @command{init}.
10573 @deffn {Command} {$tpiu_name disable}
10574 Disable the TPIU or the SWO, terminating the receiving of the trace data.
10581 @item STM32L152 board is programmed with an application that configures
10582 PLL to provide core clock with 24MHz frequency; to use ITM output it's
10585 #include <libopencm3/cm3/itm.h>
10590 (the most obvious way is to use the first stimulus port for printf,
10591 for that this ITM_STIM8 assignment can be used inside _write(); to make it
10592 blocking to avoid data loss, add @code{while (!(ITM_STIM8(0) &
10593 ITM_STIM_FIFOREADY));});
10594 @item An FT2232H UART is connected to the SWO pin of the board;
10595 @item Commands to configure UART for 12MHz baud rate:
10597 $ setserial /dev/ttyUSB1 spd_cust divisor 5
10598 $ stty -F /dev/ttyUSB1 38400
10600 (FT2232H's base frequency is 60MHz, spd_cust allows to alias 38400
10601 baud with our custom divisor to get 12MHz)
10602 @item @code{itmdump -f /dev/ttyUSB1 -d1}
10603 @item OpenOCD invocation line:
10605 openocd -f interface/stlink.cfg \
10606 -c "transport select hla_swd" \
10607 -f target/stm32l1.cfg \
10608 -c "stm32l1.tpiu configure -protocol uart" \
10609 -c "stm32l1.tpiu configure -traceclk 24000000 -pin-freq 12000000" \
10610 -c "stm32l1.tpiu enable"
10614 @subsection ARMv7-M specific commands
10621 @deffn {Command} {itm port} @var{port} (@option{0}|@option{1}|@option{on}|@option{off})
10622 Enable or disable trace output for ITM stimulus @var{port} (counting
10623 from 0). Port 0 is enabled on target creation automatically.
10626 @deffn {Command} {itm ports} (@option{0}|@option{1}|@option{on}|@option{off})
10627 Enable or disable trace output for all ITM stimulus ports.
10630 @subsection Cortex-M specific commands
10633 @deffn {Command} {cortex_m maskisr} (@option{auto}|@option{on}|@option{off}|@option{steponly})
10634 Control masking (disabling) interrupts during target step/resume.
10636 The @option{auto} option handles interrupts during stepping in a way that they
10637 get served but don't disturb the program flow. The step command first allows
10638 pending interrupt handlers to execute, then disables interrupts and steps over
10639 the next instruction where the core was halted. After the step interrupts
10640 are enabled again. If the interrupt handlers don't complete within 500ms,
10641 the step command leaves with the core running.
10643 The @option{steponly} option disables interrupts during single-stepping but
10644 enables them during normal execution. This can be used as a partial workaround
10645 for 702596 erratum in Cortex-M7 r0p1. See "Cortex-M7 (AT610) and Cortex-M7 with
10646 FPU (AT611) Software Developer Errata Notice" from ARM for further details.
10648 Note that a free hardware (FPB) breakpoint is required for the @option{auto}
10649 option. If no breakpoint is available at the time of the step, then the step
10650 is taken with interrupts enabled, i.e. the same way the @option{off} option
10653 Default is @option{auto}.
10656 @deffn {Command} {cortex_m vector_catch} [@option{all}|@option{none}|list]
10657 @cindex vector_catch
10658 Vector Catch hardware provides dedicated breakpoints
10659 for certain hardware events.
10661 Parameters request interception of
10662 @option{all} of these hardware event vectors,
10663 @option{none} of them,
10664 or one or more of the following:
10665 @option{hard_err} for a HardFault exception;
10666 @option{mm_err} for a MemManage exception;
10667 @option{bus_err} for a BusFault exception;
10669 @option{state_err},
10670 @option{chk_err}, or
10671 @option{nocp_err} for various UsageFault exceptions; or
10673 If NVIC setup code does not enable them,
10674 MemManage, BusFault, and UsageFault exceptions
10675 are mapped to HardFault.
10676 UsageFault checks for
10677 divide-by-zero and unaligned access
10678 must also be explicitly enabled.
10680 This finishes by listing the current vector catch configuration.
10683 @deffn {Command} {cortex_m reset_config} (@option{sysresetreq}|@option{vectreset})
10684 Control reset handling if hardware srst is not fitted
10685 @xref{reset_config,,reset_config}.
10688 @item @option{sysresetreq} use AIRCR SYSRESETREQ to reset system.
10689 @item @option{vectreset} use AIRCR VECTRESET to reset system (default).
10692 Using @option{vectreset} is a safe option for Cortex-M3, M4 and M7 cores.
10693 This however has the disadvantage of only resetting the core, all peripherals
10694 are unaffected. A solution would be to use a @code{reset-init} event handler
10695 to manually reset the peripherals.
10696 @xref{targetevents,,Target Events}.
10698 Cortex-M0, M0+ and M1 do not support @option{vectreset}, use @option{sysresetreq}
10702 @subsection ARMv8-A specific commands
10706 @deffn {Command} {aarch64 cache_info}
10707 Display information about target caches
10710 @deffn {Command} {aarch64 dbginit}
10711 This command enables debugging by clearing the OS Lock and sticky power-down and reset
10712 indications. It also establishes the expected, basic cross-trigger configuration the aarch64
10713 target code relies on. In a configuration file, the command would typically be called from a
10714 @code{reset-end} or @code{reset-deassert-post} handler, to re-enable debugging after a system reset.
10715 However, normally it is not necessary to use the command at all.
10718 @deffn {Command} {aarch64 disassemble} address [count]
10719 @cindex disassemble
10720 Disassembles @var{count} instructions starting at @var{address}.
10721 If @var{count} is not specified, a single instruction is disassembled.
10724 @deffn {Command} {aarch64 smp} [on|off]
10725 Display, enable or disable SMP handling mode. The state of SMP handling influences the way targets in an SMP group
10726 are handled by the run control. With SMP handling enabled, issuing halt or resume to one core will trigger
10727 halting or resuming of all cores in the group. The command @code{target smp} defines which targets are in the SMP
10728 group. With SMP handling disabled, all targets need to be treated individually.
10731 @deffn {Command} {aarch64 maskisr} [@option{on}|@option{off}]
10732 Selects whether interrupts will be processed when single stepping. The default configuration is
10736 @deffn {Command} {$target_name catch_exc} [@option{off}|@option{sec_el1}|@option{sec_el3}|@option{nsec_el1}|@option{nsec_el2}]+
10737 Cause @command{$target_name} to halt when an exception is taken. Any combination of
10738 Secure (sec) EL1/EL3 or Non-Secure (nsec) EL1/EL2 is valid. The target
10739 @command{$target_name} will halt before taking the exception. In order to resume
10740 the target, the exception catch must be disabled again with @command{$target_name catch_exc off}.
10741 Issuing the command without options prints the current configuration.
10744 @deffn {Command} {$target_name pauth} [@option{off}|@option{on}]
10745 Enable or disable pointer authentication features.
10746 When pointer authentication is used on ARM cores, GDB asks GDB servers for an 8-bytes mask to remove signature bits added by pointer authentication.
10747 If this feature is enabled, OpenOCD provides GDB with an 8-bytes mask.
10748 Pointer authentication feature is broken until gdb 12.1, going to be fixed.
10749 Consider using a newer version of gdb if you want to enable pauth feature.
10750 The default configuration is @option{off}.
10754 @section EnSilica eSi-RISC Architecture
10756 eSi-RISC is a highly configurable microprocessor architecture for embedded systems
10757 provided by EnSilica. (See: @url{http://www.ensilica.com/risc-ip/}.)
10759 @subsection eSi-RISC Configuration
10761 @deffn {Command} {esirisc cache_arch} (@option{harvard}|@option{von_neumann})
10762 Configure the caching architecture. Targets with the @code{UNIFIED_ADDRESS_SPACE}
10763 option disabled employ a Harvard architecture. By default, @option{von_neumann} is assumed.
10766 @deffn {Command} {esirisc hwdc} (@option{all}|@option{none}|mask ...)
10767 Configure hardware debug control. The HWDC register controls which exceptions return
10768 control back to the debugger. Possible masks are @option{all}, @option{none},
10769 @option{reset}, @option{interrupt}, @option{syscall}, @option{error}, and @option{debug}.
10770 By default, @option{reset}, @option{error}, and @option{debug} are enabled.
10773 @subsection eSi-RISC Operation
10775 @deffn {Command} {esirisc flush_caches}
10776 Flush instruction and data caches. This command requires that the target is halted
10777 when the command is issued and configured with an instruction or data cache.
10780 @subsection eSi-Trace Configuration
10782 eSi-RISC targets may be configured with support for instruction tracing. Trace
10783 data may be written to an in-memory buffer or FIFO. If a FIFO is configured, DMA
10784 is typically employed to move trace data off-device using a high-speed
10785 peripheral (eg. SPI). Collected trace data is encoded in one of three different
10786 formats. At a minimum, @command{esirisc trace buffer} or @command{esirisc trace
10787 fifo} must be issued along with @command{esirisc trace format} before trace data
10790 OpenOCD provides rudimentary analysis of collected trace data. If more detail is
10791 needed, collected trace data can be dumped to a file and processed by external
10795 OpenOCD is unable to process trace data sent to a FIFO. A potential workaround
10796 for this issue is to configure DMA to copy trace data to an in-memory buffer,
10797 which can then be passed to the @command{esirisc trace analyze} and
10798 @command{esirisc trace dump} commands.
10800 It is possible to corrupt trace data when using a FIFO if the peripheral
10801 responsible for draining data from the FIFO is not fast enough. This can be
10802 managed by enabling flow control, however this can impact timing-sensitive
10803 software operation on the CPU.
10806 @deffn {Command} {esirisc trace buffer} address size [@option{wrap}]
10807 Configure trace buffer using the provided address and size. If the @option{wrap}
10808 option is specified, trace collection will continue once the end of the buffer
10809 is reached. By default, wrap is disabled.
10812 @deffn {Command} {esirisc trace fifo} address
10813 Configure trace FIFO using the provided address.
10816 @deffn {Command} {esirisc trace flow_control} (@option{enable}|@option{disable})
10817 Enable or disable stalling the CPU to collect trace data. By default, flow
10818 control is disabled.
10821 @deffn {Command} {esirisc trace format} (@option{full}|@option{branch}|@option{icache}) pc_bits
10822 Configure trace format and number of PC bits to be captured. @option{pc_bits}
10823 must be within 1 and 31 as the LSB is not collected. If external tooling is used
10824 to analyze collected trace data, these values must match.
10826 Supported trace formats:
10828 @item @option{full} capture full trace data, allowing execution history and
10829 timing to be determined.
10830 @item @option{branch} capture taken branch instructions and branch target
10832 @item @option{icache} capture instruction cache misses.
10836 @deffn {Command} {esirisc trace trigger start} (@option{condition}) [start_data start_mask]
10837 Configure trigger start condition using the provided start data and mask. A
10838 brief description of each condition is provided below; for more detail on how
10839 these values are used, see the eSi-RISC Architecture Manual.
10841 Supported conditions:
10843 @item @option{none} manual tracing (see @command{esirisc trace start}).
10844 @item @option{pc} start tracing if the PC matches start data and mask.
10845 @item @option{load} start tracing if the effective address of a load
10846 instruction matches start data and mask.
10847 @item @option{store} start tracing if the effective address of a store
10848 instruction matches start data and mask.
10849 @item @option{exception} start tracing if the EID of an exception matches start
10851 @item @option{eret} start tracing when an @code{ERET} instruction is executed.
10852 @item @option{wait} start tracing when a @code{WAIT} instruction is executed.
10853 @item @option{stop} start tracing when a @code{STOP} instruction is executed.
10854 @item @option{high} start tracing when an external signal is a logical high.
10855 @item @option{low} start tracing when an external signal is a logical low.
10859 @deffn {Command} {esirisc trace trigger stop} (@option{condition}) [stop_data stop_mask]
10860 Configure trigger stop condition using the provided stop data and mask. A brief
10861 description of each condition is provided below; for more detail on how these
10862 values are used, see the eSi-RISC Architecture Manual.
10864 Supported conditions:
10866 @item @option{none} manual tracing (see @command{esirisc trace stop}).
10867 @item @option{pc} stop tracing if the PC matches stop data and mask.
10868 @item @option{load} stop tracing if the effective address of a load
10869 instruction matches stop data and mask.
10870 @item @option{store} stop tracing if the effective address of a store
10871 instruction matches stop data and mask.
10872 @item @option{exception} stop tracing if the EID of an exception matches stop
10874 @item @option{eret} stop tracing when an @code{ERET} instruction is executed.
10875 @item @option{wait} stop tracing when a @code{WAIT} instruction is executed.
10876 @item @option{stop} stop tracing when a @code{STOP} instruction is executed.
10880 @deffn {Command} {esirisc trace trigger delay} (@option{trigger}) [cycles]
10881 Configure trigger start/stop delay in clock cycles.
10883 Supported triggers:
10885 @item @option{none} no delay to start or stop collection.
10886 @item @option{start} delay @option{cycles} after trigger to start collection.
10887 @item @option{stop} delay @option{cycles} after trigger to stop collection.
10888 @item @option{both} delay @option{cycles} after both triggers to start or stop
10893 @subsection eSi-Trace Operation
10895 @deffn {Command} {esirisc trace init}
10896 Initialize trace collection. This command must be called any time the
10897 configuration changes. If a trace buffer has been configured, the contents will
10898 be overwritten when trace collection starts.
10901 @deffn {Command} {esirisc trace info}
10902 Display trace configuration.
10905 @deffn {Command} {esirisc trace status}
10906 Display trace collection status.
10909 @deffn {Command} {esirisc trace start}
10910 Start manual trace collection.
10913 @deffn {Command} {esirisc trace stop}
10914 Stop manual trace collection.
10917 @deffn {Command} {esirisc trace analyze} [address size]
10918 Analyze collected trace data. This command may only be used if a trace buffer
10919 has been configured. If a trace FIFO has been configured, trace data must be
10920 copied to an in-memory buffer identified by the @option{address} and
10921 @option{size} options using DMA.
10924 @deffn {Command} {esirisc trace dump} [address size] @file{filename}
10925 Dump collected trace data to file. This command may only be used if a trace
10926 buffer has been configured. If a trace FIFO has been configured, trace data must
10927 be copied to an in-memory buffer identified by the @option{address} and
10928 @option{size} options using DMA.
10931 @section Intel Architecture
10933 Intel Quark X10xx is the first product in the Quark family of SoCs. It is an IA-32
10934 (Pentium x86 ISA) compatible SoC. The core CPU in the X10xx is codenamed Lakemont.
10935 Lakemont version 1 (LMT1) is used in X10xx. The CPU TAP (Lakemont TAP) is used for
10936 software debug and the CLTAP is used for SoC level operations.
10937 Useful docs are here: https://communities.intel.com/community/makers/documentation
10939 @item Intel Quark SoC X1000 OpenOCD/GDB/Eclipse App Note (web search for doc num 330015)
10940 @item Intel Quark SoC X1000 Debug Operations User Guide (web search for doc num 329866)
10941 @item Intel Quark SoC X1000 Datasheet (web search for doc num 329676)
10944 @subsection x86 32-bit specific commands
10945 The three main address spaces for x86 are memory, I/O and configuration space.
10946 These commands allow a user to read and write to the 64Kbyte I/O address space.
10948 @deffn {Command} {x86_32 idw} address
10949 Display the contents of a 32-bit I/O port from address range 0x0000 - 0xffff.
10952 @deffn {Command} {x86_32 idh} address
10953 Display the contents of a 16-bit I/O port from address range 0x0000 - 0xffff.
10956 @deffn {Command} {x86_32 idb} address
10957 Display the contents of a 8-bit I/O port from address range 0x0000 - 0xffff.
10960 @deffn {Command} {x86_32 iww} address
10961 Write the contents of a 32-bit I/O port to address range 0x0000 - 0xffff.
10964 @deffn {Command} {x86_32 iwh} address
10965 Write the contents of a 16-bit I/O port to address range 0x0000 - 0xffff.
10968 @deffn {Command} {x86_32 iwb} address
10969 Write the contents of a 8-bit I/O port to address range 0x0000 - 0xffff.
10972 @section OpenRISC Architecture
10974 The OpenRISC CPU is a soft core. It is used in a programmable SoC which can be
10975 configured with any of the TAP / Debug Unit available.
10977 @subsection TAP and Debug Unit selection commands
10978 @deffn {Command} {tap_select} (@option{vjtag}|@option{mohor}|@option{xilinx_bscan})
10979 Select between the Altera Virtual JTAG , Xilinx Virtual JTAG and Mohor TAP.
10981 @deffn {Command} {du_select} (@option{adv}|@option{mohor}) [option]
10982 Select between the Advanced Debug Interface and the classic one.
10984 An option can be passed as a second argument to the debug unit.
10986 When using the Advanced Debug Interface, option = 1 means the RTL core is
10987 configured with ADBG_USE_HISPEED = 1. This configuration skips status checking
10988 between bytes while doing read or write bursts.
10991 @subsection Registers commands
10992 @deffn {Command} {addreg} [name] [address] [feature] [reg_group]
10993 Add a new register in the cpu register list. This register will be
10994 included in the generated target descriptor file.
10996 @strong{[feature]} must be "org.gnu.gdb.or1k.group[0..10]".
10998 @strong{[reg_group]} can be anything. The default register list defines "system",
10999 "dmmu", "immu", "dcache", "icache", "mac", "debug", "perf", "power", "pic"
11000 and "timer" groups.
11004 addreg rtest 0x1234 org.gnu.gdb.or1k.group0 system
11009 @section MIPS Architecture
11014 @uref{http://mips.com/, MIPS} is a simple, streamlined, highly scalable RISC
11015 architecture. The architecture is evolving over time, from MIPS I~V to
11016 MIPS release 1~6 iterations, the architecture is now able to handle various tasks
11017 with different ASEs, including SIMD(MSA), DSP, VZ, MT and more.
11018 MIPS32 supports 32-bit programs while MIPS64 can support both 32-bit and 64-bit programs.
11020 @subsection MIPS Terminology
11022 The term ASE means Application-Specific Extension, ASEs provide features that
11023 improve the efficiency and performance of certain workloads, such as
11024 digital signal processing(DSP), Virtualization(VZ), Multi-Threading(MT),
11025 SIMD(MSA) and more.
11027 MIPS Cores use Coprocessors(CPx) to configure their behaviour or to let software
11028 know the capabilities of current CPU, the main Coprocessor is CP0, containing 32
11029 registers with a maximum select number of 7.
11031 @subsection MIPS FPU & Vector Registers
11033 MIPS processors does not all comes with FPU co-processor, and when it does, the FPU
11034 appears as Coprocessor 1 whereas the Coprocessor 0 is for the main processor.
11036 Most of MIPS FPUs are 64 bits, IEEE 754 standard, and they provides both 32-bit
11037 single precision and 64-bit double precision calculations. Fixed point format
11038 calculations are also provided with both 32 and 64-bit modes.
11040 The MIPS SIMD Architecture(MSA) operates on 32 128-bit wide vector registers.
11041 If both MSA and the scalar floating-point unit (FPU) are present, the 128-bit MSA
11042 vector registers extend and share the 64-bit FPU registers. MSA and FPU can not be
11043 both present, unless the FPU has 64-bit floating-point register.
11045 @subsection MIPS Configuration Commands
11047 @deffn {Command} {mips32 cpuinfo}
11048 Displays detailed information about current CPU core. This includes core type,
11049 vendor, instruction set, cache size, and other relevant details.
11052 @deffn {Config Command} {mips32 scan_delay} [nanoseconds]
11053 Display or set scan delay in nano seconds. A value below 2_000_000 will set the
11054 scan delay into legacy mode.
11057 @deffn {Config Command} {mips32 cp0} [[reg_name|regnum select] [value]]
11058 Displays or sets coprocessor 0 register by register number and select or their name.
11059 This command shows all available cp0 register if no arguments are provided.
11061 For common MIPS Coprocessor 0 registers, you can find the definitions of them
11062 on MIPS Privileged Resource Architecture Documents(MIPS Document MD00090).
11064 For core specific cp0 registers, you can find the definitions of them on Core
11065 Specific Software User's Manual(SUM), for example, MIPS M5150 Software User Manual
11069 @deffn {Command} {mips32 ejtag_reg}
11070 Reads EJTAG Registers for inspection.
11072 EJTAG Register Specification could be found in MIPS Document MD00047F, for
11073 core specific EJTAG Register definition, please check Core Specific SUM manual.
11076 @section RISC-V Architecture
11078 @uref{http://riscv.org/, RISC-V} is a free and open ISA. OpenOCD supports JTAG
11079 debug of RV32 and RV64 cores in heterogeneous multicore systems of up to 32
11080 harts. (It's possible to increase this limit to 1024 by changing
11081 RISCV_MAX_HARTS in riscv.h.) OpenOCD primarily supports 0.13 of the RISC-V
11082 Debug Specification, but there is also support for legacy targets that
11083 implement version 0.11.
11085 @subsection RISC-V Terminology
11087 A @emph{hart} is a hardware thread. A hart may share resources (eg. FPU) with
11088 another hart, or may be a separate core. RISC-V treats those the same, and
11089 OpenOCD exposes each hart as a separate core.
11091 @subsection Vector Registers
11093 For harts that implement the vector extension, OpenOCD provides access to the
11094 relevant CSRs, as well as the vector registers (v0-v31). The size of each
11095 vector register is dependent on the value of vlenb. RISC-V allows each vector
11096 register to be divided into selected-width elements, and this division can be
11097 changed at run-time. Because OpenOCD cannot update register definitions at
11098 run-time, it exposes each vector register to gdb as a union of fields of
11099 vectors so that users can easily access individual bytes, shorts, words,
11100 longs, and quads inside each vector register. It is left to gdb or
11101 higher-level debuggers to present this data in a more intuitive format.
11103 In the XML register description, the vector registers (when vlenb=16) look as
11107 <feature name="org.gnu.gdb.riscv.vector">
11108 <vector id="bytes" type="uint8" count="16"/>
11109 <vector id="shorts" type="uint16" count="8"/>
11110 <vector id="words" type="uint32" count="4"/>
11111 <vector id="longs" type="uint64" count="2"/>
11112 <vector id="quads" type="uint128" count="1"/>
11113 <union id="riscv_vector">
11114 <field name="b" type="bytes"/>
11115 <field name="s" type="shorts"/>
11116 <field name="w" type="words"/>
11117 <field name="l" type="longs"/>
11118 <field name="q" type="quads"/>
11120 <reg name="v0" bitsize="128" regnum="4162" save-restore="no"
11121 type="riscv_vector" group="vector"/>
11123 <reg name="v31" bitsize="128" regnum="4193" save-restore="no"
11124 type="riscv_vector" group="vector"/>
11128 @subsection RISC-V Debug Configuration Commands
11130 @deffn {Config Command} {riscv expose_csrs} n[-m|=name] [...]
11131 Configure which CSRs to expose in addition to the standard ones. The CSRs to expose
11132 can be specified as individual register numbers or register ranges (inclusive). For the
11133 individually listed CSRs, a human-readable name can optionally be set using the @code{n=name}
11134 syntax, which will get @code{csr_} prepended to it. If no name is provided, the register will be
11135 named @code{csr<n>}.
11137 By default OpenOCD attempts to expose only CSRs that are mentioned in a spec,
11138 and then only if the corresponding extension appears to be implemented. This
11139 command can be used if OpenOCD gets this wrong, or if the target implements custom
11143 # Expose a single RISC-V CSR number 128 under the name "csr128":
11144 $_TARGETNAME expose_csrs 128
11146 # Expose multiple RISC-V CSRs 128..132 under names "csr128" through "csr132":
11147 $_TARGETNAME expose_csrs 128-132
11149 # Expose a single RISC-V CSR number 1996 under custom name "csr_myregister":
11150 $_TARGETNAME expose_csrs 1996=myregister
11154 @deffn {Config Command} {riscv expose_custom} n[-m|=name] [...]
11155 The RISC-V Debug Specification allows targets to expose custom registers
11156 through abstract commands. (See Section 3.5.1.1 in that document.) This command
11157 configures individual registers or register ranges (inclusive) that shall be exposed.
11158 Number 0 indicates the first custom register, whose abstract command number is 0xc000.
11159 For individually listed registers, a human-readable name can be optionally provided
11160 using the @code{n=name} syntax, which will get @code{custom_} prepended to it. If no
11161 name is provided, the register will be named @code{custom<n>}.
11164 # Expose one RISC-V custom register with number 0xc010 (0xc000 + 16)
11165 # under the name "custom16":
11166 $_TARGETNAME expose_custom 16
11168 # Expose a range of RISC-V custom registers with numbers 0xc010 .. 0xc018
11169 # (0xc000+16 .. 0xc000+24) under the names "custom16" through "custom24":
11170 $_TARGETNAME expose_custom 16-24
11172 # Expose one RISC-V custom register with number 0xc020 (0xc000 + 32) under
11173 # user-defined name "custom_myregister":
11174 $_TARGETNAME expose_custom 32=myregister
11178 @deffn {Command} {riscv info}
11179 Displays some information OpenOCD detected about the target.
11182 @deffn {Command} {riscv reset_delays} [wait]
11183 OpenOCD learns how many Run-Test/Idle cycles are required between scans to avoid
11184 encountering the target being busy. This command resets those learned values
11185 after `wait` scans. It's only useful for testing OpenOCD itself.
11188 @deffn {Command} {riscv set_command_timeout_sec} [seconds]
11189 Set the wall-clock timeout (in seconds) for individual commands. The default
11190 should work fine for all but the slowest targets (eg. simulators).
11193 @deffn {Command} {riscv set_reset_timeout_sec} [seconds]
11194 Set the maximum time to wait for a hart to come out of reset after reset is
11198 @deffn {Command} {riscv set_mem_access} method1 [method2] [method3]
11199 Specify which RISC-V memory access method(s) shall be used, and in which order
11200 of priority. At least one method must be specified.
11202 Available methods are:
11204 @item @code{progbuf} - Use RISC-V Debug Program Buffer to access memory.
11205 @item @code{sysbus} - Access memory via RISC-V Debug System Bus interface.
11206 @item @code{abstract} - Access memory via RISC-V Debug abstract commands.
11209 By default, all memory access methods are enabled in the following order:
11210 @code{progbuf sysbus abstract}.
11212 This command can be used to change the memory access methods if the default
11213 behavior is not suitable for a particular target.
11216 @deffn {Command} {riscv set_enable_virtual} on|off
11217 When on, memory accesses are performed on physical or virtual memory depending
11218 on the current system configuration. When off (default), all memory accessses are performed
11219 on physical memory.
11222 @deffn {Command} {riscv set_enable_virt2phys} on|off
11223 When on (default), memory accesses are performed on physical or virtual memory
11224 depending on the current satp configuration. When off, all memory accessses are
11225 performed on physical memory.
11228 @deffn {Command} {riscv resume_order} normal|reversed
11229 Some software assumes all harts are executing nearly continuously. Such
11230 software may be sensitive to the order that harts are resumed in. On harts
11231 that don't support hasel, this option allows the user to choose the order the
11232 harts are resumed in. If you are using this option, it's probably masking a
11233 race condition problem in your code.
11235 Normal order is from lowest hart index to highest. This is the default
11236 behavior. Reversed order is from highest hart index to lowest.
11239 @deffn {Command} {riscv set_ir} (@option{idcode}|@option{dtmcs}|@option{dmi}) [value]
11240 Set the IR value for the specified JTAG register. This is useful, for
11241 example, when using the existing JTAG interface on a Xilinx FPGA by
11242 way of BSCANE2 primitives that only permit a limited selection of IR
11245 When utilizing version 0.11 of the RISC-V Debug Specification,
11246 @option{dtmcs} and @option{dmi} set the IR values for the DTMCONTROL
11247 and DBUS registers, respectively.
11250 @deffn {Command} {riscv use_bscan_tunnel} value
11251 Enable or disable use of a BSCAN tunnel to reach DM. Supply the width of
11252 the DM transport TAP's instruction register to enable. Supply a value of 0 to disable.
11255 @deffn {Command} {riscv set_ebreakm} on|off
11256 Control dcsr.ebreakm. When on (default), M-mode ebreak instructions trap to
11257 OpenOCD. When off, they generate a breakpoint exception handled internally.
11260 @deffn {Command} {riscv set_ebreaks} on|off
11261 Control dcsr.ebreaks. When on (default), S-mode ebreak instructions trap to
11262 OpenOCD. When off, they generate a breakpoint exception handled internally.
11265 @deffn {Command} {riscv set_ebreaku} on|off
11266 Control dcsr.ebreaku. When on (default), U-mode ebreak instructions trap to
11267 OpenOCD. When off, they generate a breakpoint exception handled internally.
11270 @subsection RISC-V Authentication Commands
11272 The following commands can be used to authenticate to a RISC-V system. Eg. a
11273 trivial challenge-response protocol could be implemented as follows in a
11274 configuration file, immediately following @command{init}:
11276 set challenge [riscv authdata_read]
11277 riscv authdata_write [expr @{$challenge + 1@}]
11280 @deffn {Command} {riscv authdata_read}
11281 Return the 32-bit value read from authdata.
11284 @deffn {Command} {riscv authdata_write} value
11285 Write the 32-bit value to authdata.
11288 @subsection RISC-V DMI Commands
11290 The following commands allow direct access to the Debug Module Interface, which
11291 can be used to interact with custom debug features.
11293 @deffn {Command} {riscv dmi_read} address
11294 Perform a 32-bit DMI read at address, returning the value.
11297 @deffn {Command} {riscv dmi_write} address value
11298 Perform a 32-bit DMI write of value at address.
11301 @section ARC Architecture
11304 Synopsys DesignWare ARC Processors are a family of 32-bit CPUs that SoC
11305 designers can optimize for a wide range of uses, from deeply embedded to
11306 high-performance host applications in a variety of market segments. See more
11307 at: @url{http://www.synopsys.com/IP/ProcessorIP/ARCProcessors/Pages/default.aspx}.
11308 OpenOCD currently supports ARC EM processors.
11309 There is a set ARC-specific OpenOCD commands that allow low-level
11310 access to the core and provide necessary support for ARC extensibility and
11311 configurability capabilities. ARC processors has much more configuration
11312 capabilities than most of the other processors and in addition there is an
11313 extension interface that allows SoC designers to add custom registers and
11314 instructions. For the OpenOCD that mostly means that set of core and AUX
11315 registers in target will vary and is not fixed for a particular processor
11316 model. To enable extensibility several TCL commands are provided that allow to
11317 describe those optional registers in OpenOCD configuration files. Moreover
11318 those commands allow for a dynamic target features discovery.
11321 @subsection General ARC commands
11323 @deffn {Config Command} {arc add-reg} configparams
11325 Add a new register to processor target. By default newly created register is
11326 marked as not existing. @var{configparams} must have following required
11331 @item @code{-name} name
11332 @*Name of a register.
11334 @item @code{-num} number
11335 @*Architectural register number: core register number or AUX register number.
11337 @item @code{-feature} XML_feature
11338 @*Name of GDB XML target description feature.
11342 @var{configparams} may have following optional arguments:
11346 @item @code{-gdbnum} number
11347 @*GDB register number. It is recommended to not assign GDB register number
11348 manually, because there would be a risk that two register will have same
11349 number. When register GDB number is not set with this option, then register
11350 will get a previous register number + 1. This option is required only for those
11351 registers that must be at particular address expected by GDB.
11354 @*This option specifies that register is a core registers. If not - this is an
11355 AUX register. AUX registers and core registers reside in different address
11359 @*This options specifies that register is a BCR register. BCR means Build
11360 Configuration Registers - this is a special type of AUX registers that are read
11361 only and non-volatile, that is - they never change their value. Therefore OpenOCD
11362 never invalidates values of those registers in internal caches. Because BCR is a
11363 type of AUX registers, this option cannot be used with @code{-core}.
11365 @item @code{-type} type_name
11366 @*Name of type of this register. This can be either one of the basic GDB types,
11367 or a custom types described with @command{arc add-reg-type-[flags|struct]}.
11370 @* If specified then this is a "general" register. General registers are always
11371 read by OpenOCD on context save (when core has just been halted) and is always
11372 transferred to GDB client in a response to g-packet. Contrary to this,
11373 non-general registers are read and sent to GDB client on-demand. In general it
11374 is not recommended to apply this option to custom registers.
11380 @deffn {Config Command} {arc add-reg-type-flags} -name name flags...
11381 Adds new register type of ``flags'' class. ``Flags'' types can contain only
11382 one-bit fields. Each flag definition looks like @code{-flag name bit-position}.
11385 @anchor{add-reg-type-struct}
11386 @deffn {Config Command} {arc add-reg-type-struct} -name name structs...
11387 Adds new register type of ``struct'' class. ``Struct'' types can contain either
11388 bit-fields or fields of other types, however at the moment only bit fields are
11389 supported. Structure bit field definition looks like @code{-bitfield name
11393 @deffn {Command} {arc get-reg-field} reg-name field-name
11394 Returns value of bit-field in a register. Register must be ``struct'' register
11395 type, @xref{add-reg-type-struct}. command definition.
11398 @deffn {Command} {arc set-reg-exists} reg-names...
11399 Specify that some register exists. Any amount of names can be passed
11400 as an argument for a single command invocation.
11403 @subsection ARC JTAG commands
11405 @deffn {Command} {arc jtag set-aux-reg} regnum value
11406 This command writes value to AUX register via its number. This command access
11407 register in target directly via JTAG, bypassing any OpenOCD internal caches,
11408 therefore it is unsafe to use if that register can be operated by other means.
11412 @deffn {Command} {arc jtag set-core-reg} regnum value
11413 This command is similar to @command{arc jtag set-aux-reg} but is for core
11417 @deffn {Command} {arc jtag get-aux-reg} regnum
11418 This command returns the value storded in AUX register via its number. This commands access
11419 register in target directly via JTAG, bypassing any OpenOCD internal caches,
11420 therefore it is unsafe to use if that register can be operated by other means.
11424 @deffn {Command} {arc jtag get-core-reg} regnum
11425 This command is similar to @command{arc jtag get-aux-reg} but is for core
11429 @section STM8 Architecture
11430 @uref{http://st.com/stm8/, STM8} is a 8-bit microcontroller platform from
11431 STMicroelectronics, based on a proprietary 8-bit core architecture.
11433 OpenOCD supports debugging STM8 through the STMicroelectronics debug
11434 protocol SWIM, @pxref{swimtransport,,SWIM}.
11436 @section Xtensa Architecture
11438 Xtensa is a highly-customizable, user-extensible microprocessor and DSP
11439 architecture for complex embedded systems provided by Cadence Design
11440 Systems, Inc. See the
11441 @uref{https://www.cadence.com/en_US/home/tools/ip/tensilica-ip.html, Tensilica IP}
11442 website for additional information and documentation.
11444 OpenOCD supports generic Xtensa processor implementations which can be customized by
11445 providing a core-specific configuration file which describes every enabled
11446 Xtensa architecture option, e.g. number of address registers, exceptions, reduced
11447 size instructions support, memory banks configuration etc. OpenOCD also supports SMP
11448 configurations for Xtensa processors with any number of cores and allows configuring
11449 their debug interconnect (termed "break/stall networks"), which control how debug
11450 signals are distributed among cores. Xtensa "break networks" are compatible with
11451 ARM's Cross Trigger Interface (CTI). OpenOCD implements both generic Xtensa targets
11452 as well as several Espressif Xtensa-based chips from the
11453 @uref{https://www.espressif.com/en/products/socs, ESP32 family}.
11455 OCD sessions for Xtensa processor and DSP targets are accessed via the Xtensa
11456 Debug Module (XDM), which provides external connectivity either through a
11457 traditional JTAG interface or an ARM DAP interface. If used, the DAP interface
11458 can control Xtensa targets through JTAG or SWD probes.
11460 @subsection Xtensa Core Configuration
11462 Due to the high level of configurability in Xtensa cores, the Xtensa target
11463 configuration comprises two categories:
11466 @item Base Xtensa support common to all core configurations, and
11467 @item Core-specific support as configured for individual cores.
11470 All common Xtensa support is built into the OpenOCD Xtensa target layer and
11471 is enabled through a combination of TCL scripts: the target-specific
11472 @file{target/xtensa.cfg} and a board-specific @file{board/xtensa-*.cfg},
11473 similar to other target architectures.
11475 Importantly, core-specific configuration information must be provided by
11476 the user, and takes the form of an @file{xtensa-core-XXX.cfg} TCL script that
11477 defines the core's configurable features through a series of Xtensa
11478 configuration commands (detailed below).
11480 This core-specific @file{xtensa-core-XXX.cfg} file is typically either:
11483 @item Located within the Xtensa core configuration build as
11484 @file{src/config/xtensa-core-openocd.cfg}, or
11485 @item Generated by running the command @code{xt-gdb --dump-oocd-config}
11486 from the Xtensa processor tool-chain's command-line tools.
11489 NOTE: @file{xtensa-core-XXX.cfg} must match the target Xtensa hardware
11490 connected to OpenOCD.
11492 Some example Xtensa configurations are bundled with OpenOCD for reference:
11494 @item Cadence Palladium VDebug emulation target. The user can combine their
11495 @file{xtensa-core-XXX.cfg} with the provided
11496 @file{board/xtensa-palladium-vdebug.cfg} to debug an emulated Xtensa RTL design.
11497 @item NXP MIMXRT685-EVK evaluation kit. The relevant configuration files are:
11499 @item @file{board/xtensa-rt685-ext.cfg}
11500 @item @file{target/xtensa-core-nxp_rt600.cfg}
11502 Additional information is available by searching for "i.MX RT600 Evaluation Kit"
11503 on @url{https://www.nxp.com}.
11506 @subsection Xtensa Configuration Commands
11508 @deffn {Config Command} {xtensa xtdef} (@option{LX}|@option{NX})
11509 Configure the Xtensa target architecture. Currently, Xtensa support is limited
11510 to LX6, LX7, and NX cores.
11513 @deffn {Config Command} {xtensa xtopt} option value
11514 Configure Xtensa target options that are relevant to the debug subsystem.
11515 @var{option} is one of: @option{arnum}, @option{windowed},
11516 @option{cpenable}, @option{exceptions}, @option{intnum}, @option{hipriints},
11517 @option{excmlevel}, @option{intlevels}, @option{debuglevel},
11518 @option{ibreaknum}, or @option{dbreaknum}. @var{value} is an integer with
11519 the exact range determined by each particular option.
11521 NOTE: Some options are specific to Xtensa LX or Xtensa NX architecture, while
11522 others may be common to both but have different valid ranges.
11525 @deffn {Config Command} {xtensa xtmem} (@option{iram}|@option{dram}|@option{sram}|@option{irom}|@option{drom}|@option{srom}) baseaddr bytes
11526 Configure Xtensa target memory. Memory type determines access rights,
11527 where RAMs are read/write while ROMs are read-only. @var{baseaddr} and
11528 @var{bytes} are both integers, typically hexadecimal and decimal, respectively.
11530 NOTE: Some Xtensa memory types, such as system RAM/ROM or MMIO/device regions,
11531 can be added or modified after the Xtensa core has been generated. Additional
11532 @code{xtensa xtmem} definitions should be manually added to xtensa-core-XXX.cfg
11533 to keep OpenOCD's target address map consistent with the Xtensa configuration.
11536 @deffn {Config Command} {xtensa xtmem} (@option{icache}|@option{dcache}) linebytes cachebytes ways [writeback]
11537 Configure Xtensa processor cache. All parameters are required except for
11538 the optional @option{writeback} parameter; all are integers.
11541 @deffn {Config Command} {xtensa xtmpu} numfgseg minsegsz lockable execonly
11542 Configure an Xtensa Memory Protection Unit (MPU). MPUs can restrict access
11543 and/or control cacheability of specific address ranges, but are lighter-weight
11544 than a full traditional MMU. All parameters are required; all are integers.
11547 @deffn {Config Command} {xtensa xtmmu} numirefillentries numdrefillentries
11548 (Xtensa-LX only) Configure an Xtensa Memory Management Unit (MMU). Both
11549 parameters are required; both are integers.
11552 @deffn {Config Command} {xtensa xtregs} numregs
11553 Configure the total number of registers for the Xtensa core. Configuration
11554 logic expects to subsequently process this number of @code{xtensa xtreg}
11555 definitions. @var{numregs} is an integer.
11558 @deffn {Config Command} {xtensa xtregfmt} (@option{sparse}|@option{contiguous}) [general]
11559 Configure the type of register map used by GDB to access the Xtensa core.
11560 Generic Xtensa tools (e.g. xt-gdb) require @option{sparse} mapping (default) while
11561 Espressif tools expect @option{contiguous} mapping. Contiguous mapping takes an
11562 additional, optional integer parameter @option{numgregs}, which specifies the number
11563 of general registers used in handling g/G packets.
11566 @deffn {Config Command} {xtensa xtreg} name offset
11567 Configure an Xtensa core register. All core registers are 32 bits wide,
11568 while TIE and user registers may have variable widths. @var{name} is a
11569 character string identifier while @var{offset} is a hexadecimal integer.
11572 @subsection Xtensa Operation Commands
11574 @deffn {Command} {xtensa maskisr} (@option{on}|@option{off})
11575 (Xtensa-LX only) Mask or unmask Xtensa interrupts during instruction step.
11576 When masked, an interrupt that occurs during a step operation is handled and
11577 its ISR is executed, with the user's debug session returning after potentially
11578 executing many instructions. When unmasked, a triggered interrupt will result
11579 in execution progressing the requested number of instructions into the relevant
11583 @deffn {Command} {xtensa set_permissive} (0|1)
11584 By default accessing memory beyond defined regions is forbidden. This commnd controls memory access address check.
11585 When set to (1), skips access controls and address range check before read/write memory.
11588 @deffn {Command} {xtensa smpbreak} [none|breakinout|runstall] | [BreakIn] [BreakOut] [RunStallIn] [DebugModeOut]
11589 Configures debug signals connection ("break network") for currently selected core.
11591 @item @code{none} - Core's "break/stall network" is disconnected. Core is not affected by any debug
11592 signal from other cores.
11593 @item @code{breakinout} - Core's "break network" is fully connected (break inputs and outputs are enabled).
11594 Core will receive debug break signals from other cores and send such signals to them. For example when another core
11595 is stopped due to breakpoint hit this core will be stopped too and vice versa.
11596 @item @code{runstall} - Core's "stall network" is fully connected (stall inputs and outputs are enabled).
11597 This feature is not well implemented and tested yet.
11598 @item @code{BreakIn} - Core's "break-in" signal is enabled.
11599 Core will receive debug break signals from other cores. For example when another core is
11600 stopped due to breakpoint hit this core will be stopped too.
11601 @item @code{BreakOut} - Core's "break-out" signal is enabled.
11602 Core will send debug break signal to other cores. For example when this core is
11603 stopped due to breakpoint hit other cores with enabled break-in signals will be stopped too.
11604 @item @code{RunStallIn} - Core's "runstall-in" signal is enabled.
11605 This feature is not well implemented and tested yet.
11606 @item @code{DebugModeOut} - Core's "debugmode-out" signal is enabled.
11607 This feature is not well implemented and tested yet.
11611 @deffn {Command} {xtensa exe} <ascii-encoded hexadecimal instruction bytes>
11612 Execute one arbitrary instruction provided as an ascii string. The string represents an integer
11613 number of instruction bytes, thus its length must be even. The instruction can be of any width
11614 that is valid for the Xtensa core configuration.
11617 @deffn {Command} {xtensa dm} (address) [value]
11618 Read or write Xtensa Debug Module (DM) registers. @var{address} is required for both reads
11619 and writes and is a 4-byte-aligned value typically between 0 and 0x3ffc. @var{value} is specified
11620 only for write accesses.
11623 @subsection Xtensa Performance Monitor Configuration
11625 @deffn {Command} {xtensa perfmon_enable} <counter_id> <select> [mask] [kernelcnt] [tracelevel]
11626 Enable and start performance counter.
11628 @item @code{counter_id} - Counter ID (0-1).
11629 @item @code{select} - Selects performance metric to be counted by the counter,
11630 e.g. 0 - CPU cycles, 2 - retired instructions.
11631 @item @code{mask} - Selects input subsets to be counted (counter will
11632 increment only once even if more than one condition corresponding to a mask bit occurs).
11633 @item @code{kernelcnt} - 0 - count events with "CINTLEVEL <= tracelevel",
11634 1 - count events with "CINTLEVEL > tracelevel".
11635 @item @code{tracelevel} - Compares this value to "CINTLEVEL" when deciding
11640 @deffn {Command} {xtensa perfmon_dump} (counter_id)
11641 Dump performance counter value. If no argument specified, dumps all counters.
11644 @subsection Xtensa Trace Configuration
11646 @deffn {Command} {xtensa tracestart} [pc <pcval>/[<maskbitcount>]] [after <n> [ins|words]]
11647 Set up and start a HW trace. Optionally set PC address range to trigger tracing stop when reached during program execution.
11648 This command also allows to specify the amount of data to capture after stop trigger activation.
11650 @item @code{pcval} - PC value which will trigger trace data collection stop.
11651 @item @code{maskbitcount} - PC value mask.
11652 @item @code{n} - Maximum number of instructions/words to capture after trace stop trigger.
11656 @deffn {Command} {xtensa tracestop}
11657 Stop current trace as started by the tracestart command.
11660 @deffn {Command} {xtensa tracedump} <outfile>
11661 Dump trace memory to a file.
11664 @section Espressif Specific Commands
11666 @deffn {Command} {esp apptrace} (start <destination> [<poll_period> [<trace_size> [<stop_tmo> [<wait4halt> [<skip_size>]]]]])
11668 @uref{https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/app_trace.html#application-level-tracing-library, application level tracing}.
11669 Data will be stored to specified destination. Available destinations are:
11671 @item @code{file://<outfile>} - Save trace logs into file.
11672 @item @code{tcp://<host>:<port>} - Send trace logs to tcp port on specified host. OpenOCD will act as a tcp client.
11673 @item @code{con:} - Print trace logs to the stdout.
11675 Other parameters will be same for each destination.
11677 @item @code{poll_period} - trace data polling period in ms.
11678 @item @code{trace_size} - maximum trace data size.
11679 Tracing will be stopped automatically when that amount is reached.
11680 Use "-1" to disable the limitation.
11681 @item @code{stop_tmo} - Data reception timeout in ms.
11682 Tracing will be stopped automatically when no data is received within that period.
11683 @item @code{wait4halt} - if non-zero then wait for target to be halted before tracing start.
11684 @item @code{skip_size} - amount of tracing data to be skipped before writing it to destination.
11688 @deffn {Command} {esp apptrace} (stop)
11689 Stops tracing started with above command.
11692 @deffn {Command} {esp apptrace} (status)
11693 Requests ongoing tracing status.
11696 @deffn {Command} {esp apptrace} (dump file://<outfile>)
11697 Dumps tracing data from target buffer. It can be useful to dump the latest data
11698 buffered on target for post-mortem analysis. For example when target starts tracing automatically
11699 w/o OpenOCD command and keeps only the latest data window which fit into the buffer.
11700 @uref{https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/app_trace.html#application-level-tracing-library, application level tracing}.
11701 Data will be stored to specified destination.
11704 @deffn {Command} {esp sysview} (start file://<outfile1> [file://<outfile2>] [<poll_period> [<trace_size> [<stop_tmo> [<wait4halt> [<skip_size>]]]]])
11705 Starts @uref{https://www.segger.com/products/development-tools/systemview/, SEGGER SystemView}
11706 compatible tracing. Data will be stored to specified destination.
11707 For dual-core chips traces from every core will be saved to separate files.
11708 Resulting files can be open in "SEGGER SystemView" application.
11709 @url{https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/app_trace.html#openocd-systemview-tracing-command-options}
11710 The meaning of the arguments is identical to @command{esp apptrace start}.
11713 @deffn {Command} {esp sysview} (stop)
11714 Stops SystremView compatible tracing started with above command.
11715 @url{https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/app_trace.html#openocd-systemview-tracing-command-options}
11718 @deffn {Command} {esp sysview} (status)
11719 Requests ongoing SystremView compatible tracing status.
11720 @url{https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/app_trace.html#openocd-systemview-tracing-command-options}
11723 @deffn {Command} {esp sysview_mcore} (start file://<outfile> [<poll_period> [<trace_size> [<stop_tmo> [<wait4halt> [<skip_size>]]]]])
11724 This command is identical to @command{esp sysview start}, but uses Espressif multi-core extension to
11725 @uref{https://www.segger.com/products/development-tools/systemview/, SEGGER SystemView} data format.
11726 Data will be stored to specified destination. Tracing data from all cores are saved in the same file.
11727 The meaning of the arguments is identical to @command{esp sysview start}.
11730 @deffn {Command} {esp sysview_mcore} (stop)
11731 Stops Espressif multi-core SystremView tracing started with above command.
11734 @deffn {Command} {esp sysview_mcore} (status)
11735 Requests ongoing Espressif multi-core SystremView tracing status.
11738 @anchor{softwaredebugmessagesandtracing}
11739 @section Software Debug Messages and Tracing
11740 @cindex Linux-ARM DCC support
11744 OpenOCD can process certain requests from target software, when
11745 the target uses appropriate libraries.
11746 The most powerful mechanism is semihosting, but there is also
11747 a lighter weight mechanism using only the DCC channel.
11749 Currently @command{target_request debugmsgs}
11750 is supported only for @option{arm7_9} and @option{cortex_m} cores.
11751 These messages are received as part of target polling, so
11752 you need to have @command{poll on} active to receive them.
11753 They are intrusive in that they will affect program execution
11754 times. If that is a problem, @pxref{armhardwaretracing,,ARM Hardware Tracing}.
11756 See @file{libdcc} in the contrib dir for more details.
11757 In addition to sending strings, characters, and
11758 arrays of various size integers from the target,
11759 @file{libdcc} also exports a software trace point mechanism.
11760 The target being debugged may
11761 issue trace messages which include a 24-bit @dfn{trace point} number.
11762 Trace point support includes two distinct mechanisms,
11763 each supported by a command:
11766 @item @emph{History} ... A circular buffer of trace points
11767 can be set up, and then displayed at any time.
11768 This tracks where code has been, which can be invaluable in
11769 finding out how some fault was triggered.
11771 The buffer may overflow, since it collects records continuously.
11772 It may be useful to use some of the 24 bits to represent a
11773 particular event, and other bits to hold data.
11775 @item @emph{Counting} ... An array of counters can be set up,
11776 and then displayed at any time.
11777 This can help establish code coverage and identify hot spots.
11779 The array of counters is directly indexed by the trace point
11780 number, so trace points with higher numbers are not counted.
11783 Linux-ARM kernels have a ``Kernel low-level debugging
11784 via EmbeddedICE DCC channel'' option (CONFIG_DEBUG_ICEDCC,
11785 depends on CONFIG_DEBUG_LL) which uses this mechanism to
11786 deliver messages before a serial console can be activated.
11787 This is not the same format used by @file{libdcc}.
11788 Other software, such as the U-Boot boot loader, sometimes
11789 does the same thing.
11791 @deffn {Command} {target_request debugmsgs} [@option{enable}|@option{disable}|@option{charmsg}]
11792 Displays current handling of target DCC message requests.
11793 These messages may be sent to the debugger while the target is running.
11794 The optional @option{enable} and @option{charmsg} parameters
11795 both enable the messages, while @option{disable} disables them.
11797 With @option{charmsg} the DCC words each contain one character,
11798 as used by Linux with CONFIG_DEBUG_ICEDCC;
11799 otherwise the libdcc format is used.
11802 @deffn {Command} {trace history} [@option{clear}|count]
11803 With no parameter, displays all the trace points that have triggered
11804 in the order they triggered.
11805 With the parameter @option{clear}, erases all current trace history records.
11806 With a @var{count} parameter, allocates space for that many
11810 @deffn {Command} {trace point} [@option{clear}|identifier]
11811 With no parameter, displays all trace point identifiers and how many times
11812 they have been triggered.
11813 With the parameter @option{clear}, erases all current trace point counters.
11814 With a numeric @var{identifier} parameter, creates a new a trace point counter
11815 and associates it with that identifier.
11817 @emph{Important:} The identifier and the trace point number
11818 are not related except by this command.
11819 These trace point numbers always start at zero (from server startup,
11820 or after @command{trace point clear}) and count up from there.
11824 @node JTAG Commands
11825 @chapter JTAG Commands
11826 @cindex JTAG Commands
11827 Most general purpose JTAG commands have been presented earlier.
11828 (@xref{jtagspeed,,JTAG Speed}, @ref{Reset Configuration}, and @ref{TAP Declaration}.)
11829 Lower level JTAG commands, as presented here,
11830 may be needed to work with targets which require special
11831 attention during operations such as reset or initialization.
11833 To use these commands you will need to understand some
11834 of the basics of JTAG, including:
11837 @item A JTAG scan chain consists of a sequence of individual TAP
11838 devices such as a CPUs.
11839 @item Control operations involve moving each TAP through the same
11840 standard state machine (in parallel)
11841 using their shared TMS and clock signals.
11842 @item Data transfer involves shifting data through the chain of
11843 instruction or data registers of each TAP, writing new register values
11844 while the reading previous ones.
11845 @item Data register sizes are a function of the instruction active in
11846 a given TAP, while instruction register sizes are fixed for each TAP.
11847 All TAPs support a BYPASS instruction with a single bit data register.
11848 @item The way OpenOCD differentiates between TAP devices is by
11849 shifting different instructions into (and out of) their instruction
11853 @section Low Level JTAG Commands
11855 These commands are used by developers who need to access
11856 JTAG instruction or data registers, possibly controlling
11857 the order of TAP state transitions.
11858 If you're not debugging OpenOCD internals, or bringing up a
11859 new JTAG adapter or a new type of TAP device (like a CPU or
11860 JTAG router), you probably won't need to use these commands.
11861 In a debug session that doesn't use JTAG for its transport protocol,
11862 these commands are not available.
11864 @deffn {Command} {drscan} tap [numbits value]+ [@option{-endstate} tap_state]
11865 Loads the data register of @var{tap} with a series of bit fields
11866 that specify the entire register.
11867 Each field is @var{numbits} bits long with
11868 a numeric @var{value} (hexadecimal encouraged).
11869 The return value holds the original value of each
11872 For example, a 38 bit number might be specified as one
11873 field of 32 bits then one of 6 bits.
11874 @emph{For portability, never pass fields which are more
11875 than 32 bits long. Many OpenOCD implementations do not
11876 support 64-bit (or larger) integer values.}
11878 All TAPs other than @var{tap} must be in BYPASS mode.
11879 The single bit in their data registers does not matter.
11881 When @var{tap_state} is specified, the JTAG state machine is left
11883 For example @sc{drpause} might be specified, so that more
11884 instructions can be issued before re-entering the @sc{run/idle} state.
11885 If the end state is not specified, the @sc{run/idle} state is entered.
11888 OpenOCD does not record information about data register lengths,
11889 so @emph{it is important that you get the bit field lengths right}.
11890 Remember that different JTAG instructions refer to different
11891 data registers, which may have different lengths.
11892 Moreover, those lengths may not be fixed;
11893 the SCAN_N instruction can change the length of
11894 the register accessed by the INTEST instruction
11895 (by connecting a different scan chain).
11899 @deffn {Command} {flush_count}
11900 Returns the number of times the JTAG queue has been flushed.
11901 This may be used for performance tuning.
11903 For example, flushing a queue over USB involves a
11904 minimum latency, often several milliseconds, which does
11905 not change with the amount of data which is written.
11906 You may be able to identify performance problems by finding
11907 tasks which waste bandwidth by flushing small transfers too often,
11908 instead of batching them into larger operations.
11911 @deffn {Command} {irscan} [tap instruction]+ [@option{-endstate} tap_state]
11912 For each @var{tap} listed, loads the instruction register
11913 with its associated numeric @var{instruction}.
11914 (The number of bits in that instruction may be displayed
11915 using the @command{scan_chain} command.)
11916 For other TAPs, a BYPASS instruction is loaded.
11918 When @var{tap_state} is specified, the JTAG state machine is left
11920 For example @sc{irpause} might be specified, so the data register
11921 can be loaded before re-entering the @sc{run/idle} state.
11922 If the end state is not specified, the @sc{run/idle} state is entered.
11925 OpenOCD currently supports only a single field for instruction
11926 register values, unlike data register values.
11927 For TAPs where the instruction register length is more than 32 bits,
11928 portable scripts currently must issue only BYPASS instructions.
11932 @deffn {Command} {pathmove} start_state [next_state ...]
11933 Start by moving to @var{start_state}, which
11934 must be one of the @emph{stable} states.
11935 Unless it is the only state given, this will often be the
11936 current state, so that no TCK transitions are needed.
11937 Then, in a series of single state transitions
11938 (conforming to the JTAG state machine) shift to
11939 each @var{next_state} in sequence, one per TCK cycle.
11940 The final state must also be stable.
11943 @deffn {Command} {runtest} @var{num_cycles}
11944 Move to the @sc{run/idle} state, and execute at least
11945 @var{num_cycles} of the JTAG clock (TCK).
11946 Instructions often need some time
11947 to execute before they take effect.
11950 @c tms_sequence (short|long)
11951 @c ... temporary, debug-only, other than USBprog bug workaround...
11953 @deffn {Command} {verify_ircapture} (@option{enable}|@option{disable})
11954 Verify values captured during @sc{ircapture} and returned
11955 during IR scans. Default is enabled, but this can be
11956 overridden by @command{verify_jtag}.
11957 This flag is ignored when validating JTAG chain configuration.
11960 @deffn {Command} {verify_jtag} (@option{enable}|@option{disable})
11961 Enables verification of DR and IR scans, to help detect
11962 programming errors. For IR scans, @command{verify_ircapture}
11963 must also be enabled.
11964 Default is enabled.
11967 @section TAP state names
11968 @cindex TAP state names
11970 The @var{tap_state} names used by OpenOCD in the @command{drscan},
11971 @command{irscan}, and @command{pathmove} commands are the same
11972 as those used in SVF boundary scan documents, except that
11973 SVF uses @sc{idle} instead of @sc{run/idle}.
11976 @item @b{RESET} ... @emph{stable} (with TMS high);
11977 acts as if TRST were pulsed
11978 @item @b{RUN/IDLE} ... @emph{stable}; don't assume this always means IDLE
11980 @item @b{DRCAPTURE}
11981 @item @b{DRSHIFT} ... @emph{stable}; TDI/TDO shifting
11982 through the data register
11984 @item @b{DRPAUSE} ... @emph{stable}; data register ready
11985 for update or more shifting
11989 @item @b{IRCAPTURE}
11990 @item @b{IRSHIFT} ... @emph{stable}; TDI/TDO shifting
11991 through the instruction register
11993 @item @b{IRPAUSE} ... @emph{stable}; instruction register ready
11994 for update or more shifting
11999 Note that only six of those states are fully ``stable'' in the
12000 face of TMS fixed (low except for @sc{reset})
12001 and a free-running JTAG clock. For all the
12002 others, the next TCK transition changes to a new state.
12005 @item From @sc{drshift} and @sc{irshift}, clock transitions will
12006 produce side effects by changing register contents. The values
12007 to be latched in upcoming @sc{drupdate} or @sc{irupdate} states
12008 may not be as expected.
12009 @item @sc{run/idle}, @sc{drpause}, and @sc{irpause} are reasonable
12010 choices after @command{drscan} or @command{irscan} commands,
12011 since they are free of JTAG side effects.
12012 @item @sc{run/idle} may have side effects that appear at non-JTAG
12013 levels, such as advancing the ARM9E-S instruction pipeline.
12014 Consult the documentation for the TAP(s) you are working with.
12017 @node Boundary Scan Commands
12018 @chapter Boundary Scan Commands
12020 One of the original purposes of JTAG was to support
12021 boundary scan based hardware testing.
12022 Although its primary focus is to support On-Chip Debugging,
12023 OpenOCD also includes some boundary scan commands.
12025 @section SVF: Serial Vector Format
12026 @cindex Serial Vector Format
12029 The Serial Vector Format, better known as @dfn{SVF}, is a
12030 way to represent JTAG test patterns in text files.
12031 In a debug session using JTAG for its transport protocol,
12032 OpenOCD supports running such test files.
12034 @deffn {Command} {svf} @file{filename} [@option{-tap @var{tapname}}] [@option{-quiet}] @
12035 [@option{-nil}] [@option{-progress}] [@option{-ignore_error}] @
12036 [@option{-noreset}] [@option{-addcycles @var{cyclecount}}]
12037 This issues a JTAG reset (Test-Logic-Reset) and then
12038 runs the SVF script from @file{filename}.
12040 Arguments can be specified in any order; the optional dash doesn't
12041 affect their semantics.
12045 @item @option{-tap @var{tapname}} ignore IR and DR headers and footers
12046 specified by the SVF file with HIR, TIR, HDR and TDR commands;
12047 instead, calculate them automatically according to the current JTAG
12048 chain configuration, targeting @var{tapname};
12049 @item @option{-quiet} do not log every command before execution;
12050 @item @option{-nil} ``dry run'', i.e., do not perform any operations
12051 on the real interface;
12052 @item @option{-progress} enable progress indication;
12053 @item @option{-ignore_error} continue execution despite TDO check
12055 @item @option{-noreset} omit JTAG reset (Test-Logic-Reset) before executing
12056 content of the SVF file;
12057 @item @option{-addcycles @var{cyclecount}} inject @var{cyclecount} number of
12058 additional TCLK cycles after each SDR scan instruction;
12062 @section XSVF: Xilinx Serial Vector Format
12063 @cindex Xilinx Serial Vector Format
12066 The Xilinx Serial Vector Format, better known as @dfn{XSVF}, is a
12067 binary representation of SVF which is optimized for use with
12069 In a debug session using JTAG for its transport protocol,
12070 OpenOCD supports running such test files.
12072 @quotation Important
12073 Not all XSVF commands are supported.
12076 @deffn {Command} {xsvf} (tapname|@option{plain}) filename [@option{virt2}] [@option{quiet}]
12077 This issues a JTAG reset (Test-Logic-Reset) and then
12078 runs the XSVF script from @file{filename}.
12079 When a @var{tapname} is specified, the commands are directed at
12081 When @option{virt2} is specified, the @sc{xruntest} command counts
12082 are interpreted as TCK cycles instead of microseconds.
12083 Unless the @option{quiet} option is specified,
12084 messages are logged for comments and some retries.
12087 The OpenOCD sources also include two utility scripts
12088 for working with XSVF; they are not currently installed
12089 after building the software.
12090 You may find them useful:
12093 @item @emph{svf2xsvf} ... converts SVF files into the extended XSVF
12094 syntax understood by the @command{xsvf} command; see notes below.
12095 @item @emph{xsvfdump} ... converts XSVF files into a text output format;
12096 understands the OpenOCD extensions.
12099 The input format accepts a handful of non-standard extensions.
12100 These include three opcodes corresponding to SVF extensions
12101 from Lattice Semiconductor (LCOUNT, LDELAY, LDSR), and
12102 two opcodes supporting a more accurate translation of SVF
12103 (XTRST, XWAITSTATE).
12104 If @emph{xsvfdump} shows a file is using those opcodes, it
12105 probably will not be usable with other XSVF tools.
12108 @section IPDBG: JTAG-Host server
12109 @cindex IPDBG JTAG-Host server
12112 IPDBG is a set of tools to debug IP-Cores. It comprises, among others, a logic analyzer and an arbitrary
12113 waveform generator. These are synthesize-able hardware descriptions of
12114 logic circuits in addition to software for control, visualization and further analysis.
12115 In a session using JTAG for its transport protocol, OpenOCD supports the function
12116 of a JTAG-Host. The JTAG-Host is needed to connect the circuit over JTAG to the
12117 control-software. For more details see @url{http://ipdbg.org}.
12119 @deffn {Command} {ipdbg} [@option{-start|-stop}] @option{-tap @var{tapname}} @option{-hub @var{ir_value} [@var{dr_length}]} [@option{-vir [@var{vir_value} [@var{length} [@var{instr_code}]]]}] [@option{-port @var{number}}] [@option{-tool @var{number}}]
12120 Starts or stops a IPDBG JTAG-Host server. Arguments can be specified in any order.
12124 @item @option{-start|-stop} starts or stops a IPDBG JTAG-Host server (default: start).
12125 @item @option{-tap @var{tapname}} targeting the TAP @var{tapname}.
12126 @item @option{-hub @var{ir_value}} states that the JTAG hub is
12127 reachable with dr-scans while the JTAG instruction register has the value @var{ir_value}.
12128 @item @option{-port @var{number}} tcp port number where the JTAG-Host will listen. The default is 4242 which is used when the option is not given.
12129 @item @option{-tool @var{number}} number of the tool/feature. These corresponds to the ports "data_(up/down)_(0..6)" at the JtagHub. The default is 1 which is used when the option is not given.
12130 @item @option{-vir [@var{vir_value} [@var{length} [@var{instr_code}]]]} On some devices, the user data-register is reachable if there is a
12131 specific value in a second dr. This second dr is called vir (virtual ir). With this parameter given, the IPDBG satisfies this condition prior an
12132 access to the IPDBG-Hub. The value shifted into the vir is given by the first parameter @var{vir_value} (default: 0x11). The second
12133 parameter @var{length} is the length of the vir data register (default: 5). With the @var{instr_code} (default: 0x00e) parameter the ir value to
12134 shift data through vir can be configured.
12138 @deffn {Command} {ipdbg} [@option{-start|-stop}] @option{-pld @var{name} [@var{user}]} [@option{-port @var{number}}] [@option{-tool @var{number}}]
12139 Also starts or stops a IPDBG JTAG-Host server. The pld drivers are able to provide the tap and hub/IR for the IPDBG JTAG-Host server.
12140 With the @option{-pld @var{name} [@var{user}]} the information from the pld-driver is used and the options @option{-tap} and @option{-hub} are not required.
12141 The defined driver for the pld @var{name} gets selected. (The pld devices names can be shown by the command @command{pld devices}).
12143 The @verb{|USERx|} instructions are vendor specific and don't change between families of the same vendor.
12144 So if there's a pld driver for your vendor it should work with your FPGA even when the driver is not compatible with your device for the remaining features. If your device/vendor is not supported you have to use the previous command.
12146 With [@var{user}] one can select a different @verb{|USERx|}-Instruction. If the IPDBG JTAG-Hub is used without modification the default value of 1 which selects the first @verb{|USERx|} instruction is adequate.
12148 The remaining options are described in the previous command.
12153 ipdbg -start -tap xc6s.tap -hub 0x02 -port 4242 -tool 4
12155 Starts a server listening on tcp-port 4242 which connects to tool 4.
12156 The connection is through the TAP of a Xilinx Spartan 6 on USER1 instruction (tested with a papillion pro board).
12159 ipdbg -start -tap 10m50.tap -hub 0x00C -vir -port 60000 -tool 1
12161 Starts a server listening on tcp-port 60000 which connects to tool 1 (data_up_1/data_down_1).
12162 The connection is through the TAP of a Intel MAX10 virtual jtag component (sld_instance_index is 0; sld_ir_width is smaller than 5).
12165 ipdbg -start -pld xc7.pld -port 5555 -tool 0
12167 Starts a server listening on tcp-port 5555 which connects to tool 0 (data_up_0/data_down_0).
12168 The TAP and ir value used to reach the JTAG Hub is given by the pld driver.
12171 @node Utility Commands
12172 @chapter Utility Commands
12173 @cindex Utility Commands
12175 @section RAM testing
12176 @cindex RAM testing
12178 There is often a need to stress-test random access memory (RAM) for
12179 errors. OpenOCD comes with a Tcl implementation of well-known memory
12180 testing procedures allowing the detection of all sorts of issues with
12181 electrical wiring, defective chips, PCB layout and other common
12184 To use them, you usually need to initialise your RAM controller first;
12185 consult your SoC's documentation to get the recommended list of
12186 register operations and translate them to the corresponding
12187 @command{mww}/@command{mwb} commands.
12189 Load the memory testing functions with
12192 source [find tools/memtest.tcl]
12195 to get access to the following facilities:
12197 @deffn {Command} {memTestDataBus} address
12198 Test the data bus wiring in a memory region by performing a walking
12199 1's test at a fixed address within that region.
12202 @deffn {Command} {memTestAddressBus} baseaddress size
12203 Perform a walking 1's test on the relevant bits of the address and
12204 check for aliasing. This test will find single-bit address failures
12205 such as stuck-high, stuck-low, and shorted pins.
12208 @deffn {Command} {memTestDevice} baseaddress size
12209 Test the integrity of a physical memory device by performing an
12210 increment/decrement test over the entire region. In the process every
12211 storage bit in the device is tested as zero and as one.
12214 @deffn {Command} {runAllMemTests} baseaddress size
12215 Run all of the above tests over a specified memory region.
12218 @section Firmware recovery helpers
12219 @cindex Firmware recovery
12221 OpenOCD includes an easy-to-use script to facilitate mass-market
12222 devices recovery with JTAG.
12224 For quickstart instructions run:
12226 openocd -f tools/firmware-recovery.tcl -c firmware_help
12229 @node GDB and OpenOCD
12230 @chapter GDB and OpenOCD
12232 OpenOCD complies with the remote gdbserver protocol and, as such, can be used
12233 to debug remote targets.
12234 Setting up GDB to work with OpenOCD can involve several components:
12237 @item The OpenOCD server support for GDB may need to be configured.
12238 @xref{gdbconfiguration,,GDB Configuration}.
12239 @item GDB's support for OpenOCD may need configuration,
12240 as shown in this chapter.
12241 @item If you have a GUI environment like Eclipse,
12242 that also will probably need to be configured.
12245 Of course, the version of GDB you use will need to be one which has
12246 been built to know about the target CPU you're using. It's probably
12247 part of the tool chain you're using. For example, if you are doing
12248 cross-development for ARM on an x86 PC, instead of using the native
12249 x86 @command{gdb} command you might use @command{arm-none-eabi-gdb}
12250 if that's the tool chain used to compile your code.
12252 @section Connecting to GDB
12253 @cindex Connecting to GDB
12254 Use GDB 6.7 or newer with OpenOCD if you run into trouble. For
12255 instance GDB 6.3 has a known bug that produces bogus memory access
12256 errors, which has since been fixed; see
12257 @url{http://osdir.com/ml/gdb.bugs.discuss/2004-12/msg00018.html}
12259 OpenOCD can communicate with GDB in two ways:
12263 A socket (TCP/IP) connection is typically started as follows:
12265 target extended-remote localhost:3333
12267 This would cause GDB to connect to the gdbserver on the local pc using port 3333.
12269 The extended remote protocol is a super-set of the remote protocol and should
12270 be the preferred choice. More details are available in GDB documentation
12271 @url{https://sourceware.org/gdb/onlinedocs/gdb/Connecting.html}
12273 To speed-up typing, any GDB command can be abbreviated, including the extended
12274 remote command above that becomes:
12279 @b{Note:} If any backward compatibility issue requires using the old remote
12280 protocol in place of the extended remote one, the former protocol is still
12281 available through the command:
12283 target remote localhost:3333
12287 A pipe connection is typically started as follows:
12289 target extended-remote | \
12290 openocd -c "gdb_port pipe; log_output openocd.log"
12292 This would cause GDB to run OpenOCD and communicate using pipes (stdin/stdout).
12293 Using this method has the advantage of GDB starting/stopping OpenOCD for the debug
12294 session. log_output sends the log output to a file to ensure that the pipe is
12295 not saturated when using higher debug level outputs.
12298 To list the available OpenOCD commands type @command{monitor help} on the
12301 @section Sample GDB session startup
12303 With the remote protocol, GDB sessions start a little differently
12304 than they do when you're debugging locally.
12305 Here's an example showing how to start a debug session with a
12307 In this case the program was linked to be loaded into SRAM on a Cortex-M3.
12308 Most programs would be written into flash (address 0) and run from there.
12311 $ arm-none-eabi-gdb example.elf
12312 (gdb) target extended-remote localhost:3333
12313 Remote debugging using localhost:3333
12315 (gdb) monitor reset halt
12318 Loading section .vectors, size 0x100 lma 0x20000000
12319 Loading section .text, size 0x5a0 lma 0x20000100
12320 Loading section .data, size 0x18 lma 0x200006a0
12321 Start address 0x2000061c, load size 1720
12322 Transfer rate: 22 KB/sec, 573 bytes/write.
12328 You could then interrupt the GDB session to make the program break,
12329 type @command{where} to show the stack, @command{list} to show the
12330 code around the program counter, @command{step} through code,
12331 set breakpoints or watchpoints, and so on.
12333 @section Configuring GDB for OpenOCD
12335 OpenOCD supports the gdb @option{qSupported} packet, this enables information
12336 to be sent by the GDB remote server (i.e. OpenOCD) to GDB. Typical information includes
12337 packet size and the device's memory map.
12338 You do not need to configure the packet size by hand,
12339 and the relevant parts of the memory map should be automatically
12340 set up when you declare (NOR) flash banks.
12342 However, there are other things which GDB can't currently query.
12343 You may need to set those up by hand.
12344 As OpenOCD starts up, you will often see a line reporting
12348 Info : lm3s.cpu: hardware has 6 breakpoints, 4 watchpoints
12351 You can pass that information to GDB with these commands:
12354 set remote hardware-breakpoint-limit 6
12355 set remote hardware-watchpoint-limit 4
12358 With that particular hardware (Cortex-M3) the hardware breakpoints
12359 only work for code running from flash memory. Most other ARM systems
12360 do not have such restrictions.
12362 Rather than typing such commands interactively, you may prefer to
12363 save them in a file and have GDB execute them as it starts, perhaps
12364 using a @file{.gdbinit} in your project directory or starting GDB
12365 using @command{gdb -x filename}.
12367 @section Programming using GDB
12368 @cindex Programming using GDB
12369 @anchor{programmingusinggdb}
12371 By default the target memory map is sent to GDB. This can be disabled by
12372 the following OpenOCD configuration option:
12374 gdb_memory_map disable
12376 For this to function correctly a valid flash configuration must also be set
12377 in OpenOCD. For faster performance you should also configure a valid
12380 Informing GDB of the memory map of the target will enable GDB to protect any
12381 flash areas of the target and use hardware breakpoints by default. This means
12382 that the OpenOCD option @command{gdb_breakpoint_override} is not required when
12383 using a memory map. @xref{gdbbreakpointoverride,,gdb_breakpoint_override}.
12385 To view the configured memory map in GDB, use the GDB command @option{info mem}.
12386 All other unassigned addresses within GDB are treated as RAM.
12388 GDB 6.8 and higher set any memory area not in the memory map as inaccessible.
12389 This can be changed to the old behaviour by using the following GDB command
12391 set mem inaccessible-by-default off
12394 If @command{gdb_flash_program enable} is also used, GDB will be able to
12395 program any flash memory using the vFlash interface.
12397 GDB will look at the target memory map when a load command is given, if any
12398 areas to be programmed lie within the target flash area the vFlash packets
12401 If the target needs configuring before GDB programming, set target
12402 event gdb-flash-erase-start:
12404 $_TARGETNAME configure -event gdb-flash-erase-start BODY
12406 @xref{targetevents,,Target Events}, for other GDB programming related events.
12408 To verify any flash programming the GDB command @option{compare-sections}
12411 @section Using GDB as a non-intrusive memory inspector
12412 @cindex Using GDB as a non-intrusive memory inspector
12413 @anchor{gdbmeminspect}
12415 If your project controls more than a blinking LED, let's say a heavy industrial
12416 robot or an experimental nuclear reactor, stopping the controlling process
12417 just because you want to attach GDB is not a good option.
12419 OpenOCD does not support GDB non-stop mode (might be implemented in the future).
12420 Though there is a possible setup where the target does not get stopped
12421 and GDB treats it as it were running.
12422 If the target supports background access to memory while it is running,
12423 you can use GDB in this mode to inspect memory (mainly global variables)
12424 without any intrusion of the target process.
12426 Remove default setting of gdb-attach event. @xref{targetevents,,Target Events}.
12427 Place following command after target configuration:
12429 $_TARGETNAME configure -event gdb-attach @{@}
12432 If any of installed flash banks does not support probe on running target,
12433 switch off gdb_memory_map:
12435 gdb_memory_map disable
12438 Ensure GDB is configured without interrupt-on-connect.
12439 Some GDB versions set it by default, some does not.
12441 set remote interrupt-on-connect off
12444 If you switched gdb_memory_map off, you may want to setup GDB memory map
12445 manually or issue @command{set mem inaccessible-by-default off}
12447 Now you can issue GDB command @command{target extended-remote ...} and inspect memory
12448 of a running target. Do not use GDB commands @command{continue},
12449 @command{step} or @command{next} as they synchronize GDB with your target
12450 and GDB would require stopping the target to get the prompt back.
12452 Do not use this mode under an IDE like Eclipse as it caches values of
12453 previously shown variables.
12455 It's also possible to connect more than one GDB to the same target by the
12456 target's configuration option @code{-gdb-max-connections}. This allows, for
12457 example, one GDB to run a script that continuously polls a set of variables
12458 while other GDB can be used interactively. Be extremely careful in this case,
12459 because the two GDB can easily get out-of-sync.
12461 @section RTOS Support
12462 @cindex RTOS Support
12463 @anchor{gdbrtossupport}
12465 OpenOCD includes RTOS support, this will however need enabling as it defaults to disabled.
12466 It can be enabled by passing @option{-rtos} arg to the target. @xref{rtostype,,RTOS Type}.
12468 @xref{Threads, Debugging Programs with Multiple Threads,
12469 Debugging Programs with Multiple Threads, gdb, GDB manual}, for details about relevant
12472 @* An example setup is below:
12475 $_TARGETNAME configure -rtos auto
12478 This will attempt to auto detect the RTOS within your application.
12480 Currently supported rtos's include:
12482 @item @option{eCos}
12483 @item @option{ThreadX}
12484 @item @option{FreeRTOS}
12485 @item @option{linux}
12486 @item @option{ChibiOS}
12487 @item @option{embKernel}
12489 @item @option{uCOS-III}
12490 @item @option{nuttx}
12491 @item @option{RIOT}
12492 @item @option{hwthread} (This is not an actual RTOS. @xref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.)
12493 @item @option{Zephyr}
12494 @item @option{rtkernel}
12497 At any time, it's possible to drop the selected RTOS using:
12499 $_TARGETNAME configure -rtos none
12502 Before an RTOS can be detected, it must export certain symbols; otherwise, it cannot
12503 be used by OpenOCD. Below is a list of the required symbols for each supported RTOS.
12507 Cyg_Thread::thread_list, Cyg_Scheduler_Base::current_thread.
12508 @item ThreadX symbols
12509 _tx_thread_current_ptr, _tx_thread_created_ptr, _tx_thread_created_count.
12510 @item FreeRTOS symbols
12512 pxCurrentTCB, pxReadyTasksLists, xDelayedTaskList1, xDelayedTaskList2,
12513 pxDelayedTaskList, pxOverflowDelayedTaskList, xPendingReadyList,
12514 uxCurrentNumberOfTasks, uxTopUsedPriority, xSchedulerRunning.
12516 @item linux symbols
12518 @item ChibiOS symbols
12519 rlist, ch_debug, chSysInit.
12520 @item embKernel symbols
12521 Rtos::sCurrentTask, Rtos::sListReady, Rtos::sListSleep,
12522 Rtos::sListSuspended, Rtos::sMaxPriorities, Rtos::sCurrentTaskCount.
12524 _mqx_kernel_data, MQX_init_struct.
12525 @item uC/OS-III symbols
12526 OSRunning, OSTCBCurPtr, OSTaskDbgListPtr, OSTaskQty.
12527 @item nuttx symbols
12528 g_readytorun, g_tasklisttable.
12531 sched_threads, sched_num_threads, sched_active_pid, max_threads,
12534 @item Zephyr symbols
12535 _kernel, _kernel_openocd_offsets, _kernel_openocd_size_t_size
12536 @item rtkernel symbols
12537 Multiple struct offsets.
12540 For most RTOS supported the above symbols will be exported by default. However for
12541 some, eg. FreeRTOS, uC/OS-III and Zephyr, extra steps must be taken.
12543 Zephyr must be compiled with the DEBUG_THREAD_INFO option. This will generate some symbols
12544 with information needed in order to build the list of threads.
12546 FreeRTOS and uC/OS-III RTOSes may require additional OpenOCD-specific file to be linked
12547 along with the project:
12551 contrib/rtos-helpers/FreeRTOS-openocd.c
12553 contrib/rtos-helpers/uCOS-III-openocd.c
12556 @anchor{usingopenocdsmpwithgdb}
12557 @section Using OpenOCD SMP with GDB
12561 OpenOCD includes a pseudo RTOS called @emph{hwthread} that presents CPU cores
12562 ("hardware threads") in an SMP system as threads to GDB. With this extension,
12563 GDB can be used to inspect the state of an SMP system in a natural way.
12564 After halting the system, using the GDB command @command{info threads} will
12565 list the context of each active CPU core in the system. GDB's @command{thread}
12566 command can be used to switch the view to a different CPU core.
12567 The @command{step} and @command{stepi} commands can be used to step a specific core
12568 while other cores are free-running or remain halted, depending on the
12569 scheduler-locking mode configured in GDB.
12571 @node Tcl Scripting API
12572 @chapter Tcl Scripting API
12573 @cindex Tcl Scripting API
12574 @cindex Tcl scripts
12577 Tcl commands are stateless; e.g. the @command{telnet} command has
12578 a concept of currently active target, the Tcl API proc's take this sort
12579 of state information as an argument to each proc.
12581 There are three main types of return values: single value, name value
12582 pair list and lists.
12584 Name value pair. The proc 'foo' below returns a name/value pair
12588 > set foo(me) Duane
12589 > set foo(you) Oyvind
12590 > set foo(mouse) Micky
12591 > set foo(duck) Donald
12603 me Duane you Oyvind mouse Micky duck Donald
12606 Thus, to get the names of the associative array is easy:
12609 foreach { name value } [set foo] {
12610 puts "Name: $name, Value: $value"
12614 Lists returned should be relatively small. Otherwise, a range
12615 should be passed in to the proc in question.
12617 @section Internal low-level Commands
12619 By "low-level", we mean commands that a human would typically not
12623 @item @b{flash banks} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}> <@var{target}> [@option{driver options} ...]
12625 Return information about the flash banks
12627 @item @b{capture} <@var{command}>
12629 Run <@var{command}> and return full log output that was produced during
12630 its execution together with the command output. Example:
12633 > capture "reset init"
12638 OpenOCD commands can consist of two words, e.g. "flash banks". The
12639 @file{startup.tcl} "unknown" proc will translate this into a Tcl proc
12640 called "flash_banks".
12642 @section Tcl RPC server
12645 OpenOCD provides a simple RPC server that allows to run arbitrary Tcl
12646 commands and receive the results.
12648 To access it, your application needs to connect to a configured TCP port
12649 (see @command{tcl_port}). Then it can pass any string to the
12650 interpreter terminating it with @code{0x1a} and wait for the return
12651 value (it will be terminated with @code{0x1a} as well). This can be
12652 repeated as many times as desired without reopening the connection.
12654 It is not needed anymore to prefix the OpenOCD commands with
12655 @code{ocd_} to get the results back. But sometimes you might need the
12656 @command{capture} command.
12658 See @file{contrib/rpc_examples/} for specific client implementations.
12660 @section Tcl RPC server notifications
12661 @cindex RPC Notifications
12663 Notifications are sent asynchronously to other commands being executed over
12664 the RPC server, so the port must be polled continuously.
12666 Target event, state and reset notifications are emitted as Tcl associative arrays
12667 in the following format.
12670 type target_event event [event-name]
12671 type target_state state [state-name]
12672 type target_reset mode [reset-mode]
12675 @deffn {Command} {tcl_notifications} [on/off]
12676 Toggle output of target notifications to the current Tcl RPC server.
12677 Only available from the Tcl RPC server.
12682 @section Tcl RPC server trace output
12683 @cindex RPC trace output
12685 Trace data is sent asynchronously to other commands being executed over
12686 the RPC server, so the port must be polled continuously.
12688 Target trace data is emitted as a Tcl associative array in the following format.
12691 type target_trace data [trace-data-hex-encoded]
12694 @deffn {Command} {tcl_trace} [on/off]
12695 Toggle output of target trace data to the current Tcl RPC server.
12696 Only available from the Tcl RPC server.
12699 See an example application here:
12700 @url{https://github.com/apmorton/OpenOcdTraceUtil} [OpenOcdTraceUtil]
12709 @item @b{RTCK, also known as: Adaptive Clocking - What is it?}
12711 @cindex adaptive clocking
12714 In digital circuit design it is often referred to as ``clock
12715 synchronisation'' the JTAG interface uses one clock (TCK or TCLK)
12716 operating at some speed, your CPU target is operating at another.
12717 The two clocks are not synchronised, they are ``asynchronous''
12719 In order for the two to work together they must be synchronised
12720 well enough to work; JTAG can't go ten times faster than the CPU,
12721 for example. There are 2 basic options:
12724 Use a special "adaptive clocking" circuit to change the JTAG
12725 clock rate to match what the CPU currently supports.
12727 The JTAG clock must be fixed at some speed that's enough slower than
12728 the CPU clock that all TMS and TDI transitions can be detected.
12731 @b{Does this really matter?} For some chips and some situations, this
12732 is a non-issue, like a 500MHz ARM926 with a 5 MHz JTAG link;
12733 the CPU has no difficulty keeping up with JTAG.
12734 Startup sequences are often problematic though, as are other
12735 situations where the CPU clock rate changes (perhaps to save
12738 For example, Atmel AT91SAM chips start operation from reset with
12739 a 32kHz system clock. Boot firmware may activate the main oscillator
12740 and PLL before switching to a faster clock (perhaps that 500 MHz
12742 If you're using JTAG to debug that startup sequence, you must slow
12743 the JTAG clock to sometimes 1 to 4kHz. After startup completes,
12744 JTAG can use a faster clock.
12746 Consider also debugging a 500MHz ARM926 hand held battery powered
12747 device that enters a low power ``deep sleep'' mode, at 32kHz CPU
12748 clock, between keystrokes unless it has work to do. When would
12749 that 5 MHz JTAG clock be usable?
12751 @b{Solution #1 - A special circuit}
12753 In order to make use of this,
12754 your CPU, board, and JTAG adapter must all support the RTCK
12755 feature. Not all of them support this; keep reading!
12757 The RTCK ("Return TCK") signal in some ARM chips is used to help with
12758 this problem. ARM has a good description of the problem described at
12759 this link: @url{http://www.arm.com/support/faqdev/4170.html} [checked
12760 28/nov/2008]. Link title: ``How does the JTAG synchronisation logic
12761 work? / how does adaptive clocking work?''.
12763 The nice thing about adaptive clocking is that ``battery powered hand
12764 held device example'' - the adaptiveness works perfectly all the
12765 time. One can set a break point or halt the system in the deep power
12766 down code, slow step out until the system speeds up.
12768 Note that adaptive clocking may also need to work at the board level,
12769 when a board-level scan chain has multiple chips.
12770 Parallel clock voting schemes are good way to implement this,
12771 both within and between chips, and can easily be implemented
12773 It's not difficult to have logic fan a module's input TCK signal out
12774 to each TAP in the scan chain, and then wait until each TAP's RTCK comes
12775 back with the right polarity before changing the output RTCK signal.
12776 Texas Instruments makes some clock voting logic available
12777 for free (with no support) in VHDL form; see
12778 @url{http://tiexpressdsp.com/index.php/Adaptive_Clocking}
12780 @b{Solution #2 - Always works - but may be slower}
12782 Often this is a perfectly acceptable solution.
12784 In most simple terms: Often the JTAG clock must be 1/10 to 1/12 of
12785 the target clock speed. But what that ``magic division'' is varies
12786 depending on the chips on your board.
12787 @b{ARM rule of thumb} Most ARM based systems require an 6:1 division;
12788 ARM11 cores use an 8:1 division.
12789 @b{Xilinx rule of thumb} is 1/12 the clock speed.
12791 Note: most full speed FT2232 based JTAG adapters are limited to a
12792 maximum of 6MHz. The ones using USB high speed chips (FT2232H)
12793 often support faster clock rates (and adaptive clocking).
12795 You can still debug the 'low power' situations - you just need to
12796 either use a fixed and very slow JTAG clock rate ... or else
12797 manually adjust the clock speed at every step. (Adjusting is painful
12798 and tedious, and is not always practical.)
12800 It is however easy to ``code your way around it'' - i.e.: Cheat a little,
12801 have a special debug mode in your application that does a ``high power
12802 sleep''. If you are careful - 98% of your problems can be debugged
12805 Note that on ARM you may need to avoid using the @emph{wait for interrupt}
12806 operation in your idle loops even if you don't otherwise change the CPU
12808 That operation gates the CPU clock, and thus the JTAG clock; which
12809 prevents JTAG access. One consequence is not being able to @command{halt}
12810 cores which are executing that @emph{wait for interrupt} operation.
12812 To set the JTAG frequency use the command:
12815 # Example: 1.234MHz
12820 @item @b{Win32 Pathnames} Why don't backslashes work in Windows paths?
12822 OpenOCD uses Tcl and a backslash is an escape char. Use @{ and @}
12823 around Windows filenames.
12836 @item @b{Missing: cygwin1.dll} OpenOCD complains about a missing cygwin1.dll.
12838 Make sure you have Cygwin installed, or at least a version of OpenOCD that
12839 claims to come with all the necessary DLLs. When using Cygwin, try launching
12840 OpenOCD from the Cygwin shell.
12842 @item @b{Breakpoint Issue} I'm trying to set a breakpoint using GDB (or a front-end like Insight or
12843 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
12844 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
12846 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
12847 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720T or ARM920T,
12848 software breakpoints consume one of the two available hardware breakpoints.
12850 @item @b{LPC2000 Flash} When erasing or writing LPC2000 on-chip flash, the operation fails at random.
12852 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
12853 clock at the time you're programming the flash. If you've specified the crystal's
12854 frequency, make sure the PLL is disabled. If you've specified the full core speed
12855 (e.g. 60MHz), make sure the PLL is enabled.
12857 @item @b{Amontec Chameleon} When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
12858 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
12859 out while waiting for end of scan, rtck was disabled".
12861 Make sure your PC's parallel port operates in EPP mode. You might have to try several
12862 settings in your PC BIOS (ECP, EPP, and different versions of those).
12864 @item @b{Data Aborts} When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
12865 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
12866 memory read caused data abort".
12868 The errors are non-fatal, and are the result of GDB trying to trace stack frames
12869 beyond the last valid frame. It might be possible to prevent this by setting up
12870 a proper "initial" stack frame, if you happen to know what exactly has to
12871 be done, feel free to add this here.
12873 @b{Simple:} In your startup code - push 8 registers of zeros onto the
12874 stack before calling main(). What GDB is doing is ``climbing'' the run
12875 time stack by reading various values on the stack using the standard
12876 call frame for the target. GDB keeps going - until one of 2 things
12877 happen @b{#1} an invalid frame is found, or @b{#2} some huge number of
12878 stackframes have been processed. By pushing zeros on the stack, GDB
12881 @b{Debugging Interrupt Service Routines} - In your ISR before you call
12882 your C code, do the same - artificially push some zeros onto the stack,
12883 remember to pop them off when the ISR is done.
12885 @b{Also note:} If you have a multi-threaded operating system, they
12886 often do not @b{in the interest of saving memory} waste these few
12890 @item @b{JTAG Reset Config} I get the following message in the OpenOCD console (or log file):
12891 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
12893 This warning doesn't indicate any serious problem, as long as you don't want to
12894 debug your core right out of reset. Your .cfg file specified @option{reset_config
12895 trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
12896 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
12897 independently. With this setup, it's not possible to halt the core right out of
12898 reset, everything else should work fine.
12900 @item @b{USB Power} When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
12901 toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
12902 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
12903 quit with an error message. Is there a stability issue with OpenOCD?
12905 No, this is not a stability issue concerning OpenOCD. Most users have solved
12906 this issue by simply using a self-powered USB hub, which they connect their
12907 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
12908 supply stable enough for the Amontec JTAGkey to be operated.
12910 @b{Laptops running on battery have this problem too...}
12912 @item @b{GDB Disconnects} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
12913 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
12914 What does that mean and what might be the reason for this?
12916 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
12917 has closed the connection to OpenOCD. This might be a GDB issue.
12919 @item @b{LPC2000 Flash} In the configuration file in the section where flash device configurations
12920 are described, there is a parameter for specifying the clock frequency
12921 for LPC2000 internal flash devices (e.g. @option{flash bank $_FLASHNAME lpc2000
12922 0x0 0x40000 0 0 $_TARGETNAME lpc2000_v1 14746 calc_checksum}), which must be
12923 specified in kilohertz. However, I do have a quartz crystal of a
12924 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz,
12925 i.e. 14,745.600 kHz). Is it possible to specify real numbers for the
12928 No. The clock frequency specified here must be given as an integral number.
12929 However, this clock frequency is used by the In-Application-Programming (IAP)
12930 routines of the LPC2000 family only, which seems to be very tolerant concerning
12931 the given clock frequency, so a slight difference between the specified clock
12932 frequency and the actual clock frequency will not cause any trouble.
12934 @item @b{Command Order} Do I have to keep a specific order for the commands in the configuration file?
12936 Well, yes and no. Commands can be given in arbitrary order, yet the
12937 devices listed for the JTAG scan chain must be given in the right
12938 order (jtag newdevice), with the device closest to the TDO-Pin being
12939 listed first. In general, whenever objects of the same type exist
12940 which require an index number, then these objects must be given in the
12941 right order (jtag newtap, targets and flash banks - a target
12942 references a jtag newtap and a flash bank references a target).
12944 You can use the ``scan_chain'' command to verify and display the tap order.
12946 Also, some commands can't execute until after @command{init} has been
12947 processed. Such commands include @command{nand probe} and everything
12948 else that needs to write to controller registers, perhaps for setting
12949 up DRAM and loading it with code.
12951 @anchor{faqtaporder}
12952 @item @b{JTAG TAP Order} Do I have to declare the TAPS in some
12955 Yes; whenever you have more than one, you must declare them in
12956 the same order used by the hardware.
12958 Many newer devices have multiple JTAG TAPs. For example:
12959 STMicroelectronics STM32 chips have two TAPs, a ``boundary scan TAP'' and
12960 ``Cortex-M3'' TAP. Example: The STM32 reference manual, Document ID:
12961 RM0008, Section 26.5, Figure 259, page 651/681, the ``TDI'' pin is
12962 connected to the boundary scan TAP, which then connects to the
12963 Cortex-M3 TAP, which then connects to the TDO pin.
12965 Thus, the proper order for the STM32 chip is: (1) The Cortex-M3, then
12966 (2) The boundary scan TAP. If your board includes an additional JTAG
12967 chip in the scan chain (for example a Xilinx CPLD or FPGA) you could
12968 place it before or after the STM32 chip in the chain. For example:
12971 @item OpenOCD_TDI(output) -> STM32 TDI Pin (BS Input)
12972 @item STM32 BS TDO (output) -> STM32 Cortex-M3 TDI (input)
12973 @item STM32 Cortex-M3 TDO (output) -> SM32 TDO Pin
12974 @item STM32 TDO Pin (output) -> Xilinx TDI Pin (input)
12975 @item Xilinx TDO Pin -> OpenOCD TDO (input)
12978 The ``jtag device'' commands would thus be in the order shown below. Note:
12981 @item jtag newtap Xilinx tap -irlen ...
12982 @item jtag newtap stm32 cpu -irlen ...
12983 @item jtag newtap stm32 bs -irlen ...
12984 @item # Create the debug target and say where it is
12985 @item target create stm32.cpu -chain-position stm32.cpu ...
12989 @item @b{SYSCOMP} Sometimes my debugging session terminates with an error. When I look into the
12990 log file, I can see these error messages: Error: arm7_9_common.c:561
12991 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP
12997 @node Tcl Crash Course
12998 @chapter Tcl Crash Course
13001 Not everyone knows Tcl - this is not intended to be a replacement for
13002 learning Tcl, the intent of this chapter is to give you some idea of
13003 how the Tcl scripts work.
13005 This chapter is written with two audiences in mind. (1) OpenOCD users
13006 who need to understand a bit more of how Jim-Tcl works so they can do
13007 something useful, and (2) those that want to add a new command to
13010 @section Tcl Rule #1
13011 There is a famous joke, it goes like this:
13013 @item Rule #1: The wife is always correct
13014 @item Rule #2: If you think otherwise, See Rule #1
13017 The Tcl equal is this:
13020 @item Rule #1: Everything is a string
13021 @item Rule #2: If you think otherwise, See Rule #1
13024 As in the famous joke, the consequences of Rule #1 are profound. Once
13025 you understand Rule #1, you will understand Tcl.
13027 @section Tcl Rule #1b
13028 There is a second pair of rules.
13030 @item Rule #1: Control flow does not exist. Only commands
13031 @* For example: the classic FOR loop or IF statement is not a control
13032 flow item, they are commands, there is no such thing as control flow
13034 @item Rule #2: If you think otherwise, See Rule #1
13035 @* Actually what happens is this: There are commands that by
13036 convention, act like control flow key words in other languages. One of
13037 those commands is the word ``for'', another command is ``if''.
13040 @section Per Rule #1 - All Results are strings
13041 Every Tcl command results in a string. The word ``result'' is used
13042 deliberately. No result is just an empty string. Remember: @i{Rule #1 -
13043 Everything is a string}
13045 @section Tcl Quoting Operators
13046 In life of a Tcl script, there are two important periods of time, the
13047 difference is subtle.
13050 @item Evaluation Time
13053 The two key items here are how ``quoted things'' work in Tcl. Tcl has
13054 three primary quoting constructs, the [square-brackets] the
13055 @{curly-braces@} and ``double-quotes''
13057 By now you should know $VARIABLES always start with a $DOLLAR
13058 sign. BTW: To set a variable, you actually use the command ``set'', as
13059 in ``set VARNAME VALUE'' much like the ancient BASIC language ``let x
13060 = 1'' statement, but without the equal sign.
13063 @item @b{[square-brackets]}
13064 @* @b{[square-brackets]} are command substitutions. It operates much
13065 like Unix Shell `back-ticks`. The result of a [square-bracket]
13066 operation is exactly 1 string. @i{Remember Rule #1 - Everything is a
13067 string}. These two statements are roughly identical:
13071 echo "The Date is: $X"
13074 puts "The Date is: $X"
13076 @item @b{``double-quoted-things''}
13077 @* @b{``double-quoted-things''} are just simply quoted
13078 text. $VARIABLES and [square-brackets] are expanded in place - the
13079 result however is exactly 1 string. @i{Remember Rule #1 - Everything
13083 puts "It is now \"[date]\", $x is in 1 hour"
13085 @item @b{@{Curly-Braces@}}
13086 @*@b{@{Curly-Braces@}} are magic: $VARIABLES and [square-brackets] are
13087 parsed, but are NOT expanded or executed. @{Curly-Braces@} are like
13088 'single-quote' operators in BASH shell scripts, with the added
13089 feature: @{curly-braces@} can be nested, single quotes can not. @{@{@{this is
13090 nested 3 times@}@}@} NOTE: [date] is a bad example;
13091 at this writing, Jim/OpenOCD does not have a date command.
13094 @section Consequences of Rule 1/2/3/4
13096 The consequences of Rule 1 are profound.
13098 @subsection Tokenisation & Execution.
13100 Of course, whitespace, blank lines and #comment lines are handled in
13103 As a script is parsed, each (multi) line in the script file is
13104 tokenised and according to the quoting rules. After tokenisation, that
13105 line is immediately executed.
13107 Multi line statements end with one or more ``still-open''
13108 @{curly-braces@} which - eventually - closes a few lines later.
13110 @subsection Command Execution
13112 Remember earlier: There are no ``control flow''
13113 statements in Tcl. Instead there are COMMANDS that simply act like
13114 control flow operators.
13116 Commands are executed like this:
13119 @item Parse the next line into (argc) and (argv[]).
13120 @item Look up (argv[0]) in a table and call its function.
13121 @item Repeat until End Of File.
13124 It sort of works like this:
13127 ReadAndParse( &argc, &argv );
13129 cmdPtr = LookupCommand( argv[0] );
13131 (*cmdPtr->Execute)( argc, argv );
13135 When the command ``proc'' is parsed (which creates a procedure
13136 function) it gets 3 parameters on the command line. @b{1} the name of
13137 the proc (function), @b{2} the list of parameters, and @b{3} the body
13138 of the function. Note the choice of words: LIST and BODY. The PROC
13139 command stores these items in a table somewhere so it can be found by
13140 ``LookupCommand()''
13142 @subsection The FOR command
13144 The most interesting command to look at is the FOR command. In Tcl,
13145 the FOR command is normally implemented in C. Remember, FOR is a
13146 command just like any other command.
13148 When the ascii text containing the FOR command is parsed, the parser
13149 produces 5 parameter strings, @i{(If in doubt: Refer to Rule #1)} they
13153 @item The ascii text 'for'
13154 @item The start text
13155 @item The test expression
13156 @item The next text
13157 @item The body text
13160 Sort of reminds you of ``main( int argc, char **argv )'' does it not?
13161 Remember @i{Rule #1 - Everything is a string.} The key point is this:
13162 Often many of those parameters are in @{curly-braces@} - thus the
13163 variables inside are not expanded or replaced until later.
13165 Remember that every Tcl command looks like the classic ``main( argc,
13166 argv )'' function in C. In JimTCL - they actually look like this:
13170 MyCommand( Jim_Interp *interp,
13172 Jim_Obj * const *argvs );
13175 Real Tcl is nearly identical. Although the newer versions have
13176 introduced a byte-code parser and interpreter, but at the core, it
13177 still operates in the same basic way.
13179 @subsection FOR command implementation
13181 To understand Tcl it is perhaps most helpful to see the FOR
13182 command. Remember, it is a COMMAND not a control flow structure.
13184 In Tcl there are two underlying C helper functions.
13186 Remember Rule #1 - You are a string.
13188 The @b{first} helper parses and executes commands found in an ascii
13189 string. Commands can be separated by semicolons, or newlines. While
13190 parsing, variables are expanded via the quoting rules.
13192 The @b{second} helper evaluates an ascii string as a numerical
13193 expression and returns a value.
13195 Here is an example of how the @b{FOR} command could be
13196 implemented. The pseudo code below does not show error handling.
13198 void Execute_AsciiString( void *interp, const char *string );
13200 int Evaluate_AsciiExpression( void *interp, const char *string );
13203 MyForCommand( void *interp,
13208 SetResult( interp, "WRONG number of parameters");
13212 // argv[0] = the ascii string just like C
13214 // Execute the start statement.
13215 Execute_AsciiString( interp, argv[1] );
13217 // Top of loop test
13219 i = Evaluate_AsciiExpression(interp, argv[2]);
13223 // Execute the body
13224 Execute_AsciiString( interp, argv[3] );
13226 // Execute the LOOP part
13227 Execute_AsciiString( interp, argv[4] );
13231 SetResult( interp, "" );
13236 Every other command IF, WHILE, FORMAT, PUTS, EXPR, everything works
13237 in the same basic way.
13239 @section OpenOCD Tcl Usage
13241 @subsection source and find commands
13242 @b{Where:} In many configuration files
13243 @* Example: @b{ source [find FILENAME] }
13244 @*Remember the parsing rules
13246 @item The @command{find} command is in square brackets,
13247 and is executed with the parameter FILENAME. It should find and return
13248 the full path to a file with that name; it uses an internal search path.
13249 The RESULT is a string, which is substituted into the command line in
13250 place of the bracketed @command{find} command.
13251 (Don't try to use a FILENAME which includes the "#" character.
13252 That character begins Tcl comments.)
13253 @item The @command{source} command is executed with the resulting filename;
13254 it reads a file and executes as a script.
13256 @subsection format command
13257 @b{Where:} Generally occurs in numerous places.
13258 @* Tcl has no command like @b{printf()}, instead it has @b{format}, which is really more like
13264 puts [format "The answer: %d" [expr @{$x * $y@}]]
13267 @item The SET command creates 2 variables, X and Y.
13268 @item The double [nested] EXPR command performs math
13269 @* The EXPR command produces numerical result as a string.
13270 @* Refer to Rule #1
13271 @item The format command is executed, producing a single string
13272 @* Refer to Rule #1.
13273 @item The PUTS command outputs the text.
13275 @subsection Body or Inlined Text
13276 @b{Where:} Various TARGET scripts.
13279 proc someproc @{@} @{
13280 ... multiple lines of stuff ...
13282 $_TARGETNAME configure -event FOO someproc
13283 #2 Good - no variables
13284 $_TARGETNAME configure -event foo "this ; that;"
13285 #3 Good Curly Braces
13286 $_TARGETNAME configure -event FOO @{
13287 puts "Time: [date]"
13289 #4 DANGER DANGER DANGER
13290 $_TARGETNAME configure -event foo "puts \"Time: [date]\""
13293 @item The $_TARGETNAME is an OpenOCD variable convention.
13294 @*@b{$_TARGETNAME} represents the last target created, the value changes
13295 each time a new target is created. Remember the parsing rules. When
13296 the ascii text is parsed, the @b{$_TARGETNAME} becomes a simple string,
13297 the name of the target which happens to be a TARGET (object)
13299 @item The 2nd parameter to the @option{-event} parameter is a TCBODY
13300 @*There are 4 examples:
13302 @item The TCLBODY is a simple string that happens to be a proc name
13303 @item The TCLBODY is several simple commands separated by semicolons
13304 @item The TCLBODY is a multi-line @{curly-brace@} quoted string
13305 @item The TCLBODY is a string with variables that get expanded.
13308 In the end, when the target event FOO occurs the TCLBODY is
13309 evaluated. Method @b{#1} and @b{#2} are functionally identical. For
13310 Method @b{#3} and @b{#4} it is more interesting. What is the TCLBODY?
13312 Remember the parsing rules. In case #3, @{curly-braces@} mean the
13313 $VARS and [square-brackets] are expanded later, when the EVENT occurs,
13314 and the text is evaluated. In case #4, they are replaced before the
13315 ``Target Object Command'' is executed. This occurs at the same time
13316 $_TARGETNAME is replaced. In case #4 the date will never
13317 change. @{BTW: [date] is a bad example; at this writing,
13318 Jim/OpenOCD does not have a date command@}
13320 @subsection Global Variables
13321 @b{Where:} You might discover this when writing your own procs @* In
13322 simple terms: Inside a PROC, if you need to access a global variable
13323 you must say so. See also ``upvar''. Example:
13325 proc myproc @{ @} @{
13326 set y 0 #Local variable Y
13327 global x #Global variable X
13328 puts [format "X=%d, Y=%d" $x $y]
13331 @section Other Tcl Hacks
13332 @b{Dynamic variable creation}
13334 # Dynamically create a bunch of variables.
13335 for @{ set x 0 @} @{ $x < 32 @} @{ set x [expr @{$x + 1@}]@} @{
13337 set vn [format "BIT%d" $x]
13341 set $vn [expr @{1 << $x@}]
13344 @b{Dynamic proc/command creation}
13346 # One "X" function - 5 uart functions.
13347 foreach who @{A B C D E@}
13348 proc [format "show_uart%c" $who] @{ @} "show_UARTx $who"
13353 @appendix The GNU Free Documentation License.
13356 @node OpenOCD Concept Index
13357 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
13358 @comment case issue with ``Index.html'' and ``index.html''
13359 @comment Occurs when creating ``--html --no-split'' output
13360 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
13361 @unnumbered OpenOCD Concept Index
13365 @node Command and Driver Index
13366 @unnumbered Command and Driver Index