1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle Open On-Chip Debugger (openocd)
10 @title Open On-Chip Debugger (openocd)
11 @subtitle Edition @value{EDITION} for openocd version @value{VERSION}
12 @subtitle @value{UPDATED}
14 @vskip 0pt plus 1filll
19 @node Top, About, , (dir)
22 This is edition @value{EDITION} of the openocd manual for version
23 @value{VERSION}, @value{UPDATED}
26 * About:: About Openocd.
28 * Building:: Building Openocd
29 * Running:: Running Openocd
30 * Configuration:: Openocd Configuration.
31 * Commands:: Openocd Commands
32 * Sample Scripts:: Sample Target Scripts
33 * GDB and Openocd:: Using GDB and Openocd
34 * FAQ:: Frequently Asked Questions
35 * License:: GNU Free Documentation License
43 The Open On-Chip Debugger (openocd) aims to provide debugging, in-system programming
44 and boundary-scan testing for embedded target devices. The targets are interfaced
45 using JTAG (IEEE 1149.1) compliant hardware, but this may be extended to other
46 connection types in the future.
48 Openocd currently supports Wiggler (clones), FTDI FT2232 based JTAG interfaces, the
49 Amontec JTAG Accelerator, and the Gateworks GW1602. It allows ARM7 (ARM7TDMI and ARM720t),
50 ARM9 (ARM920t, ARM922t, ARM926ej--s, ARM966e--s), XScale (PXA25x, IXP42x) and
51 Cortex-M3 (Luminary Stellaris LM3 and ST STM32) based cores to be debugged.
53 Flash writing is supported for external CFI compatible flashes (Intel and AMD/Spansion
54 command set) and several internal flashes (LPC2000, AT91SAM7, STR7x, STR9x, LM3
55 and STM32x). Preliminary support for using the LPC3180's NAND flash controller is included.
61 Openocd has been created by Dominic Rath as part of a diploma thesis written at the
62 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
63 Others interested in improving the state of free and open debug and testing technology
64 are welcome to participate.
66 Other developers have contributed support for additional targets and flashes as well
67 as numerous bugfixes and enhancements. See the AUTHORS file for regular contributors.
71 @cindex building openocd
73 You can download the current SVN version with SVN client of your choice from the
74 following repositories:
76 (@uref{svn://svn.berlios.de/openocd/trunk})
80 (@uref{http://svn.berlios.de/svnroot/repos/openocd/trunk})
82 Using the SVN command line client, you could use the following command to fetch the
83 latest version (make sure there is no (non-svn) directory called "openocd" in the
87 svn checkout svn://svn.berlios.de/openocd/trunk
90 Building the OpenOCD requires a recent version of the GNU autotools.
91 On my build system, I'm using autoconf 2.13 and automake 1.9. For building on Windows,
92 you have to use Cygwin. Make sure that your @env{PATH} environment variable contains no
93 other locations with Unix utils (like UnxUtils) - these can't handle the Cygwin
94 paths, resulting in obscure dependency errors (This is an observation I've gathered
95 from the logs of one user - correct me if I'm wrong).
97 You further need the appropriate driver files, if you want to build support for
98 a FTDI FT2232 based interface:
100 @item @b{ftdi2232} libftdi (@uref{http://www.intra2net.com/opensource/ftdi/})
101 @item @b{ftd2xx} libftd2xx (@uref{http://www.ftdichip.com/Drivers/D2XX.htm})
102 @item When using the Amontec JTAGkey, you have to get the drivers from the Amontec
103 homepage (@uref{www.amontec.com}), as the JTAGkey uses a non-standard VID/PID.
106 Please note that the ftdi2232 variant (using libftdi) isn't supported under Cygwin.
107 You have to use the ftd2xx variant (using FTDI's D2XX) on Cygwin.
109 In general, the D2XX driver provides superior performance (several times as fast),
110 but has the draw-back of being binary-only - though that isn't as worse, as it isn't
111 a kernel module, only a user space library.
113 To build OpenOCD (on both Linux and Cygwin), use the following commands:
117 Bootstrap generates the configure script, and prepares building on your system.
121 Configure generates the Makefiles used to build OpenOCD
125 Make builds the OpenOCD, and places the final executable in ./src/
127 The configure script takes several options, specifying which JTAG interfaces
134 --enable-parport_ppdev
136 --enable-amtjtagaccel
138 --enable-ft2232_ftd2xx
139 @footnote{Using the latest D2XX drivers from FTDI and following their installation
140 instructions, I had to use @option{--enable-ft2232_libftd2xx} for the OpenOCD to
143 --enable-ft2232_libftdi
145 --with-ftd2xx=/path/to/d2xx/
148 If you want to access the parallel port using the PPDEV interface you have to specify
149 both the @option{--enable-parport} AND the @option{--enable-parport_ppdev} option since
150 the @option{--enable-parport_ppdev} option actually is an option to the parport driver
151 (see @uref{http://forum.sparkfun.com/viewtopic.php?t=3795} for more info).
153 Cygwin users have to specify the location of the FTDI D2XX package. This should be an
154 absolute path containing no spaces.
156 Linux users should copy the various parts of the D2XX package to the appropriate
157 locations, i.e. /usr/include, /usr/lib.
161 @cindex running openocd
163 @cindex --debug_level
166 The OpenOCD runs as a daemon, waiting for connections from clients (Telnet or GDB).
167 Run with @option{--help} or @option{-h} to view the available command line arguments.
169 It reads its configuration by default from the file openocd.cfg located in the current
170 working directory. This may be overwritten with the @option{-f <configfile>} command line
173 To enable debug output (when reporting problems or working on OpenOCD itself), use
174 the @option{-d} command line switch. This sets the debug_level to "3", outputting
175 the most information, including debug messages. The default setting is "2", outputting
176 only informational messages, warnings and errors. You can also change this setting
177 from within a telnet or gdb session (@option{debug_level <n>}).
179 You can redirect all output from the daemon to a file using the @option{-l <logfile>} switch.
181 Search paths for config/script files can be added to openocd by using
182 the @option{-s <search>} switch.
185 @chapter Configuration
186 @cindex configuration
187 The Open On-Chip Debugger (OpenOCD) runs as a daemon, and reads it current configuration
188 by default from the file openocd.cfg in the current directory. A different configuration
189 file can be specified with the @option{-f <conf.file>} given at the openocd command line.
191 The configuration file is used to specify on which ports the daemon listens for new
192 connections, the JTAG interface used to connect to the target, the layout of the JTAG
193 chain, the targets that should be debugged, and connected flashes.
195 @section Daemon configuration
198 @item @b{telnet_port} <@var{number}>
200 Port on which to listen for incoming telnet connections
201 @item @b{gdb_port} <@var{number}>
203 First port on which to listen for incoming GDB connections. The GDB port for the
204 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
205 @item @b{gdb_detach} <@var{resume|reset|halt|nothing}>
207 Configures what openocd will do when gdb detaches from the daeman.
208 Default behaviour is <@var{resume}>
209 @item @b{gdb_memory_map} <@var{enable|disable}>
210 @cindex gdb_memory_map
211 Set to <@var{enable}> so that openocd will send the memory configuration to gdb when
212 requested. gdb will then know when to set hardware breakpoints, and program flash
213 using the gdb load command. @option{gdb_flash_program enable} will also need enabling
214 for flash programming to work.
215 Default behaviour is <@var{disable}>
216 @item @b{gdb_flash_program} <@var{enable|disable}>
217 @cindex gdb_flash_program
218 Set to <@var{enable}> so that openocd will program the flash memory when a
219 vFlash packet is received.
220 Default behaviour is <@var{disable}>
221 @item @b{daemon_startup} <@var{mode}> either @samp{attach} or @samp{reset}
222 @cindex daemon_startup
223 Tells the OpenOCD whether it should reset the target when the daemon is launched, or
224 if it should just attach to the target.
227 @section JTAG interface configuration
230 @item @b{interface} <@var{name}>
232 Use the interface driver <@var{name}> to connect to the target. Currently supported
236 PC parallel port bit-banging (Wigglers, PLD download cable, ...)
240 Amontec Chameleon in its JTAG Accelerator configuration connected to a PC's EPP
245 FTDI FT2232 based devices using either the open-source libftdi or the binary only
246 FTD2XX driver. The FTD2XX is superior in performance, but not available on every
247 platform. The libftdi uses libusb, and should be portable to all systems that provide
252 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
257 @item @b{jtag_speed} <@var{number}>
259 Limit the maximum speed of the JTAG interface. Usually, a value of zero means maximum
260 speed. The actual effect of this option depends on the JTAG interface used.
263 @item wiggler: maximum speed / @var{number}
264 @item ft2232: 6MHz / (@var{number}+1)
265 @item amt jtagaccel: 8 / 2**@var{number}
268 Note: Make sure the jtag clock is no more than @math{1/6th × CPU-Clock}. This is
269 especially true for synthesized cores (-S).
271 @item @b{reset_config} <@var{signals}> [@var{combination}] [@var{trst_type}] [@var{srst_type}]
273 The configuration of the reset signals available on the JTAG interface AND the target.
274 If the JTAG interface provides SRST, but the target doesn't connect that signal properly,
275 then OpenOCD can't use it. <@var{signals}> can be @samp{none}, @samp{trst_only},
276 @samp{srst_only} or @samp{trst_and_srst}.
277 [@var{combination}] is an optional value specifying broken reset signal implementations.
278 @samp{srst_pulls_trst} states that the testlogic is reset together with the reset of
279 the system (e.g. Philips LPC2000, "broken" board layout), @samp{trst_pulls_srst} says
280 that the system is reset together with the test logic (only hypothetical, I haven't
281 seen hardware with such a bug, and can be worked around).
283 The [@var{trst_type}] and [@var{srst_type}] parameters allow the driver type of the
284 reset lines to be specified. Possible values are @samp{trst_push_pull} (default)
285 and @samp{trst_open_drain} for the test reset signal, and @samp{srst_open_drain}
286 (default) and @samp{srst_push_pull} for the system reset. These values only affect
287 JTAG interfaces with support for different drivers, like the Amontec JTAGkey and JTAGAccelerator.
289 @item @b{jtag_device} <@var{IR length}> <@var{IR capture}> <@var{IR mask}> <@var{IDCODE instruction}>
291 Describes the devices that form the JTAG daisy chain, with the first device being
292 the one closest to TDO. The parameters are the length of the instruction register
293 (4 for all ARM7/9s), the value captured during Capture-IR (0x1 for ARM7/9), and a mask
294 of bits that should be validated when doing IR scans (all four bits (0xf) for ARM7/9).
295 The IDCODE instruction will in future be used to query devices for their JTAG
296 identification code. This line is the same for all ARM7 and ARM9 devices.
297 Other devices, like CPLDs, require different parameters. An example configuration
298 line for a Xilinx XC9500 CPLD would look like this:
300 jtag_device 8 0x01 0x0e3 0xfe
302 The instruction register (IR) is 8 bits long, during Capture-IR 0x01 is loaded into
303 the IR, but only bits 0-1 and 5-7 should be checked, the others (2-4) might vary.
304 The IDCODE instruction is 0xfe.
306 @item @b{jtag_nsrst_delay} <@var{ms}>
307 @cindex jtag_nsrst_delay
308 How long (in miliseconds) the OpenOCD should wait after deasserting nSRST before
309 starting new JTAG operations.
310 @item @b{jtag_ntrst_delay} <@var{ms}>
311 @cindex jtag_ntrst_delay
312 How long (in miliseconds) the OpenOCD should wait after deasserting nTRST before
313 starting new JTAG operations.
315 The jtag_n[st]rst_delay options are useful if reset circuitry (like a reset supervisor,
316 or on-chip features) keep a reset line asserted for some time after the external reset
320 @section parport options
323 @item @b{parport_port} <@var{number}>
325 Either the address of the I/O port (default: 0x378 for LPT1) or the number of
326 the @file{/dev/parport} device
328 When using PPDEV to access the parallel port, use the number of the parallel port:
329 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
330 you may encounter a problem.
331 @item @b{parport_cable} <@var{name}>
332 @cindex parport_cable
333 The layout of the parallel port cable used to connect to the target.
334 Currently supported cables are
338 Original Wiggler layout, also supported by several clones, such
339 as the Olimex ARM-JTAG
340 @item old_amt_wiggler
341 @cindex old_amt_wiggler
342 The Wiggler configuration that comes with Amontec's Chameleon Programmer. The new
343 version available from the website uses the original Wiggler layout ('@var{wiggler}')
346 Describes the connection of the Amontec Chameleon's CPLD when operated in
347 configuration mode. This is only used to program the Chameleon itself, not
351 Xilinx Parallel cable III.
354 The parallel port adapter found on the 'Karo Triton 1 Development Board'.
355 This is also the layout used by the HollyGates design
356 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
361 @item @b{parport_write_on_exit} <@var{on|off}>
362 @cindex parport_write_on_exit
363 This will configure the parallel driver to write a known value to the parallel
364 interface on exiting openocd
367 @section amt_jtagaccel options
369 @item @b{parport_port} <@var{number}>
371 Either the address of the I/O port (default: 0x378 for LPT1) or the number of the
372 @file{/dev/parport} device
374 @section ft2232 options
377 @item @b{ft2232_device_desc} <@var{description}>
378 @cindex ft2232_device_desc
379 The USB device description of the FTDI FT2232 device. If not specified, the FTDI
380 default value is used. This setting is only valid if compiled with FTD2XX support.
381 @item @b{ft2232_layout} <@var{name}>
382 @cindex ft2232_layout
383 The layout of the FT2232 GPIO signals used to control output-enables and reset
384 signals. Valid layouts are
387 The "USBJTAG-1" layout described in the original OpenOCD diploma thesis
389 Amontec JTAGkey and JTAGkey-tiny
395 American Microsystems M5960
397 Luminary Micro EVB_LM3S811 as a JTAG interface (not onboard processor), no TRST or
398 SRST signals on external connector
402 Hitex STM32 Performance Stick
404 Tin Can Tools Flyswatter
406 egnite Software turtelizer2
411 @item @b{ft2232_vid_pid} <@var{vid}> <@var{pid}>
412 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
413 default values are used. This command is not available on Windows.
414 @item @b{ft2232_latency} <@var{ms}>
415 On some systems using ft2232 based JTAG interfaces the FT_Read function call in
416 ft2232_read() fails to return the expected number of bytes. This can be caused by
417 USB communication delays and has proved hard to reproduce and debug. Setting the
418 FT2232 latency timer to a larger value increases delays for short USB packages but it
419 also reduces the risk of timeouts before receiving the expected number of bytes.
420 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
423 @section ep93xx options
424 @cindex ep93xx options
425 Currently, there are no options available for the ep93xx interface.
428 @section Target configuration
431 @item @b{target} <@var{type}> <@var{endianess}> <@var{reset_mode}> <@var{JTAG pos}>
434 Defines a target that should be debugged. Currently supported types are:
448 If you want to use a target board that is not on this list, see Adding a new
451 Endianess may be @option{little} or @option{big}.
453 The reset_mode specifies what should happen to the target when a reset occurs:
457 Immediately request a target halt after reset. This allows targets to be debugged
458 from the very first instruction. This is only possible with targets and JTAG
459 interfaces that correctly implement the reset signals.
462 Similar to @option{reset_halt}, but executes the script file defined to handle the
463 'reset' event for the target. Like @option{reset_halt} this only works with
464 correct reset implementations.
467 Simply let the target run after a reset.
470 Let the target run for some time (default: 1s), and then request halt.
473 A combination of @option{reset_init} and @option{run_and_halt}. The target is allowed
474 to run for some time, then halted, and the @option{reset} event script is executed.
477 On JTAG interfaces / targets where system reset and test-logic reset can't be driven
478 completely independent (like the LPC2000 series), or where the JTAG interface is
479 unavailable for some time during startup (like the STR7 series), you can't use
480 @option{reset_halt} or @option{reset_init}.
482 @item @b{target_script} <@var{target#}> <@var{event}> <@var{script_file}>
483 @cindex target_script
484 Event is either @option{reset}, @option{post_halt}, @option{pre_resume} or @option{gdb_program_config}
486 TODO: describe exact semantic of events
487 @item @b{run_and_halt_time} <@var{target#}> <@var{time_in_ms}>
488 @cindex run_and_halt_time
489 The amount of time the debugger should wait after releasing reset before it asserts
490 a debug request. This is used by the @option{run_and_halt} and @option{run_and_init}
492 @item @b{working_area} <@var{target#}> <@var{address}> <@var{size}>
493 <@var{backup}|@var{nobackup}>
495 Specifies a working area for the debugger to use. This may be used to speed-up
496 downloads to target memory and flash operations, or to perform otherwise unavailable
497 operations (some coprocessor operations on ARM7/9 systems, for example). The last
498 parameter decides whether the memory should be preserved <@var{backup}>. If possible, use
499 a working_area that doesn't need to be backed up, as that slows down operation.
502 @subsection arm7tdmi options
503 @cindex arm7tdmi options
504 target arm7tdmi <@var{endianess}> <@var{reset_mode}> <@var{jtag#}>
505 The arm7tdmi target definition requires at least one additional argument, specifying
506 the position of the target in the JTAG daisy-chain. The first JTAG device is number 0.
507 The optional [@var{variant}] parameter has been removed in recent versions.
508 The correct feature set is determined at runtime.
510 @subsection arm720t options
511 @cindex arm720t options
512 ARM720t options are similar to ARM7TDMI options.
514 @subsection arm9tdmi options
515 @cindex arm9tdmi options
516 ARM9TDMI options are similar to ARM7TDMI options. Supported variants are
517 @option{arm920t}, @option{arm922t} and @option{arm940t}.
518 This enables the hardware single-stepping support found on these cores.
520 @subsection arm920t options
521 @cindex arm920t options
522 ARM920t options are similar to ARM9TDMI options.
524 @subsection arm966e options
525 @cindex arm966e options
526 ARM966e options are similar to ARM9TDMI options.
528 @subsection xscale options
529 @cindex xscale options
530 Supported variants are @option{ixp42x}, @option{ixp45x}, @option{ixp46x},
531 @option{pxa250}, @option{pxa255}, @option{pxa26x}.
533 @section Flash configuration
534 @cindex Flash configuration
537 @item @b{flash bank} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}>
538 <@var{bus_width}> <@var{target#}> [@var{driver_options ...}]
540 Configures a flash bank at <@var{base}> of <@var{size}> bytes and <@var{chip_width}>
541 and <@var{bus_width}> bytes using the selected flash <driver>.
543 @item @b{flash auto_erase} <@option{on}|@option{off}>
544 @cindex flash auto_erase
545 auto erase flash banks prior to writing. Currently only works when using
546 @option{flash write_image} command. Default is @option{off}.
549 @subsection lpc2000 options
550 @cindex lpc2000 options
552 @b{flash bank lpc2000} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
553 <@var{clock}> [@var{calc_checksum}]
554 LPC flashes don't require the chip and bus width to be specified. Additional
555 parameters are the <@var{variant}>, which may be @var{lpc2000_v1} (older LPC21xx and LPC22xx)
556 or @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx), the number
557 of the target this flash belongs to (first is 0), the frequency at which the core
558 is currently running (in kHz - must be an integral number), and the optional keyword
559 @var{calc_checksum}, telling the driver to calculate a valid checksum for the exception
562 @subsection cfi options
565 @b{flash bank cfi} <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}>
567 CFI flashes require the number of the target they're connected to as an additional
568 argument. The CFI driver makes use of a working area (specified for the target)
569 to significantly speed up operation.
571 @var{chip_width} and @var{bus_width} are specified in bytes.
573 @subsection at91sam7 options
574 @cindex at91sam7 options
576 @b{flash bank at91sam7} 0 0 0 0 <@var{target#}>
577 AT91SAM7 flashes only require the @var{target#}, all other values are looked up after
578 reading the chip-id and type.
580 @subsection str7 options
583 @b{flash bank str7x} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
584 variant can be either STR71x, STR73x or STR75x.
586 @subsection str9 options
589 @b{flash bank str9x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
590 The str9 needs the flash controller to be configured prior to Flash programming, eg.
592 str9x flash_config 0 4 2 0 0x80000
594 This will setup the BBSR, NBBSR, BBADR and NBBADR registers respectively.
596 @subsection str9 options (str9xpec driver)
598 @b{flash bank str9xpec} <@var{base}> <@var{size}> 0 0 <@var{target#}>
599 Before using the flash commands the turbo mode will need enabling using str9xpec
600 @option{enable_turbo} <@var{num>.}
602 Only use this driver for locking/unlocking the device or configuring the option bytes.
603 Use the standard str9 driver for programming.
605 @subsection stellaris (LM3Sxxx) options
606 @cindex stellaris (LM3Sxxx) options
608 @b{flash bank stellaris} <@var{base}> <@var{size}> 0 0 <@var{target#}>
609 stellaris flash plugin only require the @var{target#}.
611 @subsection stm32x options
612 @cindex stm32x options
614 @b{flash bank stm32x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
615 stm32x flash plugin only require the @var{target#}.
621 The Open On-Chip Debugger (OpenOCD) allows user interaction through a telnet interface
622 (default: port 4444) and a GDB server (default: port 3333). The command line interpreter
623 is available from both the telnet interface and a GDB session. To issue commands to the
624 interpreter from within a GDB session, use the @option{monitor} command, e.g. use
625 @option{monitor poll} to issue the @option{poll} command. All output is relayed through the
631 @item @b{sleep} <@var{msec}>
633 Wait for n milliseconds before resuming. Useful in connection with script files
634 (@var{script} command and @var{target_script} configuration).
638 Close the OpenOCD daemon, disconnecting all clients (GDB, Telnet).
640 @item @b{debug_level} [@var{n}]
642 Display or adjust debug level to n<0-3>
644 @item @b{log_output} <@var{file}>
646 Redirect logging to <file> (default: stderr)
648 @item @b{script} <@var{file}>
650 Execute commands from <file>
654 @subsection Target state handling
656 @item @b{poll} [@option{on}|@option{off}]
658 Poll the target for its current state. If the target is in debug mode, architecture
659 specific information about the current state are printed. An optional parameter
660 allows continuous polling to be enabled and disabled.
662 @item @b{halt} [@option{ms}]
664 Send a halt request to the target and waits for it to halt for [@option{ms}].
665 Default [@option{ms}] is 5 seconds if no arg given.
666 Optional arg @option{ms} is a timeout in milliseconds. Using 0 as the [@option{ms}]
667 will stop openocd from waiting.
669 @item @b{wait_halt} [@option{ms}]
671 Wait for the target to enter debug mode. Optional [@option{ms}] is
672 a timeout in milliseconds. Default [@option{ms}] is 5 seconds if no
675 @item @b{resume} [@var{address}]
677 Resume the target at its current code position, or at an optional address.
678 Openocd will wait 5 seconds for the target to resume.
680 @item @b{step} [@var{address}]
682 Single-step the target at its current code position, or at an optional address.
684 @item @b{reset} [@option{run}|@option{halt}|@option{init}|@option{run_and_halt}
685 |@option{run_and_init}]
687 Do a hard-reset. The optional parameter specifies what should happen after the reset.
688 This optional parameter overwrites the setting specified in the configuration file,
689 making the new behaviour the default for the @option{reset} command.
696 Immediately halt the target (works only with certain configurations).
699 Immediately halt the target, and execute the reset script (works only with certain
702 @cindex reset run_and_halt
703 Let the target run for a certain amount of time, then request a halt.
705 @cindex reset run_and_init
706 Let the target run for a certain amount of time, then request a halt. Execute the
707 reset script once the target entered debug mode.
711 @subsection Memory access commands
712 These commands allow accesses of a specific size to the memory system:
714 @item @b{mdw} <@var{addr}> [@var{count}]
717 @item @b{mdh} <@var{addr}> [@var{count}]
719 display memory half-words
720 @item @b{mdb} <@var{addr}> [@var{count}]
723 @item @b{mww} <@var{addr}> <@var{value}>
726 @item @b{mwh} <@var{addr}> <@var{value}>
728 write memory half-word
729 @item @b{mwb} <@var{addr}> <@var{value}>
733 @item @b{load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
735 Load image <@var{file}> to target memory at <@var{address}>
736 @item @b{dump_image} <@var{file}> <@var{address}> <@var{size}>
738 Dump <@var{size}> bytes of target memory starting at <@var{address}> to a
739 (binary) <@var{file}>.
740 @item @b{verify_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
742 Verify <@var{file}> to target memory starting at <@var{address}>.
743 This will first attempt using a crc checksum, if this fails it will try a binary compare.
744 @item @b{load_binary} <@var{file}> <@var{address}> [DEPRECATED]
746 Load binary <@var{file}> to target memory at <@var{address}>
747 @item @b{dump_binary} <@var{file}> <@var{address}> <@var{size}> [DEPRECATED]
749 Dump <@var{size}> bytes of target memory starting at <@var{address}> to a
750 (binary) <@var{file}>.
753 @subsection Flash commands
754 @cindex Flash commands
756 @item @b{flash banks}
758 List configured flash banks
759 @item @b{flash info} <@var{num}>
761 Print info about flash bank <@option{num}>
762 @item @b{flash probe} <@var{num}>
764 Identify the flash, or validate the parameters of the configured flash. Operation
765 depends on the flash type.
766 @item @b{flash erase_check} <@var{num}>
767 @cindex flash erase_check
768 Check erase state of sectors in flash bank <@var{num}>. This is the only operation that
769 updates the erase state information displayed by @option{flash info}. That means you have
770 to issue an @option{erase_check} command after erasing or programming the device to get
772 @item @b{flash protect_check} <@var{num}>
773 @cindex flash protect_check
774 Check protection state of sectors in flash bank <num>.
776 @item @b{flash erase} <@var{num}> <@var{first}> <@var{last}> [DEPRECATED]
778 Erase sectors at bank <@var{num}>, starting at sector <@var{first}> up to and including
779 <@var{last}>. Sector numbering starts at 0. Depending on the flash type, erasing might
780 require the protection to be disabled first (e.g. Intel Advanced Bootblock flash using
781 the CFI driver). This command was replaced by the new command
782 @option{flash erase_sector} using the same syntax.
783 @item @b{flash erase_sector} <@var{num}> <@var{first}> <@var{last}>
784 @cindex flash erase_sector
785 Erase sectors at bank <@var{num}>, starting at sector <@var{first}> up to and including
786 <@var{last}>. Sector numbering starts at 0. Depending on the flash type, erasing might
787 require the protection to be disabled first (e.g. Intel Advanced Bootblock flash using
789 @item @b{flash erase_address} <@var{address}> <@var{length}>
790 @cindex flash erase_address
791 Erase sectors starting at <@var{address}> for <@var{length}> number of bytes
792 @item @b{flash write} <@var{num}> <@var{file}> <@var{offset}> [DEPRECATED]
794 Write the binary <@var{file}> to flash bank <@var{num}>, starting at <@var{offset}>
795 bytes from the beginning of the bank. This command was replaced by the new command
796 @option{flash write_binary} using the same syntax.
797 @item @b{flash write_binary} <@var{num}> <@var{file}> <@var{offset}>
798 @cindex flash write_binary
799 Write the binary <@var{file}> to flash bank <@var{num}>, starting at
800 <@option{offset}> bytes from the beginning of the bank.
801 @item @b{flash write_image} <@var{file}> [@var{offset}] [@var{type}]
802 @cindex flash write_image
803 Write the image <@var{file}> to the current target's flash bank(s). A relocation
804 [@var{offset}] can be specified and the file [@var{type}] can be specified
805 explicitly as @option{bin} (binary), @option{ihex} (Intel hex), @option{elf}
806 (ELF file) or @option{s19} (Motorola s19).
807 @item @b{flash protect} <@var{num}> <@var{first}> <@var{last}> <@option{on}|@option{off}>
808 @cindex flash protect
809 Enable (@var{on}) or disable (@var{off}) protection of flash sectors <@var{first}> to
810 <@var{last}> of @option{flash bank} <@var{num}>.
811 @item @b{flash auto_erase} <@var{on}|@var{off}>
812 @cindex flash auto_erase
813 Enable (@option{on}) to erase flash banks prior to writing using the flash @option{write_image} command
814 only. Default is (@option{off}), flash banks have to be erased using @option{flash erase} command.
818 @section Target Specific Commands
819 @cindex Target Specific Commands
821 @subsection AT91SAM7 specific commands
822 @cindex AT91SAM7 specific commands
823 The flash configuration is deduced from the chip identification register. The flash
824 controller handles erases automatically on a page (128/265 byte) basis so erase is
825 not necessary for flash programming. AT91SAM7 processors with less than 512K flash
826 only have a single flash bank embedded on chip. AT91SAM7xx512 have two flash planes
827 that can be erased separatly.Only an EraseAll command is supported by the controller
828 for each flash plane and this is called with
830 @item @b{flash erase} <@var{num}> @var{first_plane} @var{last_plane}
831 bulk erase flash planes first_plane to last_plane.
832 @item @b{at91sam7 gpnvm} <@var{num}> <@var{bit}> <@option{set}|@option{clear}>
833 @cindex at91sam7 gpnvm
834 set or clear a gpnvm bit for the processor
837 @subsection STR9 specific commands
838 @cindex STR9 specific commands
839 These are flash specific commands when using the str9xpec driver.
841 @item @b{str9xpec enable_turbo} <@var{num}>
842 @cindex str9xpec enable_turbo
843 enable turbo mode, simply this will remove the str9 from the chain and talk
844 directly to the embedded flash controller.
845 @item @b{str9xpec disable_turbo} <@var{num}>
846 @cindex str9xpec disable_turbo
847 restore the str9 into jtag chain.
848 @item @b{str9xpec lock} <@var{num}>
849 @cindex str9xpec lock
850 lock str9 device. The str9 will only respond to an unlock command that will
852 @item @b{str9xpec unlock} <@var{num}>
853 @cindex str9xpec unlock
855 @item @b{str9xpec options_read} <@var{num}>
856 @cindex str9xpec options_read
857 read str9 option bytes.
858 @item @b{str9xpec options_write} <@var{num}>
859 @cindex str9xpec options_write
860 write str9 option bytes.
863 @subsection STR9 configuration
864 @cindex STR9 configuration
866 @item @b{str9x flash_config} <@var{bank}> <@var{BBSR}> <@var{NBBSR}>
867 <@var{BBADR}> <@var{NBBADR}>
868 @cindex str9x flash_config
869 Configure str9 flash controller.
871 eg. str9x flash_config 0 4 2 0 0x80000
873 BBSR - Boot Bank Size register
874 NBBSR - Non Boot Bank Size register
875 BBADR - Boot Bank Start Address register
876 NBBADR - Boot Bank Start Address register
880 @subsection STR9 option byte configuration
881 @cindex STR9 option byte configuration
883 @item @b{str9xpec options_cmap} <@var{num}> <@option{bank0}|@option{bank1}>
884 @cindex str9xpec options_cmap
885 configure str9 boot bank.
886 @item @b{str9xpec options_lvdthd} <@var{num}> <@option{2.4v}|@option{2.7v}>
887 @cindex str9xpec options_lvdthd
888 configure str9 lvd threshold.
889 @item @b{str9xpec options_lvdsel} <@var{num}> <@option{vdd}|@option{vdd_vddq}>
890 @cindex str9xpec options_lvdsel
891 configure str9 lvd source.
892 @item @b{str9xpec options_lvdwarn} <@var{bank}> <@option{vdd}|@option{vdd_vddq}>
893 @cindex str9xpec options_lvdwarn
894 configure str9 lvd reset warning source.
897 @subsection STM32x specific commands
898 @cindex STM32x specific commands
900 These are flash specific commands when using the stm32x driver.
902 @item @b{stm32x lock} <@var{num}>
905 @item @b{stm32x unlock} <@var{num}>
906 @cindex stm32x unlock
908 @item @b{stm32x options_read} <@var{num}>
909 @cindex stm32x options_read
910 read stm32 option bytes.
911 @item @b{stm32x options_write} <@var{num}> <@option{SWWDG}|@option{HWWDG}>
912 <@option{RSTSTNDBY}|@option{NORSTSTNDBY}> <@option{RSTSTOP}|@option{NORSTSTOP}>
913 @cindex stm32x options_write
914 write stm32 option bytes.
915 @item @b{stm32x mass_erase} <@var{num}>
916 @cindex stm32x mass_erase
917 mass erase flash memory.
921 @section Architecture Specific Commands
922 @cindex Architecture Specific Commands
924 @subsection ARMV4/5 specific commands
925 @cindex ARMV4/5 specific commands
927 These commands are specific to ARM architecture v4 and v5, like all ARM7/9 systems
928 or Intel XScale (XScale isn't supported yet).
930 @item @b{armv4_5 reg}
932 Display a list of all banked core registers, fetching the current value from every
933 core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
935 @item @b{armv4_5 core_mode} [@option{arm}|@option{thumb}]
936 @cindex armv4_5 core_mode
937 Displays the core_mode, optionally changing it to either ARM or Thumb mode.
938 The target is resumed in the currently set @option{core_mode}.
941 @subsection ARM7/9 specific commands
942 @cindex ARM7/9 specific commands
944 These commands are specific to ARM7 and ARM9 targets, like ARM7TDMI, ARM720t,
945 ARM920t or ARM926EJ-S.
947 @item @b{arm7_9 sw_bkpts} <@option{enable}|@option{disable}>
948 @cindex arm7_9 sw_bkpts
949 Enable/disable use of software breakpoints. On ARMv4 systems, this reserves
950 one of the watchpoint registers to implement software breakpoints. Disabling
951 SW Bkpts frees that register again.
952 @item @b{arm7_9 force_hw_bkpts} <@option{enable}|@option{disable}>
953 @cindex arm7_9 force_hw_bkpts
954 When @option{force_hw_bkpts} is enabled, the @option{sw_bkpts} support is disabled, and all
955 breakpoints are turned into hardware breakpoints.
956 @item @b{arm7_9 dbgrq} <@option{enable}|@option{disable}>
958 Enable use of the DBGRQ bit to force entry into debug mode. This should be
959 safe for all but ARM7TDMI--S cores (like Philips LPC).
960 @item @b{arm7_9 fast_writes} <@option{enable}|@option{disable}>
961 @cindex arm7_9 fast_writes [DEPRECATED]
962 See @option{arm7_9 fast_memory_access} instead.
963 @item @b{arm7_9 fast_memory_access} <@option{enable}|@option{disable}>
964 @cindex arm7_9 fast_memory_access
965 Allow the OpenOCD to read and write memory without checking completion of
966 the operation. This provides a huge speed increase, especially with USB JTAG
967 cables (FT2232), but might be unsafe if used with targets running at a very low
968 speed, like the 32kHz startup clock of an AT91RM9200.
969 @item @b{arm7_9 dcc_downloads} <@option{enable}|@option{disable}>
970 @cindex arm7_9 dcc_downloads
971 Enable the use of the debug communications channel (DCC) to write larger (>128 byte)
972 amounts of memory. DCC downloads offer a huge speed increase, but might be potentially
973 unsafe, especially with targets running at a very low speed. This command was introduced
974 with OpenOCD rev. 60.
977 @subsection ARM920T specific commands
978 @cindex ARM920T specific commands
981 @item @b{arm920t cache_info}
982 @cindex arm920t cache_info
983 Print information about the caches found. This allows you to see if your target
984 is a ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
985 @item @b{arm920t md<bhw>_phys} <@var{addr}> [@var{count}]
986 @cindex arm920t md<bhw>_phys
987 Display memory at physical address addr.
988 @item @b{arm920t mw<bhw>_phys} <@var{addr}> <@var{value}>
989 @cindex arm920t mw<bhw>_phys
990 Write memory at physical address addr.
991 @item @b{arm920t read_cache} <@var{filename}>
992 @cindex arm920t read_cache
993 Dump the content of ICache and DCache to a file.
994 @item @b{arm920t read_mmu} <@var{filename}>
995 @cindex arm920t read_mmu
996 Dump the content of the ITLB and DTLB to a file.
997 @item @b{arm920t virt2phys} <@var{VA}>
998 @cindex arm920t virt2phys
999 Translate a virtual address to a physical address.
1003 @section Debug commands
1004 @cindex Debug commands
1005 The following commands give direct access to the core, and are most likely
1006 only useful while debugging the OpenOCD.
1008 @item @b{arm7_9 write_xpsr} <@var{32-bit value}> <@option{0=cpsr}, @option{1=spsr}>
1009 @cindex arm7_9 write_xpsr
1010 Immediately write either the current program status register (CPSR) or the saved
1011 program status register (SPSR), without changing the register cache (as displayed
1012 by the @option{reg} and @option{armv4_5 reg} commands).
1013 @item @b{arm7_9 write_xpsr_im8} <@var{8-bit value}> <@var{rotate 4-bit}>
1014 <@var{0=cpsr},@var{1=spsr}>
1015 @cindex arm7_9 write_xpsr_im8
1016 Write the 8-bit value rotated right by 2*rotate bits, using an immediate write
1017 operation (similar to @option{write_xpsr}).
1018 @item @b{arm7_9 write_core_reg} <@var{num}> <@var{mode}> <@var{value}>
1019 @cindex arm7_9 write_core_reg
1020 Write a core register, without changing the register cache (as displayed by the
1021 @option{reg} and @option{armv4_5 reg} commands). The <@var{mode}> argument takes the
1022 encoding of the [M4:M0] bits of the PSR.
1026 @section JTAG commands
1027 @cindex JTAG commands
1029 @item @b{scan_chain}
1031 Print current scan chain configuration.
1032 @item @b{jtag_reset}
1034 Toggle reset lines <@var{trst}> <@var{srst}>.
1035 @item @b{endstate} <@var{tap_state}>
1037 Finish JTAG operations in <@var{tap_state}>.
1038 @item @b{runtest} <@var{num_cycles}>
1040 Move to Run-Test/Idle, and execute <@var{num_cycles}>
1041 @item @b{statemove} [@var{tap_state}]
1043 Move to current endstate or [@var{tap_state}]
1046 Execute IR scan <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
1049 Execute DR scan <@var{device}> [@var{dev2}] [@var{var2}] ...
1050 @item @b{verify_ircapture}
1051 @cindex verify_ircapture
1052 Verify value captured during Capture-IR <@option{enable}|@option{disable}>
1055 Allocate, display or delete variable <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
1058 Display/modify variable field <@var{var}> <@var{field}> [@var{value}|@var{flip}]
1061 @node Sample Scripts
1062 @chapter Sample Scripts
1065 This page will collect some script examples for different CPUs.
1067 The configuration script can be divided in the following section:
1069 @item daemon configuration
1071 @item jtag scan chain
1072 @item target configuration
1073 @item flash configuration
1076 Detailed information about each section can be found at OpenOCD configuration
1078 @section OMAP5912 Flash Debug
1079 @cindex OMAP5912 Flash Debug
1080 The following two scripts were used with a wiggler PP and and a TI OMAP5912
1081 dual core processor - (@uref{http://www.ti.com}), on a OMAP5912 OSK board
1082 - (@uref{http://www.spectrumdigital.com}).
1083 @subsection Openocd config
1085 #daemon configuration
1092 parport_cable wiggler
1095 #use combined on interfaces or targets that can't set TRST/SRST separately
1096 reset_config trst_and_srst
1099 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1100 jtag_device 38 0x0 0x0 0x0
1101 jtag_device 4 0x1 0x0 0xe
1102 jtag_device 8 0x0 0x0 0x0
1104 #target configuration
1105 daemon_startup reset
1107 #target <type> <endianness> <reset mode> <chainpos> <variant>
1108 target arm926ejs little run_and_init 1 arm926ejs
1109 target_script 0 reset omap5912_osk.init
1110 run_and_halt_time 0 30
1112 # omap5912 lcd frame buffer as working area
1113 working_area 0 0x20000000 0x3e800 nobackup
1115 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1116 flash bank cfi 0x00000000 0x1000000 2 2 0
1119 @subsection Openocd init
1131 mww 0xfffec808 0x000000f5
1132 mww 0xfffec808 0x000000a0
1134 mww 0xfffeb048 0x0000aaaa
1136 mww 0xfffeb048 0x00005555
1145 @section STR71x Script
1146 @cindex STR71x Script
1147 The following script was used with an Amontec JTAGkey and a STR710 / STR711 cpu:
1149 #daemon configuration
1155 ft2232_device_desc "Amontec JTAGkey A"
1156 ft2232_layout jtagkey
1157 ft2232_vid_pid 0x0403 0xcff8
1160 #use combined on interfaces or targets that can't set TRST/SRST separately
1161 reset_config trst_and_srst srst_pulls_trst
1164 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1165 jtag_device 4 0x1 0xf 0xe
1167 #target configuration
1168 daemon_startup reset
1170 #target <type> <startup mode>
1171 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1172 target arm7tdmi little run_and_halt 0 arm7tdmi
1173 run_and_halt_time 0 30
1175 working_area 0 0x2000C000 0x4000 nobackup
1177 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1178 flash bank str7x 0x40000000 0x00040000 0 0 0 STR71x
1181 @section STR750 Script
1182 @cindex STR750 Script
1183 The following script was used with an Amontec JTAGkey and a STR750 cpu:
1185 #daemon configuration
1191 ft2232_device_desc "Amontec JTAGkey A"
1192 ft2232_layout jtagkey
1193 ft2232_vid_pid 0x0403 0xcff8
1196 #use combined on interfaces or targets that can't set TRST/SRST separately
1197 #reset_config trst_and_srst srst_pulls_trst
1198 reset_config trst_and_srst srst_pulls_trst
1201 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1202 jtag_device 4 0x1 0xf 0xe
1204 #jtag nTRST and nSRST delay
1205 jtag_nsrst_delay 500
1206 jtag_ntrst_delay 500
1208 #target configuration
1209 daemon_startup reset
1211 #target <type> <startup mode>
1212 #target arm7tdmi <reset mode> <chainpos> <endianness> <variant>
1213 target arm7tdmi little run_and_halt 0 arm7tdmi
1214 run_and_halt_time 0 30
1216 working_area 0 0x40000000 0x4000 nobackup
1218 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1219 flash bank str7x 0x20000000 0x000040000 0 0 0 STR75x
1222 @section STR912 Script
1223 @cindex STR912 Script
1224 The following script was used with an Amontec JTAGkey and a STR912 cpu:
1226 #daemon configuration
1232 ft2232_device_desc "Amontec JTAGkey A"
1233 ft2232_layout jtagkey
1236 #use combined on interfaces or targets that can't set TRST/SRST separately
1237 reset_config trst_and_srst
1240 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1241 jtag_device 8 0x1 0x1 0xfe
1242 jtag_device 4 0x1 0xf 0xe
1243 jtag_device 5 0x1 0x1 0x1e
1245 #target configuration
1246 daemon_startup reset
1248 #target <type> <startup mode>
1249 #target arm966e <endianness> <reset mode> <chainpos> <variant>
1250 target arm966e little reset_halt 1 arm966e
1251 run_and_halt_time 0 30
1253 working_area 0 0x50000000 16384 nobackup
1255 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1256 flash bank str9x 0x00000000 0x00080000 0 0 0
1259 @section STR912 comstick
1260 @cindex STR912 comstick Script
1261 The following script was used with a Hitex STR9 Comstick:
1263 #daemon configuration
1269 ft2232_device_desc "STR9-comStick A"
1270 ft2232_layout comstick
1273 jtag_nsrst_delay 100
1274 jtag_ntrst_delay 100
1276 #use combined on interfaces or targets that can't set TRST/SRST separately
1277 reset_config trst_and_srst
1280 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1281 jtag_device 8 0x1 0x1 0xfe
1282 jtag_device 4 0x1 0xf 0xe
1283 jtag_device 5 0x1 0x1 0x1e
1285 #target configuration
1286 daemon_startup reset
1288 #target <type> <startup mode>
1289 #target arm966e <endianness> <reset mode> <chainpos> <variant>
1290 target arm966e little reset_halt 1 arm966e
1291 run_and_halt_time 0 30
1293 working_area 0 0x50000000 16384 nobackup
1295 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1296 flash bank str9x 0x00000000 0x00080000 0 0 0
1299 @section STM32x Script
1300 @cindex STM32x Script
1301 The following script was used with an Amontec JTAGkey and a STM32x cpu:
1303 #daemon configuration
1309 ft2232_device_desc "Amontec JTAGkey A"
1310 ft2232_layout jtagkey
1313 jtag_nsrst_delay 100
1314 jtag_ntrst_delay 100
1316 #use combined on interfaces or targets that can't set TRST/SRST separately
1317 reset_config trst_and_srst
1320 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1321 jtag_device 4 0x1 0xf 0xe
1322 jtag_device 5 0x1 0x1 0x1e
1324 #target configuration
1325 daemon_startup reset
1327 #target <type> <startup mode>
1328 #target cortex_m3 <endianness> <reset mode> <chainpos> <variant>
1329 target cortex_m3 little run_and_halt 0
1330 run_and_halt_time 0 30
1332 working_area 0 0x20000000 16384 nobackup
1334 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1335 flash bank stm32x 0x08000000 0x00020000 0 0 0
1338 @section STM32x Performance Stick
1339 @cindex STM32x Performance Stick Script
1340 The following script was used with the Hitex STM32 Performance Stick
1342 #daemon configuration
1348 ft2232_device_desc "STM32-PerformanceStick A"
1349 ft2232_layout stm32stick
1352 jtag_nsrst_delay 100
1353 jtag_ntrst_delay 100
1355 #use combined on interfaces or targets that can't set TRST/SRST separately
1356 reset_config trst_and_srst
1359 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1360 jtag_device 4 0x1 0xf 0xe
1361 jtag_device 5 0x1 0x1 0x1e
1362 jtag_device 4 0x1 0xf 0xe
1364 #target configuration
1365 daemon_startup reset
1367 #target <type> <startup mode>
1368 #target cortex_m3 <endianness> <reset mode> <chainpos> <variant>
1369 target cortex_m3 little run_and_halt 0
1370 run_and_halt_time 0 30
1372 working_area 0 0x20000000 16384 nobackup
1374 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1375 flash bank stm32x 0x08000000 0x00020000 0 0 0
1378 @section LPC2129 Script
1379 @cindex LPC2129 Script
1380 The following script was used with an wiggler PP and a LPC-2129 cpu:
1382 #daemon configuration
1389 parport_cable wiggler
1392 #use combined on interfaces or targets that can't set TRST/SRST separately
1393 reset_config trst_and_srst srst_pulls_trst
1396 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1397 jtag_device 4 0x1 0xf 0xe
1399 #target configuration
1400 daemon_startup reset
1402 #target <type> <startup mode>
1403 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1404 target arm7tdmi little run_and_halt 0 arm7tdmi-s_r4
1405 run_and_halt_time 0 30
1407 working_area 0 0x40000000 0x4000 nobackup
1409 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1410 flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14765 calc_checksum
1413 @section LPC2148 Script
1414 @cindex LPC2148 Script
1415 The following script was used with an Amontec JTAGkey and a LPC2148 cpu:
1417 #daemon configuration
1423 ft2232_device_desc "Amontec JTAGkey A"
1424 ft2232_layout jtagkey
1425 ft2232_vid_pid 0x0403 0xcff8
1428 #use combined on interfaces or targets that can't set TRST/SRST separately
1429 reset_config trst_and_srst srst_pulls_trst
1432 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1433 jtag_device 4 0x1 0xf 0xe
1435 #target configuration
1436 daemon_startup reset
1438 #target <type> <startup mode>
1439 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1440 target arm7tdmi little run_and_halt 0 arm7tdmi-s_r4
1441 run_and_halt_time 0 30
1443 working_area 0 0x40000000 0x8000 nobackup
1445 #flash configuration
1446 flash bank lpc2000 0x0 0x7d000 0 0 0 lpc2000_v1 14765 calc_checksum
1449 @section LPC2294 Script
1450 @cindex LPC2294 Script
1451 The following script was used with an Amontec JTAGkey and a LPC2294 cpu:
1453 #daemon configuration
1459 ft2232_device_desc "Amontec JTAGkey A"
1460 ft2232_layout jtagkey
1461 ft2232_vid_pid 0x0403 0xcff8
1464 #use combined on interfaces or targets that can't set TRST/SRST separately
1465 reset_config trst_and_srst srst_pulls_trst
1468 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1469 jtag_device 4 0x1 0xf 0xe
1471 #target configuration
1472 daemon_startup reset
1474 #target <type> <startup mode>
1475 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1476 target arm7tdmi little run_and_halt 0 arm7tdmi-s_r4
1477 run_and_halt_time 0 30
1479 working_area 0 0x40000000 0x4000 nobackup
1481 #flash configuration
1482 flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14765 calc_checksum
1485 @section AT91R40008 Script
1486 @cindex AT91R40008 Script
1487 The following script was used with an Amontec JTAGkey and a AT91R40008 cpu:
1489 #daemon configuration
1495 ft2232_device_desc "Amontec JTAGkey A"
1496 ft2232_layout jtagkey
1497 ft2232_vid_pid 0x0403 0xcff8
1499 jtag_nsrst_delay 200
1500 jtag_ntrst_delay 200
1502 #use combined on interfaces or targets that can't set TRST/SRST separately
1503 reset_config srst_only srst_pulls_trst
1506 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1507 jtag_device 4 0x1 0xf 0xe
1509 #target configuration
1510 daemon_startup reset
1512 #target <type> <startup mode>
1513 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1514 target arm7tdmi little run_and_halt 0 arm7tdmi
1515 run_and_halt_time 0 30
1518 @section AT91SAM7s Script
1519 @cindex AT91SAM7s Script
1520 The following script was used with an Olimex ARM-JTAG-OCD and a AT91SAM7S64 cpu:
1522 #daemon configuration
1528 ft2232_device_desc "Olimex OpenOCD JTAG A"
1529 ft2232_layout olimex-jtag
1530 ft2232_vid_pid 0x15BA 0x0003
1532 jtag_nsrst_delay 200
1533 jtag_ntrst_delay 200
1535 #use combined on interfaces or targets that can't set TRST/SRST separately
1536 reset_config srst_only srst_pulls_trst
1539 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1540 jtag_device 4 0x1 0xf 0xe
1542 #target configuration
1543 daemon_startup reset
1545 #target <type> <startup mode>
1546 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1547 target arm7tdmi little run_and_halt 0 arm7tdmi
1548 run_and_halt_time 0 30
1550 # flash-options AT91
1551 working_area 0 0x00200000 0x4000 nobackup
1552 flash bank at91sam7 0 0 0 0 0
1555 # erase command (telnet-interface) for complete flash:
1556 # flash erase <num> 0 numlockbits-1 (can be seen from output of flash info 0)
1557 # SAM7S64 with 16 lockbits and bank 0: flash erase 0 0 15
1558 # set/clear NVM-Bits:
1559 # at91sam7 gpnvm <num> <bit> <set|clear>
1560 # disable locking from SAM-BA:
1561 # flash protect 0 0 1 off
1564 @section XSCALE IXP42x Script
1565 @cindex XSCALE IXP42x Script
1566 The following script was used with an Amontec JTAGkey-Tiny and a xscale ixp42x cpu:
1568 #daemon configuration
1574 ft2232_device_desc "Amontec JTAGkey A"
1575 ft2232_layout jtagkey
1576 ft2232_vid_pid 0x0403 0xcff8
1578 jtag_nsrst_delay 200
1579 jtag_ntrst_delay 200
1581 #use combined on interfaces or targets that can't set TRST/SRST separately
1582 reset_config srst_only srst_pulls_trst
1585 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1586 jtag_device 7 0x1 0x7f 0x7e
1588 #target configuration
1589 daemon_startup reset
1591 #target <type> <startup mode>
1592 #target arm7tdmi <reset mode> <chainpos> <endianness> <variant>
1593 target xscale big run_and_halt 0 IXP42x
1594 run_and_halt_time 0 30
1597 @section Cirrus Logic EP9301 Script
1598 @cindex Cirrus Logic EP9301 Script
1599 The following script was used with FT2232 based JTAG interfaces and a
1600 Cirrus Logic EP9301 processor on an Olimex CS-E9301 board.
1602 #daemon configuration
1610 #ft2232_device_desc "Olimex OpenOCD JTAG"
1611 #ft2232_layout olimex-jtag
1612 #ft2232_vid_pid 0x15ba 0x0003
1614 #Amontec JTAGkey (and JTAGkey-Tiny)
1615 #Serial is only necessary if more than one JTAGkey is connected
1616 ft2232_device_desc "Amontec JTAGkey A"
1617 #ft2232_serial AMTJKV31
1618 #ft2232_serial T1P3S2W8
1619 ft2232_layout jtagkey
1620 ft2232_vid_pid 0x0403 0xcff8
1622 #wiggler/parallel port interface
1625 #parport_cable wiggler
1628 reset_config trst_and_srst
1631 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1632 jtag_device 4 0x1 0xf 0xe
1634 jtag_nsrst_delay 100
1635 jtag_ntrst_delay 100
1637 #target configuration
1638 daemon_startup attach
1640 #target <type> <endianess> <reset mode>
1641 target arm920t little reset_halt 0
1642 working_area 0 0x80014000 0x1000 backup
1644 #flash configuration
1645 #flash bank <driver> <base> <size> <chip_width> <bus_width> [driver_options ...]
1646 flash bank cfi 0x60000000 0x1000000 2 2 0
1649 @section Hilscher netX 100 / 500 Script
1650 @cindex Hilscher netX 100 / 500 Script
1651 The following script was used with an Amontec JTAGkey and a Hilscher
1654 #daemon configuration
1660 ft2232_device_desc "Amontec JTAGkey A"
1661 ft2232_layout jtagkey
1662 ft2232_vid_pid 0x0403 0xcff8
1665 #use combined on interfaces or targets that can't set TRST/SRST separately
1666 reset_config trst_and_srst
1669 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1670 jtag_device 4 0x1 0xf 0xe
1672 jtag_nsrst_delay 100
1673 jtag_ntrst_delay 100
1675 #target configuration
1676 daemon_startup reset
1678 #target <type> <endianness> <startup mode> <chainpos> <variant>
1679 target arm926ejs little run_and_halt 0 arm926ejs
1680 run_and_halt_time 0 500
1683 @section Marvell/Intel PXA270 Script
1684 @cindex Marvell/Intel PXA270 Script
1686 # config for Intel PXA270
1687 # not, as of 2007-06-22, openocd only works with the
1688 # libftd2xx library from ftdi. libftdi does not work.
1694 ft2232_layout olimex-jtag
1695 ft2232_vid_pid 0x15BA 0x0003
1696 ft2232_device_desc "Olimex OpenOCD JTAG"
1698 # set jtag_nsrst_delay to the delay introduced by your reset circuit
1699 # the rest of the needed delays are built into the openocd program
1700 jtag_nsrst_delay 260
1701 # set the jtag_ntrst_delay to the delay introduced by a reset circuit
1702 # the rest of the needed delays are built into the openocd program
1705 #use combined on interfaces or targets that can't set TRST/SRST separately
1706 reset_config trst_and_srst separate
1709 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1710 jtag_device 7 0x1 0x7f 0x7e
1712 #target configuration
1713 daemon_startup reset
1715 target xscale little reset_halt 0 pxa27x
1717 # maps to PXA internal RAM. If you are using a PXA255
1718 # you must initialize SDRAM or leave this option off
1719 working_area 0 0x5c000000 0x10000 nobackup
1721 run_and_halt_time 0 30
1723 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1724 # works for P30 flash
1725 flash bank cfi 0x00000000 0x1000000 2 4 0
1728 @node GDB and Openocd
1729 @chapter GDB and Openocd
1730 @cindex GDB and Openocd
1731 Openocd complies with the remote gdbserver protocol, and as such can be used
1732 to debug remote targets.
1734 @section Connecting to gdb
1735 @cindex Connecting to gdb
1736 A connection is typically started as follows:
1738 target remote localhost:3333
1740 This would cause gdb to connect to the gdbserver on the local pc using port 3333.
1742 To see a list of available openocd commands type @option{monitor help} on the
1745 Openocd supports the gdb @option{qSupported} packet, this enables information
1746 to be sent by the gdb server (openocd) to gdb. Typical information includes
1747 packet size and device memory map.
1749 Previous versions of openocd required the following gdb options to increase
1750 the packet size and speed up gdb communication.
1752 set remote memory-write-packet-size 1024
1753 set remote memory-write-packet-size fixed
1754 set remote memory-read-packet-size 1024
1755 set remote memory-read-packet-size fixed
1757 This is now handled in the @option{qSupported} PacketSize.
1759 @section Programming using gdb
1760 @cindex Programming using gdb
1762 By default the target memory map is not sent to gdb, this can be enabled by
1763 the following openocd config option:
1765 gdb_memory_map enable
1767 For this to function correctly a valid flash config must also be configured
1768 in openocd. For speed also configure a valid working area.
1770 Informing gdb of the memory map of the target will enable gdb to protect any
1771 flash area of the target and use hardware breakpoints by default. This means
1772 that the openocd option @option{arm7_9 force_hw_bkpts} is not required when
1775 To view the configured memory map in gdb, use the gdb command @option{info mem}
1776 All other unasigned addresses within gdb are treated as ram.
1778 If @option{gdb_flash_program enable} is also used, gdb will be able to
1779 program any flash memory using the vFlash interface.
1781 gdb will look at the target memory map when a load command is given, if any
1782 areas to be programmed lie within the target flash area the vFlash packets
1785 Incase the target needs configuring before gdb programming, a script can be executed.
1787 target_script 0 gdb_program_config config.script
1790 To verify any flash programming the gdb command @option{compare-sections}
1797 @item OpenOCD complains about a missing cygwin1.dll
1799 Make sure you have Cygwin installed, or at least a version of OpenOCD that
1800 claims to come with all the necessary dlls. When using Cygwin, try launching
1801 the OpenOCD from the Cygwin shell.
1803 @item I'm trying to set a breakpoint using GDB (or a frontend like Insight or
1804 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
1805 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
1807 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
1808 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720t or ARM920t,
1809 software breakpoints consume one of the two available hardware breakpoints,
1810 and are therefor disabled by default. If your code is running from RAM, you
1811 can enable software breakpoints with the @option{arm7_9 sw_bkpts enable} command. If
1812 your code resides in Flash, you can't use software breakpoints, but you can force
1813 OpenOCD to use hardware breakpoints instead: @option{arm7_9 force_hw_bkpts enable}.
1815 @item When erasing or writing LPC2000 on-chip flash, the operation fails sometimes
1816 and works sometimes fine.
1818 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
1819 clock at the time you're programming the flash. If you've specified the crystal's
1820 frequency, make sure the PLL is disabled, if you've specified the full core speed
1821 (e.g. 60MHz), make sure the PLL is enabled.
1823 @item When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
1824 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
1825 out while waiting for end of scan, rtck was disabled".
1827 Make sure your PC's parallel port operates in EPP mode. You might have to try several
1828 settings in your PC Bios (ECP, EPP, and different versions of those).
1830 @item When debugging with the OpenOCD and GDB (plain GDB, Insight, or Eclipse),
1831 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
1832 memory read caused data abort".
1834 The errors are non-fatal, and are the result of GDB trying to trace stack frames
1835 beyond the last valid frame. It might be possible to prevent this by setting up
1836 a proper "initial" stack frame, if you happen to know what exactly has to
1837 be done, feel free to add this here.
1839 @item I get the following message in the OpenOCD console (or log file):
1840 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
1842 This warning doesn't indicate any serious problem, as long as you don't want to
1843 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
1844 trst_and_srst srst_pulls_trst} to tell the OpenOCD that either your board,
1845 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
1846 independently. With this setup, it's not possible to halt the core right out of
1847 reset, everything else should work fine.
1849 @item When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
1850 Toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
1851 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
1852 quit with an error message. Is there a stability issue with OpenOCD?
1854 No, this is not a stability issue concering OpenOCD. Most users have solved
1855 this issue by simply using a self-powered USB Hub, which they connect their
1856 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
1857 supply stable enough for the Amontec JTAGkey to be operated.
1859 @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
1860 following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
1861 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
1862 What does that mean and what might be the reason for this?
1864 First of all, the reason might be the USB power supply. Try using a self-powered
1865 hub instead of a direct connection to your computer. Secondly, the error code 4
1866 corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
1867 Chip ran into some sort of error - this points us to a USB problem.
1869 @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
1870 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
1871 What does that mean and what might be the reason for this?
1873 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
1874 has closed the connection to OpenOCD. This might be a GDB issue.
1876 @item In the configuration file in the section where flash device configurations
1877 are described, there is a parameter for specifying the clock frequency for
1878 LPC2000 internal flash devices (e.g.
1879 @option{flash bank lpc2000 0x0 0x40000 0 0 lpc2000_v1 0 14746 calc_checksum}),
1880 which must be sepcified in kilohertz. However, I do have a quartz crystal of a
1881 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz, i.e. 14,745.600 kHz).
1882 Is it possible to specify real numbers for the clock frequency?
1884 No. The clock frequency specified here must be given as an integral number.
1885 However, this clock frequency is used by the In-Application-Programming (IAP)
1886 routines of the LPC2000 family only, which seems to be very tolerant concerning
1887 the given clock frequency, so a slight difference between the specified clock
1888 frequency and the actual clock frequency will not cause any trouble.
1890 @item Do I have to keep a specific order for the commands in the configuration file?
1892 Well, yes and no. Commands can be given in arbitrary order, yet the devices
1893 listed for the JTAG scan chain must be given in the right order (jtag_device),
1894 with the device closest to the TDO-Pin being listed first. In general,
1895 whenever objects of the same type exist which require an index number, then
1896 these objects must be given in the right order (jtag_devices, targets and flash
1897 banks - a target references a jtag_device and a flash bank references a target).
1899 @item Sometimes my debugging session terminates with an error. When I look into the
1900 log file, I can see these error messages: Error: arm7_9_common.c:561
1901 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP