contrib/loaders/flash/at91sam7x/samregs.h

   1 /* SPDX-License-Identifier: BSD-3-Clause */
   2
   3 /*
   4  * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
   5  *
   6  * For additional information see http://www.ethernut.de/
   7  */
   8
   9
  10 #ifndef samregsH
  11 #define samregsH
  12
  13
  14 /*
  15  * Register definitions below copied from NutOS
  16  */
  17
  18 #define DBGU_BASE       0xFFFFF200      /*!< \brief DBGU base address. */
  19
  20 #define DBGU_CIDR_OFF           0x00000040      /*!< \brief DBGU chip ID register offset. */
  21 #define DBGU_CIDR   (DBGU_BASE + DBGU_CIDR_OFF) /*!< \brief DBGU chip ID register. */
  22
  23
  24 #define MC_BASE         0xFFFFFF00      /*!< \brief Memory controller base. */
  25
  26 #define MC_FMR_OFF              0x00000060      /*!< \brief MC flash mode register offset. */
  27 #define MC_FMR      (MC_BASE + MC_FMR_OFF)      /*!< \brief MC flash mode register address. */
  28 #define MC_FRDY                 0x00000001      /*!< \brief Flash ready. */
  29 #define MC_LOCKE                0x00000004      /*!< \brief Lock error. */
  30 #define MC_PROGE                0x00000008      /*!< \brief Programming error. */
  31 #define MC_NEBP                 0x00000080      /*!< \brief No erase before programming. */
  32 #define MC_FWS_MASK             0x00000300      /*!< \brief Flash wait state mask. */
  33 #define MC_FWS_1R2W             0x00000000      /*!< \brief 1 cycle for read, 2 for write operations. */
  34 #define MC_FWS_2R3W             0x00000100      /*!< \brief 2 cycles for read, 3 for write operations. */
  35 #define MC_FWS_3R4W             0x00000200      /*!< \brief 3 cycles for read, 4 for write operations. */
  36 #define MC_FWS_4R4W             0x00000300      /*!< \brief 4 cycles for read and write operations. */
  37 #define MC_FMCN_MASK            0x00FF0000      /*!< \brief Flash microsecond cycle number mask. */
  38
  39 #define MC_FCR_OFF              0x00000064      /*!< \brief MC flash command register offset. */
  40 #define MC_FCR      (MC_BASE + MC_FCR_OFF)      /*!< \brief MC flash command register address. */
  41 #define MC_FCMD_MASK            0x0000000F      /*!< \brief Flash command mask. */
  42 #define MC_FCMD_NOP             0x00000000      /*!< \brief No command. */
  43 #define MC_FCMD_WP              0x00000001      /*!< \brief Write page. */
  44 #define MC_FCMD_SLB             0x00000002      /*!< \brief Set lock bit. */
  45 #define MC_FCMD_WPL             0x00000003      /*!< \brief Write page and lock. */
  46 #define MC_FCMD_CLB             0x00000004      /*!< \brief Clear lock bit. */
  47 #define MC_FCMD_EA              0x00000008      /*!< \brief Erase all. */
  48 #define MC_FCMD_SGPB            0x0000000B      /*!< \brief Set general purpose NVM bit. */
  49 #define MC_FCMD_CGPB            0x0000000D      /*!< \brief Clear general purpose NVM bit. */
  50 #define MC_FCMD_SSB             0x0000000F      /*!< \brief Set security bit. */
  51 #define MC_PAGEN_MASK           0x0003FF00      /*!< \brief Page number mask. */
  52 #define MC_KEY                  0x5A000000      /*!< \brief Writing protect key. */
  53
  54 #define MC_FSR_OFF              0x00000068      /*!< \brief MC flash status register offset. */
  55 #define MC_FSR      (MC_BASE + MC_FSR_OFF)      /*!< \brief MC flash status register address. */
  56 #define MC_SECURITY             0x00000010      /*!< \brief Security bit status. */
  57
  58
  59 #endif