From fc7edd57ac6678d1113bc09265798de3fdc68347 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Benedikt-Alexander=20Mokro=C3=9F?= Date: Mon, 24 Aug 2020 10:59:27 +0200 Subject: [PATCH] flash/nor/at91sam4: ATSAMG55x19 Rev.B MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Add support for ATSAMG55x19 Rev.B. Both chips have nearly the same cidr, however, Rev.B has an incremented version. Change-Id: I5939c41fa5d54c4d3bfb850964974b878f709d13 Signed-off-by: Benedikt-Alexander Mokroß Reviewed-on: http://openocd.zylin.com/5825 Reviewed-by: Tomas Vanek Tested-by: jenkins --- src/flash/nor/at91sam4.c | 72 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 70 insertions(+), 2 deletions(-) diff --git a/src/flash/nor/at91sam4.c b/src/flash/nor/at91sam4.c index 1c61064253..86abf70053 100644 --- a/src/flash/nor/at91sam4.c +++ b/src/flash/nor/at91sam4.c @@ -1330,7 +1330,7 @@ static const struct sam4_chip_details all_sam4_details[] = { } }, - /* atsamg55g19 */ + /* atsamg55g19 Rev.A */ { .chipid_cidr = 0x24470ae0, .name = "atsamg55g19", @@ -1364,7 +1364,41 @@ static const struct sam4_chip_details all_sam4_details[] = { } }, - /* atsamg55j19 */ + /* atsamg55g19 Rev.B */ + { + .chipid_cidr = 0x24470ae1, + .name = "atsamg55g19b", + .total_flash_size = 512 * 1024, + .total_sram_size = 160 * 1024, + .n_gpnvms = 2, + .n_banks = 1, + + { +/* .bank[0] = */ + { + .probed = false, + .pChip = NULL, + .pBank = NULL, + .bank_number = 0, + .base_address = FLASH_BANK_BASE_S, + .controller_address = 0x400e0a00, + .flash_wait_states = 5, + .present = true, + .size_bytes = 512 * 1024, + .nsectors = 64, + .sector_size = 8192, + .page_size = 512, + }, +/* .bank[1] = */ + { + .present = false, + .probed = false, + .bank_number = 1, + }, + } + }, + + /* atsamg55j19 Rev.A */ { .chipid_cidr = 0x24570ae0, .name = "atsamg55j19", @@ -1398,6 +1432,40 @@ static const struct sam4_chip_details all_sam4_details[] = { } }, + /* atsamg55j19 Rev.B */ + { + .chipid_cidr = 0x24570ae1, + .name = "atsamg55j19b", + .total_flash_size = 512 * 1024, + .total_sram_size = 160 * 1024, + .n_gpnvms = 2, + .n_banks = 1, + + { +/* .bank[0] = */ + { + .probed = false, + .pChip = NULL, + .pBank = NULL, + .bank_number = 0, + .base_address = FLASH_BANK_BASE_S, + .controller_address = 0x400e0a00, + .flash_wait_states = 5, + .present = true, + .size_bytes = 512 * 1024, + .nsectors = 64, + .sector_size = 8192, + .page_size = 512, + }, +/* .bank[1] = */ + { + .present = false, + .probed = false, + .bank_number = 1, + }, + } + }, + /* terminate */ { .chipid_cidr = 0, -- 2.30.2