From fad64c618025ea96be585b0900bd70c2e5a8713a Mon Sep 17 00:00:00 2001
From: Jim Norris <u17263@att.net>
Date: Fri, 2 May 2014 21:04:45 -0500
Subject: [PATCH] tcl/target: Add configuration for NXP LPC4370 processor
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New configuration for NXP LPC4370 which consists of a Cortex-M4
and two Cortex-M0 cores.

Change-Id: I9918e3ff33218a14a99e4bbab9dce2e7b45b4d96
Signed-off-by: Jim Norris <u17263@att.net>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/2124
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
---
 tcl/target/lpc4370.cfg | 85 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 85 insertions(+)
 create mode 100644 tcl/target/lpc4370.cfg

diff --git a/tcl/target/lpc4370.cfg b/tcl/target/lpc4370.cfg
new file mode 100644
index 0000000000..67bff0adca
--- /dev/null
+++ b/tcl/target/lpc4370.cfg
@@ -0,0 +1,85 @@
+#
+# NXP LPC4370 - 1x ARM Cortex-M4 + 2x ARM Cortex-M0 @ up to 204 MHz each
+#
+
+adapter_khz 500
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME lpc4370
+}
+
+#
+# M4 JTAG mode TAP
+#
+if { [info exists M4_JTAG_TAPID] } {
+	set _M4_JTAG_TAPID $M4_JTAG_TAPID
+} else {
+	set _M4_JTAG_TAPID 0x4ba00477
+}
+
+#
+# M4 SWD mode TAP
+#
+if { [info exists M4_SWD_TAPID] } {
+	set _M4_SWD_TAPID $M4_SWD_TAPID
+} else {
+	set _M4_SWD_TAPID 0x2ba01477
+}
+
+source [find target/swj-dp.tcl]
+
+if { [using_jtag] } {
+	set _M4_TAPID $_M4_JTAG_TAPID
+} else {
+	set _M4_TAPID $_M4_SWD_TAPID
+}
+
+#
+# M0 TAP
+#
+if { [info exists M0_JTAG_TAPID] } {
+	set _M0_JTAG_TAPID $M0_JTAG_TAPID
+} else {
+	set _M0_JTAG_TAPID 0x0ba01477
+}
+
+swj_newdap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \
+				-expected-id $_M4_TAPID
+
+target create $_CHIPNAME.m4 cortex_m -chain-position $_CHIPNAME.m4
+
+# LPC4370 has 96+32 KB contiguous SRAM
+if { [info exists WORKAREASIZE] } {
+	set _WORKAREASIZE $WORKAREASIZE
+} else {
+	set _WORKAREASIZE 0x20000
+}
+$_CHIPNAME.m4 configure -work-area-phys 0x10000000 \
+                        -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+if { [using_jtag] } {
+	jtag newtap $_CHIPNAME m0app -irlen 4 -ircapture 0x1 -irmask 0xf \
+					-expected-id $_M0_JTAG_TAPID
+	jtag newtap $_CHIPNAME m0sub -irlen 4 -ircapture 0x1 -irmask 0xf \
+					-expected-id $_M0_JTAG_TAPID
+
+	target create $_CHIPNAME.m0app cortex_m -chain-position $_CHIPNAME.m0app
+	target create $_CHIPNAME.m0sub cortex_m -chain-position $_CHIPNAME.m0sub
+
+	# 32+8+32 KB SRAM
+	$_CHIPNAME.m0app configure -work-area-phys 0x10080000 \
+	                           -work-area-size 0x92000 -work-area-backup 0
+
+	# 16+2 KB M0 subsystem SRAM
+	$_CHIPNAME.m0sub configure -work-area-phys 0x18000000 \
+	                           -work-area-size 0x4800 -work-area-backup 0
+
+	# Default to the Cortex-M4
+	targets $_CHIPNAME.m4
+}
+
+if { ![using_hla] } {
+	cortex_m reset_config vectreset
+}
-- 
2.30.2