From ecab0cfe25600ad13c174b78a637515943cc870a Mon Sep 17 00:00:00 2001 From: David Brownell Date: Fri, 13 Nov 2009 16:58:14 -0800 Subject: [PATCH] ARM11: ETM + ETB support Kick in ETM (and ETB) support for ARM11. Tested on OMAP 2420, so update that configuration. (That's an ARM1136ejs, ETB, OpenGL ES1.1, C55x DSP, etc.) Also update the other ARM11 ETM + ETB targets in the tree to set up these modules. (Not tested.) Signed-off-by: David Brownell --- src/target/arm11.c | 16 +++++++++++++++- tcl/target/imx31.cfg | 4 ++++ tcl/target/imx35.cfg | 4 ++++ tcl/target/omap2420.cfg | 7 +++---- tcl/target/samsung_s3c6410.cfg | 4 ++++ 5 files changed, 30 insertions(+), 5 deletions(-) diff --git a/src/target/arm11.c b/src/target/arm11.c index b30e5181a8..7a30bc7fab 100644 --- a/src/target/arm11.c +++ b/src/target/arm11.c @@ -1898,6 +1898,20 @@ static int arm11_examine(struct target *target) if (retval != ERROR_OK) return retval; + /* ETM on ARM11 still uses original scanchain 6 access mode */ + if (arm11->arm.etm && !target_was_examined(target)) { + *register_get_last_cache_p(&target->reg_cache) = + etm_build_reg_cache(target, &arm11->jtag_info, + arm11->arm.etm); + retval = etm_setup(target); + } + + /* FIXME this sets a flag in the (shared) arm11_target structure, + * not in the (per-cpu) "target" structure ... so it's clearly + * wrong in the case of e.g. two different ARM11 chips on the + * same board. (Maybe ARM11 MPCore works though.) Whoever calls + * the examine() method should set a target-specific flag... + */ target_set_examined(target); return ERROR_OK; @@ -2212,5 +2226,5 @@ int arm11_register_commands(struct command_context *cmd_ctx) arm11_handle_vcr, COMMAND_ANY, "Control (Interrupt) Vector Catch Register"); - return ERROR_OK; + return etm_register_commands(cmd_ctx); } diff --git a/tcl/target/imx31.cfg b/tcl/target/imx31.cfg index 9a2aed3222..b613ba6fce 100644 --- a/tcl/target/imx31.cfg +++ b/tcl/target/imx31.cfg @@ -60,3 +60,7 @@ target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME proc power_restore {} { puts "Sensed power restore. No action." } proc srst_deasserted {} { puts "Sensed nSRST deasserted. No action." } + +# trace setup ... NOTE, "normal full" mode fudges the real ETMv3.1 mode +etm config $_TARGETNAME 16 normal full etb +etb config $_TARGETNAME $_CHIPNAME.etb diff --git a/tcl/target/imx35.cfg b/tcl/target/imx35.cfg index b899084fdb..d47abdc692 100644 --- a/tcl/target/imx35.cfg +++ b/tcl/target/imx35.cfg @@ -48,3 +48,7 @@ target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME proc power_restore {} { puts "Sensed power restore. No action." } proc srst_deasserted {} { puts "Sensed nSRST deasserted. No action." } + +# trace setup ... NOTE, "normal full" mode fudges the real ETMv3.1 mode +etm config $_TARGETNAME 16 normal full etb +etb config $_TARGETNAME $_CHIPNAME.etb diff --git a/tcl/target/omap2420.cfg b/tcl/target/omap2420.cfg index a579866ec3..5cf47b2139 100644 --- a/tcl/target/omap2420.cfg +++ b/tcl/target/omap2420.cfg @@ -49,7 +49,6 @@ $_TARGETNAME configure -work-area-phys 0x40210000 $_TARGETNAME configure -work-area-size 0x00081000 $_TARGETNAME configure -work-area-backup 0 -# trace setup -# REVISIT ... as of 12-June-2009, OpenOCD's ETM code can't talk to ARM11 cores. -#etm config $_TARGETNAME 16 normal full etb -#etb config $_TARGETNAME $_CHIPNAME.etb +# trace setup ... NOTE, "normal full" mode fudges the real ETMv3.1 mode +etm config $_TARGETNAME 16 normal full etb +etb config $_TARGETNAME $_CHIPNAME.etb diff --git a/tcl/target/samsung_s3c6410.cfg b/tcl/target/samsung_s3c6410.cfg index e451fd64a6..91371991d9 100644 --- a/tcl/target/samsung_s3c6410.cfg +++ b/tcl/target/samsung_s3c6410.cfg @@ -47,3 +47,7 @@ jtag_ntrst_delay 500 #reset configuration reset_config trst_and_srst + +# trace setup ... NOTE, "normal full" mode fudges the real ETMv3.1 mode +etm config $_TARGETNAME 16 normal full etb +etb config $_TARGETNAME $_CHIPNAME.etb -- 2.30.2