From 016e7ebbfa034926c980b4b33b964f6078541690 Mon Sep 17 00:00:00 2001
From: oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60>
Date: Thu, 17 Sep 2009 11:23:41 +0000
Subject: [PATCH] srst_gates_jtag option. at91sam9260 needs retesting, and
 possibly srst_gates_jtag added to reset_config. Could i.MX27 be a case where
 srst does not pull trst, but really srst gates jtag clock?

git-svn-id: svn://svn.berlios.de/openocd/trunk@2720 b42882b7-edfa-0310-969c-e2dbd0fdcd60
---
 doc/openocd.texi           |  4 ++++
 src/jtag/jtag.h            |  1 +
 src/jtag/tcl.c             |  8 ++++++++
 src/target/arm7_9_common.c | 13 ++++++++++++-
 4 files changed, 25 insertions(+), 1 deletion(-)

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 0b6ecf028a..9f7314b081 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -2018,6 +2018,10 @@ haven't seen hardware with such a bug, and can be worked around).
 @option{combined} implies both @option{srst_pulls_trst} and
 @option{trst_pulls_srst}.
 
+@option{srst_gates_jtag} indicates that asserting SRST gates the
+JTAG clock. This means that no communication can happen on JTAG
+while SRST is asserted. 
+
 The optional @var{trst_type} and @var{srst_type} parameters allow the
 driver mode of each reset line to be specified.  These values only affect
 JTAG interfaces with support for different driver modes, like the Amontec
diff --git a/src/jtag/jtag.h b/src/jtag/jtag.h
index b7bfd4cc9d..f716806b48 100644
--- a/src/jtag/jtag.h
+++ b/src/jtag/jtag.h
@@ -277,6 +277,7 @@ enum reset_types {
 	RESET_TRST_PULLS_SRST = 0x8,
 	RESET_TRST_OPEN_DRAIN = 0x10,
 	RESET_SRST_PUSH_PULL  = 0x20,
+	RESET_SRST_GATES_JTAG = 0x40,
 };
 
 enum reset_types jtag_get_reset_config(void);
diff --git a/src/jtag/tcl.c b/src/jtag/tcl.c
index e6928a2bfa..1658f76a26 100644
--- a/src/jtag/tcl.c
+++ b/src/jtag/tcl.c
@@ -845,6 +845,14 @@ static int handle_reset_config_command(struct command_context_s *cmd_ctx, char *
 		int tmp = 0;
 		int m;
 
+		m = RESET_SRST_GATES_JTAG;
+		tmp = 0;
+		if (strcmp(*args, "srst_gates_jtag") == 0)
+		{
+			tmp = RESET_SRST_GATES_JTAG;
+			goto next;
+		}
+
 		/* signals */
 		m = RESET_HAS_TRST | RESET_HAS_SRST;
 		if (strcmp(*args, "none") == 0)
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 9f05d777e0..e2eb0d5cd4 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -1021,6 +1021,17 @@ int arm7_9_assert_reset(target_t *target)
 		return ERROR_FAIL;
 	}
 
+	/* at this point trst has been asserted/deasserted once. We want to
+	 * program embedded ice while SRST is asserted, but some CPUs gate
+	 * the JTAG clock while SRST is asserted
+	 */
+	bool srst_asserted = false;
+	if (((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0) && ((jtag_reset_config & RESET_SRST_GATES_JTAG) == 0))
+	{
+		jtag_add_reset(0, 1);
+		srst_asserted = true;
+	}
+
 	if (target->reset_halt)
 	{
 		/*
@@ -1053,7 +1064,7 @@ int arm7_9_assert_reset(target_t *target)
 	if (jtag_reset_config & RESET_SRST_PULLS_TRST)
 	{
 		jtag_add_reset(1, 1);
-	} else
+	} else if (!srst_asserted)
 	{
 		jtag_add_reset(0, 1);
 	}
-- 
2.30.2