openocd.git
3 years agoflash/nor/tcl: Make verify_bank parameter optional 58/3858/2
Marc Schink [Fri, 4 Nov 2016 07:09:56 +0000 (08:09 +0100)]
flash/nor/tcl: Make verify_bank parameter optional

Make the 'offset' parameter optional, if omitted simply start at the
beginning of the flash bank.

Additionally, check if the argument is out of bounds of the flash bank.

Change-Id: Id1959eee5c395666c35f26342c3c50134dd564e5
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/3858
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
3 years agoflash/nor/tcl: Fix some format specifiers 57/3857/2
Marc Schink [Tue, 16 Aug 2016 07:39:36 +0000 (09:39 +0200)]
flash/nor/tcl: Fix some format specifiers

Change-Id: I2255aede9713cb7ef538d7433dd900d8da7a51ad
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/3857
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
3 years agotcl STM32L0xx - add support for dual banked targets and for Nucleo-64 STM32L073 57/3957/7
Jan Čapek [Wed, 25 Jan 2017 09:11:48 +0000 (10:11 +0100)]
tcl STM32L0xx - add support for dual banked targets and for Nucleo-64 STM32L073

- stm32l0_dual_bank.cfg - implement dual bank configuration

- st_nucleo_l073rz.cfg - implement new board script

Change-Id: Ie8063e5bec45069a63d414d81b2068fe3cc7e4d7
Signed-off-by: Jan Čapek <jan.capek@braiins.cz>
Reviewed-on: http://openocd.zylin.com/3957
Reviewed-by: Cezary Gapiński <cezary.gapinski@gmail.com>
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
Tested-by: jenkins
Reviewed-by: Aurelio Lucchesi <me@0rel.com>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
3 years agostm32lx: fix dual-bank configuration for Cat.5 and Cat.6 devices 74/4074/5
CezaryGapinski [Mon, 20 Mar 2017 11:33:05 +0000 (12:33 +0100)]
stm32lx: fix dual-bank configuration for Cat.5 and Cat.6 devices

Default values for .first_bank_size_kb and .has_dual_banks fields
described in stm32lx_parts[] do not fully describe
the real device memory layouts.

Basing on:
STM32L0x1 RM0377
STM32L0x2 RM0376
STM32L0x3 RM0367
STM32Lxxxx RM0038

correct values for memory layouts were selected:
id = 0x447 STM32L0xx (Cat.5) <- dual bank flash
for size 192 or 128 KBytes, single bank for 64 KBytes
id = 0x436 STM32L1xx (Cat.4 / Cat.3 - Medium + /
High Density) <- only one size of the bank,
default values are correct
id = 0x437 STM32L1xx (Cat.5 / Cat.6) <- always dual bank,
but size of the bank can be different

For that reason .part_info field in struct stm32lx_flash_bank
is a dynamic field with fields copied from stm32lx_parts[]
and overwriten to correct values
for specific chips and memory sizes.

Change-Id: If638cb0a9916097bfd4eda77d64feaf1ef2d2147
Signed-off-by: Cezary Gapiński <cezary.gapinski@gmail.com>
Reviewed-on: http://openocd.zylin.com/4074
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
3 years agoFix flash writing on stm32l0 36/4036/2
Armin van der Togt [Thu, 2 Mar 2017 16:31:14 +0000 (17:31 +0100)]
Fix flash writing on stm32l0

Fix "couldn't use loader, falling back to page memory writes" error on
stm32l0 which was caused by the use of cortex-m3 instructions in the
flash loader code. The loader is rewritten using cortex-m0 compatible
instructions

Signed-off-by: Armin van der Togt <armin@otheruse.nl>
Change-Id: If23027b8e09f74e45129e1f8452a04bb994c424e
Reviewed-on: http://openocd.zylin.com/4036
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
3 years agoflash/nor/at91samd: fix chip erase of a secured device 43/4043/3
Tomas Vanek [Fri, 3 Mar 2017 16:52:00 +0000 (17:52 +0100)]
flash/nor/at91samd: fix chip erase of a secured device

'at91samd chip-erase' command did not work on secured device.

Fix it changing address of DSU.CTRL register
(see Atmel SAM D21 datasheet, 13.9. Intellectual Property Protection).

While on it check error return of DSU.CTRL write.

Change-Id: I83155a634a5458cdc0cc16c99c0e155eb1d8b3d6
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reported-by: Thomas Irmen <tirmen@gmx.net>
Reviewed-on: http://openocd.zylin.com/4043
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
3 years agojtag/drivers cmsis-dap: do not limit speed so strictly 45/3945/3
Tomas Vanek [Mon, 9 Jan 2017 16:06:52 +0000 (17:06 +0100)]
jtag/drivers cmsis-dap: do not limit speed so strictly

Adapter clock frequency is set by 32-bit number and most adapters
limit the highest speed safely. There is no reason to impose strict
limit of 5000 kHz if some adapters can do more.

While on it give informative error message in case of zero adapter_khz.

Change-Id: I45c9804678e24496ea769ea9ca6036701b04dde9
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3945
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
3 years agoAdd support for the ATMEL SAM G55 Xplained Pro board and CPU. 22/3922/5
Jerome Lambourg [Wed, 6 Apr 2016 15:16:41 +0000 (17:16 +0200)]
Add support for the ATMEL SAM G55 Xplained Pro board and CPU.

Change-Id: Iffe59dcf9f2cb1f5949c37d11fe0d2141a47f8da
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3922
Tested-by: jenkins
Reviewed-by: Leo Zhang <liang.zhang@microchip.com>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
3 years agohelp/log.c: better error handling for "log_output" 78/3878/4
Girts [Sat, 5 Nov 2016 21:38:55 +0000 (14:38 -0700)]
help/log.c: better error handling for "log_output"

* Close previous log file if one was opened before.
* Return error if opening file fails.

Change-Id: I103025cd86bcac785fe39e13bc7d5f79d78e38e7
Signed-off-by: Girts Folkmanis <opensource@girts.me>
Reviewed-on: http://openocd.zylin.com/3878
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
3 years agohelper/options.c: fail if unexpected cmdline arguments are present 79/3879/3
Girts [Sat, 5 Nov 2016 21:38:55 +0000 (14:38 -0700)]
helper/options.c: fail if unexpected cmdline arguments are present

Previously openocd would silently ignore any incorrect arguments.

Change-Id: Ibb40b57b8a9e07d191215486f3b3c4920a9963c7
Signed-off-by: Girts Folkmanis <opensource@girts.me>
Reviewed-on: http://openocd.zylin.com/3879
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
3 years agohelp/options.c: add error handling for -d arg 80/3880/3
Girts [Sat, 5 Nov 2016 21:38:55 +0000 (14:38 -0700)]
help/options.c: add error handling for -d arg

Fail if we fail to set debug level. Also, clarify in usage string that
-d<n> doesn't accept spaces.

Change-Id: I9ea9945dc068e3e7cfd18b16ffa2a29366d6e4d1
Signed-off-by: Girts Folkmanis <opensource@girts.me>
Reviewed-on: http://openocd.zylin.com/3880
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
3 years agoboard: introduce base config for TI BeagleBone family boards 99/3099/6
Matthias Welwarsky [Wed, 4 Nov 2015 10:25:51 +0000 (11:25 +0100)]
board: introduce base config for TI BeagleBone family boards

This patch adds the file ti_beaglebone-base.cfg as the common base
configuration for all TI BeagleBone derived boards. It also modifies
ti_beaglebone.cfg to source the base board and only add the on-board
JTAG adapter. Lastly, it adds a file ti_beaglebone_black.cfg with
a suitable configuraton for the BeagleBone "Black" variant.

Change-Id: I40cacb8abed7bdb308929713891f7b5e5b685c95
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3099
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
3 years agonrf51: Add new HWID 0x008F 91/4091/2
Damyan Mitev [Tue, 4 Apr 2017 07:12:44 +0000 (10:12 +0300)]
nrf51: Add new HWID 0x008F

Add new entry in nrf51_known_devices_table for nRF51822 chip found on
chinese Core51822 dev board. The chp has markings N51822 / QFAAH1 / 1630FW
Nordic Semiconductor nRF51 Series Compatibility matrix confirms that this chip
has 256K Flash and 16K RAM.

Change-Id: I571d15913c6f6e02a6f09c883d7dfc5a66b57c28
Signed-off-by: Damyan Mitev <damyan_mitev@mail.bg>
Reviewed-on: http://openocd.zylin.com/4091
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
3 years agotools/scripts/checkpatch.pl: fix unescaped brace 02/4102/2
Chengyu Zheng [Sun, 9 Apr 2017 16:55:02 +0000 (18:55 +0200)]
tools/scripts/checkpatch.pl: fix unescaped brace

Change-Id: If1d0fbe95223351ea098504cf24f076784b26a9c
Signed-off-by: Chengyu Zheng <chengyu.zheng@polimi.it>
Reviewed-on: http://openocd.zylin.com/4102
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
3 years agoadded interface config file for In-Circuit's ICprog OpenOCD JTAG adapter 07/4107/3
Matthias Bock [Wed, 19 Apr 2017 12:53:05 +0000 (14:53 +0200)]
added interface config file for In-Circuit's ICprog OpenOCD JTAG adapter

Change-Id: I9f9758d3a30bbcca9f750f604e011e5cc25809c5
Signed-off-by: Matthias Bock <mail@matthiasbock.net>
Reviewed-on: http://openocd.zylin.com/4107
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
3 years agojtag/drivers cmsis-dap: fix speed setting on Atmel EDBG 44/3944/2
Tomas Vanek [Mon, 9 Jan 2017 14:30:21 +0000 (15:30 +0100)]
jtag/drivers cmsis-dap: fix speed setting on Atmel EDBG

Without the change Atmel EDBG uses default clock freq about 168 kHz
instead adapter_khz configured before interface init.
Changing adapter speed after init works as expected.

Testing shows the EDBG firmware resets speed to default during DAP_SWJ_Sequence.
Tested with fw versions 03.1F.01AE and 02.09.0169

This change repeats the DAP_SWJ_Clock command after sending a SWJ sequence.

Change-Id: Ic70457c5df635f47cad5e70b0dc83a083ea1b3a3
Reported-by: Ladislav Laska <laska@kam.mff.cuni.cz>
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3944
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
3 years agoflash Kinetis: reduce a flash write message severity to info 05/4105/2
Joakim Nohlgård [Wed, 12 Apr 2017 08:27:28 +0000 (10:27 +0200)]
flash Kinetis: reduce a flash write message severity to info

There is nothing the user can do if their device does not support sector
programming, there is no reason to have this message at warning level.

Change-Id: Ic9b7386e59b64fece7fbfdc543bdfeeed3eae73d
Signed-off-by: Joakim Nohlgård <joakim.nohlgard@eistec.se>
Reviewed-on: http://openocd.zylin.com/4105
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
3 years agotarget: Fix memory leak 48/4048/2
Marc Schink [Sun, 8 Jan 2017 19:19:29 +0000 (20:19 +0100)]
target: Fix memory leak

Change-Id: Ib23dfd653d8edacb890a46179e9d437c027d58e8
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/4048
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Chengyu Zheng <chengyu.zheng@polimi.it>
Reviewed-by: Andreas Färber <afaerber@suse.de>
3 years agostlink: increase trace buffer size to maximum allowed on st-link v2 firmware 85/4085/2
Austin Morton [Wed, 29 Mar 2017 03:22:44 +0000 (23:22 -0400)]
stlink: increase trace buffer size to maximum allowed on st-link v2 firmware

Increasing the trace buffer size on the st-link itself gives openocd a greater
chance of avoiding trace data overflowing within the st-link between polls
when there is a large amount of data being sent over the trace port

The st-link appears to split the given buffer size in half
while one half is awaiting transfer over USB, the other half is being
filled by DMA transfer.  If you do not poll frequently enough, the DMA
transfer will overflow back to the start of its current buffer, resulting in
corrupted output

Buffer size of 4096 bytes is the maximum allowed by the st-link v2

Change-Id: I169189b021c34f8d18de1601d78b8c5890367d68
Signed-off-by: Austin Morton <austinpmorton@gmail.com>
Reviewed-on: http://openocd.zylin.com/4085
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
3 years agoaarch64: add some documentation 08/4008/8
Matthias Welwarsky [Thu, 23 Feb 2017 13:17:15 +0000 (14:17 +0100)]
aarch64: add some documentation

document aarch64 specific commands and common ARMv7 and v8 DAP commands

Change-Id: Icbb76209735ec734f2e67f82bfc7270edb40ad0b
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/4008
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
3 years agoaarch64: clear CTI halt event early at debug entry 30/4030/2
Matthias Welwarsky [Wed, 1 Mar 2017 15:15:33 +0000 (16:15 +0100)]
aarch64: clear CTI halt event early at debug entry

The halt event was left pending in the CTI, better to clear it immediately
after debug entry.

Change-Id: I6002f862681baf98769e3c73332a7f7f0ef938c1
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/4030
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
3 years agonrf51: Remove pointer cast 30/3930/2
Andreas Fritiofson [Thu, 29 Dec 2016 11:19:11 +0000 (12:19 +0100)]
nrf51: Remove pointer cast

Int may not be 32 bit long.

Change-Id: I420f7efeb484eb35c1d7c20e1575b0b31ed8c9ff
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3930
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
3 years agoarm_dpm: fix dpm setup 42/4042/3
Girts Folkmanis [Fri, 3 Mar 2017 17:49:58 +0000 (09:49 -0800)]
arm_dpm: fix dpm setup

When ARM64 support was being merged, a comparison ended up being
inverted. This causes NULL pointer access when target attempts to
use core cache.

Change-Id: Ic8873ddd13dbdd8100856a71b4717f44cd336e23
Signed-off-by: Girts Folkmanis <opensource@girts.me>
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/4042
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
3 years agotcl: add Hi6220 target and LeMaker HiKey board config 09/4009/2
Matthias Welwarsky [Thu, 23 Feb 2017 13:52:45 +0000 (14:52 +0100)]
tcl: add Hi6220 target and LeMaker HiKey board config

configuration covers all 8 Cortex-A53 cores and auxiliary Cortex-M3
used for power management.

Change-Id: I5509f275aa669abe285f9152935ecdcbcd0c402e
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/4009
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
3 years agoarmv8_dpm: fix exception handling 96/3996/4
Matthias Welwarsky [Fri, 17 Feb 2017 15:22:52 +0000 (16:22 +0100)]
armv8_dpm: fix exception handling

after handling of an exception in debug state, immediately
restore the original core state.

Change-Id: Ie53b63c9f19815f717f4df4390fbc13f0a204cc2
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3996
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
3 years agoarmv8_dpm: retrieve only necessary registers on halt 95/3995/4
Matthias Welwarsky [Fri, 17 Feb 2017 15:21:41 +0000 (16:21 +0100)]
armv8_dpm: retrieve only necessary registers on halt

to speed up debugging, don't load the complete register context
on a halt event, load only those registers that might be
clobbered during debugging.

Change-Id: I0b58e97aad6f28aefce4a52e870af61e1ef1a44f
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3995
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
3 years agoarmv8: spelling and formatting updates 94/3994/4
Matthias Welwarsky [Fri, 17 Feb 2017 14:05:15 +0000 (15:05 +0100)]
armv8: spelling and formatting updates

small changes to correct code formatting and spelling of some
log messages.

Change-Id: I645e675f8f9f4731b0271ddc55f64e8cf56ec1db
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3994
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
3 years agoaarch64: run control rework 93/3993/4
Matthias Welwarsky [Fri, 17 Feb 2017 13:24:53 +0000 (14:24 +0100)]
aarch64: run control rework

This patch contains a major overhaul of the target run control,
mainly for the sake of satisfying gdbs ideas of how a target
should respond to various control requests for the debugger.

The changes allow gdb a slightly better control on how cores
are stepped: a core can be single-stepped while
other cores remain halted or continue normal execution
until the single-stepped core halts again.

Also, on any halting event (user command or breakpoint) the
system is brought into a stable state with all cores halted
before the halt is signaled to the debugger.

This patch also transitions the target code to make use of the
new CTI abstraction instead of accessing CTI registers directly.

Change-Id: I8ddc9abb119e04580d671b57ee12240c3f5070a0
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3993
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
3 years agoaarch64: clean up struct aarch64_common 92/3992/3
Matthias Welwarsky [Fri, 17 Feb 2017 12:57:08 +0000 (13:57 +0100)]
aarch64: clean up struct aarch64_common

remove some rarely or completely unused components.

Change-Id: Id285bb7075901016297fa173a874db7f11a840d7
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3992
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
3 years agoaarch64: clean up target specific commands 91/3991/3
Matthias Welwarsky [Fri, 17 Feb 2017 12:42:50 +0000 (13:42 +0100)]
aarch64: clean up target specific commands

- rename "cortex_a" command group to "aarch64"
- remove default blank check, checksum and algorithm hooks
  since they're not going to work in aarch64 mode anyway.

Change-Id: Ieb0046786ed9425baf6774c68f42a8285cc2aefd
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3991
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
3 years agoaarch64: reset fixes 90/3990/3
Matthias Welwarsky [Wed, 15 Feb 2017 14:30:21 +0000 (15:30 +0100)]
aarch64: reset fixes

Make sure all core register caches are invalidated on reset
assert, make sure to re-init debug registers on deassert.

Change-Id: I82350d04cc3eaae5e35245d13d6c1fb0a8d59807
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3990
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
3 years agoarmv8: factor out generic bit set/clr for debug registers 89/3989/3
Matthias Welwarsky [Wed, 15 Feb 2017 13:57:21 +0000 (14:57 +0100)]
armv8: factor out generic bit set/clr for debug registers

introduce armv8_set_dbgreg_bits() function to make register
bit-field modifications easier to read.

Change-Id: I6b06f66262587fd301d848c9e0645e8327653de7
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3989
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
3 years agoarmv8: load aarch32 register through aarch64 equivalent 88/3988/3
Matthias Welwarsky [Sun, 27 Nov 2016 10:39:47 +0000 (11:39 +0100)]
armv8: load aarch32 register through aarch64 equivalent

The aarch32 register cache is only a separate view of the aarch64
registers. Load aarch32 registers through their aarch64 equivalents.

Change-Id: I3e932dfb782f03d73d30d942b24db340a5749e47
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3988
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
3 years agoaarch64: remove bogus address check before memory access 87/3987/3
Matthias Welwarsky [Sun, 27 Nov 2016 10:28:01 +0000 (11:28 +0100)]
aarch64: remove bogus address check before memory access

Mmu faults can not be prevented on aarch64, they need to be taken and
handled accordingly. Remove the remaining stub code.

Change-Id: I6241efa594fe6b963624f9628cdf1c8e46588223
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3987
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
3 years agotarget: generic ARM CTI function wrapper 86/3986/3
Matthias Welwarsky [Sat, 19 Nov 2016 09:02:34 +0000 (10:02 +0100)]
target: generic ARM CTI function wrapper

Not specific to ARMv8, the Cross Trigger Interface
deserves an independent access wrapper.

Change-Id: I84f8faad15ed3515e0fff7f6cc5d1109ef91a869
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3986
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
3 years agoaarch64: optimize core state detection 85/3985/2
Matthias Welwarsky [Tue, 15 Nov 2016 21:10:03 +0000 (22:10 +0100)]
aarch64: optimize core state detection

Replace loop by right-shift.
Inspired by patch from Alamy Liu

Change-Id: I1285f4f54c0695a93fa42e9863ed8ffa4de00f70
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3985
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
3 years agoaarch64: reduce debug output to improve legibility 84/3984/2
Matthias Welwarsky [Mon, 14 Nov 2016 20:54:26 +0000 (21:54 +0100)]
aarch64: reduce debug output to improve legibility

Suppress some very verbose LOG_DEBUG's that are not really useful
any more.

Change-Id: I67f10ba9510a9e34a027f378f4b62b8901ddc8a4
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3984
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
3 years agoaarch64: remove mrs/msr functions from struct arm 83/3983/2
Matthias Welwarsky [Mon, 14 Nov 2016 11:23:24 +0000 (12:23 +0100)]
aarch64: remove mrs/msr functions from struct arm

No longer needed, no users.

Change-Id: I0cc82a0ef11e1b72101fa9145f014e5d5d76df0e
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3983
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
3 years agoaarch64: refactor SCTLR manipulation 82/3982/2
Matthias Welwarsky [Mon, 14 Nov 2016 11:18:43 +0000 (12:18 +0100)]
aarch64: refactor SCTLR manipulation

Reduce SLOCs in SCTLR retrieval and modification functions and make them
less complex.

Change-Id: Ida1a99c223743247f171b52eef80dc9886802101
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3982
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
3 years agoaarch64: fix software breakpoints when in aarch32 state 81/3981/2
Matthias Welwarsky [Wed, 26 Oct 2016 15:32:43 +0000 (17:32 +0200)]
aarch64: fix software breakpoints when in aarch32 state

Use the correct opcode for Aarch32 state, both for the breakpoint
instruction itself and the cache handling functions.

Change-Id: I975fa67b1e577b54f5c672a01d516419c6a614b2
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3981
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
3 years agoaarch64: Fix #include guards 75/3975/2
Marc Schink [Sun, 12 Feb 2017 09:59:49 +0000 (10:59 +0100)]
aarch64: Fix #include guards

Change-Id: I9445b04a210dcde5f8a7cf1560ef23eb53149178
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/3975
Tested-by: jenkins
Reviewed-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
3 years agoflash/nor: avrf: support atmega128rfa1 90/2790/2
Karl Palsson [Sun, 31 May 2015 02:18:36 +0000 (02:18 +0000)]
flash/nor: avrf: support atmega128rfa1

Tested with a Dresden Elektronik deRFmega128 module.

Change-Id: I91da3b11b60e78755360b08453ed368d6d396651
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Reviewed-on: http://openocd.zylin.com/2790
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
3 years agoaarch64: don't try resuming if target is not halted 32/3832/4
Matthias Welwarsky [Fri, 21 Oct 2016 15:00:54 +0000 (17:00 +0200)]
aarch64: don't try resuming if target is not halted

At framework level, the resume hook is not protected. Make sure to
not attempt a resume if the target is not halted.

Change-Id: I4dd1975a95d6c513bd4f4e999e496bc11182a97a
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: don't segfault on reset when target is not examined 31/3831/4
Matthias Welwarsky [Fri, 21 Oct 2016 14:59:28 +0000 (16:59 +0200)]
aarch64: don't segfault on reset when target is not examined

Basically port a fix that was already done for the cortex_a target.

Change-Id: I4cf4519159bda03ed611bc0b2e340a5dad2d85fe
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: use cached value of dscr register where needed 30/3830/4
Matthias Welwarsky [Thu, 20 Oct 2016 15:22:26 +0000 (17:22 +0200)]
aarch64: use cached value of dscr register where needed

Instead of supplying a local, preinitialized "dscr" variable, use the
cached value from arm_dpm, which is kept up-to-date anyway.

Change-Id: I06d548d4dc6db68b9d984c83ed026fa9069d7875
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: remove arm command chain from aarch64 target commands 29/3829/4
Matthias Welwarsky [Thu, 20 Oct 2016 15:15:00 +0000 (17:15 +0200)]
aarch64: remove arm command chain from aarch64 target commands

arm commands are mostly unusable anyway, remove them. to be replaced
by aarch64 specific commands later

Change-Id: Ie994771bc0e86cff1c26f68f1f51ce8ec352a509
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: remove "mrs <Xt>, currentel" opcode 28/3828/4
Matthias Welwarsky [Thu, 20 Oct 2016 15:13:36 +0000 (17:13 +0200)]
aarch64: remove "mrs <Xt>, currentel" opcode

"currentel" special register is not accessible in debug state.

Change-Id: I9022b01b423cd9ae8227ed018d6166078ba44832
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: remove unused struct components 27/3827/4
Matthias Welwarsky [Thu, 20 Oct 2016 15:06:13 +0000 (17:06 +0200)]
aarch64: remove unused struct components

remove unused register index array from armv8_mode_data[]

Change-Id: I686c20eeb3da413f5e9ef6058e31ce939741afb4
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: improve debug output 26/3826/4
Matthias Welwarsky [Thu, 20 Oct 2016 14:59:21 +0000 (16:59 +0200)]
aarch64: improve debug output

Make debug and error messages more informative, fix spelling and
formatting errors

Change-Id: I7245f42c5153bcc95676270814d30e91c113aaed
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: enlarge value buffer of arm_reg to store 64 bit 25/3825/4
Matthias Welwarsky [Thu, 20 Oct 2016 14:48:42 +0000 (16:48 +0200)]
aarch64: enlarge value buffer of arm_reg to store 64 bit

struct arm_reg::value[] must be 8 byte to hold a 64bit register value.

Change-Id: If253e90731d0ee855eafd9d7b63b91f84630cc7c
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: consolidate sticky error handling 24/3824/4
Matthias Welwarsky [Thu, 6 Oct 2016 14:37:25 +0000 (16:37 +0200)]
aarch64: consolidate sticky error handling

Move clearing of DSCR "Sticky Error" condition to the
exception handling function. Clear once on entering debug state.

Change-Id: Iec1d09d6f2d9cdd7e92953da5ea19f3e399ca12c
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: discard async aborts on entering debug state 23/3823/4
Matthias Welwarsky [Thu, 20 Oct 2016 14:23:40 +0000 (16:23 +0200)]
aarch64: discard async aborts on entering debug state

recommended for Corte-A8 cores, not sure if necessary
for ARMv8 based cores as well.

Change-Id: Ibcb36170c5fac6a6b132de17f734c70a56919f9b
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: cleanup context restore 22/3822/4
Matthias Welwarsky [Thu, 20 Oct 2016 13:39:30 +0000 (15:39 +0200)]
aarch64: cleanup context restore

Remove register cache invalidation and target state changes that are
handled appropriately in other functions.

Change-Id: Ic903f41ddc267f4b8765ea022bd4d6da1017e21f
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: enable aarch32 debugging with arm gdb 21/3821/4
Matthias Welwarsky [Thu, 20 Oct 2016 13:36:19 +0000 (15:36 +0200)]
aarch64: enable aarch32 debugging with arm gdb

When a PE is in Aarch32 state and gdb asks for a target description,
provide a register view compatible with the "org.gnu.gdb.arm.core"
feature. Only current-mode registers are exported, banked registers are
not visible.

Change-Id: I99a85d94831cf597fe8cff6a0a1818ce0a33613b
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: allow reading TTBR register when halted in EL0 20/3820/4
Matthias Welwarsky [Thu, 20 Oct 2016 12:46:11 +0000 (14:46 +0200)]
aarch64: allow reading TTBR register when halted in EL0

There's no access to TTBR in EL0. Circumvent by moving the PE to EL1
before reading, and switch back to original mode afterwards.

Change-Id: I22891b958d3d7e6fad1cb27183c192d975d63d89
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: make sure to enable HDE for all SMP PEs to be halted 19/3819/4
Matthias Welwarsky [Thu, 20 Oct 2016 11:59:35 +0000 (13:59 +0200)]
aarch64: make sure to enable HDE for all SMP PEs to be halted

When halting a group of PEs through CTI, HDE must be set in EDSCR for
all of them.

Change-Id: Iaa4bc0b0fe31e46a463c709d8274023225affd85
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: handle exceptions taken in debug state 18/3818/4
Matthias Welwarsky [Thu, 20 Oct 2016 11:37:11 +0000 (13:37 +0200)]
aarch64: handle exceptions taken in debug state

When an armv8-a PE causes an exception while halted, e.g. by performing
a prohibited memory or register access, its state is affected in the
same way as if it was running. That means, a number of registers is
overwritten (notably DLR and DSPSR, but also others) and also
potentially the exception level and therefore also the PE state can
change. This state must be restored before resuming normal operation.

This is done by marking the relevant cached registers "dirty" so that
they are written back before resume.

Change-Id: I9b6967a62d7cb23a477a9f7839f8d2b7087eed09
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: cache identification for aarch32 state 17/3817/4
Matthias Welwarsky [Thu, 20 Oct 2016 11:20:26 +0000 (13:20 +0200)]
aarch64: cache identification for aarch32 state

Use proper T32 opcodes for cache identification when the PE is in
Aarch32 state

Change-Id: I9cd9169409889273a3fd61167f388e68d8dde86d
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: fix mode switching 16/3816/4
Matthias Welwarsky [Thu, 20 Oct 2016 09:31:40 +0000 (11:31 +0200)]
aarch64: fix mode switching

DCPS only allows to enter higher ELs, for lower ELs you need to
use DRPS. Also, of course the encoding differs between A64 and T32.
Both DCPS and DRPS also clobber DLR and DSPSR, which then need to be
restored on resume.

Change-Id: Ifa3dcfa94212702e57170bd59fd0bb25495fb6fd
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: register access rewrite 15/3815/4
Matthias Welwarsky [Thu, 6 Oct 2016 14:10:38 +0000 (16:10 +0200)]
aarch64: register access rewrite

All register access is now performed through common read/write
functions, which delegate the actual register access to the
armv8_common object. armv8_common contains function pointers
to direct read and write requests to the respective low-level
functions for each PE state.

The respective read/write functions are selected on debug state
entry.

At the same time, T32 opcodes are now formatted for ITR in
dpmv8_exec_opcode() and the T32_FMTITR macro is removed from global
visibility.

Change-Id: I9eaef017c7cc9e0c531e693c534901bfdbdb842c
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: simplify armv8_read_ttbcr 14/3814/4
Matthias Welwarsky [Thu, 6 Oct 2016 14:36:29 +0000 (16:36 +0200)]
aarch64: simplify armv8_read_ttbcr

Read registers based on current EL instead of PE mode.

Change-Id: I05d3219ac1bf8585e9f4f024a7e8599fea0913b6
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: allow reading system control register when halted in EL0 13/3813/4
Matthias Welwarsky [Thu, 6 Oct 2016 14:19:20 +0000 (16:19 +0200)]
aarch64: allow reading system control register when halted in EL0

There's no access to system control register in EL0. Circumvent by
moving the PE to EL1 before reading, and switch back to original mode
afterwards.

Change-Id: I309f4eea5597ffc88fc892e9bbb826982e8a44ec
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: simplify armv8_set_cpsr() 12/3812/4
Matthias Welwarsky [Thu, 6 Oct 2016 14:11:19 +0000 (16:11 +0200)]
aarch64: simplify armv8_set_cpsr()

Translate from cpsr value to "enum arm_mode" by shifting up 4 bits and
filling the lowest nibble with 0xF.

Change-Id: Ic32186104b0c29578c4f6f99e04840ab88a0017b
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: provide virt2phys command 11/3811/4
Matthias Welwarsky [Thu, 6 Oct 2016 13:05:53 +0000 (15:05 +0200)]
aarch64: provide virt2phys command

Use AT commands to translate virtual to physical addresses based on
current MMU configuration.

Change-Id: I1bbd7d674c435541b617b17022fa9f7f0f01bdab
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: slightly simplify breakpoint set function 10/3810/3
Matthias Welwarsky [Mon, 26 Sep 2016 09:44:25 +0000 (11:44 +0200)]
aarch64: slightly simplify breakpoint set function

Set HDE bit through helper function instead of manual mem_ap access.

Change-Id: I68c157870f3f3c47a875d425ade6e975d8075424
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: remove bogus os_border calculation 09/3809/3
Matthias Welwarsky [Mon, 26 Sep 2016 09:08:11 +0000 (11:08 +0200)]
aarch64: remove bogus os_border calculation

The artificial "os_border" doesn't exist in aarch64 state and is wrong
for aarch32 state as well. Remove it.

Change-Id: I7c673a1404b03aa78dbd505e115fa3a93f7ca05f
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: armv8 cache functions update 08/3808/3
Matthias Welwarsky [Thu, 22 Sep 2016 19:29:42 +0000 (21:29 +0200)]
aarch64: armv8 cache functions update

Update cache identification to match functionality present in
armv7a_cache.c

Change-Id: I2dc4bee80f5a22b8728334d40331c183d1406f27
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: refactor armv8 dpm 97/3797/4
Matthias Welwarsky [Thu, 22 Sep 2016 19:16:31 +0000 (21:16 +0200)]
aarch64: refactor armv8 dpm

Move all DPM related functions from aarch64.c to armv8_dpm.c.

Change-Id: I43404ff5db414ae898787a523d3219e5bee44889
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: add basic Aarch32 support 70/3770/9
Matthias Welwarsky [Thu, 15 Sep 2016 07:13:51 +0000 (09:13 +0200)]
aarch64: add basic Aarch32 support

Add database for common, equivalent opcodes for Aarch32 and
Aarch64 execution states

Revisit all functions that access Aarch64 specific registers
or use Aarch64 opcodes and rewrite them to act depending on
current state of the core.

Add core register access functions for Aarch32 state

Add function to determine the core execution state without
reading DSPSR.

Change-Id: I345e9f6d682fb4ba454e4b1d16bb5e1b27570691
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: update smp halt and resume to better facilitate CTI 96/3796/4
Matthias Welwarsky [Thu, 29 Sep 2016 12:06:42 +0000 (14:06 +0200)]
aarch64: update smp halt and resume to better facilitate CTI

Set up CTI so that halt and resume requests get routed to all PEs in the
SMP group.

Change-Id: Ie92cfd3fe54632e5fdc049a6bf5b24b99451a8c9
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: add cache handling when setting/deleting soft breakpoints 75/3775/5
Matthias Welwarsky [Tue, 20 Sep 2016 09:29:39 +0000 (11:29 +0200)]
aarch64: add cache handling when setting/deleting soft breakpoints

Flush D-Cache before, flush D-Cache and invalidate I-Cache after
modifying the breakpoint location.

Change-Id: Id2e2f4f2545c062de7e27275f66857357496d4ae
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: add cache handling functions 74/3774/5
Matthias Welwarsky [Tue, 20 Sep 2016 09:16:30 +0000 (11:16 +0200)]
aarch64: add cache handling functions

For now only D-Cache flush (Clean&Invalidate) and I-Cache
invalidate are implemented. That's enough for software breakpoints.

Change-Id: I8e96d645a230b51e3490403f4564e59ba6a76cf3
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: disable interrupts when stepping [WIP] 73/3773/5
Matthias Welwarsky [Mon, 19 Sep 2016 15:04:03 +0000 (17:04 +0200)]
aarch64: disable interrupts when stepping [WIP]

On live hardware, interrupts will happen while the core is
held for stepping. The next step will most of the time execute an
interrupt service instead of the next line of code, which is not
what you expect. Disable interrupts through DSCR before resuming
for a step, and re-enable them again after the step happened.

This should be made configurable, like on cortex_a target.

Change-Id: I94d8ffb58cf7579dedb66bc756b7eb6828b6e8e4
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: use correct instruction for software breakpoints 69/3769/7
Matthias Welwarsky [Fri, 16 Sep 2016 11:46:08 +0000 (13:46 +0200)]
aarch64: use correct instruction for software breakpoints

External debuggers need to use HLT, not BRK. HLT generates a halting
debug event while BRK generates a debug exception for self-hosted
debugging.

Change-Id: I24024b83668107f73a14cc75d951134917269e5c
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: report the correct reason for halting after singlestep 68/3768/7
Matthias Welwarsky [Fri, 16 Sep 2016 10:55:17 +0000 (12:55 +0200)]
aarch64: report the correct reason for halting after singlestep

Don't report breakpoint as debug reason when halt is due to a
single-step event.

Change-Id: Ie6c3ca1e5427c73eb726a038301b6a29a47d1217
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: fix register list 67/3767/6
Matthias Welwarsky [Fri, 16 Sep 2016 08:12:00 +0000 (10:12 +0200)]
aarch64: fix register list

According to gdb documentation, a register "cpsr" is expected if
aarch64 features are announced. Also, the value buffer must be
capable of holding a 64bit value (8 byte, not 4)

Change-Id: I7aec4e84fa87eadb26797acd0d16c988b9852616
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: fix duplication of register cache 66/3766/6
Matthias Welwarsky [Thu, 15 Sep 2016 15:17:05 +0000 (17:17 +0200)]
aarch64: fix duplication of register cache

Change-Id: Ib4422e39171f19eea3f0b5a86f9dccdbb7044265
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: remove code for AHB-AP support 65/3765/6
Matthias Welwarsky [Thu, 15 Sep 2016 08:19:42 +0000 (10:19 +0200)]
aarch64: remove code for AHB-AP support

Reduce complexity of memory access functions, anyway there are no ARMv8
platforms that actually contain an AHB-AP at all. while at it, fix
virt-to-phys function signatures to expect target_addr_t.

Change-Id: I55a369686f42993988b6323e5a77f38de12530a9
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: fix stepping from address 64/3764/6
Matthias Welwarsky [Thu, 15 Sep 2016 07:14:31 +0000 (09:14 +0200)]
aarch64: fix stepping from address

The step command optionally carries a resume address. In this case,
stepping should start not at the current PC, but at the given address.

Change-Id: Id5792a3745f470cf29efa90c63d65f33d36f6b25
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: remove references to armv7-r 63/3763/6
Matthias Welwarsky [Thu, 1 Sep 2016 20:27:28 +0000 (22:27 +0200)]
aarch64: remove references to armv7-r

aarch64 target doesn't support the -r profile anyway.

Change-Id: Iaa470ed9f95ea495ab1bafdf401f55a1ebcefddf
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: fix armv8_set_core_reg when destination is cpsr 62/3762/6
Matthias Welwarsky [Fri, 16 Sep 2016 13:36:09 +0000 (15:36 +0200)]
aarch64: fix armv8_set_core_reg when destination is cpsr

When armv8_set_core_reg is used to set the value of
the CPSR, also update the internal architecture state.

Change-Id: I5f6a2be6fde8d91ec3352d8ba23c4aa90eb02977
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: unify armv7-a and armv8 debug entry decoding 61/3761/6
Matthias Welwarsky [Fri, 16 Sep 2016 13:34:21 +0000 (15:34 +0200)]
aarch64: unify armv7-a and armv8 debug entry decoding

Make DSCR_RUN_MODE() usable for armv8 and arm7 debug

Change-Id: Ib3ba3000d5b6aa03e590f3ca4969e677474eb12c
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: use correct A64 instructions for cache handling 60/3760/6
Matthias Welwarsky [Fri, 16 Sep 2016 13:31:29 +0000 (15:31 +0200)]
aarch64: use correct A64 instructions for cache handling

Replace A32 MCR with proper A64 MSR opcodes

Change-Id: I64a60b17a58a26b199d2d1b2d5d91098e0c8cbd0
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: fix first examination 59/3759/6
Matthias Welwarsky [Fri, 16 Sep 2016 13:26:49 +0000 (15:26 +0200)]
aarch64: fix first examination

properly decode debug capabilities, remove superfluous register
accesses.

Change-Id: I2cca699b515262dd2a508d7be97826eb17b9c607
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: correct display for aarch64 state 58/3758/5
Matthias Welwarsky [Fri, 16 Sep 2016 13:23:27 +0000 (15:23 +0200)]
aarch64: correct display for aarch64 state

Aarch64 state has different PSTATE and exception level model.
Correct the printout e.g. in poll command.

Change-Id: I1820fd1836c7076ae0aa405fa335fd1a14a2e5b3
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: use symbolic constant for register count 57/3757/5
Matthias Welwarsky [Fri, 16 Sep 2016 13:22:14 +0000 (15:22 +0200)]
aarch64: use symbolic constant for register count

Aarch64 has 34 registers, but use ARMV8_LAST_REG instead of
raw integer constant.

Change-Id: I86481899ade74f27fc90eff9f367d444c03e535e
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: remove armv7-a virt-to-phys code 56/3756/5
Matthias Welwarsky [Fri, 16 Sep 2016 13:18:47 +0000 (15:18 +0200)]
aarch64: remove armv7-a virt-to-phys code

Page table layout in aarch64 is very different from armv7-a layout.
Remove the incorrect handling, to be replaced correct armv8 code in a
later patch

Change-Id: I64c728a72a24f9f4177726ccc07a02a8ca0d56ce
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: clear breakpoint value register on removal 55/3755/5
Matthias Welwarsky [Fri, 16 Sep 2016 13:17:41 +0000 (15:17 +0200)]
aarch64: clear breakpoint value register on removal

Not only null control but also value of the breakpoint when it is
removed.

Change-Id: Id99c7e3644729c64e563f1fa8b0577f350be6a98
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: correct breakpoint register offset 54/3754/5
Matthias Welwarsky [Fri, 16 Sep 2016 13:16:19 +0000 (15:16 +0200)]
aarch64: correct breakpoint register offset

armv8 breakpoint register spacing is 16, not 4 as in armv7-a

Change-Id: I0d49d06878a0c9dab35cde478064e5366f01a8e0
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: fix cache identification 53/3753/5
Matthias Welwarsky [Fri, 16 Sep 2016 09:49:57 +0000 (11:49 +0200)]
aarch64: fix cache identification

Use correct instructions to access CLIDR, CSSELR and CCSIDR.

Change-Id: I319b96c03a44fdb59fcb18a00f816f6af0261f0a
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: fix reading of translation table registers 52/3752/5
Matthias Welwarsky [Fri, 16 Sep 2016 09:43:27 +0000 (11:43 +0200)]
aarch64: fix reading of translation table registers

Correctly access and parse aarch64 ttbcr.

Change-Id: I1b1652791a6b5200f58033925286292d838e8410
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: fix entry into debug state 51/3751/5
Matthias Welwarsky [Fri, 16 Sep 2016 09:34:03 +0000 (11:34 +0200)]
aarch64: fix entry into debug state

- armv8 EDSCR has no ITR_EN bit, ITR is always enabled. Writes to this
  bit are ignored but we should not do them anyway
- use dpmv8 function to report the reason for debug entry
- WFAR is a 64bit register

Change-Id: I07b81ecf105ceb7c3ae2f764bb408eb973c1d1de
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: use symbolic opcodes instead of hex values 50/3750/5
Matthias Welwarsky [Fri, 16 Sep 2016 09:15:15 +0000 (11:15 +0200)]
aarch64: use symbolic opcodes instead of hex values

Use opcode definitions from armv8_opcodes.h where appropriate

Change-Id: Iead33fb8e62eb2dd2419ef8932f7d46c087f51a8
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: fix accesses to SCTLR_ELn register 49/3749/5
Matthias Welwarsky [Fri, 16 Sep 2016 09:10:55 +0000 (11:10 +0200)]
aarch64: fix accesses to SCTLR_ELn register

The system control register has several instances, depending on the
exception level. Make sure to access always access the correct one.

Change-Id: I9e867f4dbd9625762042f20ed905064ea4e3270f
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: fix error recovery in aarch64_dpm_prepare 48/3748/5
Matthias Welwarsky [Fri, 16 Sep 2016 09:06:42 +0000 (11:06 +0200)]
aarch64: fix error recovery in aarch64_dpm_prepare

Flush DTRRX with a dummy read if it's full, clear sticky errors
by writing CSE bit to EDRCR register.

Change-Id: Ia42ae9d3859ba6cbe892d48584e21acdd4e25c84
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: formalize use of CTI in halt and resume 47/3747/5
Matthias Welwarsky [Fri, 16 Sep 2016 09:02:36 +0000 (11:02 +0200)]
aarch64: formalize use of CTI in halt and resume

Use configured CTI base address instead of hardcoded value, if
available.
Use symbolic constants instead of raw hex offsets.
Trim halt and resume code to what is actually necessary.

Change-Id: I4997c2bcca7cebf5ad78859a6a12abe8639594ed
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: fix context and hybrid hardware breakpoints 46/3746/5
Matthias Welwarsky [Sat, 17 Sep 2016 19:43:15 +0000 (21:43 +0200)]
aarch64: fix context and hybrid hardware breakpoints

Fix 64bit address setting
Fix register spacing (16 instead of 4)
Set HMC bit for all but linked context match breakpoints,
where the bit is ignored anyway

Change-Id: I48428f39154a6fe5fadc075ca918d1500a0bb241
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: deconflict debug register names 45/3745/5
Matthias Welwarsky [Sat, 17 Sep 2016 19:11:38 +0000 (21:11 +0200)]
aarch64: deconflict debug register names

CPUDBG_ -> CPUV8_DBG_ for armv8 debug registers.

Change-Id: I3d24cc209309fa9bbeb5c3e6c88a572383c9360e
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: Implement MA mode for bulk memory reads and writes 44/3744/5
Matthias Welwarsky [Thu, 15 Sep 2016 10:12:25 +0000 (12:12 +0200)]
aarch64: Implement MA mode for bulk memory reads and writes

- 64bit addresses are supported
- Aarch32 state is supported

Change-Id: I8c37fa166954d09195d08c6963b8017194e350f5
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3 years agoaarch64: make DCC read/write functions operate on struct armv8_common 43/3743/5
Matthias Welwarsky [Thu, 1 Sep 2016 19:14:46 +0000 (21:14 +0200)]
aarch64: make DCC read/write functions operate on struct armv8_common

Change the signature of aarch64_(read|write)_dcc[_64] to take a
"struct armv8_common *" as the context to operate on. No functional
change.

Change-Id: Ie501113f65ea22aff2eee173ec717f6908a63494
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>